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ppc/pnv: introduce a CPU machine_data
[qemu/kevin.git] / hw / ppc / pnv.c
blobda540860a2b0f307ff3a39ad111b7bb70fb168cf
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
26 #include "hw/hw.h"
27 #include "target/ppc/cpu.h"
28 #include "qemu/log.h"
29 #include "hw/ppc/fdt.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39 #include "target/ppc/mmu-hash64.h"
40
41 #include "hw/ppc/xics.h"
42 #include "hw/ppc/pnv_xscom.h"
43
44 #include "hw/isa/isa.h"
45 #include "hw/char/serial.h"
46 #include "hw/timer/mc146818rtc.h"
47
48 #include <libfdt.h>
49
50 #define FDT_MAX_SIZE 0x00100000
51
52 #define FW_FILE_NAME "skiboot.lid"
53 #define FW_LOAD_ADDR 0x0
54 #define FW_MAX_SIZE 0x00400000
55
56 #define KERNEL_LOAD_ADDR 0x20000000
57 #define INITRD_LOAD_ADDR 0x60000000
58
59 static const char *pnv_chip_core_typename(const PnvChip *o)
60 {
61 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
62 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
63 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
64 const char *core_type = object_class_get_name(object_class_by_name(s));
65 g_free(s);
66 return core_type;
67 }
68
69 /*
70 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
71 * 4 * 4 sockets * 12 cores * 8 threads = 1536
72 * Let's make it 2^11
73 */
74 #define MAX_CPUS 2048
75
76 /*
77 * Memory nodes are created by hostboot, one for each range of memory
78 * that has a different "affinity". In practice, it means one range
79 * per chip.
80 */
81 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
82 {
83 char *mem_name;
84 uint64_t mem_reg_property[2];
85 int off;
86
87 mem_reg_property[0] = cpu_to_be64(start);
88 mem_reg_property[1] = cpu_to_be64(size);
89
90 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
91 off = fdt_add_subnode(fdt, 0, mem_name);
92 g_free(mem_name);
93
94 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
95 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
96 sizeof(mem_reg_property))));
97 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
98 }
99
100 static int get_cpus_node(void *fdt)
101 {
102 int cpus_offset = fdt_path_offset(fdt, "/cpus");
103
104 if (cpus_offset < 0) {
105 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
106 if (cpus_offset) {
107 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
108 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
109 }
110 }
111 _FDT(cpus_offset);
112 return cpus_offset;
113 }
114
115 /*
116 * The PowerNV cores (and threads) need to use real HW ids and not an
117 * incremental index like it has been done on other platforms. This HW
118 * id is stored in the CPU PIR, it is used to create cpu nodes in the
119 * device tree, used in XSCOM to address cores and in interrupt
120 * servers.
121 */
122 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
123 {
124 PowerPCCPU *cpu = pc->threads[0];
125 CPUState *cs = CPU(cpu);
126 DeviceClass *dc = DEVICE_GET_CLASS(cs);
127 int smt_threads = CPU_CORE(pc)->nr_threads;
128 CPUPPCState *env = &cpu->env;
129 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
130 uint32_t servers_prop[smt_threads];
131 int i;
132 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
133 0xffffffff, 0xffffffff};
134 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
135 uint32_t cpufreq = 1000000000;
136 uint32_t page_sizes_prop[64];
137 size_t page_sizes_prop_size;
138 const uint8_t pa_features[] = { 24, 0,
139 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
140 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
141 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
142 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
143 int offset;
144 char *nodename;
145 int cpus_offset = get_cpus_node(fdt);
146
147 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
148 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
149 _FDT(offset);
150 g_free(nodename);
151
152 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
153
154 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
155 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
156 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
157
158 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
160 env->dcache_line_size)));
161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
162 env->dcache_line_size)));
163 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
164 env->icache_line_size)));
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
166 env->icache_line_size)));
167
168 if (pcc->l1_dcache_size) {
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
170 pcc->l1_dcache_size)));
171 } else {
172 warn_report("Unknown L1 dcache size for cpu");
173 }
174 if (pcc->l1_icache_size) {
175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
176 pcc->l1_icache_size)));
177 } else {
178 warn_report("Unknown L1 icache size for cpu");
179 }
180
181 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
182 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
183 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
184 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
185 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
186
187 if (env->spr_cb[SPR_PURR].oea_read) {
188 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
189 }
190
191 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
192 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
193 segs, sizeof(segs))));
194 }
195
196 /* Advertise VMX/VSX (vector extensions) if available
197 * 0 / no property == no vector extensions
198 * 1 == VMX / Altivec available
199 * 2 == VSX available */
200 if (env->insns_flags & PPC_ALTIVEC) {
201 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
202
203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
204 }
205
206 /* Advertise DFP (Decimal Floating Point) if available
207 * 0 / no property == no DFP
208 * 1 == DFP available */
209 if (env->insns_flags2 & PPC2_DFP) {
210 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
211 }
212
213 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
214 sizeof(page_sizes_prop));
215 if (page_sizes_prop_size) {
216 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
217 page_sizes_prop, page_sizes_prop_size)));
218 }
219
220 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
221 pa_features, sizeof(pa_features))));
222
223 /* Build interrupt servers properties */
224 for (i = 0; i < smt_threads; i++) {
225 servers_prop[i] = cpu_to_be32(pc->pir + i);
226 }
227 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
228 servers_prop, sizeof(servers_prop))));
229 }
230
231 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
232 uint32_t nr_threads)
233 {
234 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
235 char *name;
236 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
237 uint32_t irange[2], i, rsize;
238 uint64_t *reg;
239 int offset;
240
241 irange[0] = cpu_to_be32(pir);
242 irange[1] = cpu_to_be32(nr_threads);
243
244 rsize = sizeof(uint64_t) * 2 * nr_threads;
245 reg = g_malloc(rsize);
246 for (i = 0; i < nr_threads; i++) {
247 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
248 reg[i * 2 + 1] = cpu_to_be64(0x1000);
249 }
250
251 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
252 offset = fdt_add_subnode(fdt, 0, name);
253 _FDT(offset);
254 g_free(name);
255
256 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
257 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
258 _FDT((fdt_setprop_string(fdt, offset, "device_type",
259 "PowerPC-External-Interrupt-Presentation")));
260 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
261 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
262 irange, sizeof(irange))));
263 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
264 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
265 g_free(reg);
266 }
267
268 static void pnv_dt_chip(PnvChip *chip, void *fdt)
269 {
270 const char *typename = pnv_chip_core_typename(chip);
271 size_t typesize = object_type_get_instance_size(typename);
272 int i;
273
274 pnv_dt_xscom(chip, fdt, 0);
275
276 for (i = 0; i < chip->nr_cores; i++) {
277 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
278
279 pnv_dt_core(chip, pnv_core, fdt);
280
281 /* Interrupt Control Presenters (ICP). One per core. */
282 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
283 }
284
285 if (chip->ram_size) {
286 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
287 }
288 }
289
290 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
291 {
292 uint32_t io_base = d->ioport_id;
293 uint32_t io_regs[] = {
294 cpu_to_be32(1),
295 cpu_to_be32(io_base),
296 cpu_to_be32(2)
297 };
298 char *name;
299 int node;
300
301 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
302 node = fdt_add_subnode(fdt, lpc_off, name);
303 _FDT(node);
304 g_free(name);
305
306 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
307 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
308 }
309
310 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
311 {
312 const char compatible[] = "ns16550\0pnpPNP,501";
313 uint32_t io_base = d->ioport_id;
314 uint32_t io_regs[] = {
315 cpu_to_be32(1),
316 cpu_to_be32(io_base),
317 cpu_to_be32(8)
318 };
319 char *name;
320 int node;
321
322 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
323 node = fdt_add_subnode(fdt, lpc_off, name);
324 _FDT(node);
325 g_free(name);
326
327 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
328 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
329 sizeof(compatible))));
330
331 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
332 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
333 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
334 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
335 fdt_get_phandle(fdt, lpc_off))));
336
337 /* This is needed by Linux */
338 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
339 }
340
341 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
342 {
343 const char compatible[] = "bt\0ipmi-bt";
344 uint32_t io_base;
345 uint32_t io_regs[] = {
346 cpu_to_be32(1),
347 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
348 cpu_to_be32(3)
349 };
350 uint32_t irq;
351 char *name;
352 int node;
353
354 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
355 io_regs[1] = cpu_to_be32(io_base);
356
357 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
358
359 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
360 node = fdt_add_subnode(fdt, lpc_off, name);
361 _FDT(node);
362 g_free(name);
363
364 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
365 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
366 sizeof(compatible))));
367
368 /* Mark it as reserved to avoid Linux trying to claim it */
369 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
370 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
371 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
372 fdt_get_phandle(fdt, lpc_off))));
373 }
374
375 typedef struct ForeachPopulateArgs {
376 void *fdt;
377 int offset;
378 } ForeachPopulateArgs;
379
380 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
381 {
382 ForeachPopulateArgs *args = opaque;
383 ISADevice *d = ISA_DEVICE(dev);
384
385 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
386 pnv_dt_rtc(d, args->fdt, args->offset);
387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
388 pnv_dt_serial(d, args->fdt, args->offset);
389 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
390 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
391 } else {
392 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
393 d->ioport_id);
394 }
395
396 return 0;
397 }
398
399 static int pnv_chip_isa_offset(PnvChip *chip, void *fdt)
400 {
401 char *name;
402 int offset;
403
404 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
405 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
406 offset = fdt_path_offset(fdt, name);
407 g_free(name);
408 return offset;
409 }
410
411 /* The default LPC bus of a multichip system is on chip 0. It's
412 * recognized by the firmware (skiboot) using a "primary" property.
413 */
414 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
415 {
416 int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt);
417 ForeachPopulateArgs args = {
418 .fdt = fdt,
419 .offset = isa_offset,
420 };
421
422 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
423
424 /* ISA devices are not necessarily parented to the ISA bus so we
425 * can not use object_child_foreach() */
426 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
427 &args);
428 }
429
430 static void *pnv_dt_create(MachineState *machine)
431 {
432 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
433 PnvMachineState *pnv = PNV_MACHINE(machine);
434 void *fdt;
435 char *buf;
436 int off;
437 int i;
438
439 fdt = g_malloc0(FDT_MAX_SIZE);
440 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
441
442 /* Root node */
443 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
444 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
445 _FDT((fdt_setprop_string(fdt, 0, "model",
446 "IBM PowerNV (emulated by qemu)")));
447 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
448 sizeof(plat_compat))));
449
450 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
451 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
452 if (qemu_uuid_set) {
453 _FDT((fdt_property_string(fdt, "system-id", buf)));
454 }
455 g_free(buf);
456
457 off = fdt_add_subnode(fdt, 0, "chosen");
458 if (machine->kernel_cmdline) {
459 _FDT((fdt_setprop_string(fdt, off, "bootargs",
460 machine->kernel_cmdline)));
461 }
462
463 if (pnv->initrd_size) {
464 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
465 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
466
467 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
468 &start_prop, sizeof(start_prop))));
469 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
470 &end_prop, sizeof(end_prop))));
471 }
472
473 /* Populate device tree for each chip */
474 for (i = 0; i < pnv->num_chips; i++) {
475 pnv_dt_chip(pnv->chips[i], fdt);
476 }
477
478 /* Populate ISA devices on chip 0 */
479 pnv_dt_isa(pnv, fdt);
480
481 if (pnv->bmc) {
482 pnv_dt_bmc_sensors(pnv->bmc, fdt);
483 }
484
485 return fdt;
486 }
487
488 static void pnv_powerdown_notify(Notifier *n, void *opaque)
489 {
490 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
491
492 if (pnv->bmc) {
493 pnv_bmc_powerdown(pnv->bmc);
494 }
495 }
496
497 static void pnv_reset(void)
498 {
499 MachineState *machine = MACHINE(qdev_get_machine());
500 PnvMachineState *pnv = PNV_MACHINE(machine);
501 void *fdt;
502 Object *obj;
503
504 qemu_devices_reset();
505
506 /* OpenPOWER systems have a BMC, which can be defined on the
507 * command line with:
508 *
509 * -device ipmi-bmc-sim,id=bmc0
510 *
511 * This is the internal simulator but it could also be an external
512 * BMC.
513 */
514 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
515 if (obj) {
516 pnv->bmc = IPMI_BMC(obj);
517 }
518
519 fdt = pnv_dt_create(machine);
520
521 /* Pack resulting tree */
522 _FDT((fdt_pack(fdt)));
523
524 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
525 }
526
527 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
528 {
529 Pnv8Chip *chip8 = PNV8_CHIP(chip);
530 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
531 }
532
533 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
534 {
535 Pnv8Chip *chip8 = PNV8_CHIP(chip);
536 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
537 }
538
539 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
540 {
541 return NULL;
542 }
543
544 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
545 {
546 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
547 }
548
549 static void pnv_init(MachineState *machine)
550 {
551 PnvMachineState *pnv = PNV_MACHINE(machine);
552 MemoryRegion *ram;
553 char *fw_filename;
554 long fw_size;
555 int i;
556 char *chip_typename;
557
558 /* allocate RAM */
559 if (machine->ram_size < (1 * GiB)) {
560 warn_report("skiboot may not work with < 1GB of RAM");
561 }
562
563 ram = g_new(MemoryRegion, 1);
564 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
565 machine->ram_size);
566 memory_region_add_subregion(get_system_memory(), 0, ram);
567
568 /* load skiboot firmware */
569 if (bios_name == NULL) {
570 bios_name = FW_FILE_NAME;
571 }
572
573 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
574 if (!fw_filename) {
575 error_report("Could not find OPAL firmware '%s'", bios_name);
576 exit(1);
577 }
578
579 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
580 if (fw_size < 0) {
581 error_report("Could not load OPAL firmware '%s'", fw_filename);
582 exit(1);
583 }
584 g_free(fw_filename);
585
586 /* load kernel */
587 if (machine->kernel_filename) {
588 long kernel_size;
589
590 kernel_size = load_image_targphys(machine->kernel_filename,
591 KERNEL_LOAD_ADDR, 0x2000000);
592 if (kernel_size < 0) {
593 error_report("Could not load kernel '%s'",
594 machine->kernel_filename);
595 exit(1);
596 }
597 }
598
599 /* load initrd */
600 if (machine->initrd_filename) {
601 pnv->initrd_base = INITRD_LOAD_ADDR;
602 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
603 pnv->initrd_base, 0x10000000); /* 128MB max */
604 if (pnv->initrd_size < 0) {
605 error_report("Could not load initial ram disk '%s'",
606 machine->initrd_filename);
607 exit(1);
608 }
609 }
610
611 /* Create the processor chips */
612 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
613 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
614 i, machine->cpu_type);
615 if (!object_class_by_name(chip_typename)) {
616 error_report("invalid CPU model '%.*s' for %s machine",
617 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
618 exit(1);
619 }
620
621 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
622 for (i = 0; i < pnv->num_chips; i++) {
623 char chip_name[32];
624 Object *chip = object_new(chip_typename);
625
626 pnv->chips[i] = PNV_CHIP(chip);
627
628 /* TODO: put all the memory in one node on chip 0 until we find a
629 * way to specify different ranges for each chip
630 */
631 if (i == 0) {
632 object_property_set_int(chip, machine->ram_size, "ram-size",
633 &error_fatal);
634 }
635
636 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
637 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
638 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
639 &error_fatal);
640 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
641 object_property_set_bool(chip, true, "realized", &error_fatal);
642 }
643 g_free(chip_typename);
644
645 /* Instantiate ISA bus on chip 0 */
646 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
647
648 /* Create serial port */
649 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
650
651 /* Create an RTC ISA device too */
652 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
653
654 /* OpenPOWER systems use a IPMI SEL Event message to notify the
655 * host to powerdown */
656 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
657 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
658 }
659
660 /*
661 * 0:21 Reserved - Read as zeros
662 * 22:24 Chip ID
663 * 25:28 Core number
664 * 29:31 Thread ID
665 */
666 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
667 {
668 return (chip->chip_id << 7) | (core_id << 3);
669 }
670
671 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
672 Error **errp)
673 {
674 Error *local_err = NULL;
675 Object *obj;
676 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
677
678 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
679 &local_err);
680 if (local_err) {
681 error_propagate(errp, local_err);
682 return;
683 }
684
685 pnv_cpu->icp = ICP(obj);
686 }
687
688 /*
689 * 0:48 Reserved - Read as zeroes
690 * 49:52 Node ID
691 * 53:55 Chip ID
692 * 56 Reserved - Read as zero
693 * 57:61 Core number
694 * 62:63 Thread ID
695 *
696 * We only care about the lower bits. uint32_t is fine for the moment.
697 */
698 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
699 {
700 return (chip->chip_id << 8) | (core_id << 2);
701 }
702
703 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
704 Error **errp)
705 {
706 return;
707 }
708
709 /* Allowed core identifiers on a POWER8 Processor Chip :
710 *
711 * <EX0 reserved>
712 * EX1 - Venice only
713 * EX2 - Venice only
714 * EX3 - Venice only
715 * EX4
716 * EX5
717 * EX6
718 * <EX7,8 reserved> <reserved>
719 * EX9 - Venice only
720 * EX10 - Venice only
721 * EX11 - Venice only
722 * EX12
723 * EX13
724 * EX14
725 * <EX15 reserved>
726 */
727 #define POWER8E_CORE_MASK (0x7070ull)
728 #define POWER8_CORE_MASK (0x7e7eull)
729
730 /*
731 * POWER9 has 24 cores, ids starting at 0x0
732 */
733 #define POWER9_CORE_MASK (0xffffffffffffffull)
734
735 static void pnv_chip_power8_instance_init(Object *obj)
736 {
737 Pnv8Chip *chip8 = PNV8_CHIP(obj);
738
739 object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI);
740 object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL);
741 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
742 OBJECT(qdev_get_machine()), &error_abort);
743
744 object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC);
745 object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL);
746 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
747 OBJECT(&chip8->psi), &error_abort);
748
749 object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC);
750 object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL);
751 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
752 OBJECT(&chip8->psi), &error_abort);
753 }
754
755 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
756 {
757 PnvChip *chip = PNV_CHIP(chip8);
758 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
759 const char *typename = pnv_chip_core_typename(chip);
760 size_t typesize = object_type_get_instance_size(typename);
761 int i, j;
762 char *name;
763 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
764
765 name = g_strdup_printf("icp-%x", chip->chip_id);
766 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
767 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
768 g_free(name);
769
770 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
771
772 /* Map the ICP registers for each thread */
773 for (i = 0; i < chip->nr_cores; i++) {
774 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
775 int core_hwid = CPU_CORE(pnv_core)->core_id;
776
777 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
778 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
779 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
780
781 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
782 &icp->mmio);
783 }
784 }
785 }
786
787 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
788 {
789 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
790 PnvChip *chip = PNV_CHIP(dev);
791 Pnv8Chip *chip8 = PNV8_CHIP(dev);
792 Error *local_err = NULL;
793
794 pcc->parent_realize(dev, &local_err);
795 if (local_err) {
796 error_propagate(errp, local_err);
797 return;
798 }
799
800 /* Processor Service Interface (PSI) Host Bridge */
801 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
802 "bar", &error_fatal);
803 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
804 if (local_err) {
805 error_propagate(errp, local_err);
806 return;
807 }
808 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs);
809
810 /* Create LPC controller */
811 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
812 &error_fatal);
813 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
814
815 /* Interrupt Management Area. This is the memory region holding
816 * all the Interrupt Control Presenter (ICP) registers */
817 pnv_chip_icp_realize(chip8, &local_err);
818 if (local_err) {
819 error_propagate(errp, local_err);
820 return;
821 }
822
823 /* Create the simplified OCC model */
824 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
825 if (local_err) {
826 error_propagate(errp, local_err);
827 return;
828 }
829 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
830 }
831
832 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
833 {
834 DeviceClass *dc = DEVICE_CLASS(klass);
835 PnvChipClass *k = PNV_CHIP_CLASS(klass);
836
837 k->chip_type = PNV_CHIP_POWER8E;
838 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
839 k->cores_mask = POWER8E_CORE_MASK;
840 k->core_pir = pnv_chip_core_pir_p8;
841 k->intc_create = pnv_chip_power8_intc_create;
842 k->isa_create = pnv_chip_power8_isa_create;
843 k->xscom_base = 0x003fc0000000000ull;
844 dc->desc = "PowerNV Chip POWER8E";
845
846 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
847 &k->parent_realize);
848 }
849
850 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
851 {
852 DeviceClass *dc = DEVICE_CLASS(klass);
853 PnvChipClass *k = PNV_CHIP_CLASS(klass);
854
855 k->chip_type = PNV_CHIP_POWER8;
856 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
857 k->cores_mask = POWER8_CORE_MASK;
858 k->core_pir = pnv_chip_core_pir_p8;
859 k->intc_create = pnv_chip_power8_intc_create;
860 k->isa_create = pnv_chip_power8_isa_create;
861 k->xscom_base = 0x003fc0000000000ull;
862 dc->desc = "PowerNV Chip POWER8";
863
864 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
865 &k->parent_realize);
866 }
867
868 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
869 {
870 DeviceClass *dc = DEVICE_CLASS(klass);
871 PnvChipClass *k = PNV_CHIP_CLASS(klass);
872
873 k->chip_type = PNV_CHIP_POWER8NVL;
874 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
875 k->cores_mask = POWER8_CORE_MASK;
876 k->core_pir = pnv_chip_core_pir_p8;
877 k->intc_create = pnv_chip_power8_intc_create;
878 k->isa_create = pnv_chip_power8nvl_isa_create;
879 k->xscom_base = 0x003fc0000000000ull;
880 dc->desc = "PowerNV Chip POWER8NVL";
881
882 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
883 &k->parent_realize);
884 }
885
886 static void pnv_chip_power9_instance_init(Object *obj)
887 {
888 }
889
890 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
891 {
892 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
893 Error *local_err = NULL;
894
895 pcc->parent_realize(dev, &local_err);
896 if (local_err) {
897 error_propagate(errp, local_err);
898 return;
899 }
900 }
901
902 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
903 {
904 DeviceClass *dc = DEVICE_CLASS(klass);
905 PnvChipClass *k = PNV_CHIP_CLASS(klass);
906
907 k->chip_type = PNV_CHIP_POWER9;
908 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
909 k->cores_mask = POWER9_CORE_MASK;
910 k->core_pir = pnv_chip_core_pir_p9;
911 k->intc_create = pnv_chip_power9_intc_create;
912 k->isa_create = pnv_chip_power9_isa_create;
913 k->xscom_base = 0x00603fc00000000ull;
914 dc->desc = "PowerNV Chip POWER9";
915
916 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
917 &k->parent_realize);
918 }
919
920 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
921 {
922 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
923 int cores_max;
924
925 /*
926 * No custom mask for this chip, let's use the default one from *
927 * the chip class
928 */
929 if (!chip->cores_mask) {
930 chip->cores_mask = pcc->cores_mask;
931 }
932
933 /* filter alien core ids ! some are reserved */
934 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
935 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
936 chip->cores_mask);
937 return;
938 }
939 chip->cores_mask &= pcc->cores_mask;
940
941 /* now that we have a sane layout, let check the number of cores */
942 cores_max = ctpop64(chip->cores_mask);
943 if (chip->nr_cores > cores_max) {
944 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
945 cores_max);
946 return;
947 }
948 }
949
950 static void pnv_chip_instance_init(Object *obj)
951 {
952 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base;
953 }
954
955 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
956 {
957 Error *error = NULL;
958 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
959 const char *typename = pnv_chip_core_typename(chip);
960 size_t typesize = object_type_get_instance_size(typename);
961 int i, core_hwid;
962
963 if (!object_class_by_name(typename)) {
964 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
965 return;
966 }
967
968 /* Cores */
969 pnv_chip_core_sanitize(chip, &error);
970 if (error) {
971 error_propagate(errp, error);
972 return;
973 }
974
975 chip->cores = g_malloc0(typesize * chip->nr_cores);
976
977 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
978 && (i < chip->nr_cores); core_hwid++) {
979 char core_name[32];
980 void *pnv_core = chip->cores + i * typesize;
981 uint64_t xscom_core_base;
982
983 if (!(chip->cores_mask & (1ull << core_hwid))) {
984 continue;
985 }
986
987 object_initialize(pnv_core, typesize, typename);
988 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
989 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
990 &error_fatal);
991 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
992 &error_fatal);
993 object_property_set_int(OBJECT(pnv_core), core_hwid,
994 CPU_CORE_PROP_CORE_ID, &error_fatal);
995 object_property_set_int(OBJECT(pnv_core),
996 pcc->core_pir(chip, core_hwid),
997 "pir", &error_fatal);
998 object_property_add_const_link(OBJECT(pnv_core), "chip",
999 OBJECT(chip), &error_fatal);
1000 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1001 &error_fatal);
1002 object_unref(OBJECT(pnv_core));
1003
1004 /* Each core has an XSCOM MMIO region */
1005 if (!pnv_chip_is_power9(chip)) {
1006 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1007 } else {
1008 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid);
1009 }
1010
1011 pnv_xscom_add_subregion(chip, xscom_core_base,
1012 &PNV_CORE(pnv_core)->xscom_regs);
1013 i++;
1014 }
1015 }
1016
1017 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1018 {
1019 PnvChip *chip = PNV_CHIP(dev);
1020 Error *error = NULL;
1021
1022 /* XSCOM bridge */
1023 pnv_xscom_realize(chip, &error);
1024 if (error) {
1025 error_propagate(errp, error);
1026 return;
1027 }
1028 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1029
1030 /* Cores */
1031 pnv_chip_core_realize(chip, &error);
1032 if (error) {
1033 error_propagate(errp, error);
1034 return;
1035 }
1036 }
1037
1038 static Property pnv_chip_properties[] = {
1039 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1040 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1041 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1042 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1043 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1044 DEFINE_PROP_END_OF_LIST(),
1045 };
1046
1047 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1048 {
1049 DeviceClass *dc = DEVICE_CLASS(klass);
1050
1051 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1052 dc->realize = pnv_chip_realize;
1053 dc->props = pnv_chip_properties;
1054 dc->desc = "PowerNV Chip";
1055 }
1056
1057 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1058 {
1059 PnvMachineState *pnv = PNV_MACHINE(xi);
1060 int i;
1061
1062 for (i = 0; i < pnv->num_chips; i++) {
1063 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1064
1065 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1066 return &chip8->psi.ics;
1067 }
1068 }
1069 return NULL;
1070 }
1071
1072 static void pnv_ics_resend(XICSFabric *xi)
1073 {
1074 PnvMachineState *pnv = PNV_MACHINE(xi);
1075 int i;
1076
1077 for (i = 0; i < pnv->num_chips; i++) {
1078 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1079 ics_resend(&chip8->psi.ics);
1080 }
1081 }
1082
1083 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1084 {
1085 CPUState *cs;
1086
1087 CPU_FOREACH(cs) {
1088 PowerPCCPU *cpu = POWERPC_CPU(cs);
1089 CPUPPCState *env = &cpu->env;
1090
1091 if (env->spr_cb[SPR_PIR].default_value == pir) {
1092 return cpu;
1093 }
1094 }
1095
1096 return NULL;
1097 }
1098
1099 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1100 {
1101 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1102
1103 return cpu ? pnv_cpu_state(cpu)->icp : NULL;
1104 }
1105
1106 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1107 Monitor *mon)
1108 {
1109 PnvMachineState *pnv = PNV_MACHINE(obj);
1110 int i;
1111 CPUState *cs;
1112
1113 CPU_FOREACH(cs) {
1114 PowerPCCPU *cpu = POWERPC_CPU(cs);
1115
1116 icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon);
1117 }
1118
1119 for (i = 0; i < pnv->num_chips; i++) {
1120 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1121 ics_pic_print_info(&chip8->psi.ics, mon);
1122 }
1123 }
1124
1125 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1126 void *opaque, Error **errp)
1127 {
1128 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1129 }
1130
1131 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1132 void *opaque, Error **errp)
1133 {
1134 PnvMachineState *pnv = PNV_MACHINE(obj);
1135 uint32_t num_chips;
1136 Error *local_err = NULL;
1137
1138 visit_type_uint32(v, name, &num_chips, &local_err);
1139 if (local_err) {
1140 error_propagate(errp, local_err);
1141 return;
1142 }
1143
1144 /*
1145 * TODO: should we decide on how many chips we can create based
1146 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1147 */
1148 if (!is_power_of_2(num_chips) || num_chips > 4) {
1149 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1150 return;
1151 }
1152
1153 pnv->num_chips = num_chips;
1154 }
1155
1156 static void pnv_machine_instance_init(Object *obj)
1157 {
1158 PnvMachineState *pnv = PNV_MACHINE(obj);
1159 pnv->num_chips = 1;
1160 }
1161
1162 static void pnv_machine_class_props_init(ObjectClass *oc)
1163 {
1164 object_class_property_add(oc, "num-chips", "uint32",
1165 pnv_get_num_chips, pnv_set_num_chips,
1166 NULL, NULL, NULL);
1167 object_class_property_set_description(oc, "num-chips",
1168 "Specifies the number of processor chips",
1169 NULL);
1170 }
1171
1172 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1173 {
1174 MachineClass *mc = MACHINE_CLASS(oc);
1175 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1176 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1177
1178 mc->desc = "IBM PowerNV (Non-Virtualized)";
1179 mc->init = pnv_init;
1180 mc->reset = pnv_reset;
1181 mc->max_cpus = MAX_CPUS;
1182 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1183 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1184 * storage */
1185 mc->no_parallel = 1;
1186 mc->default_boot_order = NULL;
1187 mc->default_ram_size = 1 * GiB;
1188 xic->icp_get = pnv_icp_get;
1189 xic->ics_get = pnv_ics_get;
1190 xic->ics_resend = pnv_ics_resend;
1191 ispc->print_info = pnv_pic_print_info;
1192
1193 pnv_machine_class_props_init(oc);
1194 }
1195
1196 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1197 { \
1198 .name = type, \
1199 .class_init = class_initfn, \
1200 .parent = TYPE_PNV8_CHIP, \
1201 }
1202
1203 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1204 { \
1205 .name = type, \
1206 .class_init = class_initfn, \
1207 .parent = TYPE_PNV9_CHIP, \
1208 }
1209
1210 static const TypeInfo types[] = {
1211 {
1212 .name = TYPE_PNV_MACHINE,
1213 .parent = TYPE_MACHINE,
1214 .instance_size = sizeof(PnvMachineState),
1215 .instance_init = pnv_machine_instance_init,
1216 .class_init = pnv_machine_class_init,
1217 .interfaces = (InterfaceInfo[]) {
1218 { TYPE_XICS_FABRIC },
1219 { TYPE_INTERRUPT_STATS_PROVIDER },
1220 { },
1221 },
1222 },
1223 {
1224 .name = TYPE_PNV_CHIP,
1225 .parent = TYPE_SYS_BUS_DEVICE,
1226 .class_init = pnv_chip_class_init,
1227 .instance_init = pnv_chip_instance_init,
1228 .instance_size = sizeof(PnvChip),
1229 .class_size = sizeof(PnvChipClass),
1230 .abstract = true,
1231 },
1232
1233 /*
1234 * P9 chip and variants
1235 */
1236 {
1237 .name = TYPE_PNV9_CHIP,
1238 .parent = TYPE_PNV_CHIP,
1239 .instance_init = pnv_chip_power9_instance_init,
1240 .instance_size = sizeof(Pnv9Chip),
1241 },
1242 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1243
1244 /*
1245 * P8 chip and variants
1246 */
1247 {
1248 .name = TYPE_PNV8_CHIP,
1249 .parent = TYPE_PNV_CHIP,
1250 .instance_init = pnv_chip_power8_instance_init,
1251 .instance_size = sizeof(Pnv8Chip),
1252 },
1253 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1254 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1255 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1256 pnv_chip_power8nvl_class_init),
1257 };
1258
1259 DEFINE_TYPES(types)
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