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migration/rdma: Drop qemu_rdma_search_ram_block() error handling
[qemu/kevin.git] / tests / qtest / tpm-tis-i2c-test.c
blob3a1af026f2e6aa7c77485abdb6205abe6775026c
1 /*
2 * QTest testcases for TPM TIS on I2C (derived from TPM TIS test)
3 *
4 * Copyright (c) 2023 IBM Corporation
5 * Copyright (c) 2023 Red Hat, Inc.
6 *
7 * Authors:
8 * Stefan Berger <stefanb@linux.ibm.com>
9 * Marc-André Lureau <marcandre.lureau@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 */
14
15 #include "qemu/osdep.h"
16 #include <glib/gstdio.h>
17
18 #include "libqtest-single.h"
19 #include "hw/acpi/tpm.h"
20 #include "hw/pci/pci_ids.h"
21 #include "qtest_aspeed.h"
22 #include "tpm-emu.h"
23
24 #define DEBUG_TIS_TEST 0
25
26 #define DPRINTF(fmt, ...) do { \
27 if (DEBUG_TIS_TEST) { \
28 printf(fmt, ## __VA_ARGS__); \
29 } \
30 } while (0)
31
32 #define DPRINTF_ACCESS \
33 DPRINTF("%s: %d: locty=%d l=%d access=0x%02x pending_request_flag=0x%x\n", \
34 __func__, __LINE__, locty, l, access, pending_request_flag)
35
36 #define DPRINTF_STS \
37 DPRINTF("%s: %d: sts = 0x%08x\n", __func__, __LINE__, sts)
38
39 #define I2C_SLAVE_ADDR 0x2e
40 #define I2C_DEV_BUS_NUM 10
41
42 static const uint8_t TPM_CMD[12] =
43 "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00";
44
45 static uint32_t aspeed_bus_addr;
46
47 static uint8_t cur_locty = 0xff;
48
49 static void tpm_tis_i2c_set_locty(uint8_t locty)
50 {
51 if (cur_locty != locty) {
52 cur_locty = locty;
53 aspeed_i2c_writeb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR,
54 TPM_I2C_REG_LOC_SEL, locty);
55 }
56 }
57
58 static uint8_t tpm_tis_i2c_readb(uint8_t locty, uint8_t reg)
59 {
60 tpm_tis_i2c_set_locty(locty);
61 return aspeed_i2c_readb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
62 }
63
64 static uint16_t tpm_tis_i2c_readw(uint8_t locty, uint8_t reg)
65 {
66 tpm_tis_i2c_set_locty(locty);
67 return aspeed_i2c_readw(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
68 }
69
70 static uint32_t tpm_tis_i2c_readl(uint8_t locty, uint8_t reg)
71 {
72 tpm_tis_i2c_set_locty(locty);
73 return aspeed_i2c_readl(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg);
74 }
75
76 static void tpm_tis_i2c_writeb(uint8_t locty, uint8_t reg, uint8_t v)
77 {
78 if (reg != TPM_I2C_REG_LOC_SEL) {
79 tpm_tis_i2c_set_locty(locty);
80 }
81 aspeed_i2c_writeb(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg, v);
82 }
83
84 static void tpm_tis_i2c_writel(uint8_t locty, uint8_t reg, uint32_t v)
85 {
86 if (reg != TPM_I2C_REG_LOC_SEL) {
87 tpm_tis_i2c_set_locty(locty);
88 }
89 aspeed_i2c_writel(global_qtest, aspeed_bus_addr, I2C_SLAVE_ADDR, reg, v);
90 }
91
92 static void tpm_tis_i2c_test_basic(const void *data)
93 {
94 uint8_t access;
95 uint32_t v, v2;
96
97 /*
98 * All register accesses below must work without locality 0 being the
99 * active locality. Therefore, ensure access is released.
100 */
101 tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS,
102 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
103 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
104 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
105 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
106
107 /* read interrupt capability -- none are supported */
108 v = tpm_tis_i2c_readl(0, TPM_I2C_REG_INT_CAPABILITY);
109 g_assert_cmpint(v, ==, 0);
110
111 /* try to enable all interrupts */
112 tpm_tis_i2c_writel(0, TPM_I2C_REG_INT_ENABLE, 0xffffffff);
113 v = tpm_tis_i2c_readl(0, TPM_I2C_REG_INT_ENABLE);
114 /* none could be enabled */
115 g_assert_cmpint(v, ==, 0);
116
117 /* enable csum */
118 tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_DATA_CSUM_ENABLED);
119 /* check csum enable register has bit 0 set */
120 v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
121 g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
122 /* reading it as 32bit register returns same result */
123 v = tpm_tis_i2c_readl(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
124 g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
125
126 /* disable csum */
127 tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, 0);
128 /* check csum enable register has bit 0 clear */
129 v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
130 g_assert_cmpint(v, ==, 0);
131
132 /* write to unsupported register '1' */
133 tpm_tis_i2c_writel(0, 1, 0x12345678);
134 v = tpm_tis_i2c_readl(0, 1);
135 g_assert_cmpint(v, ==, 0xffffffff);
136
137 /* request use of locality */
138 tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
139
140 /* read byte from STS + 3 */
141 v = tpm_tis_i2c_readb(0, TPM_I2C_REG_STS + 3);
142 g_assert_cmpint(v, ==, 0);
143
144 /* check STS after writing to STS + 3 */
145 v = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
146 tpm_tis_i2c_writeb(0, TPM_I2C_REG_STS + 3, 0xf);
147 v2 = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
148 g_assert_cmpint(v, ==, v2);
149
150 /* release access */
151 tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS,
152 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
153
154 /* select locality 5 -- must not be possible */
155 tpm_tis_i2c_writeb(0, TPM_I2C_REG_LOC_SEL, 5);
156 v = tpm_tis_i2c_readb(0, TPM_I2C_REG_LOC_SEL);
157 g_assert_cmpint(v, ==, 0);
158 }
159
160 static void tpm_tis_i2c_test_check_localities(const void *data)
161 {
162 uint8_t locty, l;
163 uint8_t access;
164 uint32_t capability, i2c_cap;
165 uint32_t didvid;
166 uint32_t rid;
167
168 for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES; locty++) {
169 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
170 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
171 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
172
173 capability = tpm_tis_i2c_readl(locty, TPM_I2C_REG_INTF_CAPABILITY);
174 i2c_cap = (TPM_I2C_CAP_INTERFACE_TYPE |
175 TPM_I2C_CAP_INTERFACE_VER |
176 TPM_I2C_CAP_TPM2_FAMILY |
177 TPM_I2C_CAP_LOCALITY_CAP |
178 TPM_I2C_CAP_BUS_SPEED |
179 TPM_I2C_CAP_DEV_ADDR_CHANGE);
180 g_assert_cmpint(capability, ==, i2c_cap);
181
182 didvid = tpm_tis_i2c_readl(locty, TPM_I2C_REG_DID_VID);
183 g_assert_cmpint(didvid, ==, (1 << 16) | PCI_VENDOR_ID_IBM);
184
185 rid = tpm_tis_i2c_readl(locty, TPM_I2C_REG_RID);
186 g_assert_cmpint(rid, !=, 0);
187 g_assert_cmpint(rid, !=, 0xffffffff);
188
189 /* locality selection must be at locty */
190 l = tpm_tis_i2c_readb(locty, TPM_I2C_REG_LOC_SEL);
191 g_assert_cmpint(l, ==, locty);
192 }
193 }
194
195 static void tpm_tis_i2c_test_check_access_reg(const void *data)
196 {
197 uint8_t locty;
198 uint8_t access;
199
200 /* do not test locality 4 (hw only) */
201 for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES - 1; locty++) {
202 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
203 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
204 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
205
206 /* request use of locality */
207 tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
208 TPM_TIS_ACCESS_REQUEST_USE);
209
210 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
211 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
212 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
213 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
214
215 /* release access */
216 tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
217 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
218 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
219 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
220 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
221 }
222 }
223
224 /*
225 * Test case for seizing access by a higher number locality
226 */
227 static void tpm_tis_i2c_test_check_access_reg_seize(const void *data)
228 {
229 int locty, l;
230 uint8_t access;
231 uint8_t pending_request_flag;
232
233 /* do not test locality 4 (hw only) */
234 for (locty = 0; locty < TPM_TIS_NUM_LOCALITIES - 1; locty++) {
235 pending_request_flag = 0;
236
237 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
238 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
239 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
240
241 /* request use of locality */
242 tpm_tis_i2c_writeb(locty,
243 TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
244 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
245 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
246 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
247 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
248
249 /* lower localities cannot seize access */
250 for (l = 0; l < locty; l++) {
251 /* lower locality is not active */
252 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
253 DPRINTF_ACCESS;
254 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
255 pending_request_flag |
256 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
257
258 /* try to request use from 'l' */
259 tpm_tis_i2c_writeb(l,
260 TPM_I2C_REG_ACCESS,
261 TPM_TIS_ACCESS_REQUEST_USE);
262
263 /*
264 * requesting use from 'l' was not possible;
265 * we must see REQUEST_USE and possibly PENDING_REQUEST
266 */
267 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
268 DPRINTF_ACCESS;
269 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
270 TPM_TIS_ACCESS_REQUEST_USE |
271 pending_request_flag |
272 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
273
274 /*
275 * locality 'locty' must be unchanged;
276 * we must see PENDING_REQUEST
277 */
278 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
279 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
280 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
281 TPM_TIS_ACCESS_PENDING_REQUEST |
282 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
283
284 /* try to seize from 'l' */
285 tpm_tis_i2c_writeb(l,
286 TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_SEIZE);
287 /* seize from 'l' was not possible */
288 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
289 DPRINTF_ACCESS;
290 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
291 TPM_TIS_ACCESS_REQUEST_USE |
292 pending_request_flag |
293 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
294
295 /* locality 'locty' must be unchanged */
296 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
297 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
298 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
299 TPM_TIS_ACCESS_PENDING_REQUEST |
300 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
301
302 /*
303 * on the next loop we will have a PENDING_REQUEST flag
304 * set for locality 'l'
305 */
306 pending_request_flag = TPM_TIS_ACCESS_PENDING_REQUEST;
307 }
308
309 /*
310 * higher localities can 'seize' access but not 'request use';
311 * note: this will activate first l+1, then l+2 etc.
312 */
313 for (l = locty + 1; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
314 /* try to 'request use' from 'l' */
315 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
316 TPM_TIS_ACCESS_REQUEST_USE);
317
318 /*
319 * requesting use from 'l' was not possible; we should see
320 * REQUEST_USE and may see PENDING_REQUEST
321 */
322 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
323 DPRINTF_ACCESS;
324 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
325 TPM_TIS_ACCESS_REQUEST_USE |
326 pending_request_flag |
327 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
328
329 /*
330 * locality 'l-1' must be unchanged; we should always
331 * see PENDING_REQUEST from 'l' requesting access
332 */
333 access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
334 DPRINTF_ACCESS;
335 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
336 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
337 TPM_TIS_ACCESS_PENDING_REQUEST |
338 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
339
340 /* try to seize from 'l' */
341 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_SEIZE);
342
343 /* seize from 'l' was possible */
344 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
345 DPRINTF_ACCESS;
346 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
347 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
348 pending_request_flag |
349 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
350
351 /* l - 1 should show that it has BEEN_SEIZED */
352 access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
353 DPRINTF_ACCESS;
354 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
355 TPM_TIS_ACCESS_BEEN_SEIZED |
356 pending_request_flag |
357 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
358
359 /* clear the BEEN_SEIZED flag and make sure it's gone */
360 tpm_tis_i2c_writeb(l - 1, TPM_I2C_REG_ACCESS,
361 TPM_TIS_ACCESS_BEEN_SEIZED);
362
363 access = tpm_tis_i2c_readb(l - 1, TPM_I2C_REG_ACCESS);
364 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
365 pending_request_flag |
366 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
367 }
368
369 /*
370 * PENDING_REQUEST will not be set if locty = 0 since all localities
371 * were active; in case of locty = 1, locality 0 will be active
372 * but no PENDING_REQUEST anywhere
373 */
374 if (locty <= 1) {
375 pending_request_flag = 0;
376 }
377
378 /* release access from l - 1; this activates locty - 1 */
379 l--;
380
381 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
382 DPRINTF_ACCESS;
383
384 DPRINTF("%s: %d: relinquishing control on l = %d\n",
385 __func__, __LINE__, l);
386 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
387 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
388
389 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
390 DPRINTF_ACCESS;
391 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
392 pending_request_flag |
393 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
394
395 for (l = locty - 1; l >= 0; l--) {
396 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
397 DPRINTF_ACCESS;
398 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
399 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
400 pending_request_flag |
401 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
402
403 /* release this locality */
404 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
405 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
406
407 if (l == 1) {
408 pending_request_flag = 0;
409 }
410 }
411
412 /* no locality may be active now */
413 for (l = 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
414 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
415 DPRINTF_ACCESS;
416 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
417 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
418 }
419 }
420 }
421
422 /*
423 * Test case for getting access when higher number locality relinquishes access
424 */
425 static void tpm_tis_i2c_test_check_access_reg_release(const void *data)
426 {
427 int locty, l;
428 uint8_t access;
429 uint8_t pending_request_flag;
430
431 /* do not test locality 4 (hw only) */
432 for (locty = TPM_TIS_NUM_LOCALITIES - 2; locty >= 0; locty--) {
433 pending_request_flag = 0;
434
435 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
436 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
437 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
438
439 /* request use of locality */
440 tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
441 TPM_TIS_ACCESS_REQUEST_USE);
442 access = tpm_tis_i2c_readb(locty, TPM_I2C_REG_ACCESS);
443 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
444 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
445 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
446
447 /* request use of all other localities */
448 for (l = 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) {
449 if (l == locty) {
450 continue;
451 }
452 /*
453 * request use of locality 'l' -- we MUST see REQUEST USE and
454 * may see PENDING_REQUEST
455 */
456 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
457 TPM_TIS_ACCESS_REQUEST_USE);
458 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
459 DPRINTF_ACCESS;
460 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
461 TPM_TIS_ACCESS_REQUEST_USE |
462 pending_request_flag |
463 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
464 pending_request_flag = TPM_TIS_ACCESS_PENDING_REQUEST;
465 }
466 /* release locality 'locty' */
467 tpm_tis_i2c_writeb(locty, TPM_I2C_REG_ACCESS,
468 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
469 /*
470 * highest locality should now be active; release it and make sure the
471 * next highest locality is active afterwards
472 */
473 for (l = TPM_TIS_NUM_LOCALITIES - 2; l >= 0; l--) {
474 if (l == locty) {
475 continue;
476 }
477 /* 'l' should be active now */
478 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
479 DPRINTF_ACCESS;
480 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
481 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
482 pending_request_flag |
483 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
484 /* 'l' relinquishes access */
485 tpm_tis_i2c_writeb(l, TPM_I2C_REG_ACCESS,
486 TPM_TIS_ACCESS_ACTIVE_LOCALITY);
487 access = tpm_tis_i2c_readb(l, TPM_I2C_REG_ACCESS);
488 DPRINTF_ACCESS;
489 if (l == 1 || (locty <= 1 && l == 2)) {
490 pending_request_flag = 0;
491 }
492 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
493 pending_request_flag |
494 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
495 }
496 }
497 }
498
499 /*
500 * Test case for transmitting packets
501 */
502 static void tpm_tis_i2c_test_check_transmit(const void *data)
503 {
504 const TPMTestState *s = data;
505 uint8_t access;
506 uint32_t sts, v;
507 uint16_t bcount, csum, bcount2;
508 size_t i;
509
510 /* enable csum */
511 tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_DATA_CSUM_ENABLED);
512 /* check csum enable register has bit 0 set */
513 v = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
514 g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
515 /* reading it as 32bit register returns same result */
516 v = tpm_tis_i2c_readl(0, TPM_I2C_REG_DATA_CSUM_ENABLE);
517 g_assert_cmpint(v, ==, TPM_DATA_CSUM_ENABLED);
518
519 /* request use of locality 0 */
520 tpm_tis_i2c_writeb(0, TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE);
521 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
522 g_assert_cmpint(access, ==, TPM_TIS_ACCESS_TPM_REG_VALID_STS |
523 TPM_TIS_ACCESS_ACTIVE_LOCALITY |
524 TPM_TIS_ACCESS_TPM_ESTABLISHMENT);
525
526 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
527 DPRINTF_STS;
528
529 g_assert_cmpint(sts & 0xff, ==, 0);
530
531 bcount = (sts >> 8) & 0xffff;
532 g_assert_cmpint(bcount, >=, 128);
533
534 /* read bcount from STS + 1 must work also */
535 bcount2 = tpm_tis_i2c_readw(0, TPM_I2C_REG_STS + 1);
536 g_assert_cmpint(bcount, ==, bcount2);
537
538 /* ic2 must have bits 26-31 zero */
539 g_assert_cmpint(sts & (0x1f << 26), ==, 0);
540
541 tpm_tis_i2c_writel(0, TPM_I2C_REG_STS, TPM_TIS_STS_COMMAND_READY);
542 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
543 DPRINTF_STS;
544 g_assert_cmpint(sts & 0xff, ==, TPM_TIS_STS_COMMAND_READY);
545
546 /* transmit command */
547 for (i = 0; i < sizeof(TPM_CMD); i++) {
548 tpm_tis_i2c_writeb(0, TPM_I2C_REG_DATA_FIFO, TPM_CMD[i]);
549 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
550 DPRINTF_STS;
551 if (i < sizeof(TPM_CMD) - 1) {
552 g_assert_cmpint(sts & 0xff, ==,
553 TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID);
554 } else {
555 g_assert_cmpint(sts & 0xff, ==, TPM_TIS_STS_VALID);
556 }
557 g_assert_cmpint((sts >> 8) & 0xffff, ==, --bcount);
558 }
559 /* read the checksum */
560 csum = tpm_tis_i2c_readw(0, TPM_I2C_REG_DATA_CSUM_GET);
561 g_assert_cmpint(csum, ==, 0x6733);
562
563 /* start processing */
564 tpm_tis_i2c_writeb(0, TPM_I2C_REG_STS, TPM_TIS_STS_TPM_GO);
565
566 uint64_t end_time = g_get_monotonic_time() + 50 * G_TIME_SPAN_SECOND;
567 do {
568 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
569 if ((sts & TPM_TIS_STS_DATA_AVAILABLE) != 0) {
570 break;
571 }
572 } while (g_get_monotonic_time() < end_time);
573
574 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
575 DPRINTF_STS;
576 g_assert_cmpint(sts & 0xff, == ,
577 TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE);
578 bcount = (sts >> 8) & 0xffff;
579
580 /* read response */
581 uint8_t tpm_msg[sizeof(struct tpm_hdr)];
582 g_assert_cmpint(sizeof(tpm_msg), ==, bcount);
583
584 for (i = 0; i < sizeof(tpm_msg); i++) {
585 tpm_msg[i] = tpm_tis_i2c_readb(0, TPM_I2C_REG_DATA_FIFO);
586 sts = tpm_tis_i2c_readl(0, TPM_I2C_REG_STS);
587 DPRINTF_STS;
588 if (sts & TPM_TIS_STS_DATA_AVAILABLE) {
589 g_assert_cmpint((sts >> 8) & 0xffff, ==, --bcount);
590 }
591 }
592 g_assert_cmpmem(tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_msg));
593
594 /* relinquish use of locality 0 */
595 tpm_tis_i2c_writeb(0,
596 TPM_I2C_REG_ACCESS, TPM_TIS_ACCESS_ACTIVE_LOCALITY);
597 access = tpm_tis_i2c_readb(0, TPM_I2C_REG_ACCESS);
598 }
599
600 int main(int argc, char **argv)
601 {
602 int ret;
603 char *args;
604 char *tmp_path = g_dir_make_tmp("qemu-tpm-tis-i2c-test.XXXXXX", NULL);
605 GThread *thread;
606 TPMTestState test;
607
608 module_call_init(MODULE_INIT_QOM);
609 g_test_init(&argc, &argv, NULL);
610
611 test.addr = g_new0(SocketAddress, 1);
612 test.addr->type = SOCKET_ADDRESS_TYPE_UNIX;
613 test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL);
614 g_mutex_init(&test.data_mutex);
615 g_cond_init(&test.data_cond);
616 test.data_cond_signal = false;
617 test.tpm_version = TPM_VERSION_2_0;
618
619 thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test);
620 tpm_emu_test_wait_cond(&test);
621
622 aspeed_bus_addr = ast2600_i2c_calc_bus_addr(I2C_DEV_BUS_NUM);
623
624 args = g_strdup_printf(
625 "-machine rainier-bmc -accel tcg "
626 "-chardev socket,id=chr,path=%s "
627 "-tpmdev emulator,id=tpm0,chardev=chr "
628 "-device tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.%d,address=0x%x",
629 test.addr->u.q_unix.path,
630 I2C_DEV_BUS_NUM,
631 I2C_SLAVE_ADDR);
632 qtest_start(args);
633
634 qtest_add_data_func("/tpm-tis-i2c/test_basic", &test,
635 tpm_tis_i2c_test_basic);
636
637 qtest_add_data_func("/tpm-tis-i2c/test_check_localities", &test,
638 tpm_tis_i2c_test_check_localities);
639
640 qtest_add_data_func("/tpm-tis-i2c/check_access_reg", &test,
641 tpm_tis_i2c_test_check_access_reg);
642
643 qtest_add_data_func("/tpm-tis-i2c/check_access_reg_seize", &test,
644 tpm_tis_i2c_test_check_access_reg_seize);
645
646 qtest_add_data_func("/tpm-tis-i2c/check_access_reg_release", &test,
647 tpm_tis_i2c_test_check_access_reg_release);
648
649 qtest_add_data_func("/tpm-tis-i2c/test_check_transmit", &test,
650 tpm_tis_i2c_test_check_transmit);
651
652 ret = g_test_run();
653
654 qtest_end();
655
656 g_thread_join(thread);
657 g_unlink(test.addr->u.q_unix.path);
658 qapi_free_SocketAddress(test.addr);
659 g_rmdir(tmp_path);
660 g_free(tmp_path);
661 g_free(args);
662 return ret;
663 }
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