tests/qtest/pnv-xscom-test.c

   1 /*
   2  * QTest testcase for PowerNV XSCOM bus
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or
   7  * later. See the COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10
  11 #include "libqtest.h"
  12
  13 typedef enum PnvChipType {
  14     PNV_CHIP_POWER8E,     /* AKA Murano (default) */
  15     PNV_CHIP_POWER8,      /* AKA Venice */
  16     PNV_CHIP_POWER8NVL,   /* AKA Naples */
  17     PNV_CHIP_POWER9,      /* AKA Nimbus */
  18     PNV_CHIP_POWER10,
  19 } PnvChipType;
  20
  21 typedef struct PnvChip {
  22     PnvChipType chip_type;
  23     const char *cpu_model;
  24     uint64_t    xscom_base;
  25     uint64_t    cfam_id;
  26     uint32_t    first_core;
  27 } PnvChip;
  28
  29 static const PnvChip pnv_chips[] = {
  30     {
  31         .chip_type  = PNV_CHIP_POWER8,
  32         .cpu_model  = "POWER8",
  33         .xscom_base = 0x0003fc0000000000ull,
  34         .cfam_id    = 0x220ea04980000000ull,
  35         .first_core = 0x1,
  36     }, {
  37         .chip_type  = PNV_CHIP_POWER8NVL,
  38         .cpu_model  = "POWER8NVL",
  39         .xscom_base = 0x0003fc0000000000ull,
  40         .cfam_id    = 0x120d304980000000ull,
  41         .first_core = 0x1,
  42     },
  43     {
  44         .chip_type  = PNV_CHIP_POWER9,
  45         .cpu_model  = "POWER9",
  46         .xscom_base = 0x000603fc00000000ull,
  47         .cfam_id    = 0x220d104900008000ull,
  48         .first_core = 0x0,
  49     },
  50     {
  51         .chip_type  = PNV_CHIP_POWER10,
  52         .cpu_model  = "POWER10",
  53         .xscom_base = 0x000603fc00000000ull,
  54         .cfam_id    = 0x120da04900008000ull,
  55         .first_core = 0x0,
  56     },
  57 };
  58
  59 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
  60 {
  61     uint64_t addr = chip->xscom_base;
  62
  63     if (chip->chip_type == PNV_CHIP_POWER10) {
  64         addr |= ((uint64_t) pcba << 3);
  65     } else if (chip->chip_type == PNV_CHIP_POWER9) {
  66         addr |= ((uint64_t) pcba << 3);
  67     } else {
  68         addr |= (((uint64_t) pcba << 4) & ~0xffull) |
  69             (((uint64_t) pcba << 3) & 0x78);
  70     }
  71     return addr;
  72 }
  73
  74 static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip,
  75                                uint32_t pcba)
  76 {
  77     return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
  78 }
  79
  80 static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip)
  81 {
  82     uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f);
  83
  84     g_assert_cmphex(f000f, ==, chip->cfam_id);
  85 }
  86
  87 static void test_cfam_id(const void *data)
  88 {
  89     const PnvChip *chip = data;
  90     const char *machine = "powernv8";
  91     QTestState *qts;
  92
  93     if (chip->chip_type == PNV_CHIP_POWER9) {
  94         machine = "powernv9";
  95     } else if (chip->chip_type == PNV_CHIP_POWER10) {
  96         machine = "powernv10";
  97     }
  98
  99     qts = qtest_initf("-M %s -accel tcg -cpu %s",
 100                       machine, chip->cpu_model);
 101     test_xscom_cfam_id(qts, chip);
 102     qtest_quit(qts);
 103 }
 104
 105
 106 #define PNV_XSCOM_EX_CORE_BASE    0x10000000ull
 107 #define PNV_XSCOM_EX_BASE(core) \
 108     (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
 109 #define PNV_XSCOM_P9_EC_BASE(core) \
 110     ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
 111 #define PNV_XSCOM_P10_EC_BASE(core) \
 112     ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \
 113      (0x1000 << (3 - (core & 0x3))))
 114
 115 #define PNV_XSCOM_EX_DTS_RESULT0     0x50000
 116
 117 static void test_xscom_core(QTestState *qts, const PnvChip *chip)
 118 {
 119     if (chip->chip_type == PNV_CHIP_POWER10) {
 120         uint32_t first_core_thread_state =
 121                  PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412;
 122         uint64_t thread_state;
 123
 124         thread_state = pnv_xscom_read(qts, chip, first_core_thread_state);
 125
 126         g_assert_cmphex(thread_state, ==, 0);
 127     } else {
 128         uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
 129         uint64_t dts0;
 130
 131         if (chip->chip_type == PNV_CHIP_POWER9) {
 132             first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
 133         } else { /* POWER8 */
 134             first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
 135         }
 136
 137         dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
 138
 139         g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
 140     }
 141 }
 142
 143 static void test_core(const void *data)
 144 {
 145     const PnvChip *chip = data;
 146     QTestState *qts;
 147     const char *machine = "powernv8";
 148
 149     if (chip->chip_type == PNV_CHIP_POWER9) {
 150         machine = "powernv9";
 151     } else if (chip->chip_type == PNV_CHIP_POWER10) {
 152         machine = "powernv10";
 153     }
 154
 155     qts = qtest_initf("-M %s -accel tcg -cpu %s",
 156                       machine, chip->cpu_model);
 157     test_xscom_core(qts, chip);
 158     qtest_quit(qts);
 159 }
 160
 161 static void add_test(const char *name, void (*test)(const void *data))
 162 {
 163     int i;
 164
 165     for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
 166         char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
 167                                       pnv_chips[i].cpu_model);
 168         qtest_add_data_func(tname, &pnv_chips[i], test);
 169         g_free(tname);
 170     }
 171 }
 172
 173 int main(int argc, char **argv)
 174 {
 175     g_test_init(&argc, &argv, NULL);
 176
 177     add_test("cfam_id", test_cfam_id);
 178     add_test("core", test_core);
 179     return g_test_run();
 180 }