PPC: openpic_kvm: Filter memory events properly
[qemu/kevin.git] / hw / intc / openpic_kvm.c
blob6635407b8beb9ef364ff412acea344eed23830f6
1 /*
2 * KVM in-kernel OpenPIC
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include <sys/ioctl.h>
26 #include "exec/address-spaces.h"
27 #include "hw/hw.h"
28 #include "hw/ppc/openpic.h"
29 #include "hw/pci/msi.h"
30 #include "hw/sysbus.h"
31 #include "sysemu/kvm.h"
32 #include "qemu/log.h"
34 #define KVM_OPENPIC(obj) \
35 OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
37 typedef struct KVMOpenPICState {
38 /*< private >*/
39 SysBusDevice parent_obj;
40 /*< public >*/
42 MemoryRegion mem;
43 MemoryListener mem_listener;
44 uint32_t fd;
45 uint32_t model;
46 } KVMOpenPICState;
48 static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
50 kvm_set_irq(kvm_state, n_IRQ, level);
53 static void kvm_openpic_reset(DeviceState *d)
55 qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__);
58 static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
59 unsigned size)
61 KVMOpenPICState *opp = opaque;
62 struct kvm_device_attr attr;
63 uint32_t val32 = val;
64 int ret;
66 attr.group = KVM_DEV_MPIC_GRP_REGISTER;
67 attr.attr = addr;
68 attr.addr = (uint64_t)(unsigned long)&val32;
70 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
71 if (ret < 0) {
72 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
73 strerror(errno), attr.attr);
77 static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
79 KVMOpenPICState *opp = opaque;
80 struct kvm_device_attr attr;
81 uint32_t val = 0xdeadbeef;
82 int ret;
84 attr.group = KVM_DEV_MPIC_GRP_REGISTER;
85 attr.attr = addr;
86 attr.addr = (uint64_t)(unsigned long)&val;
88 ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
89 if (ret < 0) {
90 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
91 strerror(errno), attr.attr);
92 return 0;
95 return val;
98 static const MemoryRegionOps kvm_openpic_mem_ops = {
99 .write = kvm_openpic_write,
100 .read = kvm_openpic_read,
101 .endianness = DEVICE_BIG_ENDIAN,
102 .impl = {
103 .min_access_size = 4,
104 .max_access_size = 4,
108 static void kvm_openpic_region_add(MemoryListener *listener,
109 MemoryRegionSection *section)
111 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
112 mem_listener);
113 struct kvm_device_attr attr;
114 uint64_t reg_base;
115 int ret;
117 if (section->address_space != &address_space_memory) {
118 abort();
121 /* Ignore events on regions that are not us */
122 if (section->mr != &opp->mem) {
123 return;
126 reg_base = section->offset_within_address_space;
128 attr.group = KVM_DEV_MPIC_GRP_MISC;
129 attr.attr = KVM_DEV_MPIC_BASE_ADDR;
130 attr.addr = (uint64_t)(unsigned long)&reg_base;
132 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
133 if (ret < 0) {
134 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
135 strerror(errno), reg_base);
139 static void kvm_openpic_region_del(MemoryListener *listener,
140 MemoryRegionSection *section)
142 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
143 mem_listener);
144 struct kvm_device_attr attr;
145 uint64_t reg_base = 0;
146 int ret;
148 /* Ignore events on regions that are not us */
149 if (section->mr != &opp->mem) {
150 return;
153 attr.group = KVM_DEV_MPIC_GRP_MISC;
154 attr.attr = KVM_DEV_MPIC_BASE_ADDR;
155 attr.addr = (uint64_t)(unsigned long)&reg_base;
157 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
158 if (ret < 0) {
159 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
160 strerror(errno), reg_base);
164 static void kvm_openpic_init(Object *obj)
166 KVMOpenPICState *opp = KVM_OPENPIC(obj);
168 memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
169 "kvm-openpic", 0x40000);
172 static void kvm_openpic_realize(DeviceState *dev, Error **errp)
174 SysBusDevice *d = SYS_BUS_DEVICE(dev);
175 KVMOpenPICState *opp = KVM_OPENPIC(dev);
176 KVMState *s = kvm_state;
177 int kvm_openpic_model;
178 struct kvm_create_device cd = {0};
179 int ret, i;
181 if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
182 error_setg(errp, "Kernel is lacking Device Control API");
183 return;
186 switch (opp->model) {
187 case OPENPIC_MODEL_FSL_MPIC_20:
188 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
189 break;
191 case OPENPIC_MODEL_FSL_MPIC_42:
192 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
193 break;
195 default:
196 error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
197 return;
200 cd.type = kvm_openpic_model;
201 ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
202 if (ret < 0) {
203 error_setg(errp, "Can't create device %d: %s",
204 cd.type, strerror(errno));
205 return;
207 opp->fd = cd.fd;
209 sysbus_init_mmio(d, &opp->mem);
210 qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
212 opp->mem_listener.region_add = kvm_openpic_region_add;
213 opp->mem_listener.region_del = kvm_openpic_region_del;
214 memory_listener_register(&opp->mem_listener, &address_space_memory);
216 /* indicate pic capabilities */
217 msi_supported = true;
218 kvm_kernel_irqchip = true;
219 kvm_async_interrupts_allowed = true;
221 /* set up irq routing */
222 kvm_init_irq_routing(kvm_state);
223 for (i = 0; i < 256; ++i) {
224 kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
227 kvm_irqfds_allowed = true;
228 kvm_msi_via_irqfd_allowed = true;
229 kvm_gsi_routing_allowed = true;
231 kvm_irqchip_commit_routes(s);
234 int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
236 KVMOpenPICState *opp = KVM_OPENPIC(d);
237 struct kvm_enable_cap encap = {};
239 encap.cap = KVM_CAP_IRQ_MPIC;
240 encap.args[0] = opp->fd;
241 encap.args[1] = kvm_arch_vcpu_id(cs);
243 return kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);
246 static Property kvm_openpic_properties[] = {
247 DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
248 OPENPIC_MODEL_FSL_MPIC_20),
249 DEFINE_PROP_END_OF_LIST(),
252 static void kvm_openpic_class_init(ObjectClass *oc, void *data)
254 DeviceClass *dc = DEVICE_CLASS(oc);
256 dc->realize = kvm_openpic_realize;
257 dc->props = kvm_openpic_properties;
258 dc->reset = kvm_openpic_reset;
261 static const TypeInfo kvm_openpic_info = {
262 .name = TYPE_KVM_OPENPIC,
263 .parent = TYPE_SYS_BUS_DEVICE,
264 .instance_size = sizeof(KVMOpenPICState),
265 .instance_init = kvm_openpic_init,
266 .class_init = kvm_openpic_class_init,
269 static void kvm_openpic_register_types(void)
271 type_register_static(&kvm_openpic_info);
274 type_init(kvm_openpic_register_types)