2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/arch_init.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/cpu/icc_bus.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
53 /* Cache topology CPUID constants: */
55 /* CPUID Leaf 2 Descriptors */
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
62 /* CPUID Leaf 4 constants: */
65 #define CPUID_4_TYPE_DCACHE 1
66 #define CPUID_4_TYPE_ICACHE 2
67 #define CPUID_4_TYPE_UNIFIED 3
69 #define CPUID_4_LEVEL(l) ((l) << 5)
71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72 #define CPUID_4_FULLY_ASSOC (1 << 9)
75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
76 #define CPUID_4_INCLUSIVE (1 << 1)
77 #define CPUID_4_COMPLEX_IDX (1 << 2)
79 #define ASSOC_FULL 0xFF
81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
96 /* Definitions of the hardcoded cache entries we expose: */
99 #define L1D_LINE_SIZE 64
100 #define L1D_ASSOCIATIVITY 8
102 #define L1D_PARTITIONS 1
103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106 #define L1D_LINES_PER_TAG 1
107 #define L1D_SIZE_KB_AMD 64
108 #define L1D_ASSOCIATIVITY_AMD 2
110 /* L1 instruction cache: */
111 #define L1I_LINE_SIZE 64
112 #define L1I_ASSOCIATIVITY 8
114 #define L1I_PARTITIONS 1
115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118 #define L1I_LINES_PER_TAG 1
119 #define L1I_SIZE_KB_AMD 64
120 #define L1I_ASSOCIATIVITY_AMD 2
122 /* Level 2 unified cache: */
123 #define L2_LINE_SIZE 64
124 #define L2_ASSOCIATIVITY 16
126 #define L2_PARTITIONS 1
127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131 #define L2_LINES_PER_TAG 1
132 #define L2_SIZE_KB_AMD 512
135 #define L3_SIZE_KB 0 /* disabled */
136 #define L3_ASSOCIATIVITY 0 /* disabled */
137 #define L3_LINES_PER_TAG 0 /* disabled */
138 #define L3_LINE_SIZE 0 /* disabled */
140 /* TLB definitions: */
142 #define L1_DTLB_2M_ASSOC 1
143 #define L1_DTLB_2M_ENTRIES 255
144 #define L1_DTLB_4K_ASSOC 1
145 #define L1_DTLB_4K_ENTRIES 255
147 #define L1_ITLB_2M_ASSOC 1
148 #define L1_ITLB_2M_ENTRIES 255
149 #define L1_ITLB_4K_ASSOC 1
150 #define L1_ITLB_4K_ENTRIES 255
152 #define L2_DTLB_2M_ASSOC 0 /* disabled */
153 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
154 #define L2_DTLB_4K_ASSOC 4
155 #define L2_DTLB_4K_ENTRIES 512
157 #define L2_ITLB_2M_ASSOC 0 /* disabled */
158 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
159 #define L2_ITLB_4K_ASSOC 4
160 #define L2_ITLB_4K_ENTRIES 512
164 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
165 uint32_t vendor2
, uint32_t vendor3
)
168 for (i
= 0; i
< 4; i
++) {
169 dst
[i
] = vendor1
>> (8 * i
);
170 dst
[i
+ 4] = vendor2
>> (8 * i
);
171 dst
[i
+ 8] = vendor3
>> (8 * i
);
173 dst
[CPUID_VENDOR_SZ
] = '\0';
176 /* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
180 static const char *feature_name
[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL
, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190 static const char *ext_feature_name
[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL
,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL
, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
200 /* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
205 static const char *ext2_feature_name
[] = {
206 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
207 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
208 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
209 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
210 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
211 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
212 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL
, "lm|i64", "3dnowext", "3dnow",
215 static const char *ext3_feature_name
[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL
, "lwp",
220 "fma4", "tce", NULL
, "nodeid_msr",
221 NULL
, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL
, NULL
, NULL
,
223 NULL
, NULL
, NULL
, NULL
,
226 static const char *ext4_feature_name
[] = {
227 NULL
, NULL
, "xstore", "xstore-en",
228 NULL
, NULL
, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL
, NULL
,
231 NULL
, NULL
, NULL
, NULL
,
232 NULL
, NULL
, NULL
, NULL
,
233 NULL
, NULL
, NULL
, NULL
,
234 NULL
, NULL
, NULL
, NULL
,
237 static const char *kvm_feature_name
[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL
, NULL
, NULL
, NULL
,
241 NULL
, NULL
, NULL
, NULL
,
242 NULL
, NULL
, NULL
, NULL
,
243 NULL
, NULL
, NULL
, NULL
,
244 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
245 NULL
, NULL
, NULL
, NULL
,
248 static const char *svm_feature_name
[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL
, NULL
, "pause_filter", NULL
,
252 "pfthreshold", NULL
, NULL
, NULL
,
253 NULL
, NULL
, NULL
, NULL
,
254 NULL
, NULL
, NULL
, NULL
,
255 NULL
, NULL
, NULL
, NULL
,
256 NULL
, NULL
, NULL
, NULL
,
259 static const char *cpuid_7_0_ebx_feature_name
[] = {
260 "fsgsbase", "tsc_adjust", NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, "mpx", NULL
,
262 "avx512f", NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
263 NULL
, NULL
, "avx512pf", "avx512er", "avx512cd", NULL
, NULL
, NULL
,
266 static const char *cpuid_apm_edx_feature_name
[] = {
267 NULL
, NULL
, NULL
, NULL
,
268 NULL
, NULL
, NULL
, NULL
,
269 "invtsc", NULL
, NULL
, NULL
,
270 NULL
, NULL
, NULL
, NULL
,
271 NULL
, NULL
, NULL
, NULL
,
272 NULL
, NULL
, NULL
, NULL
,
273 NULL
, NULL
, NULL
, NULL
,
274 NULL
, NULL
, NULL
, NULL
,
277 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
278 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
279 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
280 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
281 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
282 CPUID_PSE36 | CPUID_FXSR)
283 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
284 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
285 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
286 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
287 CPUID_PAE | CPUID_SEP | CPUID_APIC)
289 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
290 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
291 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
292 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
293 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
294 /* partly implemented:
295 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
297 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
298 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
299 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
300 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
301 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
303 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
304 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
305 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
306 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
307 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
311 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
313 #define TCG_EXT2_X86_64_FEATURES 0
316 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
317 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
318 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
319 TCG_EXT2_X86_64_FEATURES)
320 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
321 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
322 #define TCG_EXT4_FEATURES 0
323 #define TCG_SVM_FEATURES 0
324 #define TCG_KVM_FEATURES 0
325 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
326 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
328 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
329 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
330 CPUID_7_0_EBX_RDSEED */
331 #define TCG_APM_FEATURES 0
334 typedef struct FeatureWordInfo
{
335 const char **feat_names
;
336 uint32_t cpuid_eax
; /* Input EAX for CPUID */
337 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
338 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
339 int cpuid_reg
; /* output register (R_* constant) */
340 uint32_t tcg_features
; /* Feature flags supported by TCG */
341 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
344 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
346 .feat_names
= feature_name
,
347 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
348 .tcg_features
= TCG_FEATURES
,
351 .feat_names
= ext_feature_name
,
352 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
353 .tcg_features
= TCG_EXT_FEATURES
,
355 [FEAT_8000_0001_EDX
] = {
356 .feat_names
= ext2_feature_name
,
357 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
358 .tcg_features
= TCG_EXT2_FEATURES
,
360 [FEAT_8000_0001_ECX
] = {
361 .feat_names
= ext3_feature_name
,
362 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
363 .tcg_features
= TCG_EXT3_FEATURES
,
365 [FEAT_C000_0001_EDX
] = {
366 .feat_names
= ext4_feature_name
,
367 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
368 .tcg_features
= TCG_EXT4_FEATURES
,
371 .feat_names
= kvm_feature_name
,
372 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
373 .tcg_features
= TCG_KVM_FEATURES
,
376 .feat_names
= svm_feature_name
,
377 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
378 .tcg_features
= TCG_SVM_FEATURES
,
381 .feat_names
= cpuid_7_0_ebx_feature_name
,
383 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
385 .tcg_features
= TCG_7_0_EBX_FEATURES
,
387 [FEAT_8000_0007_EDX
] = {
388 .feat_names
= cpuid_apm_edx_feature_name
,
389 .cpuid_eax
= 0x80000007,
391 .tcg_features
= TCG_APM_FEATURES
,
392 .unmigratable_flags
= CPUID_APM_INVTSC
,
396 typedef struct X86RegisterInfo32
{
397 /* Name of register */
399 /* QAPI enum value register */
400 X86CPURegister32 qapi_enum
;
403 #define REGISTER(reg) \
404 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
405 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
417 typedef struct ExtSaveArea
{
418 uint32_t feature
, bits
;
419 uint32_t offset
, size
;
422 static const ExtSaveArea ext_save_areas
[] = {
423 [2] = { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
424 .offset
= 0x240, .size
= 0x100 },
425 [3] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
426 .offset
= 0x3c0, .size
= 0x40 },
427 [4] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
428 .offset
= 0x400, .size
= 0x40 },
429 [5] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
430 .offset
= 0x440, .size
= 0x40 },
431 [6] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
432 .offset
= 0x480, .size
= 0x200 },
433 [7] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
434 .offset
= 0x680, .size
= 0x400 },
437 const char *get_register_name_32(unsigned int reg
)
439 if (reg
>= CPU_NB_REGS32
) {
442 return x86_reg_info_32
[reg
].name
;
445 /* KVM-specific features that are automatically added to all CPU models
446 * when KVM is enabled.
448 static uint32_t kvm_default_features
[FEATURE_WORDS
] = {
449 [FEAT_KVM
] = (1 << KVM_FEATURE_CLOCKSOURCE
) |
450 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
451 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
452 (1 << KVM_FEATURE_ASYNC_PF
) |
453 (1 << KVM_FEATURE_STEAL_TIME
) |
454 (1 << KVM_FEATURE_PV_EOI
) |
455 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
),
456 [FEAT_1_ECX
] = CPUID_EXT_X2APIC
,
459 /* Features that are not added by default to any CPU model when KVM is enabled.
461 static uint32_t kvm_default_unset_features
[FEATURE_WORDS
] = {
462 [FEAT_1_EDX
] = CPUID_ACPI
,
463 [FEAT_1_ECX
] = CPUID_EXT_MONITOR
,
466 void x86_cpu_compat_kvm_no_autoenable(FeatureWord w
, uint32_t features
)
468 kvm_default_features
[w
] &= ~features
;
472 * Returns the set of feature flags that are supported and migratable by
473 * QEMU, for a given FeatureWord.
475 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
477 FeatureWordInfo
*wi
= &feature_word_info
[w
];
481 for (i
= 0; i
< 32; i
++) {
482 uint32_t f
= 1U << i
;
483 /* If the feature name is unknown, it is not supported by QEMU yet */
484 if (!wi
->feat_names
[i
]) {
487 /* Skip features known to QEMU, but explicitly marked as unmigratable */
488 if (wi
->unmigratable_flags
& f
) {
496 void host_cpuid(uint32_t function
, uint32_t count
,
497 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
503 : "=a"(vec
[0]), "=b"(vec
[1]),
504 "=c"(vec
[2]), "=d"(vec
[3])
505 : "0"(function
), "c"(count
) : "cc");
506 #elif defined(__i386__)
507 asm volatile("pusha \n\t"
509 "mov %%eax, 0(%2) \n\t"
510 "mov %%ebx, 4(%2) \n\t"
511 "mov %%ecx, 8(%2) \n\t"
512 "mov %%edx, 12(%2) \n\t"
514 : : "a"(function
), "c"(count
), "S"(vec
)
530 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
532 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
533 * a substring. ex if !NULL points to the first char after a substring,
534 * otherwise the string is assumed to sized by a terminating nul.
535 * Return lexical ordering of *s1:*s2.
537 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
541 if (!*s1
|| !*s2
|| *s1
!= *s2
)
544 if (s1
== e1
&& s2
== e2
)
553 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
554 * '|' delimited (possibly empty) strings in which case search for a match
555 * within the alternatives proceeds left to right. Return 0 for success,
556 * non-zero otherwise.
558 static int altcmp(const char *s
, const char *e
, const char *altstr
)
562 for (q
= p
= altstr
; ; ) {
563 while (*p
&& *p
!= '|')
565 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
574 /* search featureset for flag *[s..e), if found set corresponding bit in
575 * *pval and return true, otherwise return false
577 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
578 const char **featureset
)
584 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
585 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
593 static void add_flagname_to_bitmaps(const char *flagname
,
594 FeatureWordArray words
,
598 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
599 FeatureWordInfo
*wi
= &feature_word_info
[w
];
600 if (wi
->feat_names
&&
601 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
605 if (w
== FEATURE_WORDS
) {
606 error_setg(errp
, "CPU feature %s not found", flagname
);
610 /* CPU class name definitions: */
612 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
613 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
615 /* Return type name for a given CPU model name
616 * Caller is responsible for freeing the returned string.
618 static char *x86_cpu_type_name(const char *model_name
)
620 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
623 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
628 if (cpu_model
== NULL
) {
632 typename
= x86_cpu_type_name(cpu_model
);
633 oc
= object_class_by_name(typename
);
638 struct X86CPUDefinition
{
643 /* vendor is zero-terminated, 12 character ASCII string */
644 char vendor
[CPUID_VENDOR_SZ
+ 1];
648 FeatureWordArray features
;
650 bool cache_info_passthrough
;
653 static X86CPUDefinition builtin_x86_defs
[] = {
657 .vendor
= CPUID_VENDOR_AMD
,
661 .features
[FEAT_1_EDX
] =
663 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
665 .features
[FEAT_1_ECX
] =
666 CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
667 .features
[FEAT_8000_0001_EDX
] =
668 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
669 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
670 .features
[FEAT_8000_0001_ECX
] =
671 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
672 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
673 .xlevel
= 0x8000000A,
678 .vendor
= CPUID_VENDOR_AMD
,
682 .features
[FEAT_1_EDX
] =
684 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
685 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
686 .features
[FEAT_1_ECX
] =
687 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
689 .features
[FEAT_8000_0001_EDX
] =
690 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
691 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
692 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
693 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
694 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
696 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
697 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
698 .features
[FEAT_8000_0001_ECX
] =
699 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
700 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
701 .features
[FEAT_SVM
] =
702 CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
703 .xlevel
= 0x8000001A,
704 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
709 .vendor
= CPUID_VENDOR_INTEL
,
713 .features
[FEAT_1_EDX
] =
715 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
716 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
717 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
718 .features
[FEAT_1_ECX
] =
719 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
720 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
721 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
722 .features
[FEAT_8000_0001_EDX
] =
723 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
724 .features
[FEAT_8000_0001_ECX
] =
726 .xlevel
= 0x80000008,
727 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
732 .vendor
= CPUID_VENDOR_INTEL
,
736 /* Missing: CPUID_VME, CPUID_HT */
737 .features
[FEAT_1_EDX
] =
739 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
741 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
742 .features
[FEAT_1_ECX
] =
743 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
744 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
745 .features
[FEAT_8000_0001_EDX
] =
746 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
747 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
748 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
749 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
750 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
751 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
752 .features
[FEAT_8000_0001_ECX
] =
754 .xlevel
= 0x80000008,
755 .model_id
= "Common KVM processor"
760 .vendor
= CPUID_VENDOR_INTEL
,
764 .features
[FEAT_1_EDX
] =
766 .features
[FEAT_1_ECX
] =
767 CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
768 .xlevel
= 0x80000004,
773 .vendor
= CPUID_VENDOR_INTEL
,
777 .features
[FEAT_1_EDX
] =
779 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
780 .features
[FEAT_1_ECX
] =
782 .features
[FEAT_8000_0001_EDX
] =
783 PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
784 .features
[FEAT_8000_0001_ECX
] =
786 .xlevel
= 0x80000008,
787 .model_id
= "Common 32-bit KVM processor"
792 .vendor
= CPUID_VENDOR_INTEL
,
796 .features
[FEAT_1_EDX
] =
797 PPRO_FEATURES
| CPUID_VME
|
798 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
799 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
800 .features
[FEAT_1_ECX
] =
801 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
802 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
803 .features
[FEAT_8000_0001_EDX
] =
805 .xlevel
= 0x80000008,
806 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
811 .vendor
= CPUID_VENDOR_INTEL
,
815 .features
[FEAT_1_EDX
] =
822 .vendor
= CPUID_VENDOR_INTEL
,
826 .features
[FEAT_1_EDX
] =
833 .vendor
= CPUID_VENDOR_INTEL
,
837 .features
[FEAT_1_EDX
] =
844 .vendor
= CPUID_VENDOR_INTEL
,
848 .features
[FEAT_1_EDX
] =
855 .vendor
= CPUID_VENDOR_AMD
,
859 .features
[FEAT_1_EDX
] =
860 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
862 .features
[FEAT_8000_0001_EDX
] =
863 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
864 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
865 .xlevel
= 0x80000008,
869 /* original is on level 10 */
871 .vendor
= CPUID_VENDOR_INTEL
,
875 .features
[FEAT_1_EDX
] =
877 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
878 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
879 /* Some CPUs got no CPUID_SEP */
880 .features
[FEAT_1_ECX
] =
881 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
882 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
|
884 .features
[FEAT_8000_0001_EDX
] =
885 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
887 .features
[FEAT_8000_0001_ECX
] =
889 .xlevel
= 0x8000000A,
890 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
895 .vendor
= CPUID_VENDOR_INTEL
,
899 .features
[FEAT_1_EDX
] =
900 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
901 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
902 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
903 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
904 CPUID_DE
| CPUID_FP87
,
905 .features
[FEAT_1_ECX
] =
906 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
907 .features
[FEAT_8000_0001_EDX
] =
908 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
909 .features
[FEAT_8000_0001_ECX
] =
911 .xlevel
= 0x8000000A,
912 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
917 .vendor
= CPUID_VENDOR_INTEL
,
921 .features
[FEAT_1_EDX
] =
922 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
923 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
924 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
925 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
926 CPUID_DE
| CPUID_FP87
,
927 .features
[FEAT_1_ECX
] =
928 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
930 .features
[FEAT_8000_0001_EDX
] =
931 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
932 .features
[FEAT_8000_0001_ECX
] =
934 .xlevel
= 0x8000000A,
935 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
940 .vendor
= CPUID_VENDOR_INTEL
,
944 .features
[FEAT_1_EDX
] =
945 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
946 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
947 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
948 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
949 CPUID_DE
| CPUID_FP87
,
950 .features
[FEAT_1_ECX
] =
951 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
952 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
953 .features
[FEAT_8000_0001_EDX
] =
954 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
955 .features
[FEAT_8000_0001_ECX
] =
957 .xlevel
= 0x8000000A,
958 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
963 .vendor
= CPUID_VENDOR_INTEL
,
967 .features
[FEAT_1_EDX
] =
968 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
969 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
970 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
971 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
972 CPUID_DE
| CPUID_FP87
,
973 .features
[FEAT_1_ECX
] =
974 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
975 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
976 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
977 .features
[FEAT_8000_0001_EDX
] =
978 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
979 .features
[FEAT_8000_0001_ECX
] =
981 .xlevel
= 0x8000000A,
982 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
985 .name
= "SandyBridge",
987 .vendor
= CPUID_VENDOR_INTEL
,
991 .features
[FEAT_1_EDX
] =
992 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
993 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
994 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
995 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
996 CPUID_DE
| CPUID_FP87
,
997 .features
[FEAT_1_ECX
] =
998 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
999 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1000 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1001 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1003 .features
[FEAT_8000_0001_EDX
] =
1004 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1006 .features
[FEAT_8000_0001_ECX
] =
1008 .xlevel
= 0x8000000A,
1009 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1014 .vendor
= CPUID_VENDOR_INTEL
,
1018 .features
[FEAT_1_EDX
] =
1019 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1020 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1021 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1022 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1023 CPUID_DE
| CPUID_FP87
,
1024 .features
[FEAT_1_ECX
] =
1025 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1026 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1027 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1028 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1029 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1031 .features
[FEAT_8000_0001_EDX
] =
1032 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1034 .features
[FEAT_8000_0001_ECX
] =
1036 .features
[FEAT_7_0_EBX
] =
1037 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1038 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1039 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1041 .xlevel
= 0x8000000A,
1042 .model_id
= "Intel Core Processor (Haswell)",
1045 .name
= "Broadwell",
1047 .vendor
= CPUID_VENDOR_INTEL
,
1051 .features
[FEAT_1_EDX
] =
1052 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1053 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1054 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1055 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1056 CPUID_DE
| CPUID_FP87
,
1057 .features
[FEAT_1_ECX
] =
1058 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1059 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1060 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1061 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1062 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1064 .features
[FEAT_8000_0001_EDX
] =
1065 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1067 .features
[FEAT_8000_0001_ECX
] =
1068 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1069 .features
[FEAT_7_0_EBX
] =
1070 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1071 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1072 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1073 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1075 .xlevel
= 0x8000000A,
1076 .model_id
= "Intel Core Processor (Broadwell)",
1079 .name
= "Opteron_G1",
1081 .vendor
= CPUID_VENDOR_AMD
,
1085 .features
[FEAT_1_EDX
] =
1086 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1087 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1088 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1089 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1090 CPUID_DE
| CPUID_FP87
,
1091 .features
[FEAT_1_ECX
] =
1093 .features
[FEAT_8000_0001_EDX
] =
1094 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1095 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1096 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1097 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1098 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1099 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1100 .xlevel
= 0x80000008,
1101 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1104 .name
= "Opteron_G2",
1106 .vendor
= CPUID_VENDOR_AMD
,
1110 .features
[FEAT_1_EDX
] =
1111 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1112 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1113 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1114 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1115 CPUID_DE
| CPUID_FP87
,
1116 .features
[FEAT_1_ECX
] =
1117 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1118 .features
[FEAT_8000_0001_EDX
] =
1119 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1120 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1121 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1122 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1123 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1124 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1125 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1126 .features
[FEAT_8000_0001_ECX
] =
1127 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1128 .xlevel
= 0x80000008,
1129 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1132 .name
= "Opteron_G3",
1134 .vendor
= CPUID_VENDOR_AMD
,
1138 .features
[FEAT_1_EDX
] =
1139 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1140 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1141 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1142 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1143 CPUID_DE
| CPUID_FP87
,
1144 .features
[FEAT_1_ECX
] =
1145 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1147 .features
[FEAT_8000_0001_EDX
] =
1148 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1149 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1150 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1151 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1152 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1153 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1154 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1155 .features
[FEAT_8000_0001_ECX
] =
1156 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1157 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1158 .xlevel
= 0x80000008,
1159 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1162 .name
= "Opteron_G4",
1164 .vendor
= CPUID_VENDOR_AMD
,
1168 .features
[FEAT_1_EDX
] =
1169 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1170 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1171 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1172 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1173 CPUID_DE
| CPUID_FP87
,
1174 .features
[FEAT_1_ECX
] =
1175 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1176 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1177 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1179 .features
[FEAT_8000_0001_EDX
] =
1180 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1181 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1182 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1183 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1184 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1185 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1186 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1187 .features
[FEAT_8000_0001_ECX
] =
1188 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1189 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1190 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1192 .xlevel
= 0x8000001A,
1193 .model_id
= "AMD Opteron 62xx class CPU",
1196 .name
= "Opteron_G5",
1198 .vendor
= CPUID_VENDOR_AMD
,
1202 .features
[FEAT_1_EDX
] =
1203 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1204 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1205 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1206 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1207 CPUID_DE
| CPUID_FP87
,
1208 .features
[FEAT_1_ECX
] =
1209 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1210 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1211 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1212 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1213 .features
[FEAT_8000_0001_EDX
] =
1214 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1215 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1216 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1217 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1218 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1219 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1220 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1221 .features
[FEAT_8000_0001_ECX
] =
1222 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1223 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1224 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1226 .xlevel
= 0x8000001A,
1227 .model_id
= "AMD Opteron 63xx class CPU",
1232 * x86_cpu_compat_set_features:
1233 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1234 * @w: Identifies the feature word to be changed.
1235 * @feat_add: Feature bits to be added to feature word
1236 * @feat_remove: Feature bits to be removed from feature word
1238 * Change CPU model feature bits for compatibility.
1240 * This function may be used by machine-type compatibility functions
1241 * to enable or disable feature bits on specific CPU models.
1243 void x86_cpu_compat_set_features(const char *cpu_model
, FeatureWord w
,
1244 uint32_t feat_add
, uint32_t feat_remove
)
1246 X86CPUDefinition
*def
;
1248 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1249 def
= &builtin_x86_defs
[i
];
1250 if (!cpu_model
|| !strcmp(cpu_model
, def
->name
)) {
1251 def
->features
[w
] |= feat_add
;
1252 def
->features
[w
] &= ~feat_remove
;
1257 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1258 bool migratable_only
);
1262 static int cpu_x86_fill_model_id(char *str
)
1264 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1267 for (i
= 0; i
< 3; i
++) {
1268 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1269 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1270 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1271 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1272 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1277 static X86CPUDefinition host_cpudef
;
1279 static Property host_x86_cpu_properties
[] = {
1280 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1281 DEFINE_PROP_END_OF_LIST()
1284 /* class_init for the "host" CPU model
1286 * This function may be called before KVM is initialized.
1288 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1290 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1291 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1292 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1294 xcc
->kvm_required
= true;
1296 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1297 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1299 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1300 host_cpudef
.family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1301 host_cpudef
.model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1302 host_cpudef
.stepping
= eax
& 0x0F;
1304 cpu_x86_fill_model_id(host_cpudef
.model_id
);
1306 xcc
->cpu_def
= &host_cpudef
;
1307 host_cpudef
.cache_info_passthrough
= true;
1309 /* level, xlevel, xlevel2, and the feature words are initialized on
1310 * instance_init, because they require KVM to be initialized.
1313 dc
->props
= host_x86_cpu_properties
;
1316 static void host_x86_cpu_initfn(Object
*obj
)
1318 X86CPU
*cpu
= X86_CPU(obj
);
1319 CPUX86State
*env
= &cpu
->env
;
1320 KVMState
*s
= kvm_state
;
1322 assert(kvm_enabled());
1324 /* We can't fill the features array here because we don't know yet if
1325 * "migratable" is true or false.
1327 cpu
->host_features
= true;
1329 env
->cpuid_level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1330 env
->cpuid_xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1331 env
->cpuid_xlevel2
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1333 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1336 static const TypeInfo host_x86_cpu_type_info
= {
1337 .name
= X86_CPU_TYPE_NAME("host"),
1338 .parent
= TYPE_X86_CPU
,
1339 .instance_init
= host_x86_cpu_initfn
,
1340 .class_init
= host_x86_cpu_class_init
,
1345 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1347 FeatureWordInfo
*f
= &feature_word_info
[w
];
1350 for (i
= 0; i
< 32; ++i
) {
1351 if (1 << i
& mask
) {
1352 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1354 fprintf(stderr
, "warning: %s doesn't support requested feature: "
1355 "CPUID.%02XH:%s%s%s [bit %d]\n",
1356 kvm_enabled() ? "host" : "TCG",
1358 f
->feat_names
[i
] ? "." : "",
1359 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1364 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1365 const char *name
, Error
**errp
)
1367 X86CPU
*cpu
= X86_CPU(obj
);
1368 CPUX86State
*env
= &cpu
->env
;
1371 value
= (env
->cpuid_version
>> 8) & 0xf;
1373 value
+= (env
->cpuid_version
>> 20) & 0xff;
1375 visit_type_int(v
, &value
, name
, errp
);
1378 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1379 const char *name
, Error
**errp
)
1381 X86CPU
*cpu
= X86_CPU(obj
);
1382 CPUX86State
*env
= &cpu
->env
;
1383 const int64_t min
= 0;
1384 const int64_t max
= 0xff + 0xf;
1385 Error
*local_err
= NULL
;
1388 visit_type_int(v
, &value
, name
, &local_err
);
1390 error_propagate(errp
, local_err
);
1393 if (value
< min
|| value
> max
) {
1394 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1395 name
? name
: "null", value
, min
, max
);
1399 env
->cpuid_version
&= ~0xff00f00;
1401 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1403 env
->cpuid_version
|= value
<< 8;
1407 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1408 const char *name
, Error
**errp
)
1410 X86CPU
*cpu
= X86_CPU(obj
);
1411 CPUX86State
*env
= &cpu
->env
;
1414 value
= (env
->cpuid_version
>> 4) & 0xf;
1415 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1416 visit_type_int(v
, &value
, name
, errp
);
1419 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1420 const char *name
, Error
**errp
)
1422 X86CPU
*cpu
= X86_CPU(obj
);
1423 CPUX86State
*env
= &cpu
->env
;
1424 const int64_t min
= 0;
1425 const int64_t max
= 0xff;
1426 Error
*local_err
= NULL
;
1429 visit_type_int(v
, &value
, name
, &local_err
);
1431 error_propagate(errp
, local_err
);
1434 if (value
< min
|| value
> max
) {
1435 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1436 name
? name
: "null", value
, min
, max
);
1440 env
->cpuid_version
&= ~0xf00f0;
1441 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1444 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1445 void *opaque
, const char *name
,
1448 X86CPU
*cpu
= X86_CPU(obj
);
1449 CPUX86State
*env
= &cpu
->env
;
1452 value
= env
->cpuid_version
& 0xf;
1453 visit_type_int(v
, &value
, name
, errp
);
1456 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1457 void *opaque
, const char *name
,
1460 X86CPU
*cpu
= X86_CPU(obj
);
1461 CPUX86State
*env
= &cpu
->env
;
1462 const int64_t min
= 0;
1463 const int64_t max
= 0xf;
1464 Error
*local_err
= NULL
;
1467 visit_type_int(v
, &value
, name
, &local_err
);
1469 error_propagate(errp
, local_err
);
1472 if (value
< min
|| value
> max
) {
1473 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1474 name
? name
: "null", value
, min
, max
);
1478 env
->cpuid_version
&= ~0xf;
1479 env
->cpuid_version
|= value
& 0xf;
1482 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1483 const char *name
, Error
**errp
)
1485 X86CPU
*cpu
= X86_CPU(obj
);
1487 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1490 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1491 const char *name
, Error
**errp
)
1493 X86CPU
*cpu
= X86_CPU(obj
);
1495 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1498 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1499 const char *name
, Error
**errp
)
1501 X86CPU
*cpu
= X86_CPU(obj
);
1503 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1506 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1507 const char *name
, Error
**errp
)
1509 X86CPU
*cpu
= X86_CPU(obj
);
1511 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1514 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1516 X86CPU
*cpu
= X86_CPU(obj
);
1517 CPUX86State
*env
= &cpu
->env
;
1520 value
= (char *)g_malloc(CPUID_VENDOR_SZ
+ 1);
1521 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1522 env
->cpuid_vendor3
);
1526 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1529 X86CPU
*cpu
= X86_CPU(obj
);
1530 CPUX86State
*env
= &cpu
->env
;
1533 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1534 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1539 env
->cpuid_vendor1
= 0;
1540 env
->cpuid_vendor2
= 0;
1541 env
->cpuid_vendor3
= 0;
1542 for (i
= 0; i
< 4; i
++) {
1543 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1544 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1545 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1549 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1551 X86CPU
*cpu
= X86_CPU(obj
);
1552 CPUX86State
*env
= &cpu
->env
;
1556 value
= g_malloc(48 + 1);
1557 for (i
= 0; i
< 48; i
++) {
1558 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1564 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1567 X86CPU
*cpu
= X86_CPU(obj
);
1568 CPUX86State
*env
= &cpu
->env
;
1571 if (model_id
== NULL
) {
1574 len
= strlen(model_id
);
1575 memset(env
->cpuid_model
, 0, 48);
1576 for (i
= 0; i
< 48; i
++) {
1580 c
= (uint8_t)model_id
[i
];
1582 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1586 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1587 const char *name
, Error
**errp
)
1589 X86CPU
*cpu
= X86_CPU(obj
);
1592 value
= cpu
->env
.tsc_khz
* 1000;
1593 visit_type_int(v
, &value
, name
, errp
);
1596 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1597 const char *name
, Error
**errp
)
1599 X86CPU
*cpu
= X86_CPU(obj
);
1600 const int64_t min
= 0;
1601 const int64_t max
= INT64_MAX
;
1602 Error
*local_err
= NULL
;
1605 visit_type_int(v
, &value
, name
, &local_err
);
1607 error_propagate(errp
, local_err
);
1610 if (value
< min
|| value
> max
) {
1611 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1612 name
? name
: "null", value
, min
, max
);
1616 cpu
->env
.tsc_khz
= value
/ 1000;
1619 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1620 const char *name
, Error
**errp
)
1622 X86CPU
*cpu
= X86_CPU(obj
);
1623 int64_t value
= cpu
->env
.cpuid_apic_id
;
1625 visit_type_int(v
, &value
, name
, errp
);
1628 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1629 const char *name
, Error
**errp
)
1631 X86CPU
*cpu
= X86_CPU(obj
);
1632 DeviceState
*dev
= DEVICE(obj
);
1633 const int64_t min
= 0;
1634 const int64_t max
= UINT32_MAX
;
1635 Error
*error
= NULL
;
1638 if (dev
->realized
) {
1639 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1640 "it was realized", name
, object_get_typename(obj
));
1644 visit_type_int(v
, &value
, name
, &error
);
1646 error_propagate(errp
, error
);
1649 if (value
< min
|| value
> max
) {
1650 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1651 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1652 object_get_typename(obj
), name
, value
, min
, max
);
1656 if ((value
!= cpu
->env
.cpuid_apic_id
) && cpu_exists(value
)) {
1657 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1660 cpu
->env
.cpuid_apic_id
= value
;
1663 /* Generic getter for "feature-words" and "filtered-features" properties */
1664 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
, void *opaque
,
1665 const char *name
, Error
**errp
)
1667 uint32_t *array
= (uint32_t *)opaque
;
1670 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1671 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1672 X86CPUFeatureWordInfoList
*list
= NULL
;
1674 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1675 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1676 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1677 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1678 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1679 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1680 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1681 qwi
->features
= array
[w
];
1683 /* List will be in reverse order, but order shouldn't matter */
1684 list_entries
[w
].next
= list
;
1685 list_entries
[w
].value
= &word_infos
[w
];
1686 list
= &list_entries
[w
];
1689 visit_type_X86CPUFeatureWordInfoList(v
, &list
, "feature-words", &err
);
1690 error_propagate(errp
, err
);
1693 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1694 const char *name
, Error
**errp
)
1696 X86CPU
*cpu
= X86_CPU(obj
);
1697 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1699 visit_type_int(v
, &value
, name
, errp
);
1702 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1703 const char *name
, Error
**errp
)
1705 const int64_t min
= 0xFFF;
1706 const int64_t max
= UINT_MAX
;
1707 X86CPU
*cpu
= X86_CPU(obj
);
1711 visit_type_int(v
, &value
, name
, &err
);
1713 error_propagate(errp
, err
);
1717 if (value
< min
|| value
> max
) {
1718 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1719 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1720 object_get_typename(obj
), name
? name
: "null",
1724 cpu
->hyperv_spinlock_attempts
= value
;
1727 static PropertyInfo qdev_prop_spinlocks
= {
1729 .get
= x86_get_hv_spinlocks
,
1730 .set
= x86_set_hv_spinlocks
,
1733 /* Convert all '_' in a feature string option name to '-', to make feature
1734 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1736 static inline void feat2prop(char *s
)
1738 while ((s
= strchr(s
, '_'))) {
1743 /* Parse "+feature,-feature,feature=foo" CPU feature string
1745 static void x86_cpu_parse_featurestr(CPUState
*cs
, char *features
,
1748 X86CPU
*cpu
= X86_CPU(cs
);
1749 char *featurestr
; /* Single 'key=value" string being parsed */
1751 /* Features to be added */
1752 FeatureWordArray plus_features
= { 0 };
1753 /* Features to be removed */
1754 FeatureWordArray minus_features
= { 0 };
1756 CPUX86State
*env
= &cpu
->env
;
1757 Error
*local_err
= NULL
;
1759 featurestr
= features
? strtok(features
, ",") : NULL
;
1761 while (featurestr
) {
1763 if (featurestr
[0] == '+') {
1764 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
, &local_err
);
1765 } else if (featurestr
[0] == '-') {
1766 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
, &local_err
);
1767 } else if ((val
= strchr(featurestr
, '='))) {
1769 feat2prop(featurestr
);
1770 if (!strcmp(featurestr
, "xlevel")) {
1774 numvalue
= strtoul(val
, &err
, 0);
1775 if (!*val
|| *err
) {
1776 error_setg(errp
, "bad numerical value %s", val
);
1779 if (numvalue
< 0x80000000) {
1780 error_report("xlevel value shall always be >= 0x80000000"
1781 ", fixup will be removed in future versions");
1782 numvalue
+= 0x80000000;
1784 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1785 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1786 } else if (!strcmp(featurestr
, "tsc-freq")) {
1791 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1792 STRTOSZ_DEFSUFFIX_B
, 1000);
1793 if (tsc_freq
< 0 || *err
) {
1794 error_setg(errp
, "bad numerical value %s", val
);
1797 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1798 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency",
1800 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1802 const int min
= 0xFFF;
1804 numvalue
= strtoul(val
, &err
, 0);
1805 if (!*val
|| *err
) {
1806 error_setg(errp
, "bad numerical value %s", val
);
1809 if (numvalue
< min
) {
1810 error_report("hv-spinlocks value shall always be >= 0x%x"
1811 ", fixup will be removed in future versions",
1815 snprintf(num
, sizeof(num
), "%" PRId32
, numvalue
);
1816 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1818 object_property_parse(OBJECT(cpu
), val
, featurestr
, &local_err
);
1821 feat2prop(featurestr
);
1822 object_property_parse(OBJECT(cpu
), "on", featurestr
, &local_err
);
1825 error_propagate(errp
, local_err
);
1828 featurestr
= strtok(NULL
, ",");
1831 if (cpu
->host_features
) {
1832 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1834 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1838 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1839 env
->features
[w
] |= plus_features
[w
];
1840 env
->features
[w
] &= ~minus_features
[w
];
1844 /* generate a composite string into buf of all cpuid names in featureset
1845 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1846 * if flags, suppress names undefined in featureset.
1848 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1849 const char **featureset
, uint32_t flags
)
1851 const char **p
= &featureset
[31];
1855 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1857 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1858 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1860 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1862 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1863 if (bufsize
<= nc
) {
1865 memcpy(b
, "...", sizeof("..."));
1874 /* generate CPU information. */
1875 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1877 X86CPUDefinition
*def
;
1881 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1882 def
= &builtin_x86_defs
[i
];
1883 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1884 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1887 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
1888 "KVM processor with all supported host features "
1889 "(only available in KVM mode)");
1892 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1893 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
1894 FeatureWordInfo
*fw
= &feature_word_info
[i
];
1896 listflags(buf
, sizeof(buf
), (uint32_t)~0, fw
->feat_names
, 1);
1897 (*cpu_fprintf
)(f
, " %s\n", buf
);
1901 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1903 CpuDefinitionInfoList
*cpu_list
= NULL
;
1904 X86CPUDefinition
*def
;
1907 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1908 CpuDefinitionInfoList
*entry
;
1909 CpuDefinitionInfo
*info
;
1911 def
= &builtin_x86_defs
[i
];
1912 info
= g_malloc0(sizeof(*info
));
1913 info
->name
= g_strdup(def
->name
);
1915 entry
= g_malloc0(sizeof(*entry
));
1916 entry
->value
= info
;
1917 entry
->next
= cpu_list
;
1924 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1925 bool migratable_only
)
1927 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1930 if (kvm_enabled()) {
1931 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
1934 } else if (tcg_enabled()) {
1935 r
= wi
->tcg_features
;
1939 if (migratable_only
) {
1940 r
&= x86_cpu_get_migratable_flags(w
);
1946 * Filters CPU feature words based on host availability of each feature.
1948 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1950 static int x86_cpu_filter_features(X86CPU
*cpu
)
1952 CPUX86State
*env
= &cpu
->env
;
1956 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1957 uint32_t host_feat
=
1958 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1959 uint32_t requested_features
= env
->features
[w
];
1960 env
->features
[w
] &= host_feat
;
1961 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
1962 if (cpu
->filtered_features
[w
]) {
1963 if (cpu
->check_cpuid
|| cpu
->enforce_cpuid
) {
1964 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
1973 /* Load data from X86CPUDefinition
1975 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
1977 CPUX86State
*env
= &cpu
->env
;
1979 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
1982 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
1983 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
1984 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
1985 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
1986 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
1987 env
->cpuid_xlevel2
= def
->xlevel2
;
1988 cpu
->cache_info_passthrough
= def
->cache_info_passthrough
;
1989 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
1990 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1991 env
->features
[w
] = def
->features
[w
];
1994 /* Special cases not set in the X86CPUDefinition structs: */
1995 if (kvm_enabled()) {
1997 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1998 env
->features
[w
] |= kvm_default_features
[w
];
1999 env
->features
[w
] &= ~kvm_default_unset_features
[w
];
2003 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2005 /* sysenter isn't supported in compatibility mode on AMD,
2006 * syscall isn't supported in compatibility mode on Intel.
2007 * Normally we advertise the actual CPU vendor, but you can
2008 * override this using the 'vendor' property if you want to use
2009 * KVM's sysenter/syscall emulation in compatibility mode and
2010 * when doing cross vendor migration
2012 vendor
= def
->vendor
;
2013 if (kvm_enabled()) {
2014 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2015 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2016 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2017 vendor
= host_vendor
;
2020 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2024 X86CPU
*cpu_x86_create(const char *cpu_model
, DeviceState
*icc_bridge
,
2030 gchar
**model_pieces
;
2031 char *name
, *features
;
2032 Error
*error
= NULL
;
2034 model_pieces
= g_strsplit(cpu_model
, ",", 2);
2035 if (!model_pieces
[0]) {
2036 error_setg(&error
, "Invalid/empty CPU model name");
2039 name
= model_pieces
[0];
2040 features
= model_pieces
[1];
2042 oc
= x86_cpu_class_by_name(name
);
2044 error_setg(&error
, "Unable to find CPU definition: %s", name
);
2047 xcc
= X86_CPU_CLASS(oc
);
2049 if (xcc
->kvm_required
&& !kvm_enabled()) {
2050 error_setg(&error
, "CPU model '%s' requires KVM", name
);
2054 cpu
= X86_CPU(object_new(object_class_get_name(oc
)));
2056 #ifndef CONFIG_USER_ONLY
2057 if (icc_bridge
== NULL
) {
2058 error_setg(&error
, "Invalid icc-bridge value");
2061 qdev_set_parent_bus(DEVICE(cpu
), qdev_get_child_bus(icc_bridge
, "icc"));
2062 object_unref(OBJECT(cpu
));
2065 x86_cpu_parse_featurestr(CPU(cpu
), features
, &error
);
2071 if (error
!= NULL
) {
2072 error_propagate(errp
, error
);
2074 object_unref(OBJECT(cpu
));
2078 g_strfreev(model_pieces
);
2082 X86CPU
*cpu_x86_init(const char *cpu_model
)
2084 Error
*error
= NULL
;
2087 cpu
= cpu_x86_create(cpu_model
, NULL
, &error
);
2092 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
2096 error_report("%s", error_get_pretty(error
));
2099 object_unref(OBJECT(cpu
));
2106 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2108 X86CPUDefinition
*cpudef
= data
;
2109 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2111 xcc
->cpu_def
= cpudef
;
2114 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2116 char *typename
= x86_cpu_type_name(def
->name
);
2119 .parent
= TYPE_X86_CPU
,
2120 .class_init
= x86_cpu_cpudef_class_init
,
2128 #if !defined(CONFIG_USER_ONLY)
2130 void cpu_clear_apic_feature(CPUX86State
*env
)
2132 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2135 #endif /* !CONFIG_USER_ONLY */
2137 /* Initialize list of CPU models, filling some non-static fields if necessary
2139 void x86_cpudef_setup(void)
2142 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
2144 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
2145 X86CPUDefinition
*def
= &builtin_x86_defs
[i
];
2147 /* Look for specific "cpudef" models that */
2148 /* have the QEMU version in .model_id */
2149 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
2150 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
2151 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
2152 "QEMU Virtual CPU version ");
2153 pstrcat(def
->model_id
, sizeof(def
->model_id
),
2154 qemu_get_version());
2161 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
2162 uint32_t *ecx
, uint32_t *edx
)
2164 *ebx
= env
->cpuid_vendor1
;
2165 *edx
= env
->cpuid_vendor2
;
2166 *ecx
= env
->cpuid_vendor3
;
2169 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2170 uint32_t *eax
, uint32_t *ebx
,
2171 uint32_t *ecx
, uint32_t *edx
)
2173 X86CPU
*cpu
= x86_env_get_cpu(env
);
2174 CPUState
*cs
= CPU(cpu
);
2176 /* test if maximum index reached */
2177 if (index
& 0x80000000) {
2178 if (index
> env
->cpuid_xlevel
) {
2179 if (env
->cpuid_xlevel2
> 0) {
2180 /* Handle the Centaur's CPUID instruction. */
2181 if (index
> env
->cpuid_xlevel2
) {
2182 index
= env
->cpuid_xlevel2
;
2183 } else if (index
< 0xC0000000) {
2184 index
= env
->cpuid_xlevel
;
2187 /* Intel documentation states that invalid EAX input will
2188 * return the same information as EAX=cpuid_level
2189 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2191 index
= env
->cpuid_level
;
2195 if (index
> env
->cpuid_level
)
2196 index
= env
->cpuid_level
;
2201 *eax
= env
->cpuid_level
;
2202 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
2205 *eax
= env
->cpuid_version
;
2206 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2207 *ecx
= env
->features
[FEAT_1_ECX
];
2208 *edx
= env
->features
[FEAT_1_EDX
];
2209 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2210 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2211 *edx
|= 1 << 28; /* HTT bit */
2215 /* cache info: needed for Pentium Pro compatibility */
2216 if (cpu
->cache_info_passthrough
) {
2217 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2220 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2223 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2224 (L1I_DESCRIPTOR
<< 8) | \
2228 /* cache info: needed for Core compatibility */
2229 if (cpu
->cache_info_passthrough
) {
2230 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2231 *eax
&= ~0xFC000000;
2235 case 0: /* L1 dcache info */
2236 *eax
|= CPUID_4_TYPE_DCACHE
| \
2237 CPUID_4_LEVEL(1) | \
2238 CPUID_4_SELF_INIT_LEVEL
;
2239 *ebx
= (L1D_LINE_SIZE
- 1) | \
2240 ((L1D_PARTITIONS
- 1) << 12) | \
2241 ((L1D_ASSOCIATIVITY
- 1) << 22);
2242 *ecx
= L1D_SETS
- 1;
2243 *edx
= CPUID_4_NO_INVD_SHARING
;
2245 case 1: /* L1 icache info */
2246 *eax
|= CPUID_4_TYPE_ICACHE
| \
2247 CPUID_4_LEVEL(1) | \
2248 CPUID_4_SELF_INIT_LEVEL
;
2249 *ebx
= (L1I_LINE_SIZE
- 1) | \
2250 ((L1I_PARTITIONS
- 1) << 12) | \
2251 ((L1I_ASSOCIATIVITY
- 1) << 22);
2252 *ecx
= L1I_SETS
- 1;
2253 *edx
= CPUID_4_NO_INVD_SHARING
;
2255 case 2: /* L2 cache info */
2256 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2257 CPUID_4_LEVEL(2) | \
2258 CPUID_4_SELF_INIT_LEVEL
;
2259 if (cs
->nr_threads
> 1) {
2260 *eax
|= (cs
->nr_threads
- 1) << 14;
2262 *ebx
= (L2_LINE_SIZE
- 1) | \
2263 ((L2_PARTITIONS
- 1) << 12) | \
2264 ((L2_ASSOCIATIVITY
- 1) << 22);
2266 *edx
= CPUID_4_NO_INVD_SHARING
;
2268 default: /* end of info */
2277 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2278 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2279 *eax
|= (cs
->nr_cores
- 1) << 26;
2283 /* mwait info: needed for Core compatibility */
2284 *eax
= 0; /* Smallest monitor-line size in bytes */
2285 *ebx
= 0; /* Largest monitor-line size in bytes */
2286 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2290 /* Thermal and Power Leaf */
2297 /* Structured Extended Feature Flags Enumeration Leaf */
2299 *eax
= 0; /* Maximum ECX value for sub-leaves */
2300 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2301 *ecx
= 0; /* Reserved */
2302 *edx
= 0; /* Reserved */
2311 /* Direct Cache Access Information Leaf */
2312 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2318 /* Architectural Performance Monitoring Leaf */
2319 if (kvm_enabled() && cpu
->enable_pmu
) {
2320 KVMState
*s
= cs
->kvm_state
;
2322 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2323 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2324 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2325 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2334 KVMState
*s
= cs
->kvm_state
;
2338 /* Processor Extended State */
2343 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) || !kvm_enabled()) {
2347 kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EAX
) |
2348 ((uint64_t)kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EDX
) << 32);
2352 for (i
= 2; i
< ARRAY_SIZE(ext_save_areas
); i
++) {
2353 const ExtSaveArea
*esa
= &ext_save_areas
[i
];
2354 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2355 (kvm_mask
& (1 << i
)) != 0) {
2359 *edx
|= 1 << (i
- 32);
2361 *ecx
= MAX(*ecx
, esa
->offset
+ esa
->size
);
2364 *eax
|= kvm_mask
& (XSTATE_FP
| XSTATE_SSE
);
2366 } else if (count
== 1) {
2367 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, 1, R_EAX
);
2368 } else if (count
< ARRAY_SIZE(ext_save_areas
)) {
2369 const ExtSaveArea
*esa
= &ext_save_areas
[count
];
2370 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2371 (kvm_mask
& (1 << count
)) != 0) {
2379 *eax
= env
->cpuid_xlevel
;
2380 *ebx
= env
->cpuid_vendor1
;
2381 *edx
= env
->cpuid_vendor2
;
2382 *ecx
= env
->cpuid_vendor3
;
2385 *eax
= env
->cpuid_version
;
2387 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2388 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2390 /* The Linux kernel checks for the CMPLegacy bit and
2391 * discards multiple thread information if it is set.
2392 * So dont set it here for Intel to make Linux guests happy.
2394 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2395 uint32_t tebx
, tecx
, tedx
;
2396 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
2397 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2398 tedx
!= CPUID_VENDOR_INTEL_2
||
2399 tecx
!= CPUID_VENDOR_INTEL_3
) {
2400 *ecx
|= 1 << 1; /* CmpLegacy bit */
2407 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2408 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2409 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2410 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2413 /* cache info (L1 cache) */
2414 if (cpu
->cache_info_passthrough
) {
2415 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2418 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2419 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2420 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2421 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2422 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2423 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2424 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2425 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2428 /* cache info (L2 cache) */
2429 if (cpu
->cache_info_passthrough
) {
2430 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2433 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2434 (L2_DTLB_2M_ENTRIES
<< 16) | \
2435 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2436 (L2_ITLB_2M_ENTRIES
);
2437 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2438 (L2_DTLB_4K_ENTRIES
<< 16) | \
2439 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2440 (L2_ITLB_4K_ENTRIES
);
2441 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2442 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2443 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2444 *edx
= ((L3_SIZE_KB
/512) << 18) | \
2445 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2446 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2452 *edx
= env
->features
[FEAT_8000_0007_EDX
];
2455 /* virtual & phys address size in low 2 bytes. */
2456 /* XXX: This value must match the one used in the MMU code. */
2457 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2458 /* 64 bit processor */
2459 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2460 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2462 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2463 *eax
= 0x00000024; /* 36 bits physical */
2465 *eax
= 0x00000020; /* 32 bits physical */
2471 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2472 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2476 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2477 *eax
= 0x00000001; /* SVM Revision */
2478 *ebx
= 0x00000010; /* nr of ASIDs */
2480 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2489 *eax
= env
->cpuid_xlevel2
;
2495 /* Support for VIA CPU's CPUID instruction */
2496 *eax
= env
->cpuid_version
;
2499 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2504 /* Reserved for the future, and now filled with zero */
2511 /* reserved values: zero */
2520 /* CPUClass::reset() */
2521 static void x86_cpu_reset(CPUState
*s
)
2523 X86CPU
*cpu
= X86_CPU(s
);
2524 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2525 CPUX86State
*env
= &cpu
->env
;
2528 xcc
->parent_reset(s
);
2530 memset(env
, 0, offsetof(CPUX86State
, cpuid_level
));
2534 env
->old_exception
= -1;
2536 /* init to reset state */
2538 #ifdef CONFIG_SOFTMMU
2539 env
->hflags
|= HF_SOFTMMU_MASK
;
2541 env
->hflags2
|= HF2_GIF_MASK
;
2543 cpu_x86_update_cr0(env
, 0x60000010);
2544 env
->a20_mask
= ~0x0;
2545 env
->smbase
= 0x30000;
2547 env
->idt
.limit
= 0xffff;
2548 env
->gdt
.limit
= 0xffff;
2549 env
->ldt
.limit
= 0xffff;
2550 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2551 env
->tr
.limit
= 0xffff;
2552 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2554 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2555 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2556 DESC_R_MASK
| DESC_A_MASK
);
2557 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2558 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2560 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2561 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2563 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2564 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2566 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2567 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2569 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2570 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2574 env
->regs
[R_EDX
] = env
->cpuid_version
;
2579 for (i
= 0; i
< 8; i
++) {
2582 cpu_set_fpuc(env
, 0x37f);
2584 env
->mxcsr
= 0x1f80;
2585 env
->xstate_bv
= XSTATE_FP
| XSTATE_SSE
;
2587 env
->pat
= 0x0007040600070406ULL
;
2588 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2590 memset(env
->dr
, 0, sizeof(env
->dr
));
2591 env
->dr
[6] = DR6_FIXED_1
;
2592 env
->dr
[7] = DR7_FIXED_1
;
2593 cpu_breakpoint_remove_all(s
, BP_CPU
);
2594 cpu_watchpoint_remove_all(s
, BP_CPU
);
2599 * SDM 11.11.5 requires:
2600 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2601 * - IA32_MTRR_PHYSMASKn.V = 0
2602 * All other bits are undefined. For simplification, zero it all.
2604 env
->mtrr_deftype
= 0;
2605 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
2606 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
2608 #if !defined(CONFIG_USER_ONLY)
2609 /* We hard-wire the BSP to the first CPU. */
2610 if (s
->cpu_index
== 0) {
2611 apic_designate_bsp(cpu
->apic_state
);
2614 s
->halted
= !cpu_is_bsp(cpu
);
2616 if (kvm_enabled()) {
2617 kvm_arch_reset_vcpu(cpu
);
2622 #ifndef CONFIG_USER_ONLY
2623 bool cpu_is_bsp(X86CPU
*cpu
)
2625 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2628 /* TODO: remove me, when reset over QOM tree is implemented */
2629 static void x86_cpu_machine_reset_cb(void *opaque
)
2631 X86CPU
*cpu
= opaque
;
2632 cpu_reset(CPU(cpu
));
2636 static void mce_init(X86CPU
*cpu
)
2638 CPUX86State
*cenv
= &cpu
->env
;
2641 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2642 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2643 (CPUID_MCE
| CPUID_MCA
)) {
2644 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2645 cenv
->mcg_ctl
= ~(uint64_t)0;
2646 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2647 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2652 #ifndef CONFIG_USER_ONLY
2653 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2655 CPUX86State
*env
= &cpu
->env
;
2656 DeviceState
*dev
= DEVICE(cpu
);
2657 APICCommonState
*apic
;
2658 const char *apic_type
= "apic";
2660 if (kvm_irqchip_in_kernel()) {
2661 apic_type
= "kvm-apic";
2662 } else if (xen_enabled()) {
2663 apic_type
= "xen-apic";
2666 cpu
->apic_state
= qdev_try_create(qdev_get_parent_bus(dev
), apic_type
);
2667 if (cpu
->apic_state
== NULL
) {
2668 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2672 object_property_add_child(OBJECT(cpu
), "apic",
2673 OBJECT(cpu
->apic_state
), NULL
);
2674 qdev_prop_set_uint8(cpu
->apic_state
, "id", env
->cpuid_apic_id
);
2675 /* TODO: convert to link<> */
2676 apic
= APIC_COMMON(cpu
->apic_state
);
2680 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2682 if (cpu
->apic_state
== NULL
) {
2686 if (qdev_init(cpu
->apic_state
)) {
2687 error_setg(errp
, "APIC device '%s' could not be initialized",
2688 object_get_typename(OBJECT(cpu
->apic_state
)));
2693 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2699 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2700 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2701 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2702 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2703 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2704 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2705 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2707 CPUState
*cs
= CPU(dev
);
2708 X86CPU
*cpu
= X86_CPU(dev
);
2709 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2710 CPUX86State
*env
= &cpu
->env
;
2711 Error
*local_err
= NULL
;
2712 static bool ht_warned
;
2714 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2715 env
->cpuid_level
= 7;
2718 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2721 if (IS_AMD_CPU(env
)) {
2722 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2723 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2724 & CPUID_EXT2_AMD_ALIASES
);
2728 if (x86_cpu_filter_features(cpu
) && cpu
->enforce_cpuid
) {
2729 error_setg(&local_err
,
2731 "Host doesn't support requested features" :
2732 "TCG doesn't support requested features");
2736 #ifndef CONFIG_USER_ONLY
2737 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2739 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2740 x86_cpu_apic_create(cpu
, &local_err
);
2741 if (local_err
!= NULL
) {
2750 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2751 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2752 * based on inputs (sockets,cores,threads), it is still better to gives
2755 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2756 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2758 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
2759 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2760 " -smp options properly.");
2764 x86_cpu_apic_realize(cpu
, &local_err
);
2765 if (local_err
!= NULL
) {
2770 xcc
->parent_realize(dev
, &local_err
);
2772 if (local_err
!= NULL
) {
2773 error_propagate(errp
, local_err
);
2778 /* Enables contiguous-apic-ID mode, for compatibility */
2779 static bool compat_apic_id_mode
;
2781 void enable_compat_apic_id_mode(void)
2783 compat_apic_id_mode
= true;
2786 /* Calculates initial APIC ID for a specific CPU index
2788 * Currently we need to be able to calculate the APIC ID from the CPU index
2789 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2790 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2791 * all CPUs up to max_cpus.
2793 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
2795 uint32_t correct_id
;
2798 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
2799 if (compat_apic_id_mode
) {
2800 if (cpu_index
!= correct_id
&& !warned
) {
2801 error_report("APIC IDs set in compatibility mode, "
2802 "CPU topology won't match the configuration");
2811 static void x86_cpu_initfn(Object
*obj
)
2813 CPUState
*cs
= CPU(obj
);
2814 X86CPU
*cpu
= X86_CPU(obj
);
2815 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
2816 CPUX86State
*env
= &cpu
->env
;
2822 object_property_add(obj
, "family", "int",
2823 x86_cpuid_version_get_family
,
2824 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2825 object_property_add(obj
, "model", "int",
2826 x86_cpuid_version_get_model
,
2827 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2828 object_property_add(obj
, "stepping", "int",
2829 x86_cpuid_version_get_stepping
,
2830 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2831 object_property_add(obj
, "level", "int",
2832 x86_cpuid_get_level
,
2833 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2834 object_property_add(obj
, "xlevel", "int",
2835 x86_cpuid_get_xlevel
,
2836 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2837 object_property_add_str(obj
, "vendor",
2838 x86_cpuid_get_vendor
,
2839 x86_cpuid_set_vendor
, NULL
);
2840 object_property_add_str(obj
, "model-id",
2841 x86_cpuid_get_model_id
,
2842 x86_cpuid_set_model_id
, NULL
);
2843 object_property_add(obj
, "tsc-frequency", "int",
2844 x86_cpuid_get_tsc_freq
,
2845 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2846 object_property_add(obj
, "apic-id", "int",
2847 x86_cpuid_get_apic_id
,
2848 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
2849 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
2850 x86_cpu_get_feature_words
,
2851 NULL
, NULL
, (void *)env
->features
, NULL
);
2852 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
2853 x86_cpu_get_feature_words
,
2854 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
2856 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
2857 env
->cpuid_apic_id
= x86_cpu_apic_id_from_index(cs
->cpu_index
);
2859 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
2861 /* init various static tables used in TCG mode */
2862 if (tcg_enabled() && !inited
) {
2864 optimize_flags_init();
2868 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
2870 X86CPU
*cpu
= X86_CPU(cs
);
2871 CPUX86State
*env
= &cpu
->env
;
2873 return env
->cpuid_apic_id
;
2876 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
2878 X86CPU
*cpu
= X86_CPU(cs
);
2880 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
2883 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
2885 X86CPU
*cpu
= X86_CPU(cs
);
2887 cpu
->env
.eip
= value
;
2890 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
2892 X86CPU
*cpu
= X86_CPU(cs
);
2894 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
2897 static bool x86_cpu_has_work(CPUState
*cs
)
2899 X86CPU
*cpu
= X86_CPU(cs
);
2900 CPUX86State
*env
= &cpu
->env
;
2902 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
2903 CPU_INTERRUPT_POLL
)) &&
2904 (env
->eflags
& IF_MASK
)) ||
2905 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
2906 CPU_INTERRUPT_INIT
|
2907 CPU_INTERRUPT_SIPI
|
2908 CPU_INTERRUPT_MCE
));
2911 static Property x86_cpu_properties
[] = {
2912 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
2913 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
2914 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
2915 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
2916 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
2917 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, false),
2918 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
2919 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
2920 DEFINE_PROP_END_OF_LIST()
2923 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2925 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2926 CPUClass
*cc
= CPU_CLASS(oc
);
2927 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2929 xcc
->parent_realize
= dc
->realize
;
2930 dc
->realize
= x86_cpu_realizefn
;
2931 dc
->bus_type
= TYPE_ICC_BUS
;
2932 dc
->props
= x86_cpu_properties
;
2934 xcc
->parent_reset
= cc
->reset
;
2935 cc
->reset
= x86_cpu_reset
;
2936 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
2938 cc
->class_by_name
= x86_cpu_class_by_name
;
2939 cc
->parse_features
= x86_cpu_parse_featurestr
;
2940 cc
->has_work
= x86_cpu_has_work
;
2941 cc
->do_interrupt
= x86_cpu_do_interrupt
;
2942 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
2943 cc
->dump_state
= x86_cpu_dump_state
;
2944 cc
->set_pc
= x86_cpu_set_pc
;
2945 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
2946 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
2947 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
2948 cc
->get_arch_id
= x86_cpu_get_arch_id
;
2949 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
2950 #ifdef CONFIG_USER_ONLY
2951 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
2953 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
2954 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
2955 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
2956 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
2957 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
2958 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
2959 cc
->vmsd
= &vmstate_x86_cpu
;
2961 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
2962 #ifndef CONFIG_USER_ONLY
2963 cc
->debug_excp_handler
= breakpoint_handler
;
2965 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
2966 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
2969 static const TypeInfo x86_cpu_type_info
= {
2970 .name
= TYPE_X86_CPU
,
2972 .instance_size
= sizeof(X86CPU
),
2973 .instance_init
= x86_cpu_initfn
,
2975 .class_size
= sizeof(X86CPUClass
),
2976 .class_init
= x86_cpu_common_class_init
,
2979 static void x86_cpu_register_types(void)
2983 type_register_static(&x86_cpu_type_info
);
2984 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
2985 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
2988 type_register_static(&host_x86_cpu_type_info
);
2992 type_init(x86_cpu_register_types
)