tests/qtest: replace qmp_discard_response with qtest_qmp_assert_success
[qemu/kevin.git] / target / ppc / timebase_helper.c
blobb80f56af7e4082df26e3c36e62e571e86e22f700
1 /*
2 * PowerPC emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "qemu/log.h"
24 #include "qemu/main-loop.h"
26 /*****************************************************************************/
27 /* SPR accesses */
29 target_ulong helper_load_tbl(CPUPPCState *env)
31 return (target_ulong)cpu_ppc_load_tbl(env);
34 target_ulong helper_load_tbu(CPUPPCState *env)
36 return cpu_ppc_load_tbu(env);
39 target_ulong helper_load_atbl(CPUPPCState *env)
41 return (target_ulong)cpu_ppc_load_atbl(env);
44 target_ulong helper_load_atbu(CPUPPCState *env)
46 return cpu_ppc_load_atbu(env);
49 target_ulong helper_load_vtb(CPUPPCState *env)
51 return cpu_ppc_load_vtb(env);
54 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
55 target_ulong helper_load_purr(CPUPPCState *env)
57 return (target_ulong)cpu_ppc_load_purr(env);
60 void helper_store_purr(CPUPPCState *env, target_ulong val)
62 cpu_ppc_store_purr(env, val);
64 #endif
66 #if !defined(CONFIG_USER_ONLY)
67 void helper_store_tbl(CPUPPCState *env, target_ulong val)
69 cpu_ppc_store_tbl(env, val);
72 void helper_store_tbu(CPUPPCState *env, target_ulong val)
74 cpu_ppc_store_tbu(env, val);
77 void helper_store_atbl(CPUPPCState *env, target_ulong val)
79 cpu_ppc_store_atbl(env, val);
82 void helper_store_atbu(CPUPPCState *env, target_ulong val)
84 cpu_ppc_store_atbu(env, val);
87 target_ulong helper_load_decr(CPUPPCState *env)
89 return cpu_ppc_load_decr(env);
92 void helper_store_decr(CPUPPCState *env, target_ulong val)
94 cpu_ppc_store_decr(env, val);
97 target_ulong helper_load_hdecr(CPUPPCState *env)
99 return cpu_ppc_load_hdecr(env);
102 void helper_store_hdecr(CPUPPCState *env, target_ulong val)
104 cpu_ppc_store_hdecr(env, val);
107 void helper_store_vtb(CPUPPCState *env, target_ulong val)
109 cpu_ppc_store_vtb(env, val);
112 void helper_store_tbu40(CPUPPCState *env, target_ulong val)
114 cpu_ppc_store_tbu40(env, val);
117 target_ulong helper_load_40x_pit(CPUPPCState *env)
119 return load_40x_pit(env);
122 void helper_store_40x_pit(CPUPPCState *env, target_ulong val)
124 store_40x_pit(env, val);
127 void helper_store_40x_tcr(CPUPPCState *env, target_ulong val)
129 store_40x_tcr(env, val);
132 void helper_store_40x_tsr(CPUPPCState *env, target_ulong val)
134 store_40x_tsr(env, val);
137 void helper_store_booke_tcr(CPUPPCState *env, target_ulong val)
139 store_booke_tcr(env, val);
142 void helper_store_booke_tsr(CPUPPCState *env, target_ulong val)
144 store_booke_tsr(env, val);
147 /*****************************************************************************/
148 /* Embedded PowerPC specific helpers */
150 /* XXX: to be improved to check access rights when in user-mode */
151 target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
153 uint32_t val = 0;
155 if (unlikely(env->dcr_env == NULL)) {
156 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
157 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
158 POWERPC_EXCP_INVAL |
159 POWERPC_EXCP_INVAL_INVAL, GETPC());
160 } else {
161 int ret;
163 qemu_mutex_lock_iothread();
164 ret = ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val);
165 qemu_mutex_unlock_iothread();
166 if (unlikely(ret != 0)) {
167 qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n",
168 (uint32_t)dcrn, (uint32_t)dcrn);
169 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
170 POWERPC_EXCP_INVAL |
171 POWERPC_EXCP_INVAL_INVAL, GETPC());
174 return val;
177 void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val)
179 if (unlikely(env->dcr_env == NULL)) {
180 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
181 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
182 POWERPC_EXCP_INVAL |
183 POWERPC_EXCP_INVAL_INVAL, GETPC());
184 } else {
185 int ret;
186 qemu_mutex_lock_iothread();
187 ret = ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val);
188 qemu_mutex_unlock_iothread();
189 if (unlikely(ret != 0)) {
190 qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n",
191 (uint32_t)dcrn, (uint32_t)dcrn);
192 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
193 POWERPC_EXCP_INVAL |
194 POWERPC_EXCP_INVAL_INVAL, GETPC());
198 #endif