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usb: add speed mask to ports
[qemu/kevin.git] / hw / usb-musb.c
blob87eb9ca0ce687d1f19f8ddfd397e14167958e6e3
1 /*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "usb.h"
26 #include "irq.h"
27 #include "hw.h"
28
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46 /* EP FIFOs */
47 #define MUSB_HDRC_FIFO 0x20
48
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
68
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
83
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
105
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
109
110 /*
111 * MUSBHDRC Register bit masks
112 */
113
114 /* POWER */
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
123
124 /* INTRUSB */
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136 /* DEVCTL */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
145
146 /* TESTMODE */
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
155
156 /* CSR0 */
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
160
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
179
180 /* CONFIGDATA */
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
214
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
240
241 /* HUBADDR */
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
243
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
251
252 /* #define MUSB_DEBUG */
253
254 #ifdef MUSB_DEBUG
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257 #else
258 #define TRACE(...)
259 #endif
260
261
262 static void musb_attach(USBPort *port);
263 static void musb_detach(USBPort *port);
264
265 static USBPortOps musb_port_ops = {
266 .attach = musb_attach,
267 .detach = musb_detach,
268 };
269
270 typedef struct {
271 uint16_t faddr[2];
272 uint8_t haddr[2];
273 uint8_t hport[2];
274 uint16_t csr[2];
275 uint16_t maxp[2];
276 uint16_t rxcount;
277 uint8_t type[2];
278 uint8_t interval[2];
279 uint8_t config;
280 uint8_t fifosize;
281 int timeout[2]; /* Always in microframes */
282
283 uint8_t *buf[2];
284 int fifolen[2];
285 int fifostart[2];
286 int fifoaddr[2];
287 USBPacket packey[2];
288 int status[2];
289 int ext_size[2];
290
291 /* For callbacks' use */
292 int epnum;
293 int interrupt[2];
294 MUSBState *musb;
295 USBCallback *delayed_cb[2];
296 QEMUTimer *intv_timer[2];
297 } MUSBEndPoint;
298
299 struct MUSBState {
300 qemu_irq *irqs;
301 USBBus bus;
302 USBPort port;
303
304 int idx;
305 uint8_t devctl;
306 uint8_t power;
307 uint8_t faddr;
308
309 uint8_t intr;
310 uint8_t mask;
311 uint16_t tx_intr;
312 uint16_t tx_mask;
313 uint16_t rx_intr;
314 uint16_t rx_mask;
315
316 int setup_len;
317 int session;
318
319 uint8_t buf[0x8000];
320
321 /* Duplicating the world since 2008!... probably we should have 32
322 * logical, single endpoints instead. */
323 MUSBEndPoint ep[16];
324 } *musb_init(qemu_irq *irqs)
325 {
326 MUSBState *s = qemu_mallocz(sizeof(*s));
327 int i;
328
329 s->irqs = irqs;
330
331 s->faddr = 0x00;
332 s->power = MGC_M_POWER_HSENAB;
333 s->tx_intr = 0x0000;
334 s->rx_intr = 0x0000;
335 s->tx_mask = 0xffff;
336 s->rx_mask = 0xffff;
337 s->intr = 0x00;
338 s->mask = 0x06;
339 s->idx = 0;
340
341 /* TODO: _DW */
342 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
343 for (i = 0; i < 16; i ++) {
344 s->ep[i].fifosize = 64;
345 s->ep[i].maxp[0] = 0x40;
346 s->ep[i].maxp[1] = 0x40;
347 s->ep[i].musb = s;
348 s->ep[i].epnum = i;
349 }
350
351 usb_bus_new(&s->bus, NULL /* FIXME */);
352 usb_register_port(&s->bus, &s->port, s, 0, NULL, &musb_port_ops,
353 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
354
355 return s;
356 }
357
358 static void musb_vbus_set(MUSBState *s, int level)
359 {
360 if (level)
361 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
362 else
363 s->devctl &= ~MGC_M_DEVCTL_VBUS;
364
365 qemu_set_irq(s->irqs[musb_set_vbus], level);
366 }
367
368 static void musb_intr_set(MUSBState *s, int line, int level)
369 {
370 if (!level) {
371 s->intr &= ~(1 << line);
372 qemu_irq_lower(s->irqs[line]);
373 } else if (s->mask & (1 << line)) {
374 s->intr |= 1 << line;
375 qemu_irq_raise(s->irqs[line]);
376 }
377 }
378
379 static void musb_tx_intr_set(MUSBState *s, int line, int level)
380 {
381 if (!level) {
382 s->tx_intr &= ~(1 << line);
383 if (!s->tx_intr)
384 qemu_irq_lower(s->irqs[musb_irq_tx]);
385 } else if (s->tx_mask & (1 << line)) {
386 s->tx_intr |= 1 << line;
387 qemu_irq_raise(s->irqs[musb_irq_tx]);
388 }
389 }
390
391 static void musb_rx_intr_set(MUSBState *s, int line, int level)
392 {
393 if (line) {
394 if (!level) {
395 s->rx_intr &= ~(1 << line);
396 if (!s->rx_intr)
397 qemu_irq_lower(s->irqs[musb_irq_rx]);
398 } else if (s->rx_mask & (1 << line)) {
399 s->rx_intr |= 1 << line;
400 qemu_irq_raise(s->irqs[musb_irq_rx]);
401 }
402 } else
403 musb_tx_intr_set(s, line, level);
404 }
405
406 uint32_t musb_core_intr_get(MUSBState *s)
407 {
408 return (s->rx_intr << 15) | s->tx_intr;
409 }
410
411 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
412 {
413 if (s->rx_intr) {
414 s->rx_intr &= mask >> 15;
415 if (!s->rx_intr)
416 qemu_irq_lower(s->irqs[musb_irq_rx]);
417 }
418
419 if (s->tx_intr) {
420 s->tx_intr &= mask & 0xffff;
421 if (!s->tx_intr)
422 qemu_irq_lower(s->irqs[musb_irq_tx]);
423 }
424 }
425
426 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
427 {
428 s->ep[epnum].ext_size[!is_tx] = size;
429 s->ep[epnum].fifostart[0] = 0;
430 s->ep[epnum].fifostart[1] = 0;
431 s->ep[epnum].fifolen[0] = 0;
432 s->ep[epnum].fifolen[1] = 0;
433 }
434
435 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
436 {
437 int detect_prev = prev_dev && prev_sess;
438 int detect = !!s->port.dev && s->session;
439
440 if (detect && !detect_prev) {
441 /* Let's skip the ID pin sense and VBUS sense formalities and
442 * and signal a successful SRP directly. This should work at least
443 * for the Linux driver stack. */
444 musb_intr_set(s, musb_irq_connect, 1);
445
446 if (s->port.dev->speed == USB_SPEED_LOW) {
447 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
448 s->devctl |= MGC_M_DEVCTL_LSDEV;
449 } else {
450 s->devctl |= MGC_M_DEVCTL_FSDEV;
451 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
452 }
453
454 /* A-mode? */
455 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
456
457 /* Host-mode bit? */
458 s->devctl |= MGC_M_DEVCTL_HM;
459 #if 1
460 musb_vbus_set(s, 1);
461 #endif
462 } else if (!detect && detect_prev) {
463 #if 1
464 musb_vbus_set(s, 0);
465 #endif
466 }
467 }
468
469 /* Attach or detach a device on our only port. */
470 static void musb_attach(USBPort *port)
471 {
472 MUSBState *s = (MUSBState *) port->opaque;
473
474 musb_intr_set(s, musb_irq_vbus_request, 1);
475 musb_session_update(s, 0, s->session);
476 }
477
478 static void musb_detach(USBPort *port)
479 {
480 MUSBState *s = (MUSBState *) port->opaque;
481
482 musb_intr_set(s, musb_irq_disconnect, 1);
483 musb_session_update(s, 1, s->session);
484 }
485
486 static inline void musb_cb_tick0(void *opaque)
487 {
488 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
489
490 ep->delayed_cb[0](&ep->packey[0], opaque);
491 }
492
493 static inline void musb_cb_tick1(void *opaque)
494 {
495 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
496
497 ep->delayed_cb[1](&ep->packey[1], opaque);
498 }
499
500 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
501
502 static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
503 {
504 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
505 int timeout = 0;
506
507 if (ep->status[dir] == USB_RET_NAK)
508 timeout = ep->timeout[dir];
509 else if (ep->interrupt[dir])
510 timeout = 8;
511 else
512 return musb_cb_tick(opaque);
513
514 if (!ep->intv_timer[dir])
515 ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
516
517 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
518 muldiv64(timeout, get_ticks_per_sec(), 8000));
519 }
520
521 static void musb_schedule0_cb(USBPacket *packey, void *opaque)
522 {
523 return musb_schedule_cb(packey, opaque, 0);
524 }
525
526 static void musb_schedule1_cb(USBPacket *packey, void *opaque)
527 {
528 return musb_schedule_cb(packey, opaque, 1);
529 }
530
531 static int musb_timeout(int ttype, int speed, int val)
532 {
533 #if 1
534 return val << 3;
535 #endif
536
537 switch (ttype) {
538 case USB_ENDPOINT_XFER_CONTROL:
539 if (val < 2)
540 return 0;
541 else if (speed == USB_SPEED_HIGH)
542 return 1 << (val - 1);
543 else
544 return 8 << (val - 1);
545
546 case USB_ENDPOINT_XFER_INT:
547 if (speed == USB_SPEED_HIGH)
548 if (val < 2)
549 return 0;
550 else
551 return 1 << (val - 1);
552 else
553 return val << 3;
554
555 case USB_ENDPOINT_XFER_BULK:
556 case USB_ENDPOINT_XFER_ISOC:
557 if (val < 2)
558 return 0;
559 else if (speed == USB_SPEED_HIGH)
560 return 1 << (val - 1);
561 else
562 return 8 << (val - 1);
563 /* TODO: what with low-speed Bulk and Isochronous? */
564 }
565
566 hw_error("bad interval\n");
567 }
568
569 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
570 int epnum, int pid, int len, USBCallback cb, int dir)
571 {
572 int ret;
573 int idx = epnum && dir;
574 int ttype;
575
576 /* ep->type[0,1] contains:
577 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
578 * in bits 5:4 the transfer type (BULK / INT)
579 * in bits 3:0 the EP num
580 */
581 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
582
583 ep->timeout[dir] = musb_timeout(ttype,
584 ep->type[idx] >> 6, ep->interval[idx]);
585 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
586 ep->delayed_cb[dir] = cb;
587 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
588
589 ep->packey[dir].pid = pid;
590 /* A wild guess on the FADDR semantics... */
591 ep->packey[dir].devaddr = ep->faddr[idx];
592 ep->packey[dir].devep = ep->type[idx] & 0xf;
593 ep->packey[dir].data = (void *) ep->buf[idx];
594 ep->packey[dir].len = len;
595 ep->packey[dir].complete_cb = cb;
596 ep->packey[dir].complete_opaque = ep;
597
598 if (s->port.dev)
599 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir]);
600 else
601 ret = USB_RET_NODEV;
602
603 if (ret == USB_RET_ASYNC) {
604 ep->status[dir] = len;
605 return;
606 }
607
608 ep->status[dir] = ret;
609 usb_packet_complete(&ep->packey[dir]);
610 }
611
612 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
613 {
614 /* Unfortunately we can't use packey->devep because that's the remote
615 * endpoint number and may be different than our local. */
616 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
617 int epnum = ep->epnum;
618 MUSBState *s = ep->musb;
619
620 ep->fifostart[0] = 0;
621 ep->fifolen[0] = 0;
622 #ifdef CLEAR_NAK
623 if (ep->status[0] != USB_RET_NAK) {
624 #endif
625 if (epnum)
626 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
627 else
628 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
629 #ifdef CLEAR_NAK
630 }
631 #endif
632
633 /* Clear all of the error bits first */
634 if (epnum)
635 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
636 MGC_M_TXCSR_H_NAKTIMEOUT);
637 else
638 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
639 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
640
641 if (ep->status[0] == USB_RET_STALL) {
642 /* Command not supported by target! */
643 ep->status[0] = 0;
644
645 if (epnum)
646 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
647 else
648 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
649 }
650
651 if (ep->status[0] == USB_RET_NAK) {
652 ep->status[0] = 0;
653
654 /* NAK timeouts are only generated in Bulk transfers and
655 * Data-errors in Isochronous. */
656 if (ep->interrupt[0]) {
657 return;
658 }
659
660 if (epnum)
661 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
662 else
663 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
664 }
665
666 if (ep->status[0] < 0) {
667 if (ep->status[0] == USB_RET_BABBLE)
668 musb_intr_set(s, musb_irq_rst_babble, 1);
669
670 /* Pretend we've tried three times already and failed (in
671 * case of USB_TOKEN_SETUP). */
672 if (epnum)
673 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
674 else
675 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
676
677 musb_tx_intr_set(s, epnum, 1);
678 return;
679 }
680 /* TODO: check len for over/underruns of an OUT packet? */
681
682 #ifdef SETUPLEN_HACK
683 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
684 s->setup_len = ep->packey[0].data[6];
685 #endif
686
687 /* In DMA mode: if no error, assert DMA request for this EP,
688 * and skip the interrupt. */
689 musb_tx_intr_set(s, epnum, 1);
690 }
691
692 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
693 {
694 /* Unfortunately we can't use packey->devep because that's the remote
695 * endpoint number and may be different than our local. */
696 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
697 int epnum = ep->epnum;
698 MUSBState *s = ep->musb;
699
700 ep->fifostart[1] = 0;
701 ep->fifolen[1] = 0;
702
703 #ifdef CLEAR_NAK
704 if (ep->status[1] != USB_RET_NAK) {
705 #endif
706 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
707 if (!epnum)
708 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
709 #ifdef CLEAR_NAK
710 }
711 #endif
712
713 /* Clear all of the imaginable error bits first */
714 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
715 MGC_M_RXCSR_DATAERROR);
716 if (!epnum)
717 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
718 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
719
720 if (ep->status[1] == USB_RET_STALL) {
721 ep->status[1] = 0;
722 packey->len = 0;
723
724 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
725 if (!epnum)
726 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
727 }
728
729 if (ep->status[1] == USB_RET_NAK) {
730 ep->status[1] = 0;
731
732 /* NAK timeouts are only generated in Bulk transfers and
733 * Data-errors in Isochronous. */
734 if (ep->interrupt[1])
735 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
736 packey->len, musb_rx_packet_complete, 1);
737
738 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
739 if (!epnum)
740 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
741 }
742
743 if (ep->status[1] < 0) {
744 if (ep->status[1] == USB_RET_BABBLE) {
745 musb_intr_set(s, musb_irq_rst_babble, 1);
746 return;
747 }
748
749 /* Pretend we've tried three times already and failed (in
750 * case of a control transfer). */
751 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
752 if (!epnum)
753 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
754
755 musb_rx_intr_set(s, epnum, 1);
756 return;
757 }
758 /* TODO: check len for over/underruns of an OUT packet? */
759 /* TODO: perhaps make use of e->ext_size[1] here. */
760
761 packey->len = ep->status[1];
762
763 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
764 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
765 if (!epnum)
766 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
767
768 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
769 /* In DMA mode: assert DMA request for this EP */
770 }
771
772 /* Only if DMA has not been asserted */
773 musb_rx_intr_set(s, epnum, 1);
774 }
775
776 static void musb_tx_rdy(MUSBState *s, int epnum)
777 {
778 MUSBEndPoint *ep = s->ep + epnum;
779 int pid;
780 int total, valid = 0;
781 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
782 ep->fifostart[0] += ep->fifolen[0];
783 ep->fifolen[0] = 0;
784
785 /* XXX: how's the total size of the packet retrieved exactly in
786 * the generic case? */
787 total = ep->maxp[0] & 0x3ff;
788
789 if (ep->ext_size[0]) {
790 total = ep->ext_size[0];
791 ep->ext_size[0] = 0;
792 valid = 1;
793 }
794
795 /* If the packet is not fully ready yet, wait for a next segment. */
796 if (epnum && (ep->fifostart[0]) < total)
797 return;
798
799 if (!valid)
800 total = ep->fifostart[0];
801
802 pid = USB_TOKEN_OUT;
803 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
804 pid = USB_TOKEN_SETUP;
805 if (total != 8) {
806 TRACE("illegal SETUPPKT length of %i bytes", total);
807 }
808 /* Controller should retry SETUP packets three times on errors
809 * but it doesn't make sense for us to do that. */
810 }
811
812 return musb_packet(s, ep, epnum, pid,
813 total, musb_tx_packet_complete, 0);
814 }
815
816 static void musb_rx_req(MUSBState *s, int epnum)
817 {
818 MUSBEndPoint *ep = s->ep + epnum;
819 int total;
820
821 /* If we already have a packet, which didn't fit into the
822 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
823 if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
824 (ep->fifostart[1]) + ep->rxcount <
825 ep->packey[1].len) {
826 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
827 ep->fifostart[1] += ep->rxcount;
828 ep->fifolen[1] = 0;
829
830 ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1]),
831 ep->maxp[1]);
832
833 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
834 if (!epnum)
835 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
836
837 /* Clear all of the error bits first */
838 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
839 MGC_M_RXCSR_DATAERROR);
840 if (!epnum)
841 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
842 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
843
844 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
845 if (!epnum)
846 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
847 musb_rx_intr_set(s, epnum, 1);
848 return;
849 }
850
851 /* The driver sets maxp[1] to 64 or less because it knows the hardware
852 * FIFO is this deep. Bigger packets get split in
853 * usb_generic_handle_packet but we can also do the splitting locally
854 * for performance. It turns out we can also have a bigger FIFO and
855 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
856 * OK with single packets of even 32KB and we avoid splitting, however
857 * usb_msd.c sometimes sends a packet bigger than what Linux expects
858 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
859 * hides this overrun from Linux. Up to 4096 everything is fine
860 * though. Currently this is disabled.
861 *
862 * XXX: mind ep->fifosize. */
863 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
864
865 #ifdef SETUPLEN_HACK
866 /* Why should *we* do that instead of Linux? */
867 if (!epnum) {
868 if (ep->packey[0].devaddr == 2)
869 total = MIN(s->setup_len, 8);
870 else
871 total = MIN(s->setup_len, 64);
872 s->setup_len -= total;
873 }
874 #endif
875
876 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
877 total, musb_rx_packet_complete, 1);
878 }
879
880 static uint8_t musb_read_fifo(MUSBEndPoint *ep)
881 {
882 uint8_t value;
883 if (ep->fifolen[1] >= 64) {
884 /* We have a FIFO underrun */
885 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
886 return 0x00000000;
887 }
888 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
889 * (if AUTOREQ is set) */
890
891 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
892 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
893 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
894 return value;
895 }
896
897 static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
898 {
899 TRACE("EP%d = %02x", ep->epnum, value);
900 if (ep->fifolen[0] >= 64) {
901 /* We have a FIFO overrun */
902 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
903 return;
904 }
905
906 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
907 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
908 }
909
910 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
911 {
912 if (ep->intv_timer[dir])
913 qemu_del_timer(ep->intv_timer[dir]);
914 }
915
916 /* Bus control */
917 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
918 {
919 MUSBState *s = (MUSBState *) opaque;
920
921 switch (addr) {
922 /* For USB2.0 HS hubs only */
923 case MUSB_HDRC_TXHUBADDR:
924 return s->ep[ep].haddr[0];
925 case MUSB_HDRC_TXHUBPORT:
926 return s->ep[ep].hport[0];
927 case MUSB_HDRC_RXHUBADDR:
928 return s->ep[ep].haddr[1];
929 case MUSB_HDRC_RXHUBPORT:
930 return s->ep[ep].hport[1];
931
932 default:
933 TRACE("unknown register 0x%02x", addr);
934 return 0x00;
935 };
936 }
937
938 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
939 {
940 MUSBState *s = (MUSBState *) opaque;
941
942 switch (addr) {
943 case MUSB_HDRC_TXFUNCADDR:
944 s->ep[ep].faddr[0] = value;
945 break;
946 case MUSB_HDRC_RXFUNCADDR:
947 s->ep[ep].faddr[1] = value;
948 break;
949 case MUSB_HDRC_TXHUBADDR:
950 s->ep[ep].haddr[0] = value;
951 break;
952 case MUSB_HDRC_TXHUBPORT:
953 s->ep[ep].hport[0] = value;
954 break;
955 case MUSB_HDRC_RXHUBADDR:
956 s->ep[ep].haddr[1] = value;
957 break;
958 case MUSB_HDRC_RXHUBPORT:
959 s->ep[ep].hport[1] = value;
960 break;
961
962 default:
963 TRACE("unknown register 0x%02x", addr);
964 break;
965 };
966 }
967
968 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
969 {
970 MUSBState *s = (MUSBState *) opaque;
971
972 switch (addr) {
973 case MUSB_HDRC_TXFUNCADDR:
974 return s->ep[ep].faddr[0];
975 case MUSB_HDRC_RXFUNCADDR:
976 return s->ep[ep].faddr[1];
977
978 default:
979 return musb_busctl_readb(s, ep, addr) |
980 (musb_busctl_readb(s, ep, addr | 1) << 8);
981 };
982 }
983
984 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
985 {
986 MUSBState *s = (MUSBState *) opaque;
987
988 switch (addr) {
989 case MUSB_HDRC_TXFUNCADDR:
990 s->ep[ep].faddr[0] = value;
991 break;
992 case MUSB_HDRC_RXFUNCADDR:
993 s->ep[ep].faddr[1] = value;
994 break;
995
996 default:
997 musb_busctl_writeb(s, ep, addr, value & 0xff);
998 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
999 };
1000 }
1001
1002 /* Endpoint control */
1003 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1004 {
1005 MUSBState *s = (MUSBState *) opaque;
1006
1007 switch (addr) {
1008 case MUSB_HDRC_TXTYPE:
1009 return s->ep[ep].type[0];
1010 case MUSB_HDRC_TXINTERVAL:
1011 return s->ep[ep].interval[0];
1012 case MUSB_HDRC_RXTYPE:
1013 return s->ep[ep].type[1];
1014 case MUSB_HDRC_RXINTERVAL:
1015 return s->ep[ep].interval[1];
1016 case (MUSB_HDRC_FIFOSIZE & ~1):
1017 return 0x00;
1018 case MUSB_HDRC_FIFOSIZE:
1019 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
1020 case MUSB_HDRC_RXCOUNT:
1021 return s->ep[ep].rxcount;
1022
1023 default:
1024 TRACE("unknown register 0x%02x", addr);
1025 return 0x00;
1026 };
1027 }
1028
1029 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1030 {
1031 MUSBState *s = (MUSBState *) opaque;
1032
1033 switch (addr) {
1034 case MUSB_HDRC_TXTYPE:
1035 s->ep[ep].type[0] = value;
1036 break;
1037 case MUSB_HDRC_TXINTERVAL:
1038 s->ep[ep].interval[0] = value;
1039 musb_ep_frame_cancel(&s->ep[ep], 0);
1040 break;
1041 case MUSB_HDRC_RXTYPE:
1042 s->ep[ep].type[1] = value;
1043 break;
1044 case MUSB_HDRC_RXINTERVAL:
1045 s->ep[ep].interval[1] = value;
1046 musb_ep_frame_cancel(&s->ep[ep], 1);
1047 break;
1048 case (MUSB_HDRC_FIFOSIZE & ~1):
1049 break;
1050 case MUSB_HDRC_FIFOSIZE:
1051 TRACE("somebody messes with fifosize (now %i bytes)", value);
1052 s->ep[ep].fifosize = value;
1053 break;
1054 default:
1055 TRACE("unknown register 0x%02x", addr);
1056 break;
1057 };
1058 }
1059
1060 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1061 {
1062 MUSBState *s = (MUSBState *) opaque;
1063 uint16_t ret;
1064
1065 switch (addr) {
1066 case MUSB_HDRC_TXMAXP:
1067 return s->ep[ep].maxp[0];
1068 case MUSB_HDRC_TXCSR:
1069 return s->ep[ep].csr[0];
1070 case MUSB_HDRC_RXMAXP:
1071 return s->ep[ep].maxp[1];
1072 case MUSB_HDRC_RXCSR:
1073 ret = s->ep[ep].csr[1];
1074
1075 /* TODO: This and other bits probably depend on
1076 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1077 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1078 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1079
1080 return ret;
1081 case MUSB_HDRC_RXCOUNT:
1082 return s->ep[ep].rxcount;
1083
1084 default:
1085 return musb_ep_readb(s, ep, addr) |
1086 (musb_ep_readb(s, ep, addr | 1) << 8);
1087 };
1088 }
1089
1090 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1091 {
1092 MUSBState *s = (MUSBState *) opaque;
1093
1094 switch (addr) {
1095 case MUSB_HDRC_TXMAXP:
1096 s->ep[ep].maxp[0] = value;
1097 break;
1098 case MUSB_HDRC_TXCSR:
1099 if (ep) {
1100 s->ep[ep].csr[0] &= value & 0xa6;
1101 s->ep[ep].csr[0] |= value & 0xff59;
1102 } else {
1103 s->ep[ep].csr[0] &= value & 0x85;
1104 s->ep[ep].csr[0] |= value & 0xf7a;
1105 }
1106
1107 musb_ep_frame_cancel(&s->ep[ep], 0);
1108
1109 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1110 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1111 s->ep[ep].fifolen[0] = 0;
1112 s->ep[ep].fifostart[0] = 0;
1113 if (ep)
1114 s->ep[ep].csr[0] &=
1115 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1116 else
1117 s->ep[ep].csr[0] &=
1118 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1119 }
1120 if (
1121 (ep &&
1122 #ifdef CLEAR_NAK
1123 (value & MGC_M_TXCSR_TXPKTRDY) &&
1124 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1125 #else
1126 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1127 #endif
1128 (!ep &&
1129 #ifdef CLEAR_NAK
1130 (value & MGC_M_CSR0_TXPKTRDY) &&
1131 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1132 #else
1133 (value & MGC_M_CSR0_TXPKTRDY)))
1134 #endif
1135 musb_tx_rdy(s, ep);
1136 if (!ep &&
1137 (value & MGC_M_CSR0_H_REQPKT) &&
1138 #ifdef CLEAR_NAK
1139 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1140 MGC_M_CSR0_RXPKTRDY)))
1141 #else
1142 !(value & MGC_M_CSR0_RXPKTRDY))
1143 #endif
1144 musb_rx_req(s, ep);
1145 break;
1146
1147 case MUSB_HDRC_RXMAXP:
1148 s->ep[ep].maxp[1] = value;
1149 break;
1150 case MUSB_HDRC_RXCSR:
1151 /* (DMA mode only) */
1152 if (
1153 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1154 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1155 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1156 value |= MGC_M_RXCSR_H_REQPKT;
1157
1158 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1159 s->ep[ep].csr[1] |= value & 0xfeb0;
1160
1161 musb_ep_frame_cancel(&s->ep[ep], 1);
1162
1163 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1164 s->ep[ep].fifolen[1] = 0;
1165 s->ep[ep].fifostart[1] = 0;
1166 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1167 /* If double buffering and we have two packets ready, flush
1168 * only the first one and set up the fifo at the second packet. */
1169 }
1170 #ifdef CLEAR_NAK
1171 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1172 #else
1173 if (value & MGC_M_RXCSR_H_REQPKT)
1174 #endif
1175 musb_rx_req(s, ep);
1176 break;
1177 case MUSB_HDRC_RXCOUNT:
1178 s->ep[ep].rxcount = value;
1179 break;
1180
1181 default:
1182 musb_ep_writeb(s, ep, addr, value & 0xff);
1183 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1184 };
1185 }
1186
1187 /* Generic control */
1188 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1189 {
1190 MUSBState *s = (MUSBState *) opaque;
1191 int ep, i;
1192 uint8_t ret;
1193
1194 switch (addr) {
1195 case MUSB_HDRC_FADDR:
1196 return s->faddr;
1197 case MUSB_HDRC_POWER:
1198 return s->power;
1199 case MUSB_HDRC_INTRUSB:
1200 ret = s->intr;
1201 for (i = 0; i < sizeof(ret) * 8; i ++)
1202 if (ret & (1 << i))
1203 musb_intr_set(s, i, 0);
1204 return ret;
1205 case MUSB_HDRC_INTRUSBE:
1206 return s->mask;
1207 case MUSB_HDRC_INDEX:
1208 return s->idx;
1209 case MUSB_HDRC_TESTMODE:
1210 return 0x00;
1211
1212 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1213 return musb_ep_readb(s, s->idx, addr & 0xf);
1214
1215 case MUSB_HDRC_DEVCTL:
1216 return s->devctl;
1217
1218 case MUSB_HDRC_TXFIFOSZ:
1219 case MUSB_HDRC_RXFIFOSZ:
1220 case MUSB_HDRC_VCTRL:
1221 /* TODO */
1222 return 0x00;
1223
1224 case MUSB_HDRC_HWVERS:
1225 return (1 << 10) | 400;
1226
1227 case (MUSB_HDRC_VCTRL | 1):
1228 case (MUSB_HDRC_HWVERS | 1):
1229 case (MUSB_HDRC_DEVCTL | 1):
1230 return 0x00;
1231
1232 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1233 ep = (addr >> 3) & 0xf;
1234 return musb_busctl_readb(s, ep, addr & 0x7);
1235
1236 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1237 ep = (addr >> 4) & 0xf;
1238 return musb_ep_readb(s, ep, addr & 0xf);
1239
1240 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1241 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1242 return musb_read_fifo(s->ep + ep);
1243
1244 default:
1245 TRACE("unknown register 0x%02x", (int) addr);
1246 return 0x00;
1247 };
1248 }
1249
1250 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1251 {
1252 MUSBState *s = (MUSBState *) opaque;
1253 int ep;
1254
1255 switch (addr) {
1256 case MUSB_HDRC_FADDR:
1257 s->faddr = value & 0x7f;
1258 break;
1259 case MUSB_HDRC_POWER:
1260 s->power = (value & 0xef) | (s->power & 0x10);
1261 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1262 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1263 usb_send_msg(s->port.dev, USB_MSG_RESET);
1264 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1265 if ((value & MGC_M_POWER_HSENAB) &&
1266 s->port.dev->speed == USB_SPEED_HIGH)
1267 s->power |= MGC_M_POWER_HSMODE; /* Success */
1268 /* Restart frame counting. */
1269 }
1270 if (value & MGC_M_POWER_SUSPENDM) {
1271 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1272 * is set, also go into low power mode. Frame counting stops. */
1273 /* XXX: Cleared when the interrupt register is read */
1274 }
1275 if (value & MGC_M_POWER_RESUME) {
1276 /* Wait 20ms and signal resuming on the bus. Frame counting
1277 * restarts. */
1278 }
1279 break;
1280 case MUSB_HDRC_INTRUSB:
1281 break;
1282 case MUSB_HDRC_INTRUSBE:
1283 s->mask = value & 0xff;
1284 break;
1285 case MUSB_HDRC_INDEX:
1286 s->idx = value & 0xf;
1287 break;
1288 case MUSB_HDRC_TESTMODE:
1289 break;
1290
1291 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1292 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1293 break;
1294
1295 case MUSB_HDRC_DEVCTL:
1296 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1297 musb_session_update(s,
1298 !!s->port.dev,
1299 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1300
1301 /* It seems this is the only R/W bit in this register? */
1302 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1303 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1304 break;
1305
1306 case MUSB_HDRC_TXFIFOSZ:
1307 case MUSB_HDRC_RXFIFOSZ:
1308 case MUSB_HDRC_VCTRL:
1309 /* TODO */
1310 break;
1311
1312 case (MUSB_HDRC_VCTRL | 1):
1313 case (MUSB_HDRC_DEVCTL | 1):
1314 break;
1315
1316 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1317 ep = (addr >> 3) & 0xf;
1318 musb_busctl_writeb(s, ep, addr & 0x7, value);
1319 break;
1320
1321 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1322 ep = (addr >> 4) & 0xf;
1323 musb_ep_writeb(s, ep, addr & 0xf, value);
1324 break;
1325
1326 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1327 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1328 musb_write_fifo(s->ep + ep, value & 0xff);
1329 break;
1330
1331 default:
1332 TRACE("unknown register 0x%02x", (int) addr);
1333 break;
1334 };
1335 }
1336
1337 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1338 {
1339 MUSBState *s = (MUSBState *) opaque;
1340 int ep, i;
1341 uint16_t ret;
1342
1343 switch (addr) {
1344 case MUSB_HDRC_INTRTX:
1345 ret = s->tx_intr;
1346 /* Auto clear */
1347 for (i = 0; i < sizeof(ret) * 8; i ++)
1348 if (ret & (1 << i))
1349 musb_tx_intr_set(s, i, 0);
1350 return ret;
1351 case MUSB_HDRC_INTRRX:
1352 ret = s->rx_intr;
1353 /* Auto clear */
1354 for (i = 0; i < sizeof(ret) * 8; i ++)
1355 if (ret & (1 << i))
1356 musb_rx_intr_set(s, i, 0);
1357 return ret;
1358 case MUSB_HDRC_INTRTXE:
1359 return s->tx_mask;
1360 case MUSB_HDRC_INTRRXE:
1361 return s->rx_mask;
1362
1363 case MUSB_HDRC_FRAME:
1364 /* TODO */
1365 return 0x0000;
1366 case MUSB_HDRC_TXFIFOADDR:
1367 return s->ep[s->idx].fifoaddr[0];
1368 case MUSB_HDRC_RXFIFOADDR:
1369 return s->ep[s->idx].fifoaddr[1];
1370
1371 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1372 return musb_ep_readh(s, s->idx, addr & 0xf);
1373
1374 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1375 ep = (addr >> 3) & 0xf;
1376 return musb_busctl_readh(s, ep, addr & 0x7);
1377
1378 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1379 ep = (addr >> 4) & 0xf;
1380 return musb_ep_readh(s, ep, addr & 0xf);
1381
1382 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1383 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1384 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1385
1386 default:
1387 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1388 };
1389 }
1390
1391 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1392 {
1393 MUSBState *s = (MUSBState *) opaque;
1394 int ep;
1395
1396 switch (addr) {
1397 case MUSB_HDRC_INTRTXE:
1398 s->tx_mask = value;
1399 /* XXX: the masks seem to apply on the raising edge like with
1400 * edge-triggered interrupts, thus no need to update. I may be
1401 * wrong though. */
1402 break;
1403 case MUSB_HDRC_INTRRXE:
1404 s->rx_mask = value;
1405 break;
1406
1407 case MUSB_HDRC_FRAME:
1408 /* TODO */
1409 break;
1410 case MUSB_HDRC_TXFIFOADDR:
1411 s->ep[s->idx].fifoaddr[0] = value;
1412 s->ep[s->idx].buf[0] =
1413 s->buf + ((value << 3) & 0x7ff );
1414 break;
1415 case MUSB_HDRC_RXFIFOADDR:
1416 s->ep[s->idx].fifoaddr[1] = value;
1417 s->ep[s->idx].buf[1] =
1418 s->buf + ((value << 3) & 0x7ff);
1419 break;
1420
1421 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1422 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1423 break;
1424
1425 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1426 ep = (addr >> 3) & 0xf;
1427 musb_busctl_writeh(s, ep, addr & 0x7, value);
1428 break;
1429
1430 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1431 ep = (addr >> 4) & 0xf;
1432 musb_ep_writeh(s, ep, addr & 0xf, value);
1433 break;
1434
1435 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1436 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1437 musb_write_fifo(s->ep + ep, value & 0xff);
1438 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1439 break;
1440
1441 default:
1442 musb_writeb(s, addr, value & 0xff);
1443 musb_writeb(s, addr | 1, value >> 8);
1444 };
1445 }
1446
1447 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1448 {
1449 MUSBState *s = (MUSBState *) opaque;
1450 int ep;
1451
1452 switch (addr) {
1453 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1454 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1455 return ( musb_read_fifo(s->ep + ep) |
1456 musb_read_fifo(s->ep + ep) << 8 |
1457 musb_read_fifo(s->ep + ep) << 16 |
1458 musb_read_fifo(s->ep + ep) << 24 );
1459 default:
1460 TRACE("unknown register 0x%02x", (int) addr);
1461 return 0x00000000;
1462 };
1463 }
1464
1465 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1466 {
1467 MUSBState *s = (MUSBState *) opaque;
1468 int ep;
1469
1470 switch (addr) {
1471 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1472 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1473 musb_write_fifo(s->ep + ep, value & 0xff);
1474 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1475 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1476 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
1477 break;
1478 default:
1479 TRACE("unknown register 0x%02x", (int) addr);
1480 break;
1481 };
1482 }
1483
1484 CPUReadMemoryFunc * const musb_read[] = {
1485 musb_readb,
1486 musb_readh,
1487 musb_readw,
1488 };
1489
1490 CPUWriteMemoryFunc * const musb_write[] = {
1491 musb_writeb,
1492 musb_writeh,
1493 musb_writew,
1494 };
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