target/sparc/cpu.h

   1 #ifndef SPARC_CPU_H
   2 #define SPARC_CPU_H
   3
   4 #include "qemu/bswap.h"
   5 #include "cpu-qom.h"
   6 #include "exec/cpu-defs.h"
   7 #include "qemu/cpu-float.h"
   8
   9 /*
  10  * From Oracle SPARC Architecture 2015:
  11  *
  12  *   Compatibility notes: The PSO memory model described in SPARC V8 and
  13  *   SPARC V9 compatibility architecture specifications was never implemented
  14  *   in a SPARC V9 implementation and is not included in the Oracle SPARC
  15  *   Architecture specification.
  16  *
  17  *   The RMO memory model described in the SPARC V9 specification was
  18  *   implemented in some non-Sun SPARC V9 implementations, but is not
  19  *   directly supported in Oracle SPARC Architecture 2015 implementations.
  20  *
  21  * Therefore always use TSO in QEMU.
  22  *
  23  * D.5 Specification of Partial Store Order (PSO)
  24  *   ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
  25  *
  26  * D.6 Specification of Total Store Order (TSO)
  27  *   ... PSO with the additional requirement that all [stores] are followed
  28  *   by an implied MEMBAR #StoreStore.
  29  */
  30 #define TCG_GUEST_DEFAULT_MO  (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
  31
  32 #if !defined(TARGET_SPARC64)
  33 #define TARGET_DPREGS 16
  34 #else
  35 #define TARGET_DPREGS 32
  36 #endif
  37
  38 /*#define EXCP_INTERRUPT 0x100*/
  39
  40 /* Windowed register indexes.  */
  41 enum {
  42     WREG_O0,
  43     WREG_O1,
  44     WREG_O2,
  45     WREG_O3,
  46     WREG_O4,
  47     WREG_O5,
  48     WREG_O6,
  49     WREG_O7,
  50
  51     WREG_L0,
  52     WREG_L1,
  53     WREG_L2,
  54     WREG_L3,
  55     WREG_L4,
  56     WREG_L5,
  57     WREG_L6,
  58     WREG_L7,
  59
  60     WREG_I0,
  61     WREG_I1,
  62     WREG_I2,
  63     WREG_I3,
  64     WREG_I4,
  65     WREG_I5,
  66     WREG_I6,
  67     WREG_I7,
  68
  69     WREG_SP = WREG_O6,
  70     WREG_FP = WREG_I6,
  71 };
  72
  73 /* trap definitions */
  74 #ifndef TARGET_SPARC64
  75 #define TT_TFAULT   0x01
  76 #define TT_ILL_INSN 0x02
  77 #define TT_PRIV_INSN 0x03
  78 #define TT_NFPU_INSN 0x04
  79 #define TT_WIN_OVF  0x05
  80 #define TT_WIN_UNF  0x06
  81 #define TT_UNALIGNED 0x07
  82 #define TT_FP_EXCP  0x08
  83 #define TT_DFAULT   0x09
  84 #define TT_TOVF     0x0a
  85 #define TT_EXTINT   0x10
  86 #define TT_CODE_ACCESS 0x21
  87 #define TT_UNIMP_FLUSH 0x25
  88 #define TT_DATA_ACCESS 0x29
  89 #define TT_DIV_ZERO 0x2a
  90 #define TT_NCP_INSN 0x24
  91 #define TT_TRAP     0x80
  92 #else
  93 #define TT_POWER_ON_RESET 0x01
  94 #define TT_TFAULT   0x08
  95 #define TT_CODE_ACCESS 0x0a
  96 #define TT_ILL_INSN 0x10
  97 #define TT_UNIMP_FLUSH TT_ILL_INSN
  98 #define TT_PRIV_INSN 0x11
  99 #define TT_NFPU_INSN 0x20
 100 #define TT_FP_EXCP  0x21
 101 #define TT_TOVF     0x23
 102 #define TT_CLRWIN   0x24
 103 #define TT_DIV_ZERO 0x28
 104 #define TT_DFAULT   0x30
 105 #define TT_DATA_ACCESS 0x32
 106 #define TT_UNALIGNED 0x34
 107 #define TT_PRIV_ACT 0x37
 108 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e
 109 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f
 110 #define TT_EXTINT   0x40
 111 #define TT_IVEC     0x60
 112 #define TT_TMISS    0x64
 113 #define TT_DMISS    0x68
 114 #define TT_DPROT    0x6c
 115 #define TT_SPILL    0x80
 116 #define TT_FILL     0xc0
 117 #define TT_WOTHER   (1 << 5)
 118 #define TT_TRAP     0x100
 119 #define TT_HTRAP    0x180
 120 #endif
 121
 122 #define PSR_NEG_SHIFT 23
 123 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
 124 #define PSR_ZERO_SHIFT 22
 125 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
 126 #define PSR_OVF_SHIFT 21
 127 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
 128 #define PSR_CARRY_SHIFT 20
 129 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
 130 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
 131 #if !defined(TARGET_SPARC64)
 132 #define PSR_EF    (1<<12)
 133 #define PSR_PIL   0xf00
 134 #define PSR_S     (1<<7)
 135 #define PSR_PS    (1<<6)
 136 #define PSR_ET    (1<<5)
 137 #define PSR_CWP   0x1f
 138 #endif
 139
 140 #define CC_SRC (env->cc_src)
 141 #define CC_SRC2 (env->cc_src2)
 142 #define CC_DST (env->cc_dst)
 143 #define CC_OP  (env->cc_op)
 144
 145 /* Even though lazy evaluation of CPU condition codes tends to be less
 146  * important on RISC systems where condition codes are only updated
 147  * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
 148  * condition codes.
 149  */
 150 enum {
 151     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 152     CC_OP_FLAGS,   /* all cc are back in status register */
 153     CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 154     CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 155     CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 156     CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 157     CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 158     CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 159     CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 160     CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 161     CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 162     CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 163     CC_OP_NB,
 164 };
 165
 166 /* Trap base register */
 167 #define TBR_BASE_MASK 0xfffff000
 168
 169 #if defined(TARGET_SPARC64)
 170 #define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 171 #define PS_IG    (1<<11) /* v9, zero on UA2007 */
 172 #define PS_MG    (1<<10) /* v9, zero on UA2007 */
 173 #define PS_CLE   (1<<9) /* UA2007 */
 174 #define PS_TLE   (1<<8) /* UA2007 */
 175 #define PS_RMO   (1<<7)
 176 #define PS_RED   (1<<5) /* v9, zero on UA2007 */
 177 #define PS_PEF   (1<<4) /* enable fpu */
 178 #define PS_AM    (1<<3) /* address mask */
 179 #define PS_PRIV  (1<<2)
 180 #define PS_IE    (1<<1)
 181 #define PS_AG    (1<<0) /* v9, zero on UA2007 */
 182
 183 #define FPRS_DL (1 << 0)
 184 #define FPRS_DU (1 << 1)
 185 #define FPRS_FEF (1 << 2)
 186
 187 #define HS_PRIV  (1<<2)
 188 #endif
 189
 190 /* Fcc */
 191 #define FSR_RD1        (1ULL << 31)
 192 #define FSR_RD0        (1ULL << 30)
 193 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 194 #define FSR_RD_NEAREST 0
 195 #define FSR_RD_ZERO    FSR_RD0
 196 #define FSR_RD_POS     FSR_RD1
 197 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 198
 199 #define FSR_NVM   (1ULL << 27)
 200 #define FSR_OFM   (1ULL << 26)
 201 #define FSR_UFM   (1ULL << 25)
 202 #define FSR_DZM   (1ULL << 24)
 203 #define FSR_NXM   (1ULL << 23)
 204 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 205
 206 #define FSR_NVA   (1ULL << 9)
 207 #define FSR_OFA   (1ULL << 8)
 208 #define FSR_UFA   (1ULL << 7)
 209 #define FSR_DZA   (1ULL << 6)
 210 #define FSR_NXA   (1ULL << 5)
 211 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 212
 213 #define FSR_NVC   (1ULL << 4)
 214 #define FSR_OFC   (1ULL << 3)
 215 #define FSR_UFC   (1ULL << 2)
 216 #define FSR_DZC   (1ULL << 1)
 217 #define FSR_NXC   (1ULL << 0)
 218 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 219
 220 #define FSR_FTT2   (1ULL << 16)
 221 #define FSR_FTT1   (1ULL << 15)
 222 #define FSR_FTT0   (1ULL << 14)
 223 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 224 #ifdef TARGET_SPARC64
 225 #define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 226 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 227 #define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 228 #define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 229 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 230 #else
 231 #define FSR_FTT_NMASK      0xfffe3fffULL
 232 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 233 #define FSR_LDFSR_OLDMASK  0x000fc000ULL
 234 #endif
 235 #define FSR_LDFSR_MASK     0xcfc00fffULL
 236 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
 237 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
 238 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
 239 #define FSR_FTT_INVAL_FPR (6ULL << 14)
 240
 241 #define FSR_FCC1_SHIFT 11
 242 #define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 243 #define FSR_FCC0_SHIFT 10
 244 #define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 245
 246 /* MMU */
 247 #define MMU_E     (1<<0)
 248 #define MMU_NF    (1<<1)
 249
 250 #define PTE_ENTRYTYPE_MASK 3
 251 #define PTE_ACCESS_MASK    0x1c
 252 #define PTE_ACCESS_SHIFT   2
 253 #define PTE_PPN_SHIFT      7
 254 #define PTE_ADDR_MASK      0xffffff00
 255
 256 #define PG_ACCESSED_BIT 5
 257 #define PG_MODIFIED_BIT 6
 258 #define PG_CACHE_BIT    7
 259
 260 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 261 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 262 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 263
 264 /* 3 <= NWINDOWS <= 32. */
 265 #define MIN_NWINDOWS 3
 266 #define MAX_NWINDOWS 32
 267
 268 #ifdef TARGET_SPARC64
 269 typedef struct trap_state {
 270     uint64_t tpc;
 271     uint64_t tnpc;
 272     uint64_t tstate;
 273     uint32_t tt;
 274 } trap_state;
 275 #endif
 276 #define TARGET_INSN_START_EXTRA_WORDS 1
 277
 278 struct sparc_def_t {
 279     const char *name;
 280     target_ulong iu_version;
 281     uint32_t fpu_version;
 282     uint32_t mmu_version;
 283     uint32_t mmu_bm;
 284     uint32_t mmu_ctpr_mask;
 285     uint32_t mmu_cxr_mask;
 286     uint32_t mmu_sfsr_mask;
 287     uint32_t mmu_trcr_mask;
 288     uint32_t mxcc_version;
 289     uint32_t features;
 290     uint32_t nwindows;
 291     uint32_t maxtl;
 292 };
 293
 294 #define FEATURE(X)  CPU_FEATURE_BIT_##X,
 295 enum {
 296 #include "cpu-feature.h.inc"
 297 };
 298
 299 #undef FEATURE
 300 #define FEATURE(X)  CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X,
 301
 302 enum {
 303 #include "cpu-feature.h.inc"
 304 };
 305
 306 #undef FEATURE
 307
 308 #ifndef TARGET_SPARC64
 309 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
 310                               CPU_FEATURE_FSMULD)
 311 #else
 312 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
 313                               CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \
 314                               CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2)
 315 enum {
 316     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 317     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 318     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 319     mmu_sun4v, // T1, T2
 320 };
 321 #endif
 322
 323 #define TTE_VALID_BIT       (1ULL << 63)
 324 #define TTE_NFO_BIT         (1ULL << 60)
 325 #define TTE_IE_BIT          (1ULL << 59)
 326 #define TTE_USED_BIT        (1ULL << 41)
 327 #define TTE_LOCKED_BIT      (1ULL <<  6)
 328 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 329 #define TTE_PRIV_BIT        (1ULL <<  2)
 330 #define TTE_W_OK_BIT        (1ULL <<  1)
 331 #define TTE_GLOBAL_BIT      (1ULL <<  0)
 332
 333 #define TTE_NFO_BIT_UA2005  (1ULL << 62)
 334 #define TTE_USED_BIT_UA2005 (1ULL << 47)
 335 #define TTE_LOCKED_BIT_UA2005 (1ULL <<  61)
 336 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL <<  11)
 337 #define TTE_PRIV_BIT_UA2005 (1ULL <<  8)
 338 #define TTE_W_OK_BIT_UA2005 (1ULL <<  6)
 339
 340 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 341 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 342 #define TTE_IS_IE(tte)      ((tte) & TTE_IE_BIT)
 343 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 344 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 345 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 346 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 347 #define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 348 #define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 349
 350 #define TTE_IS_NFO_UA2005(tte)     ((tte) & TTE_NFO_BIT_UA2005)
 351 #define TTE_IS_USED_UA2005(tte)    ((tte) & TTE_USED_BIT_UA2005)
 352 #define TTE_IS_LOCKED_UA2005(tte)  ((tte) & TTE_LOCKED_BIT_UA2005)
 353 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 354 #define TTE_IS_PRIV_UA2005(tte)    ((tte) & TTE_PRIV_BIT_UA2005)
 355 #define TTE_IS_W_OK_UA2005(tte)    ((tte) & TTE_W_OK_BIT_UA2005)
 356
 357 #define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 358
 359 #define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 360 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 361
 362 #define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 363 #define TTE_PGSIZE_UA2005(tte)     ((tte) & 7ULL)
 364 #define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 365
 366 /* UltraSPARC T1 specific */
 367 #define TLB_UST1_IS_REAL_BIT   (1ULL << 9)  /* Real translation entry */
 368 #define TLB_UST1_IS_SUN4V_BIT  (1ULL << 10) /* sun4u/sun4v TTE format switch */
 369
 370 #define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 371 #define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 372 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 373 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 374 #define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 375 #define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 376 #define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 377 #define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 378 #define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 379 #define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 380 #define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 381 #define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 382 #define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 383
 384 #define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 385 #define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 386 #define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 387 #define SFSR_CT_SECONDARY   (1ULL <<  4)
 388 #define SFSR_CT_NUCLEUS     (2ULL <<  4)
 389 #define SFSR_CT_NOTRANS     (3ULL <<  4)
 390 #define SFSR_CT_MASK        (3ULL <<  4)
 391
 392 /* Leon3 cache control */
 393
 394 /* Cache control: emulate the behavior of cache control registers but without
 395    any effect on the emulated */
 396
 397 #define CACHE_STATE_MASK 0x3
 398 #define CACHE_DISABLED   0x0
 399 #define CACHE_FROZEN     0x1
 400 #define CACHE_ENABLED    0x3
 401
 402 /* Cache Control register fields */
 403
 404 #define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
 405 #define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
 406 #define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
 407 #define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
 408 #define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
 409 #define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
 410 #define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
 411 #define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
 412
 413 #define CONVERT_BIT(X, SRC, DST) \
 414          (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
 415
 416 typedef struct SparcTLBEntry {
 417     uint64_t tag;
 418     uint64_t tte;
 419 } SparcTLBEntry;
 420
 421 struct CPUTimer
 422 {
 423     const char *name;
 424     uint32_t    frequency;
 425     uint32_t    disabled;
 426     uint64_t    disabled_mask;
 427     uint32_t    npt;
 428     uint64_t    npt_mask;
 429     int64_t     clock_offset;
 430     QEMUTimer  *qtimer;
 431 };
 432
 433 typedef struct CPUTimer CPUTimer;
 434
 435 typedef struct CPUArchState CPUSPARCState;
 436 #if defined(TARGET_SPARC64)
 437 typedef union {
 438    uint64_t mmuregs[16];
 439    struct {
 440     uint64_t tsb_tag_target;
 441     uint64_t mmu_primary_context;
 442     uint64_t mmu_secondary_context;
 443     uint64_t sfsr;
 444     uint64_t sfar;
 445     uint64_t tsb;
 446     uint64_t tag_access;
 447     uint64_t virtual_watchpoint;
 448     uint64_t physical_watchpoint;
 449     uint64_t sun4v_ctx_config[2];
 450     uint64_t sun4v_tsb_pointers[4];
 451    };
 452 } SparcV9MMU;
 453 #endif
 454 struct CPUArchState {
 455     target_ulong gregs[8]; /* general registers */
 456     target_ulong *regwptr; /* pointer to current register window */
 457     target_ulong pc;       /* program counter */
 458     target_ulong npc;      /* next program counter */
 459     target_ulong y;        /* multiply/divide register */
 460
 461     /* emulator internal flags handling */
 462     target_ulong cc_src, cc_src2;
 463     target_ulong cc_dst;
 464     uint32_t cc_op;
 465
 466     target_ulong cond; /* conditional branch result (XXX: save it in a
 467                           temporary register when possible) */
 468
 469     uint32_t psr;      /* processor state register */
 470     target_ulong fsr;      /* FPU state register */
 471     CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
 472     uint32_t cwp;      /* index of current register window (extracted
 473                           from PSR) */
 474 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 475     uint32_t wim;      /* window invalid mask */
 476 #endif
 477     target_ulong tbr;  /* trap base register */
 478 #if !defined(TARGET_SPARC64)
 479     int      psrs;     /* supervisor mode (extracted from PSR) */
 480     int      psrps;    /* previous supervisor mode */
 481     int      psret;    /* enable traps */
 482 #endif
 483     uint32_t psrpil;   /* interrupt blocking level */
 484     uint32_t pil_in;   /* incoming interrupt level bitmap */
 485 #if !defined(TARGET_SPARC64)
 486     int      psref;    /* enable fpu */
 487 #endif
 488     int interrupt_index;
 489     /* NOTE: we allow 8 more registers to handle wrapping */
 490     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 491
 492     /* Fields up to this point are cleared by a CPU reset */
 493     struct {} end_reset_fields;
 494
 495     /* Fields from here on are preserved across CPU reset. */
 496     target_ulong version;
 497     uint32_t nwindows;
 498
 499     /* MMU regs */
 500 #if defined(TARGET_SPARC64)
 501     uint64_t lsu;
 502 #define DMMU_E 0x8
 503 #define IMMU_E 0x4
 504     SparcV9MMU immu;
 505     SparcV9MMU dmmu;
 506     SparcTLBEntry itlb[64];
 507     SparcTLBEntry dtlb[64];
 508     uint32_t mmu_version;
 509 #else
 510     uint32_t mmuregs[32];
 511     uint64_t mxccdata[4];
 512     uint64_t mxccregs[8];
 513     uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 514     uint64_t mmubpaction;
 515     uint64_t mmubpregs[4];
 516     uint64_t prom_addr;
 517 #endif
 518     /* temporary float registers */
 519     float128 qt0, qt1;
 520     float_status fp_status;
 521 #if defined(TARGET_SPARC64)
 522 #define MAXTL_MAX 8
 523 #define MAXTL_MASK (MAXTL_MAX - 1)
 524     trap_state ts[MAXTL_MAX];
 525     uint32_t xcc;               /* Extended integer condition codes */
 526     uint32_t asi;
 527     uint32_t pstate;
 528     uint32_t tl;
 529     uint32_t maxtl;
 530     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 531     uint64_t agregs[8]; /* alternate general registers */
 532     uint64_t bgregs[8]; /* backup for normal global registers */
 533     uint64_t igregs[8]; /* interrupt general registers */
 534     uint64_t mgregs[8]; /* mmu general registers */
 535     uint64_t glregs[8 * MAXTL_MAX];
 536     uint32_t fprs;
 537     uint64_t tick_cmpr, stick_cmpr;
 538     CPUTimer *tick, *stick;
 539 #define TICK_NPT_MASK        0x8000000000000000ULL
 540 #define TICK_INT_DIS         0x8000000000000000ULL
 541     uint64_t gsr;
 542     uint32_t gl; // UA2005
 543     /* UA 2005 hyperprivileged registers */
 544     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 545     uint64_t scratch[8];
 546     CPUTimer *hstick; // UA 2005
 547     /* Interrupt vector registers */
 548     uint64_t ivec_status;
 549     uint64_t ivec_data[3];
 550     uint32_t softint;
 551 #define SOFTINT_TIMER   1
 552 #define SOFTINT_STIMER  (1 << 16)
 553 #define SOFTINT_INTRMASK (0xFFFE)
 554 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 555 #endif
 556     sparc_def_t def;
 557
 558     void *irq_manager;
 559     void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
 560
 561     /* Leon3 cache control */
 562     uint32_t cache_control;
 563 };
 564
 565 /**
 566  * SPARCCPU:
 567  * @env: #CPUSPARCState
 568  *
 569  * A SPARC CPU.
 570  */
 571 struct ArchCPU {
 572     /*< private >*/
 573     CPUState parent_obj;
 574     /*< public >*/
 575
 576     CPUSPARCState env;
 577 };
 578
 579
 580 #ifndef CONFIG_USER_ONLY
 581 extern const VMStateDescription vmstate_sparc_cpu;
 582
 583 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 584 #endif
 585
 586 void sparc_cpu_do_interrupt(CPUState *cpu);
 587 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 588 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 589 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 590                                               MMUAccessType access_type,
 591                                               int mmu_idx,
 592                                               uintptr_t retaddr);
 593 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t);
 594
 595 /* cpu_init.c */
 596 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 597 void sparc_cpu_list(void);
 598 /* mmu_helper.c */
 599 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 600                         MMUAccessType access_type, int mmu_idx,
 601                         bool probe, uintptr_t retaddr);
 602 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 603 void dump_mmu(CPUSPARCState *env);
 604
 605 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 606 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 607                               uint8_t *buf, int len, bool is_write);
 608 #endif
 609
 610
 611 /* translate.c */
 612 void sparc_tcg_init(void);
 613 void sparc_restore_state_to_opc(CPUState *cs,
 614                                 const TranslationBlock *tb,
 615                                 const uint64_t *data);
 616
 617 /* cpu-exec.c */
 618
 619 /* win_helper.c */
 620 target_ulong cpu_get_psr(CPUSPARCState *env1);
 621 void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
 622 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
 623 #ifdef TARGET_SPARC64
 624 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
 625 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
 626 #endif
 627 int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 628 int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
 629 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 630
 631 /* sun4m.c, sun4u.c */
 632 void cpu_check_irqs(CPUSPARCState *env);
 633
 634 #if defined (TARGET_SPARC64)
 635
 636 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 637 {
 638     return (x & mask) == (y & mask);
 639 }
 640
 641 #define MMU_CONTEXT_BITS 13
 642 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 643
 644 static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 645                                       uint64_t context)
 646 {
 647     return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 648 }
 649
 650 #endif
 651
 652 /* cpu-exec.c */
 653 #if !defined(CONFIG_USER_ONLY)
 654 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 655                                      vaddr addr, unsigned size,
 656                                      MMUAccessType access_type,
 657                                      int mmu_idx, MemTxAttrs attrs,
 658                                      MemTxResult response, uintptr_t retaddr);
 659 #if defined(TARGET_SPARC64)
 660 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 661                                            int mmu_idx);
 662 #endif
 663 #endif
 664
 665 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
 666 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 667 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
 668
 669 #define cpu_list sparc_cpu_list
 670
 671 /* MMU modes definitions */
 672 #if defined (TARGET_SPARC64)
 673 #define MMU_USER_IDX   0
 674 #define MMU_USER_SECONDARY_IDX   1
 675 #define MMU_KERNEL_IDX 2
 676 #define MMU_KERNEL_SECONDARY_IDX 3
 677 #define MMU_NUCLEUS_IDX 4
 678 #define MMU_PHYS_IDX   5
 679 #else
 680 #define MMU_USER_IDX   0
 681 #define MMU_KERNEL_IDX 1
 682 #define MMU_PHYS_IDX   2
 683 #endif
 684
 685 #if defined (TARGET_SPARC64)
 686 static inline int cpu_has_hypervisor(CPUSPARCState *env1)
 687 {
 688     return env1->def.features & CPU_FEATURE_HYPV;
 689 }
 690
 691 static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
 692 {
 693     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 694 }
 695
 696 static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 697 {
 698     return env1->pstate & PS_PRIV;
 699 }
 700 #else
 701 static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 702 {
 703     return env1->psrs;
 704 }
 705 #endif
 706
 707 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
 708 {
 709 #if defined(CONFIG_USER_ONLY)
 710     return MMU_USER_IDX;
 711 #elif !defined(TARGET_SPARC64)
 712     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 713         return MMU_PHYS_IDX;
 714     } else {
 715         return env->psrs;
 716     }
 717 #else
 718     /* IMMU or DMMU disabled.  */
 719     if (ifetch
 720         ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
 721         : (env->lsu & DMMU_E) == 0) {
 722         return MMU_PHYS_IDX;
 723     } else if (cpu_hypervisor_mode(env)) {
 724         return MMU_PHYS_IDX;
 725     } else if (env->tl > 0) {
 726         return MMU_NUCLEUS_IDX;
 727     } else if (cpu_supervisor_mode(env)) {
 728         return MMU_KERNEL_IDX;
 729     } else {
 730         return MMU_USER_IDX;
 731     }
 732 #endif
 733 }
 734
 735 static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
 736 {
 737 #if !defined (TARGET_SPARC64)
 738     if (env1->psret != 0)
 739         return 1;
 740 #else
 741     if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
 742         return 1;
 743     }
 744 #endif
 745
 746     return 0;
 747 }
 748
 749 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 750 {
 751 #if !defined(TARGET_SPARC64)
 752     /* level 15 is non-maskable on sparc v8 */
 753     return pil == 15 || pil > env1->psrpil;
 754 #else
 755     return pil > env1->psrpil;
 756 #endif
 757 }
 758
 759 #include "exec/cpu-all.h"
 760
 761 #ifdef TARGET_SPARC64
 762 /* sun4u.c */
 763 void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 764 uint64_t cpu_tick_get_count(CPUTimer *timer);
 765 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 766 trap_state* cpu_tsptr(CPUSPARCState* env);
 767 #endif
 768
 769 #define TB_FLAG_MMU_MASK     7
 770 #define TB_FLAG_FPU_ENABLED  (1 << 4)
 771 #define TB_FLAG_AM_ENABLED   (1 << 5)
 772 #define TB_FLAG_SUPER        (1 << 6)
 773 #define TB_FLAG_HYPER        (1 << 7)
 774 #define TB_FLAG_ASI_SHIFT    24
 775
 776 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
 777                                         uint64_t *cs_base, uint32_t *pflags)
 778 {
 779     uint32_t flags;
 780     *pc = env->pc;
 781     *cs_base = env->npc;
 782     flags = cpu_mmu_index(env, false);
 783 #ifndef CONFIG_USER_ONLY
 784     if (cpu_supervisor_mode(env)) {
 785         flags |= TB_FLAG_SUPER;
 786     }
 787 #endif
 788 #ifdef TARGET_SPARC64
 789 #ifndef CONFIG_USER_ONLY
 790     if (cpu_hypervisor_mode(env)) {
 791         flags |= TB_FLAG_HYPER;
 792     }
 793 #endif
 794     if (env->pstate & PS_AM) {
 795         flags |= TB_FLAG_AM_ENABLED;
 796     }
 797     if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
 798         flags |= TB_FLAG_FPU_ENABLED;
 799     }
 800     flags |= env->asi << TB_FLAG_ASI_SHIFT;
 801 #else
 802     if (env->psref) {
 803         flags |= TB_FLAG_FPU_ENABLED;
 804     }
 805 #endif
 806     *pflags = flags;
 807 }
 808
 809 static inline bool tb_fpu_enabled(int tb_flags)
 810 {
 811 #if defined(CONFIG_USER_ONLY)
 812     return true;
 813 #else
 814     return tb_flags & TB_FLAG_FPU_ENABLED;
 815 #endif
 816 }
 817
 818 static inline bool tb_am_enabled(int tb_flags)
 819 {
 820 #ifndef TARGET_SPARC64
 821     return false;
 822 #else
 823     return tb_flags & TB_FLAG_AM_ENABLED;
 824 #endif
 825 }
 826
 827 #ifdef TARGET_SPARC64
 828 /* win_helper.c */
 829 target_ulong cpu_get_ccr(CPUSPARCState *env1);
 830 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
 831 target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 832 void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 833
 834 static inline uint64_t sparc64_tstate(CPUSPARCState *env)
 835 {
 836     uint64_t tstate = (cpu_get_ccr(env) << 32) |
 837         ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
 838         cpu_get_cwp64(env);
 839
 840     if (env->def.features & CPU_FEATURE_GL) {
 841         tstate |= (env->gl & 7ULL) << 40;
 842     }
 843     return tstate;
 844 }
 845 #endif
 846
 847 #endif