hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2.1 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/southbridge/piix.h"
  25 #include "hw/irq.h"
  26 #include "hw/isa/apm.h"
  27 #include "hw/i2c/pm_smbus.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/acpi/acpi.h"
  31 #include "sysemu/runstate.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/xen.h"
  34 #include "qapi/error.h"
  35 #include "qemu/range.h"
  36 #include "hw/acpi/pcihp.h"
  37 #include "hw/acpi/cpu_hotplug.h"
  38 #include "hw/acpi/cpu.h"
  39 #include "hw/hotplug.h"
  40 #include "hw/mem/pc-dimm.h"
  41 #include "hw/mem/nvdimm.h"
  42 #include "hw/acpi/memory_hotplug.h"
  43 #include "hw/acpi/acpi_dev_interface.h"
  44 #include "migration/vmstate.h"
  45 #include "hw/core/cpu.h"
  46 #include "trace.h"
  47 #include "qom/object.h"
  48
  49 #define GPE_BASE 0xafe0
  50 #define GPE_LEN 4
  51
  52 #define ACPI_PCIHP_ADDR_PIIX4 0xae00
  53
  54 struct pci_status {
  55     uint32_t up; /* deprecated, maintained for migration compatibility */
  56     uint32_t down;
  57 };
  58
  59 struct PIIX4PMState {
  60     /*< private >*/
  61     PCIDevice parent_obj;
  62     /*< public >*/
  63
  64     MemoryRegion io;
  65     uint32_t io_base;
  66
  67     MemoryRegion io_gpe;
  68     ACPIREGS ar;
  69
  70     APMState apm;
  71
  72     PMSMBus smb;
  73     uint32_t smb_io_base;
  74
  75     qemu_irq irq;
  76     qemu_irq smi_irq;
  77     int smm_enabled;
  78     bool smm_compat;
  79     Notifier machine_ready;
  80     Notifier powerdown_notifier;
  81
  82     AcpiPciHpState acpi_pci_hotplug;
  83     bool use_acpi_hotplug_bridge;
  84     bool use_acpi_root_pci_hotplug;
  85     bool not_migrate_acpi_index;
  86
  87     uint8_t disable_s3;
  88     uint8_t disable_s4;
  89     uint8_t s4_val;
  90
  91     bool cpu_hotplug_legacy;
  92     AcpiCpuHotplug gpe_cpu;
  93     CPUHotplugState cpuhp_state;
  94
  95     MemHotplugState acpi_memory_hotplug;
  96 };
  97
  98 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
  99
 100 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 101                                            PCIBus *bus, PIIX4PMState *s);
 102
 103 #define ACPI_ENABLE 0xf1
 104 #define ACPI_DISABLE 0xf0
 105
 106 static void pm_tmr_timer(ACPIREGS *ar)
 107 {
 108     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 109     acpi_update_sci(&s->ar, s->irq);
 110 }
 111
 112 static void apm_ctrl_changed(uint32_t val, void *arg)
 113 {
 114     PIIX4PMState *s = arg;
 115     PCIDevice *d = PCI_DEVICE(s);
 116
 117     /* ACPI specs 3.0, 4.7.2.5 */
 118     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 119     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 120         return;
 121     }
 122
 123     if (d->config[0x5b] & (1 << 1)) {
 124         if (s->smi_irq) {
 125             qemu_irq_raise(s->smi_irq);
 126         }
 127     }
 128 }
 129
 130 static void pm_io_space_update(PIIX4PMState *s)
 131 {
 132     PCIDevice *d = PCI_DEVICE(s);
 133
 134     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 135     s->io_base &= 0xffc0;
 136
 137     memory_region_transaction_begin();
 138     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 139     memory_region_set_address(&s->io, s->io_base);
 140     memory_region_transaction_commit();
 141 }
 142
 143 static void smbus_io_space_update(PIIX4PMState *s)
 144 {
 145     PCIDevice *d = PCI_DEVICE(s);
 146
 147     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 148     s->smb_io_base &= 0xffc0;
 149
 150     memory_region_transaction_begin();
 151     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 152     memory_region_set_address(&s->smb.io, s->smb_io_base);
 153     memory_region_transaction_commit();
 154 }
 155
 156 static void pm_write_config(PCIDevice *d,
 157                             uint32_t address, uint32_t val, int len)
 158 {
 159     pci_default_write_config(d, address, val, len);
 160     if (range_covers_byte(address, len, 0x80) ||
 161         ranges_overlap(address, len, 0x40, 4)) {
 162         pm_io_space_update((PIIX4PMState *)d);
 163     }
 164     if (range_covers_byte(address, len, 0xd2) ||
 165         ranges_overlap(address, len, 0x90, 4)) {
 166         smbus_io_space_update((PIIX4PMState *)d);
 167     }
 168 }
 169
 170 static int vmstate_acpi_post_load(void *opaque, int version_id)
 171 {
 172     PIIX4PMState *s = opaque;
 173
 174     pm_io_space_update(s);
 175     smbus_io_space_update(s);
 176     return 0;
 177 }
 178
 179 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 180  {                                                                   \
 181      .name       = (stringify(_field)),                              \
 182      .version_id = 0,                                                \
 183      .info       = &vmstate_info_uint16,                             \
 184      .size       = sizeof(uint16_t),                                 \
 185      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 186      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 187  }
 188
 189 static const VMStateDescription vmstate_gpe = {
 190     .name = "gpe",
 191     .version_id = 1,
 192     .minimum_version_id = 1,
 193     .fields = (VMStateField[]) {
 194         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 195         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static const VMStateDescription vmstate_pci_status = {
 201     .name = "pci_status",
 202     .version_id = 1,
 203     .minimum_version_id = 1,
 204     .fields = (VMStateField[]) {
 205         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 206         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 207         VMSTATE_END_OF_LIST()
 208     }
 209 };
 210
 211 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id)
 212 {
 213     PIIX4PMState *s = opaque;
 214     return s->use_acpi_hotplug_bridge;
 215 }
 216
 217 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque,
 218                                                     int version_id)
 219 {
 220     PIIX4PMState *s = opaque;
 221     return !s->use_acpi_hotplug_bridge;
 222 }
 223
 224 static bool vmstate_test_use_memhp(void *opaque)
 225 {
 226     PIIX4PMState *s = opaque;
 227     return s->acpi_memory_hotplug.is_enabled;
 228 }
 229
 230 static const VMStateDescription vmstate_memhp_state = {
 231     .name = "piix4_pm/memhp",
 232     .version_id = 1,
 233     .minimum_version_id = 1,
 234     .needed = vmstate_test_use_memhp,
 235     .fields      = (VMStateField[]) {
 236         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 237         VMSTATE_END_OF_LIST()
 238     }
 239 };
 240
 241 static bool vmstate_test_use_cpuhp(void *opaque)
 242 {
 243     PIIX4PMState *s = opaque;
 244     return !s->cpu_hotplug_legacy;
 245 }
 246
 247 static int vmstate_cpuhp_pre_load(void *opaque)
 248 {
 249     Object *obj = OBJECT(opaque);
 250     object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
 251     return 0;
 252 }
 253
 254 static const VMStateDescription vmstate_cpuhp_state = {
 255     .name = "piix4_pm/cpuhp",
 256     .version_id = 1,
 257     .minimum_version_id = 1,
 258     .needed = vmstate_test_use_cpuhp,
 259     .pre_load = vmstate_cpuhp_pre_load,
 260     .fields      = (VMStateField[]) {
 261         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 262         VMSTATE_END_OF_LIST()
 263     }
 264 };
 265
 266 static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
 267 {
 268     return pm_smbus_vmstate_needed();
 269 }
 270
 271 /*
 272  * This is a fudge to turn off the acpi_index field,
 273  * whose test was always broken on piix4 with 6.2 and older machine types.
 274  */
 275 static bool vmstate_test_migrate_acpi_index(void *opaque, int version_id)
 276 {
 277     PIIX4PMState *s = PIIX4_PM(opaque);
 278     return s->use_acpi_hotplug_bridge && !s->not_migrate_acpi_index;
 279 }
 280
 281 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 282  * To support incoming qemu-kvm 1.2 migration, change version_id
 283  * and minimum_version_id to 2 below (which breaks migration from
 284  * qemu 1.2).
 285  *
 286  */
 287 static const VMStateDescription vmstate_acpi = {
 288     .name = "piix4_pm",
 289     .version_id = 3,
 290     .minimum_version_id = 3,
 291     .post_load = vmstate_acpi_post_load,
 292     .fields = (VMStateField[]) {
 293         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 294         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 295         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 296         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 297         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 298         VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
 299                             pmsmb_vmstate, PMSMBus),
 300         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 301         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 302         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 303         VMSTATE_STRUCT_TEST(
 304             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 305             PIIX4PMState,
 306             vmstate_test_no_use_acpi_hotplug_bridge,
 307             2, vmstate_pci_status,
 308             struct AcpiPciHpPciStatus),
 309         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 310                             vmstate_test_use_acpi_hotplug_bridge,
 311                             vmstate_test_migrate_acpi_index),
 312         VMSTATE_END_OF_LIST()
 313     },
 314     .subsections = (const VMStateDescription*[]) {
 315          &vmstate_memhp_state,
 316          &vmstate_cpuhp_state,
 317          NULL
 318     }
 319 };
 320
 321 static void piix4_pm_reset(DeviceState *dev)
 322 {
 323     PIIX4PMState *s = PIIX4_PM(dev);
 324     PCIDevice *d = PCI_DEVICE(s);
 325     uint8_t *pci_conf = d->config;
 326
 327     pci_conf[0x58] = 0;
 328     pci_conf[0x59] = 0;
 329     pci_conf[0x5a] = 0;
 330     pci_conf[0x5b] = 0;
 331
 332     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 333     pci_conf[0x80] = 0;
 334
 335     if (!s->smm_enabled) {
 336         /* Mark SMM as already inited (until KVM supports SMM). */
 337         pci_conf[0x5B] = 0x02;
 338     }
 339
 340     acpi_pm1_evt_reset(&s->ar);
 341     acpi_pm1_cnt_reset(&s->ar);
 342     acpi_pm_tmr_reset(&s->ar);
 343     acpi_gpe_reset(&s->ar);
 344     acpi_update_sci(&s->ar, s->irq);
 345
 346     pm_io_space_update(s);
 347     acpi_pcihp_reset(&s->acpi_pci_hotplug, !s->use_acpi_root_pci_hotplug);
 348 }
 349
 350 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 351 {
 352     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 353
 354     assert(s != NULL);
 355     acpi_pm1_evt_power_down(&s->ar);
 356 }
 357
 358 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
 359                                     DeviceState *dev, Error **errp)
 360 {
 361     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 362
 363     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 364         acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
 365     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 366         if (!s->acpi_memory_hotplug.is_enabled) {
 367             error_setg(errp,
 368                 "memory hotplug is not enabled: %s.memory-hotplug-support "
 369                 "is not set", object_get_typename(OBJECT(s)));
 370         }
 371     } else if (
 372                !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 373         error_setg(errp, "acpi: device pre plug request for not supported"
 374                    " device type: %s", object_get_typename(OBJECT(dev)));
 375     }
 376 }
 377
 378 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 379                                  DeviceState *dev, Error **errp)
 380 {
 381     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 382
 383     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 384         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 385             nvdimm_acpi_plug_cb(hotplug_dev, dev);
 386         } else {
 387             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 388                                 dev, errp);
 389         }
 390     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 391         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 392     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 393         if (s->cpu_hotplug_legacy) {
 394             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 395         } else {
 396             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 397         }
 398     } else {
 399         g_assert_not_reached();
 400     }
 401 }
 402
 403 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 404                                            DeviceState *dev, Error **errp)
 405 {
 406     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 407
 408     if (s->acpi_memory_hotplug.is_enabled &&
 409         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 410         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 411                                       dev, errp);
 412     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 413         acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
 414                                             dev, errp);
 415     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 416                !s->cpu_hotplug_legacy) {
 417         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 418     } else {
 419         error_setg(errp, "acpi: device unplug request for not supported device"
 420                    " type: %s", object_get_typename(OBJECT(dev)));
 421     }
 422 }
 423
 424 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 425                                    DeviceState *dev, Error **errp)
 426 {
 427     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 428
 429     if (s->acpi_memory_hotplug.is_enabled &&
 430         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 431         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 432     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 433         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 434                                     errp);
 435     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 436                !s->cpu_hotplug_legacy) {
 437         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 438     } else {
 439         error_setg(errp, "acpi: device unplug for not supported device"
 440                    " type: %s", object_get_typename(OBJECT(dev)));
 441     }
 442 }
 443
 444 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 445 {
 446     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 447     PCIDevice *d = PCI_DEVICE(s);
 448     MemoryRegion *io_as = pci_address_space_io(d);
 449     uint8_t *pci_conf;
 450
 451     pci_conf = d->config;
 452     pci_conf[0x5f] = 0x10 |
 453         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 454     pci_conf[0x63] = 0x60;
 455     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 456         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 457 }
 458
 459 static void piix4_pm_add_properties(PIIX4PMState *s)
 460 {
 461     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 462     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 463     static const uint32_t gpe0_blk = GPE_BASE;
 464     static const uint32_t gpe0_blk_len = GPE_LEN;
 465     static const uint16_t sci_int = 9;
 466
 467     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 468                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
 469     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 470                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
 471     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 472                                   &gpe0_blk, OBJ_PROP_FLAG_READ);
 473     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 474                                   &gpe0_blk_len, OBJ_PROP_FLAG_READ);
 475     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 476                                   &sci_int, OBJ_PROP_FLAG_READ);
 477     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 478                                   &s->io_base, OBJ_PROP_FLAG_READ);
 479 }
 480
 481 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 482 {
 483     PIIX4PMState *s = PIIX4_PM(dev);
 484     uint8_t *pci_conf;
 485
 486     pci_conf = dev->config;
 487     pci_conf[0x06] = 0x80;
 488     pci_conf[0x07] = 0x02;
 489     pci_conf[0x09] = 0x00;
 490     pci_conf[0x3d] = 0x01; // interrupt pin 1
 491
 492     /* APM */
 493     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 494
 495     if (!s->smm_enabled) {
 496         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 497          * support SMM mode. */
 498         pci_conf[0x5B] = 0x02;
 499     }
 500
 501     /* XXX: which specification is used ? The i82731AB has different
 502        mappings */
 503     pci_conf[0x90] = s->smb_io_base | 1;
 504     pci_conf[0x91] = s->smb_io_base >> 8;
 505     pci_conf[0xd2] = 0x09;
 506     pm_smbus_init(DEVICE(dev), &s->smb, true);
 507     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 508     memory_region_add_subregion(pci_address_space_io(dev),
 509                                 s->smb_io_base, &s->smb.io);
 510
 511     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 512     memory_region_set_enabled(&s->io, false);
 513     memory_region_add_subregion(pci_address_space_io(dev),
 514                                 0, &s->io);
 515
 516     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 517     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 518     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val,
 519                       !s->smm_compat && !s->smm_enabled);
 520     acpi_gpe_init(&s->ar, GPE_LEN);
 521
 522     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 523     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 524
 525     s->machine_ready.notify = piix4_pm_machine_ready;
 526     qemu_add_machine_init_done_notifier(&s->machine_ready);
 527
 528     piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
 529                                    pci_get_bus(dev), s);
 530     qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s));
 531
 532     piix4_pm_add_properties(s);
 533 }
 534
 535 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 536                       qemu_irq sci_irq, qemu_irq smi_irq,
 537                       int smm_enabled, DeviceState **piix4_pm)
 538 {
 539     PCIDevice *pci_dev;
 540     DeviceState *dev;
 541     PIIX4PMState *s;
 542
 543     pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
 544     dev = DEVICE(pci_dev);
 545     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 546     if (piix4_pm) {
 547         *piix4_pm = dev;
 548     }
 549
 550     s = PIIX4_PM(dev);
 551     s->irq = sci_irq;
 552     s->smi_irq = smi_irq;
 553     s->smm_enabled = smm_enabled;
 554     if (xen_enabled()) {
 555         s->use_acpi_hotplug_bridge = false;
 556     }
 557
 558     pci_realize_and_unref(pci_dev, bus, &error_fatal);
 559
 560     return s->smb.smbus;
 561 }
 562
 563 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 564 {
 565     PIIX4PMState *s = opaque;
 566     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 567
 568     trace_piix4_gpe_readb(addr, width, val);
 569     return val;
 570 }
 571
 572 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 573                        unsigned width)
 574 {
 575     PIIX4PMState *s = opaque;
 576
 577     trace_piix4_gpe_writeb(addr, width, val);
 578     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 579     acpi_update_sci(&s->ar, s->irq);
 580 }
 581
 582 static const MemoryRegionOps piix4_gpe_ops = {
 583     .read = gpe_readb,
 584     .write = gpe_writeb,
 585     .valid.min_access_size = 1,
 586     .valid.max_access_size = 4,
 587     .impl.min_access_size = 1,
 588     .impl.max_access_size = 1,
 589     .endianness = DEVICE_LITTLE_ENDIAN,
 590 };
 591
 592
 593 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 594 {
 595     PIIX4PMState *s = PIIX4_PM(obj);
 596
 597     return s->cpu_hotplug_legacy;
 598 }
 599
 600 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 601 {
 602     PIIX4PMState *s = PIIX4_PM(obj);
 603
 604     assert(!value);
 605     if (s->cpu_hotplug_legacy && value == false) {
 606         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 607                                    PIIX4_CPU_HOTPLUG_IO_BASE);
 608     }
 609     s->cpu_hotplug_legacy = value;
 610 }
 611
 612 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 613                                            PCIBus *bus, PIIX4PMState *s)
 614 {
 615     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 616                           "acpi-gpe0", GPE_LEN);
 617     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 618
 619     if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) {
 620         acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 621                         s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4);
 622     }
 623
 624     s->cpu_hotplug_legacy = true;
 625     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 626                              piix4_get_cpu_hotplug_legacy,
 627                              piix4_set_cpu_hotplug_legacy);
 628     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 629                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 630
 631     if (s->acpi_memory_hotplug.is_enabled) {
 632         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
 633                                  ACPI_MEMORY_HOTPLUG_BASE);
 634     }
 635 }
 636
 637 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 638 {
 639     PIIX4PMState *s = PIIX4_PM(adev);
 640
 641     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 642     if (!s->cpu_hotplug_legacy) {
 643         acpi_cpu_ospm_status(&s->cpuhp_state, list);
 644     }
 645 }
 646
 647 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 648 {
 649     PIIX4PMState *s = PIIX4_PM(adev);
 650
 651     acpi_send_gpe_event(&s->ar, s->irq, ev);
 652 }
 653
 654 static Property piix4_pm_properties[] = {
 655     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 656     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 657     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 658     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 659     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState,
 660                      use_acpi_hotplug_bridge, true),
 661     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState,
 662                      use_acpi_root_pci_hotplug, true),
 663     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 664                      acpi_memory_hotplug.is_enabled, true),
 665     DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
 666     DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState,
 667                       not_migrate_acpi_index, false),
 668     DEFINE_PROP_END_OF_LIST(),
 669 };
 670
 671 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 672 {
 673     DeviceClass *dc = DEVICE_CLASS(klass);
 674     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 675     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 676     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 677
 678     k->realize = piix4_pm_realize;
 679     k->config_write = pm_write_config;
 680     k->vendor_id = PCI_VENDOR_ID_INTEL;
 681     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 682     k->revision = 0x03;
 683     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 684     dc->reset = piix4_pm_reset;
 685     dc->desc = "PM";
 686     dc->vmsd = &vmstate_acpi;
 687     device_class_set_props(dc, piix4_pm_properties);
 688     /*
 689      * Reason: part of PIIX4 southbridge, needs to be wired up,
 690      * e.g. by mips_malta_init()
 691      */
 692     dc->user_creatable = false;
 693     dc->hotpluggable = false;
 694     hc->pre_plug = piix4_device_pre_plug_cb;
 695     hc->plug = piix4_device_plug_cb;
 696     hc->unplug_request = piix4_device_unplug_request_cb;
 697     hc->unplug = piix4_device_unplug_cb;
 698     adevc->ospm_status = piix4_ospm_status;
 699     adevc->send_event = piix4_send_gpe;
 700     adevc->madt_cpu = pc_madt_cpu_entry;
 701 }
 702
 703 static const TypeInfo piix4_pm_info = {
 704     .name          = TYPE_PIIX4_PM,
 705     .parent        = TYPE_PCI_DEVICE,
 706     .instance_size = sizeof(PIIX4PMState),
 707     .class_init    = piix4_pm_class_init,
 708     .interfaces = (InterfaceInfo[]) {
 709         { TYPE_HOTPLUG_HANDLER },
 710         { TYPE_ACPI_DEVICE_IF },
 711         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 712         { }
 713     }
 714 };
 715
 716 static void piix4_pm_register_types(void)
 717 {
 718     type_register_static(&piix4_pm_info);
 719 }
 720
 721 type_init(piix4_pm_register_types)