hw/usb-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw.h"
  29 #include "usb.h"
  30 #include "pci.h"
  31 #include "qemu-timer.h"
  32 #include "usb-uhci.h"
  33 #include "iov.h"
  34 #include "dma.h"
  35
  36 //#define DEBUG
  37 //#define DEBUG_DUMP_DATA
  38
  39 #define UHCI_CMD_FGR      (1 << 4)
  40 #define UHCI_CMD_EGSM     (1 << 3)
  41 #define UHCI_CMD_GRESET   (1 << 2)
  42 #define UHCI_CMD_HCRESET  (1 << 1)
  43 #define UHCI_CMD_RS       (1 << 0)
  44
  45 #define UHCI_STS_HCHALTED (1 << 5)
  46 #define UHCI_STS_HCPERR   (1 << 4)
  47 #define UHCI_STS_HSERR    (1 << 3)
  48 #define UHCI_STS_RD       (1 << 2)
  49 #define UHCI_STS_USBERR   (1 << 1)
  50 #define UHCI_STS_USBINT   (1 << 0)
  51
  52 #define TD_CTRL_SPD     (1 << 29)
  53 #define TD_CTRL_ERROR_SHIFT  27
  54 #define TD_CTRL_IOS     (1 << 25)
  55 #define TD_CTRL_IOC     (1 << 24)
  56 #define TD_CTRL_ACTIVE  (1 << 23)
  57 #define TD_CTRL_STALL   (1 << 22)
  58 #define TD_CTRL_BABBLE  (1 << 20)
  59 #define TD_CTRL_NAK     (1 << 19)
  60 #define TD_CTRL_TIMEOUT (1 << 18)
  61
  62 #define UHCI_PORT_SUSPEND (1 << 12)
  63 #define UHCI_PORT_RESET (1 << 9)
  64 #define UHCI_PORT_LSDA  (1 << 8)
  65 #define UHCI_PORT_RD    (1 << 6)
  66 #define UHCI_PORT_ENC   (1 << 3)
  67 #define UHCI_PORT_EN    (1 << 2)
  68 #define UHCI_PORT_CSC   (1 << 1)
  69 #define UHCI_PORT_CCS   (1 << 0)
  70
  71 #define UHCI_PORT_READ_ONLY    (0x1bb)
  72 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  73
  74 #define FRAME_TIMER_FREQ 1000
  75
  76 #define FRAME_MAX_LOOPS  256
  77
  78 #define NB_PORTS 2
  79
  80 #ifdef DEBUG
  81 #define DPRINTF printf
  82
  83 static const char *pid2str(int pid)
  84 {
  85     switch (pid) {
  86     case USB_TOKEN_SETUP: return "SETUP";
  87     case USB_TOKEN_IN:    return "IN";
  88     case USB_TOKEN_OUT:   return "OUT";
  89     }
  90     return "?";
  91 }
  92
  93 #else
  94 #define DPRINTF(...)
  95 #endif
  96
  97 typedef struct UHCIState UHCIState;
  98 typedef struct UHCIAsync UHCIAsync;
  99 typedef struct UHCIQueue UHCIQueue;
 100
 101 /*
 102  * Pending async transaction.
 103  * 'packet' must be the first field because completion
 104  * handler does "(UHCIAsync *) pkt" cast.
 105  */
 106
 107 struct UHCIAsync {
 108     USBPacket packet;
 109     QEMUSGList sgl;
 110     UHCIQueue *queue;
 111     QTAILQ_ENTRY(UHCIAsync) next;
 112     uint32_t  td;
 113     uint8_t   isoc;
 114     uint8_t   done;
 115 };
 116
 117 struct UHCIQueue {
 118     uint32_t  token;
 119     UHCIState *uhci;
 120     QTAILQ_ENTRY(UHCIQueue) next;
 121     QTAILQ_HEAD(, UHCIAsync) asyncs;
 122     int8_t    valid;
 123 };
 124
 125 typedef struct UHCIPort {
 126     USBPort port;
 127     uint16_t ctrl;
 128 } UHCIPort;
 129
 130 struct UHCIState {
 131     PCIDevice dev;
 132     MemoryRegion io_bar;
 133     USBBus bus; /* Note unused when we're a companion controller */
 134     uint16_t cmd; /* cmd register */
 135     uint16_t status;
 136     uint16_t intr; /* interrupt enable register */
 137     uint16_t frnum; /* frame number */
 138     uint32_t fl_base_addr; /* frame list base address */
 139     uint8_t sof_timing;
 140     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 141     int64_t expire_time;
 142     QEMUTimer *frame_timer;
 143     UHCIPort ports[NB_PORTS];
 144
 145     /* Interrupts that should be raised at the end of the current frame.  */
 146     uint32_t pending_int_mask;
 147
 148     /* Active packets */
 149     QTAILQ_HEAD(, UHCIQueue) queues;
 150     uint8_t num_ports_vmstate;
 151
 152     /* Properties */
 153     char *masterbus;
 154     uint32_t firstport;
 155 };
 156
 157 typedef struct UHCI_TD {
 158     uint32_t link;
 159     uint32_t ctrl; /* see TD_CTRL_xxx */
 160     uint32_t token;
 161     uint32_t buffer;
 162 } UHCI_TD;
 163
 164 typedef struct UHCI_QH {
 165     uint32_t link;
 166     uint32_t el_link;
 167 } UHCI_QH;
 168
 169 static inline int32_t uhci_queue_token(UHCI_TD *td)
 170 {
 171     /* covers ep, dev, pid -> identifies the endpoint */
 172     return td->token & 0x7ffff;
 173 }
 174
 175 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
 176 {
 177     uint32_t token = uhci_queue_token(td);
 178     UHCIQueue *queue;
 179
 180     QTAILQ_FOREACH(queue, &s->queues, next) {
 181         if (queue->token == token) {
 182             return queue;
 183         }
 184     }
 185
 186     queue = g_new0(UHCIQueue, 1);
 187     queue->uhci = s;
 188     queue->token = token;
 189     QTAILQ_INIT(&queue->asyncs);
 190     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 191     return queue;
 192 }
 193
 194 static void uhci_queue_free(UHCIQueue *queue)
 195 {
 196     UHCIState *s = queue->uhci;
 197
 198     QTAILQ_REMOVE(&s->queues, queue, next);
 199     g_free(queue);
 200 }
 201
 202 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue)
 203 {
 204     UHCIAsync *async = g_new0(UHCIAsync, 1);
 205
 206     async->queue = queue;
 207     usb_packet_init(&async->packet);
 208     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 209
 210     return async;
 211 }
 212
 213 static void uhci_async_free(UHCIAsync *async)
 214 {
 215     usb_packet_cleanup(&async->packet);
 216     qemu_sglist_destroy(&async->sgl);
 217     g_free(async);
 218 }
 219
 220 static void uhci_async_link(UHCIAsync *async)
 221 {
 222     UHCIQueue *queue = async->queue;
 223     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 224 }
 225
 226 static void uhci_async_unlink(UHCIAsync *async)
 227 {
 228     UHCIQueue *queue = async->queue;
 229     QTAILQ_REMOVE(&queue->asyncs, async, next);
 230 }
 231
 232 static void uhci_async_cancel(UHCIAsync *async)
 233 {
 234     DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
 235            async->td, async->token, async->done);
 236
 237     if (!async->done)
 238         usb_cancel_packet(&async->packet);
 239     uhci_async_free(async);
 240 }
 241
 242 /*
 243  * Mark all outstanding async packets as invalid.
 244  * This is used for canceling them when TDs are removed by the HCD.
 245  */
 246 static void uhci_async_validate_begin(UHCIState *s)
 247 {
 248     UHCIQueue *queue;
 249
 250     QTAILQ_FOREACH(queue, &s->queues, next) {
 251         queue->valid--;
 252     }
 253 }
 254
 255 /*
 256  * Cancel async packets that are no longer valid
 257  */
 258 static void uhci_async_validate_end(UHCIState *s)
 259 {
 260     UHCIQueue *queue, *n;
 261     UHCIAsync *async;
 262
 263     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 264         if (queue->valid > 0) {
 265             continue;
 266         }
 267         while (!QTAILQ_EMPTY(&queue->asyncs)) {
 268             async = QTAILQ_FIRST(&queue->asyncs);
 269             uhci_async_unlink(async);
 270             uhci_async_cancel(async);
 271         }
 272         uhci_queue_free(queue);
 273     }
 274 }
 275
 276 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 277 {
 278     UHCIQueue *queue;
 279     UHCIAsync *curr, *n;
 280
 281     QTAILQ_FOREACH(queue, &s->queues, next) {
 282         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 283             if (!usb_packet_is_inflight(&curr->packet) ||
 284                 curr->packet.ep->dev != dev) {
 285                 continue;
 286             }
 287             uhci_async_unlink(curr);
 288             uhci_async_cancel(curr);
 289         }
 290     }
 291 }
 292
 293 static void uhci_async_cancel_all(UHCIState *s)
 294 {
 295     UHCIQueue *queue;
 296     UHCIAsync *curr, *n;
 297
 298     QTAILQ_FOREACH(queue, &s->queues, next) {
 299         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 300             uhci_async_unlink(curr);
 301             uhci_async_cancel(curr);
 302         }
 303     }
 304 }
 305
 306 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
 307 {
 308     uint32_t token = uhci_queue_token(td);
 309     UHCIQueue *queue;
 310     UHCIAsync *async;
 311
 312     QTAILQ_FOREACH(queue, &s->queues, next) {
 313         if (queue->token == token) {
 314             break;
 315         }
 316     }
 317     if (queue == NULL) {
 318         return NULL;
 319     }
 320
 321     QTAILQ_FOREACH(async, &queue->asyncs, next) {
 322         if (async->td == addr) {
 323             return async;
 324         }
 325     }
 326
 327     return NULL;
 328 }
 329
 330 static void uhci_update_irq(UHCIState *s)
 331 {
 332     int level;
 333     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 334         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 335         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 336         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 337         (s->status & UHCI_STS_HSERR) ||
 338         (s->status & UHCI_STS_HCPERR)) {
 339         level = 1;
 340     } else {
 341         level = 0;
 342     }
 343     qemu_set_irq(s->dev.irq[3], level);
 344 }
 345
 346 static void uhci_reset(void *opaque)
 347 {
 348     UHCIState *s = opaque;
 349     uint8_t *pci_conf;
 350     int i;
 351     UHCIPort *port;
 352
 353     DPRINTF("uhci: full reset\n");
 354
 355     pci_conf = s->dev.config;
 356
 357     pci_conf[0x6a] = 0x01; /* usb clock */
 358     pci_conf[0x6b] = 0x00;
 359     s->cmd = 0;
 360     s->status = 0;
 361     s->status2 = 0;
 362     s->intr = 0;
 363     s->fl_base_addr = 0;
 364     s->sof_timing = 64;
 365
 366     for(i = 0; i < NB_PORTS; i++) {
 367         port = &s->ports[i];
 368         port->ctrl = 0x0080;
 369         if (port->port.dev && port->port.dev->attached) {
 370             usb_port_reset(&port->port);
 371         }
 372     }
 373
 374     uhci_async_cancel_all(s);
 375 }
 376
 377 static void uhci_pre_save(void *opaque)
 378 {
 379     UHCIState *s = opaque;
 380
 381     uhci_async_cancel_all(s);
 382 }
 383
 384 static const VMStateDescription vmstate_uhci_port = {
 385     .name = "uhci port",
 386     .version_id = 1,
 387     .minimum_version_id = 1,
 388     .minimum_version_id_old = 1,
 389     .fields      = (VMStateField []) {
 390         VMSTATE_UINT16(ctrl, UHCIPort),
 391         VMSTATE_END_OF_LIST()
 392     }
 393 };
 394
 395 static const VMStateDescription vmstate_uhci = {
 396     .name = "uhci",
 397     .version_id = 2,
 398     .minimum_version_id = 1,
 399     .minimum_version_id_old = 1,
 400     .pre_save = uhci_pre_save,
 401     .fields      = (VMStateField []) {
 402         VMSTATE_PCI_DEVICE(dev, UHCIState),
 403         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 404         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 405                              vmstate_uhci_port, UHCIPort),
 406         VMSTATE_UINT16(cmd, UHCIState),
 407         VMSTATE_UINT16(status, UHCIState),
 408         VMSTATE_UINT16(intr, UHCIState),
 409         VMSTATE_UINT16(frnum, UHCIState),
 410         VMSTATE_UINT32(fl_base_addr, UHCIState),
 411         VMSTATE_UINT8(sof_timing, UHCIState),
 412         VMSTATE_UINT8(status2, UHCIState),
 413         VMSTATE_TIMER(frame_timer, UHCIState),
 414         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 415         VMSTATE_END_OF_LIST()
 416     }
 417 };
 418
 419 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 420 {
 421     UHCIState *s = opaque;
 422
 423     addr &= 0x1f;
 424     switch(addr) {
 425     case 0x0c:
 426         s->sof_timing = val;
 427         break;
 428     }
 429 }
 430
 431 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 432 {
 433     UHCIState *s = opaque;
 434     uint32_t val;
 435
 436     addr &= 0x1f;
 437     switch(addr) {
 438     case 0x0c:
 439         val = s->sof_timing;
 440         break;
 441     default:
 442         val = 0xff;
 443         break;
 444     }
 445     return val;
 446 }
 447
 448 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 449 {
 450     UHCIState *s = opaque;
 451
 452     addr &= 0x1f;
 453     DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
 454
 455     switch(addr) {
 456     case 0x00:
 457         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 458             /* start frame processing */
 459             s->expire_time = qemu_get_clock_ns(vm_clock) +
 460                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 461             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 462             s->status &= ~UHCI_STS_HCHALTED;
 463         } else if (!(val & UHCI_CMD_RS)) {
 464             s->status |= UHCI_STS_HCHALTED;
 465         }
 466         if (val & UHCI_CMD_GRESET) {
 467             UHCIPort *port;
 468             int i;
 469
 470             /* send reset on the USB bus */
 471             for(i = 0; i < NB_PORTS; i++) {
 472                 port = &s->ports[i];
 473                 usb_device_reset(port->port.dev);
 474             }
 475             uhci_reset(s);
 476             return;
 477         }
 478         if (val & UHCI_CMD_HCRESET) {
 479             uhci_reset(s);
 480             return;
 481         }
 482         s->cmd = val;
 483         break;
 484     case 0x02:
 485         s->status &= ~val;
 486         /* XXX: the chip spec is not coherent, so we add a hidden
 487            register to distinguish between IOC and SPD */
 488         if (val & UHCI_STS_USBINT)
 489             s->status2 = 0;
 490         uhci_update_irq(s);
 491         break;
 492     case 0x04:
 493         s->intr = val;
 494         uhci_update_irq(s);
 495         break;
 496     case 0x06:
 497         if (s->status & UHCI_STS_HCHALTED)
 498             s->frnum = val & 0x7ff;
 499         break;
 500     case 0x10 ... 0x1f:
 501         {
 502             UHCIPort *port;
 503             USBDevice *dev;
 504             int n;
 505
 506             n = (addr >> 1) & 7;
 507             if (n >= NB_PORTS)
 508                 return;
 509             port = &s->ports[n];
 510             dev = port->port.dev;
 511             if (dev && dev->attached) {
 512                 /* port reset */
 513                 if ( (val & UHCI_PORT_RESET) &&
 514                      !(port->ctrl & UHCI_PORT_RESET) ) {
 515                     usb_device_reset(dev);
 516                 }
 517             }
 518             port->ctrl &= UHCI_PORT_READ_ONLY;
 519             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 520             /* some bits are reset when a '1' is written to them */
 521             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 522         }
 523         break;
 524     }
 525 }
 526
 527 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 528 {
 529     UHCIState *s = opaque;
 530     uint32_t val;
 531
 532     addr &= 0x1f;
 533     switch(addr) {
 534     case 0x00:
 535         val = s->cmd;
 536         break;
 537     case 0x02:
 538         val = s->status;
 539         break;
 540     case 0x04:
 541         val = s->intr;
 542         break;
 543     case 0x06:
 544         val = s->frnum;
 545         break;
 546     case 0x10 ... 0x1f:
 547         {
 548             UHCIPort *port;
 549             int n;
 550             n = (addr >> 1) & 7;
 551             if (n >= NB_PORTS)
 552                 goto read_default;
 553             port = &s->ports[n];
 554             val = port->ctrl;
 555         }
 556         break;
 557     default:
 558     read_default:
 559         val = 0xff7f; /* disabled port */
 560         break;
 561     }
 562
 563     DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
 564
 565     return val;
 566 }
 567
 568 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 569 {
 570     UHCIState *s = opaque;
 571
 572     addr &= 0x1f;
 573     DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
 574
 575     switch(addr) {
 576     case 0x08:
 577         s->fl_base_addr = val & ~0xfff;
 578         break;
 579     }
 580 }
 581
 582 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 583 {
 584     UHCIState *s = opaque;
 585     uint32_t val;
 586
 587     addr &= 0x1f;
 588     switch(addr) {
 589     case 0x08:
 590         val = s->fl_base_addr;
 591         break;
 592     default:
 593         val = 0xffffffff;
 594         break;
 595     }
 596     return val;
 597 }
 598
 599 /* signal resume if controller suspended */
 600 static void uhci_resume (void *opaque)
 601 {
 602     UHCIState *s = (UHCIState *)opaque;
 603
 604     if (!s)
 605         return;
 606
 607     if (s->cmd & UHCI_CMD_EGSM) {
 608         s->cmd |= UHCI_CMD_FGR;
 609         s->status |= UHCI_STS_RD;
 610         uhci_update_irq(s);
 611     }
 612 }
 613
 614 static void uhci_attach(USBPort *port1)
 615 {
 616     UHCIState *s = port1->opaque;
 617     UHCIPort *port = &s->ports[port1->index];
 618
 619     /* set connect status */
 620     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 621
 622     /* update speed */
 623     if (port->port.dev->speed == USB_SPEED_LOW) {
 624         port->ctrl |= UHCI_PORT_LSDA;
 625     } else {
 626         port->ctrl &= ~UHCI_PORT_LSDA;
 627     }
 628
 629     uhci_resume(s);
 630 }
 631
 632 static void uhci_detach(USBPort *port1)
 633 {
 634     UHCIState *s = port1->opaque;
 635     UHCIPort *port = &s->ports[port1->index];
 636
 637     uhci_async_cancel_device(s, port1->dev);
 638
 639     /* set connect status */
 640     if (port->ctrl & UHCI_PORT_CCS) {
 641         port->ctrl &= ~UHCI_PORT_CCS;
 642         port->ctrl |= UHCI_PORT_CSC;
 643     }
 644     /* disable port */
 645     if (port->ctrl & UHCI_PORT_EN) {
 646         port->ctrl &= ~UHCI_PORT_EN;
 647         port->ctrl |= UHCI_PORT_ENC;
 648     }
 649
 650     uhci_resume(s);
 651 }
 652
 653 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 654 {
 655     UHCIState *s = port1->opaque;
 656
 657     uhci_async_cancel_device(s, child);
 658 }
 659
 660 static void uhci_wakeup(USBPort *port1)
 661 {
 662     UHCIState *s = port1->opaque;
 663     UHCIPort *port = &s->ports[port1->index];
 664
 665     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 666         port->ctrl |= UHCI_PORT_RD;
 667         uhci_resume(s);
 668     }
 669 }
 670
 671 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 672 {
 673     USBDevice *dev;
 674     int i;
 675
 676     for (i = 0; i < NB_PORTS; i++) {
 677         UHCIPort *port = &s->ports[i];
 678         if (!(port->ctrl & UHCI_PORT_EN)) {
 679             continue;
 680         }
 681         dev = usb_find_device(&port->port, addr);
 682         if (dev != NULL) {
 683             return dev;
 684         }
 685     }
 686     return NULL;
 687 }
 688
 689 static void uhci_async_complete(USBPort *port, USBPacket *packet);
 690 static void uhci_process_frame(UHCIState *s);
 691
 692 /* return -1 if fatal error (frame must be stopped)
 693           0 if TD successful
 694           1 if TD unsuccessful or inactive
 695 */
 696 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 697 {
 698     int len = 0, max_len, err, ret;
 699     uint8_t pid;
 700
 701     max_len = ((td->token >> 21) + 1) & 0x7ff;
 702     pid = td->token & 0xff;
 703
 704     ret = async->packet.result;
 705
 706     if (td->ctrl & TD_CTRL_IOS)
 707         td->ctrl &= ~TD_CTRL_ACTIVE;
 708
 709     if (ret < 0)
 710         goto out;
 711
 712     len = async->packet.result;
 713     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 714
 715     /* The NAK bit may have been set by a previous frame, so clear it
 716        here.  The docs are somewhat unclear, but win2k relies on this
 717        behavior.  */
 718     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 719     if (td->ctrl & TD_CTRL_IOC)
 720         *int_mask |= 0x01;
 721
 722     if (pid == USB_TOKEN_IN) {
 723         if (len > max_len) {
 724             ret = USB_RET_BABBLE;
 725             goto out;
 726         }
 727
 728         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 729             *int_mask |= 0x02;
 730             /* short packet: do not update QH */
 731             DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
 732             return 1;
 733         }
 734     }
 735
 736     /* success */
 737     return 0;
 738
 739 out:
 740     switch(ret) {
 741     case USB_RET_STALL:
 742         td->ctrl |= TD_CTRL_STALL;
 743         td->ctrl &= ~TD_CTRL_ACTIVE;
 744         s->status |= UHCI_STS_USBERR;
 745         if (td->ctrl & TD_CTRL_IOC) {
 746             *int_mask |= 0x01;
 747         }
 748         uhci_update_irq(s);
 749         return 1;
 750
 751     case USB_RET_BABBLE:
 752         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 753         td->ctrl &= ~TD_CTRL_ACTIVE;
 754         s->status |= UHCI_STS_USBERR;
 755         if (td->ctrl & TD_CTRL_IOC) {
 756             *int_mask |= 0x01;
 757         }
 758         uhci_update_irq(s);
 759         /* frame interrupted */
 760         return -1;
 761
 762     case USB_RET_NAK:
 763         td->ctrl |= TD_CTRL_NAK;
 764         if (pid == USB_TOKEN_SETUP)
 765             break;
 766         return 1;
 767
 768     case USB_RET_NODEV:
 769     default:
 770         break;
 771     }
 772
 773     /* Retry the TD if error count is not zero */
 774
 775     td->ctrl |= TD_CTRL_TIMEOUT;
 776     err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
 777     if (err != 0) {
 778         err--;
 779         if (err == 0) {
 780             td->ctrl &= ~TD_CTRL_ACTIVE;
 781             s->status |= UHCI_STS_USBERR;
 782             if (td->ctrl & TD_CTRL_IOC)
 783                 *int_mask |= 0x01;
 784             uhci_update_irq(s);
 785         }
 786     }
 787     td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
 788         (err << TD_CTRL_ERROR_SHIFT);
 789     return 1;
 790 }
 791
 792 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask)
 793 {
 794     UHCIAsync *async;
 795     int len = 0, max_len;
 796     uint8_t pid;
 797     USBDevice *dev;
 798     USBEndpoint *ep;
 799
 800     /* Is active ? */
 801     if (!(td->ctrl & TD_CTRL_ACTIVE))
 802         return 1;
 803
 804     async = uhci_async_find_td(s, addr, td);
 805     if (async) {
 806         /* Already submitted */
 807         async->queue->valid = 32;
 808
 809         if (!async->done)
 810             return 1;
 811
 812         uhci_async_unlink(async);
 813         goto done;
 814     }
 815
 816     /* Allocate new packet */
 817     async = uhci_async_alloc(uhci_queue_get(s, td));
 818     if (!async)
 819         return 1;
 820
 821     /* valid needs to be large enough to handle 10 frame delay
 822      * for initial isochronous requests
 823      */
 824     async->queue->valid = 32;
 825     async->td    = addr;
 826     async->isoc  = td->ctrl & TD_CTRL_IOS;
 827
 828     max_len = ((td->token >> 21) + 1) & 0x7ff;
 829     pid = td->token & 0xff;
 830
 831     dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 832     ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 833     usb_packet_setup(&async->packet, pid, ep);
 834     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 835     usb_packet_map(&async->packet, &async->sgl);
 836
 837     switch(pid) {
 838     case USB_TOKEN_OUT:
 839     case USB_TOKEN_SETUP:
 840         len = usb_handle_packet(dev, &async->packet);
 841         if (len >= 0)
 842             len = max_len;
 843         break;
 844
 845     case USB_TOKEN_IN:
 846         len = usb_handle_packet(dev, &async->packet);
 847         break;
 848
 849     default:
 850         /* invalid pid : frame interrupted */
 851         uhci_async_free(async);
 852         s->status |= UHCI_STS_HCPERR;
 853         uhci_update_irq(s);
 854         return -1;
 855     }
 856
 857     if (len == USB_RET_ASYNC) {
 858         uhci_async_link(async);
 859         return 2;
 860     }
 861
 862     async->packet.result = len;
 863
 864 done:
 865     len = uhci_complete_td(s, td, async, int_mask);
 866     usb_packet_unmap(&async->packet);
 867     uhci_async_free(async);
 868     return len;
 869 }
 870
 871 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 872 {
 873     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 874     UHCIState *s = async->queue->uhci;
 875
 876     DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
 877
 878     if (async->isoc) {
 879         UHCI_TD td;
 880         uint32_t link = async->td;
 881         uint32_t int_mask = 0, val;
 882
 883         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
 884         le32_to_cpus(&td.link);
 885         le32_to_cpus(&td.ctrl);
 886         le32_to_cpus(&td.token);
 887         le32_to_cpus(&td.buffer);
 888
 889         uhci_async_unlink(async);
 890         uhci_complete_td(s, &td, async, &int_mask);
 891         s->pending_int_mask |= int_mask;
 892
 893         /* update the status bits of the TD */
 894         val = cpu_to_le32(td.ctrl);
 895         pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
 896         uhci_async_free(async);
 897     } else {
 898         async->done = 1;
 899         uhci_process_frame(s);
 900     }
 901 }
 902
 903 static int is_valid(uint32_t link)
 904 {
 905     return (link & 1) == 0;
 906 }
 907
 908 static int is_qh(uint32_t link)
 909 {
 910     return (link & 2) != 0;
 911 }
 912
 913 static int depth_first(uint32_t link)
 914 {
 915     return (link & 4) != 0;
 916 }
 917
 918 /* QH DB used for detecting QH loops */
 919 #define UHCI_MAX_QUEUES 128
 920 typedef struct {
 921     uint32_t addr[UHCI_MAX_QUEUES];
 922     int      count;
 923 } QhDb;
 924
 925 static void qhdb_reset(QhDb *db)
 926 {
 927     db->count = 0;
 928 }
 929
 930 /* Add QH to DB. Returns 1 if already present or DB is full. */
 931 static int qhdb_insert(QhDb *db, uint32_t addr)
 932 {
 933     int i;
 934     for (i = 0; i < db->count; i++)
 935         if (db->addr[i] == addr)
 936             return 1;
 937
 938     if (db->count >= UHCI_MAX_QUEUES)
 939         return 1;
 940
 941     db->addr[db->count++] = addr;
 942     return 0;
 943 }
 944
 945 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td)
 946 {
 947     uint32_t int_mask = 0;
 948     uint32_t plink = td->link;
 949     uint32_t token = uhci_queue_token(td);
 950     UHCI_TD ptd;
 951     int ret;
 952
 953     fprintf(stderr, "%s: -- %x\n", __func__, token);
 954     while (is_valid(plink)) {
 955         pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd));
 956         le32_to_cpus(&ptd.link);
 957         le32_to_cpus(&ptd.ctrl);
 958         le32_to_cpus(&ptd.token);
 959         le32_to_cpus(&ptd.buffer);
 960         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 961             break;
 962         }
 963         if (uhci_queue_token(&ptd) != token) {
 964             break;
 965         }
 966         ret = uhci_handle_td(s, plink, &ptd, &int_mask);
 967         assert(ret == 2); /* got USB_RET_ASYNC */
 968         assert(int_mask == 0);
 969         plink = ptd.link;
 970     }
 971 }
 972
 973 static void uhci_process_frame(UHCIState *s)
 974 {
 975     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
 976     uint32_t curr_qh, td_count = 0, bytes_count = 0;
 977     int cnt, ret;
 978     UHCI_TD td;
 979     UHCI_QH qh;
 980     QhDb qhdb;
 981
 982     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
 983
 984     DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
 985
 986     pci_dma_read(&s->dev, frame_addr, &link, 4);
 987     le32_to_cpus(&link);
 988
 989     int_mask = 0;
 990     curr_qh  = 0;
 991
 992     qhdb_reset(&qhdb);
 993
 994     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
 995         if (is_qh(link)) {
 996             /* QH */
 997
 998             if (qhdb_insert(&qhdb, link)) {
 999                 /*
1000                  * We're going in circles. Which is not a bug because
1001                  * HCD is allowed to do that as part of the BW management.
1002                  *
1003                  * Stop processing here if
1004                  *  (a) no transaction has been done since we've been
1005                  *      here last time, or
1006                  *  (b) we've reached the usb 1.1 bandwidth, which is
1007                  *      1280 bytes/frame.
1008                  */
1009                 DPRINTF("uhci: detected loop. qh 0x%x\n", link);
1010                 if (td_count == 0) {
1011                     DPRINTF("uhci: no transaction last round, stop\n");
1012                     break;
1013                 } else if (bytes_count >= 1280) {
1014                     DPRINTF("uhci: bandwidth limit reached, stop\n");
1015                     break;
1016                 } else {
1017                     td_count = 0;
1018                     qhdb_reset(&qhdb);
1019                     qhdb_insert(&qhdb, link);
1020                 }
1021             }
1022
1023             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1024             le32_to_cpus(&qh.link);
1025             le32_to_cpus(&qh.el_link);
1026
1027             DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
1028                     link, qh.link, qh.el_link);
1029
1030             if (!is_valid(qh.el_link)) {
1031                 /* QH w/o elements */
1032                 curr_qh = 0;
1033                 link = qh.link;
1034             } else {
1035                 /* QH with elements */
1036                 curr_qh = link;
1037                 link = qh.el_link;
1038             }
1039             continue;
1040         }
1041
1042         /* TD */
1043         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
1044         le32_to_cpus(&td.link);
1045         le32_to_cpus(&td.ctrl);
1046         le32_to_cpus(&td.token);
1047         le32_to_cpus(&td.buffer);
1048
1049         DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1050                 link, td.link, td.ctrl, td.token, curr_qh);
1051
1052         old_td_ctrl = td.ctrl;
1053         ret = uhci_handle_td(s, link, &td, &int_mask);
1054         if (old_td_ctrl != td.ctrl) {
1055             /* update the status bits of the TD */
1056             val = cpu_to_le32(td.ctrl);
1057             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1058         }
1059
1060         switch (ret) {
1061         case -1: /* interrupted frame */
1062             goto out;
1063
1064         case 1: /* goto next queue */
1065             DPRINTF("uhci: TD 0x%x skip. "
1066                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1067                     link, td.link, td.ctrl, td.token, curr_qh);
1068             link = curr_qh ? qh.link : td.link;
1069             continue;
1070
1071         case 2: /* got USB_RET_ASYNC */
1072             DPRINTF("uhci: TD 0x%x async. "
1073                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1074                     link, td.link, td.ctrl, td.token, curr_qh);
1075             if (is_valid(td.link)) {
1076                 uhci_fill_queue(s, &td);
1077             }
1078             link = curr_qh ? qh.link : td.link;
1079             continue;
1080
1081         case 0: /* completed TD */
1082             DPRINTF("uhci: TD 0x%x done. "
1083                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1084                     link, td.link, td.ctrl, td.token, curr_qh);
1085
1086             link = td.link;
1087             td_count++;
1088             bytes_count += (td.ctrl & 0x7ff) + 1;
1089
1090             if (curr_qh) {
1091                 /* update QH element link */
1092                 qh.el_link = link;
1093                 val = cpu_to_le32(qh.el_link);
1094                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1095
1096                 if (!depth_first(link)) {
1097                     /* done with this QH */
1098
1099                     DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
1100                             curr_qh, qh.link, qh.el_link);
1101
1102                     curr_qh = 0;
1103                     link    = qh.link;
1104                 }
1105             }
1106             break;
1107
1108         default:
1109             assert(!"unknown return code");
1110         }
1111
1112         /* go to the next entry */
1113     }
1114
1115 out:
1116     s->pending_int_mask |= int_mask;
1117 }
1118
1119 static void uhci_frame_timer(void *opaque)
1120 {
1121     UHCIState *s = opaque;
1122
1123     /* prepare the timer for the next frame */
1124     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1125
1126     if (!(s->cmd & UHCI_CMD_RS)) {
1127         /* Full stop */
1128         qemu_del_timer(s->frame_timer);
1129         /* set hchalted bit in status - UHCI11D 2.1.2 */
1130         s->status |= UHCI_STS_HCHALTED;
1131
1132         DPRINTF("uhci: halted\n");
1133         return;
1134     }
1135
1136     /* Complete the previous frame */
1137     if (s->pending_int_mask) {
1138         s->status2 |= s->pending_int_mask;
1139         s->status  |= UHCI_STS_USBINT;
1140         uhci_update_irq(s);
1141     }
1142     s->pending_int_mask = 0;
1143
1144     /* Start new frame */
1145     s->frnum = (s->frnum + 1) & 0x7ff;
1146
1147     DPRINTF("uhci: new frame #%u\n" , s->frnum);
1148
1149     uhci_async_validate_begin(s);
1150
1151     uhci_process_frame(s);
1152
1153     uhci_async_validate_end(s);
1154
1155     qemu_mod_timer(s->frame_timer, s->expire_time);
1156 }
1157
1158 static const MemoryRegionPortio uhci_portio[] = {
1159     { 0, 32, 2, .write = uhci_ioport_writew, },
1160     { 0, 32, 2, .read = uhci_ioport_readw, },
1161     { 0, 32, 4, .write = uhci_ioport_writel, },
1162     { 0, 32, 4, .read = uhci_ioport_readl, },
1163     { 0, 32, 1, .write = uhci_ioport_writeb, },
1164     { 0, 32, 1, .read = uhci_ioport_readb, },
1165     PORTIO_END_OF_LIST()
1166 };
1167
1168 static const MemoryRegionOps uhci_ioport_ops = {
1169     .old_portio = uhci_portio,
1170 };
1171
1172 static USBPortOps uhci_port_ops = {
1173     .attach = uhci_attach,
1174     .detach = uhci_detach,
1175     .child_detach = uhci_child_detach,
1176     .wakeup = uhci_wakeup,
1177     .complete = uhci_async_complete,
1178 };
1179
1180 static USBBusOps uhci_bus_ops = {
1181 };
1182
1183 static int usb_uhci_common_initfn(PCIDevice *dev)
1184 {
1185     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1186     uint8_t *pci_conf = s->dev.config;
1187     int i;
1188
1189     pci_conf[PCI_CLASS_PROG] = 0x00;
1190     /* TODO: reset value should be 0. */
1191     pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */
1192     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1193
1194     if (s->masterbus) {
1195         USBPort *ports[NB_PORTS];
1196         for(i = 0; i < NB_PORTS; i++) {
1197             ports[i] = &s->ports[i].port;
1198         }
1199         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1200                 s->firstport, s, &uhci_port_ops,
1201                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1202             return -1;
1203         }
1204     } else {
1205         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1206         for (i = 0; i < NB_PORTS; i++) {
1207             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1208                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1209         }
1210     }
1211     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1212     s->num_ports_vmstate = NB_PORTS;
1213     QTAILQ_INIT(&s->queues);
1214
1215     qemu_register_reset(uhci_reset, s);
1216
1217     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1218     /* Use region 4 for consistency with real hardware.  BSD guests seem
1219        to rely on this.  */
1220     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1221
1222     return 0;
1223 }
1224
1225 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1226 {
1227     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1228     uint8_t *pci_conf = s->dev.config;
1229
1230     /* USB misc control 1/2 */
1231     pci_set_long(pci_conf + 0x40,0x00001000);
1232     /* PM capability */
1233     pci_set_long(pci_conf + 0x80,0x00020001);
1234     /* USB legacy support  */
1235     pci_set_long(pci_conf + 0xc0,0x00002000);
1236
1237     return usb_uhci_common_initfn(dev);
1238 }
1239
1240 static int usb_uhci_exit(PCIDevice *dev)
1241 {
1242     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1243
1244     memory_region_destroy(&s->io_bar);
1245     return 0;
1246 }
1247
1248 static Property uhci_properties[] = {
1249     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1250     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1251     DEFINE_PROP_END_OF_LIST(),
1252 };
1253
1254 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1255 {
1256     DeviceClass *dc = DEVICE_CLASS(klass);
1257     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1258
1259     k->init = usb_uhci_common_initfn;
1260     k->exit = usb_uhci_exit;
1261     k->vendor_id = PCI_VENDOR_ID_INTEL;
1262     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1263     k->revision = 0x01;
1264     k->class_id = PCI_CLASS_SERIAL_USB;
1265     dc->vmsd = &vmstate_uhci;
1266     dc->props = uhci_properties;
1267 }
1268
1269 static TypeInfo piix3_uhci_info = {
1270     .name          = "piix3-usb-uhci",
1271     .parent        = TYPE_PCI_DEVICE,
1272     .instance_size = sizeof(UHCIState),
1273     .class_init    = piix3_uhci_class_init,
1274 };
1275
1276 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1277 {
1278     DeviceClass *dc = DEVICE_CLASS(klass);
1279     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1280
1281     k->init = usb_uhci_common_initfn;
1282     k->exit = usb_uhci_exit;
1283     k->vendor_id = PCI_VENDOR_ID_INTEL;
1284     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1285     k->revision = 0x01;
1286     k->class_id = PCI_CLASS_SERIAL_USB;
1287     dc->vmsd = &vmstate_uhci;
1288     dc->props = uhci_properties;
1289 }
1290
1291 static TypeInfo piix4_uhci_info = {
1292     .name          = "piix4-usb-uhci",
1293     .parent        = TYPE_PCI_DEVICE,
1294     .instance_size = sizeof(UHCIState),
1295     .class_init    = piix4_uhci_class_init,
1296 };
1297
1298 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1299 {
1300     DeviceClass *dc = DEVICE_CLASS(klass);
1301     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1302
1303     k->init = usb_uhci_vt82c686b_initfn;
1304     k->exit = usb_uhci_exit;
1305     k->vendor_id = PCI_VENDOR_ID_VIA;
1306     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1307     k->revision = 0x01;
1308     k->class_id = PCI_CLASS_SERIAL_USB;
1309     dc->vmsd = &vmstate_uhci;
1310     dc->props = uhci_properties;
1311 }
1312
1313 static TypeInfo vt82c686b_uhci_info = {
1314     .name          = "vt82c686b-usb-uhci",
1315     .parent        = TYPE_PCI_DEVICE,
1316     .instance_size = sizeof(UHCIState),
1317     .class_init    = vt82c686b_uhci_class_init,
1318 };
1319
1320 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1321 {
1322     DeviceClass *dc = DEVICE_CLASS(klass);
1323     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1324
1325     k->init = usb_uhci_common_initfn;
1326     k->vendor_id = PCI_VENDOR_ID_INTEL;
1327     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1328     k->revision = 0x03;
1329     k->class_id = PCI_CLASS_SERIAL_USB;
1330     dc->vmsd = &vmstate_uhci;
1331     dc->props = uhci_properties;
1332 }
1333
1334 static TypeInfo ich9_uhci1_info = {
1335     .name          = "ich9-usb-uhci1",
1336     .parent        = TYPE_PCI_DEVICE,
1337     .instance_size = sizeof(UHCIState),
1338     .class_init    = ich9_uhci1_class_init,
1339 };
1340
1341 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1342 {
1343     DeviceClass *dc = DEVICE_CLASS(klass);
1344     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1345
1346     k->init = usb_uhci_common_initfn;
1347     k->vendor_id = PCI_VENDOR_ID_INTEL;
1348     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1349     k->revision = 0x03;
1350     k->class_id = PCI_CLASS_SERIAL_USB;
1351     dc->vmsd = &vmstate_uhci;
1352     dc->props = uhci_properties;
1353 }
1354
1355 static TypeInfo ich9_uhci2_info = {
1356     .name          = "ich9-usb-uhci2",
1357     .parent        = TYPE_PCI_DEVICE,
1358     .instance_size = sizeof(UHCIState),
1359     .class_init    = ich9_uhci2_class_init,
1360 };
1361
1362 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1363 {
1364     DeviceClass *dc = DEVICE_CLASS(klass);
1365     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1366
1367     k->init = usb_uhci_common_initfn;
1368     k->vendor_id = PCI_VENDOR_ID_INTEL;
1369     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1370     k->revision = 0x03;
1371     k->class_id = PCI_CLASS_SERIAL_USB;
1372     dc->vmsd = &vmstate_uhci;
1373     dc->props = uhci_properties;
1374 }
1375
1376 static TypeInfo ich9_uhci3_info = {
1377     .name          = "ich9-usb-uhci3",
1378     .parent        = TYPE_PCI_DEVICE,
1379     .instance_size = sizeof(UHCIState),
1380     .class_init    = ich9_uhci3_class_init,
1381 };
1382
1383 static void uhci_register_types(void)
1384 {
1385     type_register_static(&piix3_uhci_info);
1386     type_register_static(&piix4_uhci_info);
1387     type_register_static(&vt82c686b_uhci_info);
1388     type_register_static(&ich9_uhci1_info);
1389     type_register_static(&ich9_uhci2_info);
1390     type_register_static(&ich9_uhci3_info);
1391 }
1392
1393 type_init(uhci_register_types)
1394
1395 void usb_uhci_piix3_init(PCIBus *bus, int devfn)
1396 {
1397     pci_create_simple(bus, devfn, "piix3-usb-uhci");
1398 }
1399
1400 void usb_uhci_piix4_init(PCIBus *bus, int devfn)
1401 {
1402     pci_create_simple(bus, devfn, "piix4-usb-uhci");
1403 }
1404
1405 void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn)
1406 {
1407     pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
1408 }