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blkdebug: remove sync i/o events
[qemu/kevin.git] / target-i386 / translate.c
blob1988dae2908becea7db17fd892182bca4f9431ce
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define CODE64(s) ((s)->code64)
42 #define REX_X(s) ((s)->rex_x)
43 #define REX_B(s) ((s)->rex_b)
44 #else
45 #define CODE64(s) 0
46 #define REX_X(s) 0
47 #define REX_B(s) 0
48 #endif
49
50 //#define MACRO_TEST 1
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
55 static TCGv_i32 cpu_cc_op;
56 static TCGv cpu_regs[CPU_NB_REGS];
57 /* local temps */
58 static TCGv cpu_T[2], cpu_T3;
59 /* local register indexes (only used inside old micro ops) */
60 static TCGv cpu_tmp0, cpu_tmp4;
61 static TCGv_ptr cpu_ptr0, cpu_ptr1;
62 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
63 static TCGv_i64 cpu_tmp1_i64;
64 static TCGv cpu_tmp5;
65
66 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
67
68 #include "gen-icount.h"
69
70 #ifdef TARGET_X86_64
71 static int x86_64_hregs;
72 #endif
73
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
77 int prefix;
78 int aflag, dflag;
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
86 #ifdef TARGET_X86_64
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
89 int rex_x, rex_b;
90 #endif
91 int ss32; /* 32 bit stack segment */
92 int cc_op; /* current CC operation */
93 int addseg; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st; /* currently unused */
95 int vm86; /* vm86 mode */
96 int cpl;
97 int iopl;
98 int tf; /* TF cpu flag */
99 int singlestep_enabled; /* "hardware" single step enabled */
100 int jmp_opt; /* use direct block chaining for direct jumps */
101 int mem_index; /* select memory access functions */
102 uint64_t flags; /* all execution flags */
103 struct TranslationBlock *tb;
104 int popl_esp_hack; /* for correct popl with esp base handling */
105 int rip_offset; /* only used in x86_64, but left for simplicity */
106 int cpuid_features;
107 int cpuid_ext_features;
108 int cpuid_ext2_features;
109 int cpuid_ext3_features;
110 } DisasContext;
111
112 static void gen_eob(DisasContext *s);
113 static void gen_jmp(DisasContext *s, target_ulong eip);
114 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
115
116 /* i386 arith/logic operations */
117 enum {
118 OP_ADDL,
119 OP_ORL,
120 OP_ADCL,
121 OP_SBBL,
122 OP_ANDL,
123 OP_SUBL,
124 OP_XORL,
125 OP_CMPL,
126 };
127
128 /* i386 shift ops */
129 enum {
130 OP_ROL,
131 OP_ROR,
132 OP_RCL,
133 OP_RCR,
134 OP_SHL,
135 OP_SHR,
136 OP_SHL1, /* undocumented */
137 OP_SAR = 7,
138 };
139
140 enum {
141 JCC_O,
142 JCC_B,
143 JCC_Z,
144 JCC_BE,
145 JCC_S,
146 JCC_P,
147 JCC_L,
148 JCC_LE,
149 };
150
151 /* operand size */
152 enum {
153 OT_BYTE = 0,
154 OT_WORD,
155 OT_LONG,
156 OT_QUAD,
157 };
158
159 enum {
160 /* I386 int registers */
161 OR_EAX, /* MUST be even numbered */
162 OR_ECX,
163 OR_EDX,
164 OR_EBX,
165 OR_ESP,
166 OR_EBP,
167 OR_ESI,
168 OR_EDI,
169
170 OR_TMP0 = 16, /* temporary operand register */
171 OR_TMP1,
172 OR_A0, /* temporary register used when doing address evaluation */
173 };
174
175 static inline void gen_op_movl_T0_0(void)
176 {
177 tcg_gen_movi_tl(cpu_T[0], 0);
178 }
179
180 static inline void gen_op_movl_T0_im(int32_t val)
181 {
182 tcg_gen_movi_tl(cpu_T[0], val);
183 }
184
185 static inline void gen_op_movl_T0_imu(uint32_t val)
186 {
187 tcg_gen_movi_tl(cpu_T[0], val);
188 }
189
190 static inline void gen_op_movl_T1_im(int32_t val)
191 {
192 tcg_gen_movi_tl(cpu_T[1], val);
193 }
194
195 static inline void gen_op_movl_T1_imu(uint32_t val)
196 {
197 tcg_gen_movi_tl(cpu_T[1], val);
198 }
199
200 static inline void gen_op_movl_A0_im(uint32_t val)
201 {
202 tcg_gen_movi_tl(cpu_A0, val);
203 }
204
205 #ifdef TARGET_X86_64
206 static inline void gen_op_movq_A0_im(int64_t val)
207 {
208 tcg_gen_movi_tl(cpu_A0, val);
209 }
210 #endif
211
212 static inline void gen_movtl_T0_im(target_ulong val)
213 {
214 tcg_gen_movi_tl(cpu_T[0], val);
215 }
216
217 static inline void gen_movtl_T1_im(target_ulong val)
218 {
219 tcg_gen_movi_tl(cpu_T[1], val);
220 }
221
222 static inline void gen_op_andl_T0_ffff(void)
223 {
224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
225 }
226
227 static inline void gen_op_andl_T0_im(uint32_t val)
228 {
229 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
230 }
231
232 static inline void gen_op_movl_T0_T1(void)
233 {
234 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
235 }
236
237 static inline void gen_op_andl_A0_ffff(void)
238 {
239 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
240 }
241
242 #ifdef TARGET_X86_64
243
244 #define NB_OP_SIZES 4
245
246 #else /* !TARGET_X86_64 */
247
248 #define NB_OP_SIZES 3
249
250 #endif /* !TARGET_X86_64 */
251
252 #if defined(HOST_WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
258 #else
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
264 #endif
265
266 /* In instruction encodings for byte register accesses the
267 * register number usually indicates "low 8 bits of register N";
268 * however there are some special cases where N 4..7 indicates
269 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
270 * true for this special case, false otherwise.
271 */
272 static inline bool byte_reg_is_xH(int reg)
273 {
274 if (reg < 4) {
275 return false;
276 }
277 #ifdef TARGET_X86_64
278 if (reg >= 8 || x86_64_hregs) {
279 return false;
280 }
281 #endif
282 return true;
283 }
284
285 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
286 {
287 switch(ot) {
288 case OT_BYTE:
289 if (!byte_reg_is_xH(reg)) {
290 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
291 } else {
292 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
293 }
294 break;
295 case OT_WORD:
296 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
297 break;
298 default: /* XXX this shouldn't be reached; abort? */
299 case OT_LONG:
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
303 break;
304 #ifdef TARGET_X86_64
305 case OT_QUAD:
306 tcg_gen_mov_tl(cpu_regs[reg], t0);
307 break;
308 #endif
309 }
310 }
311
312 static inline void gen_op_mov_reg_T0(int ot, int reg)
313 {
314 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315 }
316
317 static inline void gen_op_mov_reg_T1(int ot, int reg)
318 {
319 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320 }
321
322 static inline void gen_op_mov_reg_A0(int size, int reg)
323 {
324 switch(size) {
325 case 0:
326 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
327 break;
328 default: /* XXX this shouldn't be reached; abort? */
329 case 1:
330 /* For x86_64, this sets the higher half of register to zero.
331 For i386, this is equivalent to a mov. */
332 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
333 break;
334 #ifdef TARGET_X86_64
335 case 2:
336 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
337 break;
338 #endif
339 }
340 }
341
342 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
343 {
344 if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
345 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
346 tcg_gen_ext8u_tl(t0, t0);
347 } else {
348 tcg_gen_mov_tl(t0, cpu_regs[reg]);
349 }
350 }
351
352 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
353 {
354 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
355 }
356
357 static inline void gen_op_movl_A0_reg(int reg)
358 {
359 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
360 }
361
362 static inline void gen_op_addl_A0_im(int32_t val)
363 {
364 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
365 #ifdef TARGET_X86_64
366 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
367 #endif
368 }
369
370 #ifdef TARGET_X86_64
371 static inline void gen_op_addq_A0_im(int64_t val)
372 {
373 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 }
375 #endif
376
377 static void gen_add_A0_im(DisasContext *s, int val)
378 {
379 #ifdef TARGET_X86_64
380 if (CODE64(s))
381 gen_op_addq_A0_im(val);
382 else
383 #endif
384 gen_op_addl_A0_im(val);
385 }
386
387 static inline void gen_op_addl_T0_T1(void)
388 {
389 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390 }
391
392 static inline void gen_op_jmp_T0(void)
393 {
394 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
395 }
396
397 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
398 {
399 switch(size) {
400 case 0:
401 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
402 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
403 break;
404 case 1:
405 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
406 /* For x86_64, this sets the higher half of register to zero.
407 For i386, this is equivalent to a nop. */
408 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
409 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
410 break;
411 #ifdef TARGET_X86_64
412 case 2:
413 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
414 break;
415 #endif
416 }
417 }
418
419 static inline void gen_op_add_reg_T0(int size, int reg)
420 {
421 switch(size) {
422 case 0:
423 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
424 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
425 break;
426 case 1:
427 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
428 /* For x86_64, this sets the higher half of register to zero.
429 For i386, this is equivalent to a nop. */
430 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
431 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
432 break;
433 #ifdef TARGET_X86_64
434 case 2:
435 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
436 break;
437 #endif
438 }
439 }
440
441 static inline void gen_op_set_cc_op(int32_t val)
442 {
443 tcg_gen_movi_i32(cpu_cc_op, val);
444 }
445
446 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
447 {
448 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
449 if (shift != 0)
450 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
451 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
452 /* For x86_64, this sets the higher half of register to zero.
453 For i386, this is equivalent to a nop. */
454 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
455 }
456
457 static inline void gen_op_movl_A0_seg(int reg)
458 {
459 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
460 }
461
462 static inline void gen_op_addl_A0_seg(int reg)
463 {
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
465 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
466 #ifdef TARGET_X86_64
467 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
468 #endif
469 }
470
471 #ifdef TARGET_X86_64
472 static inline void gen_op_movq_A0_seg(int reg)
473 {
474 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
475 }
476
477 static inline void gen_op_addq_A0_seg(int reg)
478 {
479 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
480 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
481 }
482
483 static inline void gen_op_movq_A0_reg(int reg)
484 {
485 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
486 }
487
488 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
489 {
490 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
491 if (shift != 0)
492 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
493 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
494 }
495 #endif
496
497 static inline void gen_op_lds_T0_A0(int idx)
498 {
499 int mem_index = (idx >> 2) - 1;
500 switch(idx & 3) {
501 case 0:
502 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
503 break;
504 case 1:
505 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
506 break;
507 default:
508 case 2:
509 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
510 break;
511 }
512 }
513
514 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
515 {
516 int mem_index = (idx >> 2) - 1;
517 switch(idx & 3) {
518 case 0:
519 tcg_gen_qemu_ld8u(t0, a0, mem_index);
520 break;
521 case 1:
522 tcg_gen_qemu_ld16u(t0, a0, mem_index);
523 break;
524 case 2:
525 tcg_gen_qemu_ld32u(t0, a0, mem_index);
526 break;
527 default:
528 case 3:
529 /* Should never happen on 32-bit targets. */
530 #ifdef TARGET_X86_64
531 tcg_gen_qemu_ld64(t0, a0, mem_index);
532 #endif
533 break;
534 }
535 }
536
537 /* XXX: always use ldu or lds */
538 static inline void gen_op_ld_T0_A0(int idx)
539 {
540 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
541 }
542
543 static inline void gen_op_ldu_T0_A0(int idx)
544 {
545 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
546 }
547
548 static inline void gen_op_ld_T1_A0(int idx)
549 {
550 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
551 }
552
553 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
554 {
555 int mem_index = (idx >> 2) - 1;
556 switch(idx & 3) {
557 case 0:
558 tcg_gen_qemu_st8(t0, a0, mem_index);
559 break;
560 case 1:
561 tcg_gen_qemu_st16(t0, a0, mem_index);
562 break;
563 case 2:
564 tcg_gen_qemu_st32(t0, a0, mem_index);
565 break;
566 default:
567 case 3:
568 /* Should never happen on 32-bit targets. */
569 #ifdef TARGET_X86_64
570 tcg_gen_qemu_st64(t0, a0, mem_index);
571 #endif
572 break;
573 }
574 }
575
576 static inline void gen_op_st_T0_A0(int idx)
577 {
578 gen_op_st_v(idx, cpu_T[0], cpu_A0);
579 }
580
581 static inline void gen_op_st_T1_A0(int idx)
582 {
583 gen_op_st_v(idx, cpu_T[1], cpu_A0);
584 }
585
586 static inline void gen_jmp_im(target_ulong pc)
587 {
588 tcg_gen_movi_tl(cpu_tmp0, pc);
589 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
590 }
591
592 static inline void gen_string_movl_A0_ESI(DisasContext *s)
593 {
594 int override;
595
596 override = s->override;
597 #ifdef TARGET_X86_64
598 if (s->aflag == 2) {
599 if (override >= 0) {
600 gen_op_movq_A0_seg(override);
601 gen_op_addq_A0_reg_sN(0, R_ESI);
602 } else {
603 gen_op_movq_A0_reg(R_ESI);
604 }
605 } else
606 #endif
607 if (s->aflag) {
608 /* 32 bit address */
609 if (s->addseg && override < 0)
610 override = R_DS;
611 if (override >= 0) {
612 gen_op_movl_A0_seg(override);
613 gen_op_addl_A0_reg_sN(0, R_ESI);
614 } else {
615 gen_op_movl_A0_reg(R_ESI);
616 }
617 } else {
618 /* 16 address, always override */
619 if (override < 0)
620 override = R_DS;
621 gen_op_movl_A0_reg(R_ESI);
622 gen_op_andl_A0_ffff();
623 gen_op_addl_A0_seg(override);
624 }
625 }
626
627 static inline void gen_string_movl_A0_EDI(DisasContext *s)
628 {
629 #ifdef TARGET_X86_64
630 if (s->aflag == 2) {
631 gen_op_movq_A0_reg(R_EDI);
632 } else
633 #endif
634 if (s->aflag) {
635 if (s->addseg) {
636 gen_op_movl_A0_seg(R_ES);
637 gen_op_addl_A0_reg_sN(0, R_EDI);
638 } else {
639 gen_op_movl_A0_reg(R_EDI);
640 }
641 } else {
642 gen_op_movl_A0_reg(R_EDI);
643 gen_op_andl_A0_ffff();
644 gen_op_addl_A0_seg(R_ES);
645 }
646 }
647
648 static inline void gen_op_movl_T0_Dshift(int ot)
649 {
650 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
651 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
652 };
653
654 static void gen_extu(int ot, TCGv reg)
655 {
656 switch(ot) {
657 case OT_BYTE:
658 tcg_gen_ext8u_tl(reg, reg);
659 break;
660 case OT_WORD:
661 tcg_gen_ext16u_tl(reg, reg);
662 break;
663 case OT_LONG:
664 tcg_gen_ext32u_tl(reg, reg);
665 break;
666 default:
667 break;
668 }
669 }
670
671 static void gen_exts(int ot, TCGv reg)
672 {
673 switch(ot) {
674 case OT_BYTE:
675 tcg_gen_ext8s_tl(reg, reg);
676 break;
677 case OT_WORD:
678 tcg_gen_ext16s_tl(reg, reg);
679 break;
680 case OT_LONG:
681 tcg_gen_ext32s_tl(reg, reg);
682 break;
683 default:
684 break;
685 }
686 }
687
688 static inline void gen_op_jnz_ecx(int size, int label1)
689 {
690 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
691 gen_extu(size + 1, cpu_tmp0);
692 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
693 }
694
695 static inline void gen_op_jz_ecx(int size, int label1)
696 {
697 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
698 gen_extu(size + 1, cpu_tmp0);
699 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
700 }
701
702 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
703 {
704 switch (ot) {
705 case 0: gen_helper_inb(v, n); break;
706 case 1: gen_helper_inw(v, n); break;
707 case 2: gen_helper_inl(v, n); break;
708 }
709
710 }
711
712 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
713 {
714 switch (ot) {
715 case 0: gen_helper_outb(v, n); break;
716 case 1: gen_helper_outw(v, n); break;
717 case 2: gen_helper_outl(v, n); break;
718 }
719
720 }
721
722 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
723 uint32_t svm_flags)
724 {
725 int state_saved;
726 target_ulong next_eip;
727
728 state_saved = 0;
729 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
730 if (s->cc_op != CC_OP_DYNAMIC)
731 gen_op_set_cc_op(s->cc_op);
732 gen_jmp_im(cur_eip);
733 state_saved = 1;
734 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
735 switch (ot) {
736 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
737 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
738 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
739 }
740 }
741 if(s->flags & HF_SVMI_MASK) {
742 if (!state_saved) {
743 if (s->cc_op != CC_OP_DYNAMIC)
744 gen_op_set_cc_op(s->cc_op);
745 gen_jmp_im(cur_eip);
746 }
747 svm_flags |= (1 << (4 + ot));
748 next_eip = s->pc - s->cs_base;
749 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
750 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
751 tcg_const_i32(next_eip - cur_eip));
752 }
753 }
754
755 static inline void gen_movs(DisasContext *s, int ot)
756 {
757 gen_string_movl_A0_ESI(s);
758 gen_op_ld_T0_A0(ot + s->mem_index);
759 gen_string_movl_A0_EDI(s);
760 gen_op_st_T0_A0(ot + s->mem_index);
761 gen_op_movl_T0_Dshift(ot);
762 gen_op_add_reg_T0(s->aflag, R_ESI);
763 gen_op_add_reg_T0(s->aflag, R_EDI);
764 }
765
766 static inline void gen_update_cc_op(DisasContext *s)
767 {
768 if (s->cc_op != CC_OP_DYNAMIC) {
769 gen_op_set_cc_op(s->cc_op);
770 s->cc_op = CC_OP_DYNAMIC;
771 }
772 }
773
774 static void gen_op_update1_cc(void)
775 {
776 tcg_gen_discard_tl(cpu_cc_src);
777 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
778 }
779
780 static void gen_op_update2_cc(void)
781 {
782 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
783 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
784 }
785
786 static inline void gen_op_cmpl_T0_T1_cc(void)
787 {
788 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
789 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
790 }
791
792 static inline void gen_op_testl_T0_T1_cc(void)
793 {
794 tcg_gen_discard_tl(cpu_cc_src);
795 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
796 }
797
798 static void gen_op_update_neg_cc(void)
799 {
800 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
801 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
802 }
803
804 /* compute eflags.C to reg */
805 static void gen_compute_eflags_c(TCGv reg)
806 {
807 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
808 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
809 }
810
811 /* compute all eflags to cc_src */
812 static void gen_compute_eflags(TCGv reg)
813 {
814 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
815 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
816 }
817
818 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
819 {
820 if (s->cc_op != CC_OP_DYNAMIC)
821 gen_op_set_cc_op(s->cc_op);
822 switch(jcc_op) {
823 case JCC_O:
824 gen_compute_eflags(cpu_T[0]);
825 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
826 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
827 break;
828 case JCC_B:
829 gen_compute_eflags_c(cpu_T[0]);
830 break;
831 case JCC_Z:
832 gen_compute_eflags(cpu_T[0]);
833 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
834 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
835 break;
836 case JCC_BE:
837 gen_compute_eflags(cpu_tmp0);
838 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
839 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
840 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
841 break;
842 case JCC_S:
843 gen_compute_eflags(cpu_T[0]);
844 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
845 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
846 break;
847 case JCC_P:
848 gen_compute_eflags(cpu_T[0]);
849 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
850 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
851 break;
852 case JCC_L:
853 gen_compute_eflags(cpu_tmp0);
854 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
855 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
856 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
857 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
858 break;
859 default:
860 case JCC_LE:
861 gen_compute_eflags(cpu_tmp0);
862 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
863 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
864 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
865 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
866 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
867 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
868 break;
869 }
870 }
871
872 /* return true if setcc_slow is not needed (WARNING: must be kept in
873 sync with gen_jcc1) */
874 static int is_fast_jcc_case(DisasContext *s, int b)
875 {
876 int jcc_op;
877 jcc_op = (b >> 1) & 7;
878 switch(s->cc_op) {
879 /* we optimize the cmp/jcc case */
880 case CC_OP_SUBB:
881 case CC_OP_SUBW:
882 case CC_OP_SUBL:
883 case CC_OP_SUBQ:
884 if (jcc_op == JCC_O || jcc_op == JCC_P)
885 goto slow_jcc;
886 break;
887
888 /* some jumps are easy to compute */
889 case CC_OP_ADDB:
890 case CC_OP_ADDW:
891 case CC_OP_ADDL:
892 case CC_OP_ADDQ:
893
894 case CC_OP_LOGICB:
895 case CC_OP_LOGICW:
896 case CC_OP_LOGICL:
897 case CC_OP_LOGICQ:
898
899 case CC_OP_INCB:
900 case CC_OP_INCW:
901 case CC_OP_INCL:
902 case CC_OP_INCQ:
903
904 case CC_OP_DECB:
905 case CC_OP_DECW:
906 case CC_OP_DECL:
907 case CC_OP_DECQ:
908
909 case CC_OP_SHLB:
910 case CC_OP_SHLW:
911 case CC_OP_SHLL:
912 case CC_OP_SHLQ:
913 if (jcc_op != JCC_Z && jcc_op != JCC_S)
914 goto slow_jcc;
915 break;
916 default:
917 slow_jcc:
918 return 0;
919 }
920 return 1;
921 }
922
923 /* generate a conditional jump to label 'l1' according to jump opcode
924 value 'b'. In the fast case, T0 is guaranted not to be used. */
925 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
926 {
927 int inv, jcc_op, size, cond;
928 TCGv t0;
929
930 inv = b & 1;
931 jcc_op = (b >> 1) & 7;
932
933 switch(cc_op) {
934 /* we optimize the cmp/jcc case */
935 case CC_OP_SUBB:
936 case CC_OP_SUBW:
937 case CC_OP_SUBL:
938 case CC_OP_SUBQ:
939
940 size = cc_op - CC_OP_SUBB;
941 switch(jcc_op) {
942 case JCC_Z:
943 fast_jcc_z:
944 switch(size) {
945 case 0:
946 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
947 t0 = cpu_tmp0;
948 break;
949 case 1:
950 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
951 t0 = cpu_tmp0;
952 break;
953 #ifdef TARGET_X86_64
954 case 2:
955 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
956 t0 = cpu_tmp0;
957 break;
958 #endif
959 default:
960 t0 = cpu_cc_dst;
961 break;
962 }
963 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
964 break;
965 case JCC_S:
966 fast_jcc_s:
967 switch(size) {
968 case 0:
969 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
970 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
971 0, l1);
972 break;
973 case 1:
974 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
975 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
976 0, l1);
977 break;
978 #ifdef TARGET_X86_64
979 case 2:
980 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
981 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
982 0, l1);
983 break;
984 #endif
985 default:
986 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
987 0, l1);
988 break;
989 }
990 break;
991
992 case JCC_B:
993 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
994 goto fast_jcc_b;
995 case JCC_BE:
996 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
997 fast_jcc_b:
998 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
999 switch(size) {
1000 case 0:
1001 t0 = cpu_tmp0;
1002 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1003 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1004 break;
1005 case 1:
1006 t0 = cpu_tmp0;
1007 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1008 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1009 break;
1010 #ifdef TARGET_X86_64
1011 case 2:
1012 t0 = cpu_tmp0;
1013 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1014 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1015 break;
1016 #endif
1017 default:
1018 t0 = cpu_cc_src;
1019 break;
1020 }
1021 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1022 break;
1023
1024 case JCC_L:
1025 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1026 goto fast_jcc_l;
1027 case JCC_LE:
1028 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1029 fast_jcc_l:
1030 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1031 switch(size) {
1032 case 0:
1033 t0 = cpu_tmp0;
1034 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1035 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1036 break;
1037 case 1:
1038 t0 = cpu_tmp0;
1039 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1040 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1041 break;
1042 #ifdef TARGET_X86_64
1043 case 2:
1044 t0 = cpu_tmp0;
1045 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1046 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1047 break;
1048 #endif
1049 default:
1050 t0 = cpu_cc_src;
1051 break;
1052 }
1053 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1054 break;
1055
1056 default:
1057 goto slow_jcc;
1058 }
1059 break;
1060
1061 /* some jumps are easy to compute */
1062 case CC_OP_ADDB:
1063 case CC_OP_ADDW:
1064 case CC_OP_ADDL:
1065 case CC_OP_ADDQ:
1066
1067 case CC_OP_ADCB:
1068 case CC_OP_ADCW:
1069 case CC_OP_ADCL:
1070 case CC_OP_ADCQ:
1071
1072 case CC_OP_SBBB:
1073 case CC_OP_SBBW:
1074 case CC_OP_SBBL:
1075 case CC_OP_SBBQ:
1076
1077 case CC_OP_LOGICB:
1078 case CC_OP_LOGICW:
1079 case CC_OP_LOGICL:
1080 case CC_OP_LOGICQ:
1081
1082 case CC_OP_INCB:
1083 case CC_OP_INCW:
1084 case CC_OP_INCL:
1085 case CC_OP_INCQ:
1086
1087 case CC_OP_DECB:
1088 case CC_OP_DECW:
1089 case CC_OP_DECL:
1090 case CC_OP_DECQ:
1091
1092 case CC_OP_SHLB:
1093 case CC_OP_SHLW:
1094 case CC_OP_SHLL:
1095 case CC_OP_SHLQ:
1096
1097 case CC_OP_SARB:
1098 case CC_OP_SARW:
1099 case CC_OP_SARL:
1100 case CC_OP_SARQ:
1101 switch(jcc_op) {
1102 case JCC_Z:
1103 size = (cc_op - CC_OP_ADDB) & 3;
1104 goto fast_jcc_z;
1105 case JCC_S:
1106 size = (cc_op - CC_OP_ADDB) & 3;
1107 goto fast_jcc_s;
1108 default:
1109 goto slow_jcc;
1110 }
1111 break;
1112 default:
1113 slow_jcc:
1114 gen_setcc_slow_T0(s, jcc_op);
1115 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1116 cpu_T[0], 0, l1);
1117 break;
1118 }
1119 }
1120
1121 /* XXX: does not work with gdbstub "ice" single step - not a
1122 serious problem */
1123 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1124 {
1125 int l1, l2;
1126
1127 l1 = gen_new_label();
1128 l2 = gen_new_label();
1129 gen_op_jnz_ecx(s->aflag, l1);
1130 gen_set_label(l2);
1131 gen_jmp_tb(s, next_eip, 1);
1132 gen_set_label(l1);
1133 return l2;
1134 }
1135
1136 static inline void gen_stos(DisasContext *s, int ot)
1137 {
1138 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1139 gen_string_movl_A0_EDI(s);
1140 gen_op_st_T0_A0(ot + s->mem_index);
1141 gen_op_movl_T0_Dshift(ot);
1142 gen_op_add_reg_T0(s->aflag, R_EDI);
1143 }
1144
1145 static inline void gen_lods(DisasContext *s, int ot)
1146 {
1147 gen_string_movl_A0_ESI(s);
1148 gen_op_ld_T0_A0(ot + s->mem_index);
1149 gen_op_mov_reg_T0(ot, R_EAX);
1150 gen_op_movl_T0_Dshift(ot);
1151 gen_op_add_reg_T0(s->aflag, R_ESI);
1152 }
1153
1154 static inline void gen_scas(DisasContext *s, int ot)
1155 {
1156 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1157 gen_string_movl_A0_EDI(s);
1158 gen_op_ld_T1_A0(ot + s->mem_index);
1159 gen_op_cmpl_T0_T1_cc();
1160 gen_op_movl_T0_Dshift(ot);
1161 gen_op_add_reg_T0(s->aflag, R_EDI);
1162 }
1163
1164 static inline void gen_cmps(DisasContext *s, int ot)
1165 {
1166 gen_string_movl_A0_ESI(s);
1167 gen_op_ld_T0_A0(ot + s->mem_index);
1168 gen_string_movl_A0_EDI(s);
1169 gen_op_ld_T1_A0(ot + s->mem_index);
1170 gen_op_cmpl_T0_T1_cc();
1171 gen_op_movl_T0_Dshift(ot);
1172 gen_op_add_reg_T0(s->aflag, R_ESI);
1173 gen_op_add_reg_T0(s->aflag, R_EDI);
1174 }
1175
1176 static inline void gen_ins(DisasContext *s, int ot)
1177 {
1178 if (use_icount)
1179 gen_io_start();
1180 gen_string_movl_A0_EDI(s);
1181 /* Note: we must do this dummy write first to be restartable in
1182 case of page fault. */
1183 gen_op_movl_T0_0();
1184 gen_op_st_T0_A0(ot + s->mem_index);
1185 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1186 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1187 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1188 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1189 gen_op_st_T0_A0(ot + s->mem_index);
1190 gen_op_movl_T0_Dshift(ot);
1191 gen_op_add_reg_T0(s->aflag, R_EDI);
1192 if (use_icount)
1193 gen_io_end();
1194 }
1195
1196 static inline void gen_outs(DisasContext *s, int ot)
1197 {
1198 if (use_icount)
1199 gen_io_start();
1200 gen_string_movl_A0_ESI(s);
1201 gen_op_ld_T0_A0(ot + s->mem_index);
1202
1203 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1204 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1205 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1206 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1207 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1208
1209 gen_op_movl_T0_Dshift(ot);
1210 gen_op_add_reg_T0(s->aflag, R_ESI);
1211 if (use_icount)
1212 gen_io_end();
1213 }
1214
1215 /* same method as Valgrind : we generate jumps to current or next
1216 instruction */
1217 #define GEN_REPZ(op) \
1218 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1219 target_ulong cur_eip, target_ulong next_eip) \
1220 { \
1221 int l2;\
1222 gen_update_cc_op(s); \
1223 l2 = gen_jz_ecx_string(s, next_eip); \
1224 gen_ ## op(s, ot); \
1225 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1226 /* a loop would cause two single step exceptions if ECX = 1 \
1227 before rep string_insn */ \
1228 if (!s->jmp_opt) \
1229 gen_op_jz_ecx(s->aflag, l2); \
1230 gen_jmp(s, cur_eip); \
1231 }
1232
1233 #define GEN_REPZ2(op) \
1234 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1235 target_ulong cur_eip, \
1236 target_ulong next_eip, \
1237 int nz) \
1238 { \
1239 int l2;\
1240 gen_update_cc_op(s); \
1241 l2 = gen_jz_ecx_string(s, next_eip); \
1242 gen_ ## op(s, ot); \
1243 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1244 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1245 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1246 if (!s->jmp_opt) \
1247 gen_op_jz_ecx(s->aflag, l2); \
1248 gen_jmp(s, cur_eip); \
1249 }
1250
1251 GEN_REPZ(movs)
1252 GEN_REPZ(stos)
1253 GEN_REPZ(lods)
1254 GEN_REPZ(ins)
1255 GEN_REPZ(outs)
1256 GEN_REPZ2(scas)
1257 GEN_REPZ2(cmps)
1258
1259 static void gen_helper_fp_arith_ST0_FT0(int op)
1260 {
1261 switch (op) {
1262 case 0: gen_helper_fadd_ST0_FT0(); break;
1263 case 1: gen_helper_fmul_ST0_FT0(); break;
1264 case 2: gen_helper_fcom_ST0_FT0(); break;
1265 case 3: gen_helper_fcom_ST0_FT0(); break;
1266 case 4: gen_helper_fsub_ST0_FT0(); break;
1267 case 5: gen_helper_fsubr_ST0_FT0(); break;
1268 case 6: gen_helper_fdiv_ST0_FT0(); break;
1269 case 7: gen_helper_fdivr_ST0_FT0(); break;
1270 }
1271 }
1272
1273 /* NOTE the exception in "r" op ordering */
1274 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1275 {
1276 TCGv_i32 tmp = tcg_const_i32(opreg);
1277 switch (op) {
1278 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1279 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1280 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1281 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1282 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1283 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1284 }
1285 }
1286
1287 /* if d == OR_TMP0, it means memory operand (address in A0) */
1288 static void gen_op(DisasContext *s1, int op, int ot, int d)
1289 {
1290 if (d != OR_TMP0) {
1291 gen_op_mov_TN_reg(ot, 0, d);
1292 } else {
1293 gen_op_ld_T0_A0(ot + s1->mem_index);
1294 }
1295 switch(op) {
1296 case OP_ADCL:
1297 if (s1->cc_op != CC_OP_DYNAMIC)
1298 gen_op_set_cc_op(s1->cc_op);
1299 gen_compute_eflags_c(cpu_tmp4);
1300 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1301 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1302 if (d != OR_TMP0)
1303 gen_op_mov_reg_T0(ot, d);
1304 else
1305 gen_op_st_T0_A0(ot + s1->mem_index);
1306 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1307 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1308 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1309 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1310 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1311 s1->cc_op = CC_OP_DYNAMIC;
1312 break;
1313 case OP_SBBL:
1314 if (s1->cc_op != CC_OP_DYNAMIC)
1315 gen_op_set_cc_op(s1->cc_op);
1316 gen_compute_eflags_c(cpu_tmp4);
1317 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1318 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1319 if (d != OR_TMP0)
1320 gen_op_mov_reg_T0(ot, d);
1321 else
1322 gen_op_st_T0_A0(ot + s1->mem_index);
1323 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1324 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1325 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1326 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1327 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1328 s1->cc_op = CC_OP_DYNAMIC;
1329 break;
1330 case OP_ADDL:
1331 gen_op_addl_T0_T1();
1332 if (d != OR_TMP0)
1333 gen_op_mov_reg_T0(ot, d);
1334 else
1335 gen_op_st_T0_A0(ot + s1->mem_index);
1336 gen_op_update2_cc();
1337 s1->cc_op = CC_OP_ADDB + ot;
1338 break;
1339 case OP_SUBL:
1340 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1341 if (d != OR_TMP0)
1342 gen_op_mov_reg_T0(ot, d);
1343 else
1344 gen_op_st_T0_A0(ot + s1->mem_index);
1345 gen_op_update2_cc();
1346 s1->cc_op = CC_OP_SUBB + ot;
1347 break;
1348 default:
1349 case OP_ANDL:
1350 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1351 if (d != OR_TMP0)
1352 gen_op_mov_reg_T0(ot, d);
1353 else
1354 gen_op_st_T0_A0(ot + s1->mem_index);
1355 gen_op_update1_cc();
1356 s1->cc_op = CC_OP_LOGICB + ot;
1357 break;
1358 case OP_ORL:
1359 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1360 if (d != OR_TMP0)
1361 gen_op_mov_reg_T0(ot, d);
1362 else
1363 gen_op_st_T0_A0(ot + s1->mem_index);
1364 gen_op_update1_cc();
1365 s1->cc_op = CC_OP_LOGICB + ot;
1366 break;
1367 case OP_XORL:
1368 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1369 if (d != OR_TMP0)
1370 gen_op_mov_reg_T0(ot, d);
1371 else
1372 gen_op_st_T0_A0(ot + s1->mem_index);
1373 gen_op_update1_cc();
1374 s1->cc_op = CC_OP_LOGICB + ot;
1375 break;
1376 case OP_CMPL:
1377 gen_op_cmpl_T0_T1_cc();
1378 s1->cc_op = CC_OP_SUBB + ot;
1379 break;
1380 }
1381 }
1382
1383 /* if d == OR_TMP0, it means memory operand (address in A0) */
1384 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1385 {
1386 if (d != OR_TMP0)
1387 gen_op_mov_TN_reg(ot, 0, d);
1388 else
1389 gen_op_ld_T0_A0(ot + s1->mem_index);
1390 if (s1->cc_op != CC_OP_DYNAMIC)
1391 gen_op_set_cc_op(s1->cc_op);
1392 if (c > 0) {
1393 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1394 s1->cc_op = CC_OP_INCB + ot;
1395 } else {
1396 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1397 s1->cc_op = CC_OP_DECB + ot;
1398 }
1399 if (d != OR_TMP0)
1400 gen_op_mov_reg_T0(ot, d);
1401 else
1402 gen_op_st_T0_A0(ot + s1->mem_index);
1403 gen_compute_eflags_c(cpu_cc_src);
1404 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1405 }
1406
1407 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1408 int is_right, int is_arith)
1409 {
1410 target_ulong mask;
1411 int shift_label;
1412 TCGv t0, t1, t2;
1413
1414 if (ot == OT_QUAD) {
1415 mask = 0x3f;
1416 } else {
1417 mask = 0x1f;
1418 }
1419
1420 /* load */
1421 if (op1 == OR_TMP0) {
1422 gen_op_ld_T0_A0(ot + s->mem_index);
1423 } else {
1424 gen_op_mov_TN_reg(ot, 0, op1);
1425 }
1426
1427 t0 = tcg_temp_local_new();
1428 t1 = tcg_temp_local_new();
1429 t2 = tcg_temp_local_new();
1430
1431 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1432
1433 if (is_right) {
1434 if (is_arith) {
1435 gen_exts(ot, cpu_T[0]);
1436 tcg_gen_mov_tl(t0, cpu_T[0]);
1437 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1438 } else {
1439 gen_extu(ot, cpu_T[0]);
1440 tcg_gen_mov_tl(t0, cpu_T[0]);
1441 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1442 }
1443 } else {
1444 tcg_gen_mov_tl(t0, cpu_T[0]);
1445 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1446 }
1447
1448 /* store */
1449 if (op1 == OR_TMP0) {
1450 gen_op_st_T0_A0(ot + s->mem_index);
1451 } else {
1452 gen_op_mov_reg_T0(ot, op1);
1453 }
1454
1455 /* update eflags if non zero shift */
1456 if (s->cc_op != CC_OP_DYNAMIC) {
1457 gen_op_set_cc_op(s->cc_op);
1458 }
1459
1460 tcg_gen_mov_tl(t1, cpu_T[0]);
1461
1462 shift_label = gen_new_label();
1463 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1464
1465 tcg_gen_addi_tl(t2, t2, -1);
1466 tcg_gen_mov_tl(cpu_cc_dst, t1);
1467
1468 if (is_right) {
1469 if (is_arith) {
1470 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1471 } else {
1472 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1473 }
1474 } else {
1475 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1476 }
1477
1478 if (is_right) {
1479 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1480 } else {
1481 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1482 }
1483
1484 gen_set_label(shift_label);
1485 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1486
1487 tcg_temp_free(t0);
1488 tcg_temp_free(t1);
1489 tcg_temp_free(t2);
1490 }
1491
1492 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1493 int is_right, int is_arith)
1494 {
1495 int mask;
1496
1497 if (ot == OT_QUAD)
1498 mask = 0x3f;
1499 else
1500 mask = 0x1f;
1501
1502 /* load */
1503 if (op1 == OR_TMP0)
1504 gen_op_ld_T0_A0(ot + s->mem_index);
1505 else
1506 gen_op_mov_TN_reg(ot, 0, op1);
1507
1508 op2 &= mask;
1509 if (op2 != 0) {
1510 if (is_right) {
1511 if (is_arith) {
1512 gen_exts(ot, cpu_T[0]);
1513 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1514 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1515 } else {
1516 gen_extu(ot, cpu_T[0]);
1517 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1518 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1519 }
1520 } else {
1521 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1522 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1523 }
1524 }
1525
1526 /* store */
1527 if (op1 == OR_TMP0)
1528 gen_op_st_T0_A0(ot + s->mem_index);
1529 else
1530 gen_op_mov_reg_T0(ot, op1);
1531
1532 /* update eflags if non zero shift */
1533 if (op2 != 0) {
1534 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1535 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1536 if (is_right)
1537 s->cc_op = CC_OP_SARB + ot;
1538 else
1539 s->cc_op = CC_OP_SHLB + ot;
1540 }
1541 }
1542
1543 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1544 {
1545 if (arg2 >= 0)
1546 tcg_gen_shli_tl(ret, arg1, arg2);
1547 else
1548 tcg_gen_shri_tl(ret, arg1, -arg2);
1549 }
1550
1551 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1552 int is_right)
1553 {
1554 target_ulong mask;
1555 int label1, label2, data_bits;
1556 TCGv t0, t1, t2, a0;
1557
1558 /* XXX: inefficient, but we must use local temps */
1559 t0 = tcg_temp_local_new();
1560 t1 = tcg_temp_local_new();
1561 t2 = tcg_temp_local_new();
1562 a0 = tcg_temp_local_new();
1563
1564 if (ot == OT_QUAD)
1565 mask = 0x3f;
1566 else
1567 mask = 0x1f;
1568
1569 /* load */
1570 if (op1 == OR_TMP0) {
1571 tcg_gen_mov_tl(a0, cpu_A0);
1572 gen_op_ld_v(ot + s->mem_index, t0, a0);
1573 } else {
1574 gen_op_mov_v_reg(ot, t0, op1);
1575 }
1576
1577 tcg_gen_mov_tl(t1, cpu_T[1]);
1578
1579 tcg_gen_andi_tl(t1, t1, mask);
1580
1581 /* Must test zero case to avoid using undefined behaviour in TCG
1582 shifts. */
1583 label1 = gen_new_label();
1584 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1585
1586 if (ot <= OT_WORD)
1587 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1588 else
1589 tcg_gen_mov_tl(cpu_tmp0, t1);
1590
1591 gen_extu(ot, t0);
1592 tcg_gen_mov_tl(t2, t0);
1593
1594 data_bits = 8 << ot;
1595 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1596 fix TCG definition) */
1597 if (is_right) {
1598 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1599 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1600 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1601 } else {
1602 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1603 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1604 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1605 }
1606 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1607
1608 gen_set_label(label1);
1609 /* store */
1610 if (op1 == OR_TMP0) {
1611 gen_op_st_v(ot + s->mem_index, t0, a0);
1612 } else {
1613 gen_op_mov_reg_v(ot, op1, t0);
1614 }
1615
1616 /* update eflags */
1617 if (s->cc_op != CC_OP_DYNAMIC)
1618 gen_op_set_cc_op(s->cc_op);
1619
1620 label2 = gen_new_label();
1621 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1622
1623 gen_compute_eflags(cpu_cc_src);
1624 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1625 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1626 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1627 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1628 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1629 if (is_right) {
1630 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1631 }
1632 tcg_gen_andi_tl(t0, t0, CC_C);
1633 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1634
1635 tcg_gen_discard_tl(cpu_cc_dst);
1636 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1637
1638 gen_set_label(label2);
1639 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1640
1641 tcg_temp_free(t0);
1642 tcg_temp_free(t1);
1643 tcg_temp_free(t2);
1644 tcg_temp_free(a0);
1645 }
1646
1647 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1648 int is_right)
1649 {
1650 int mask;
1651 int data_bits;
1652 TCGv t0, t1, a0;
1653
1654 /* XXX: inefficient, but we must use local temps */
1655 t0 = tcg_temp_local_new();
1656 t1 = tcg_temp_local_new();
1657 a0 = tcg_temp_local_new();
1658
1659 if (ot == OT_QUAD)
1660 mask = 0x3f;
1661 else
1662 mask = 0x1f;
1663
1664 /* load */
1665 if (op1 == OR_TMP0) {
1666 tcg_gen_mov_tl(a0, cpu_A0);
1667 gen_op_ld_v(ot + s->mem_index, t0, a0);
1668 } else {
1669 gen_op_mov_v_reg(ot, t0, op1);
1670 }
1671
1672 gen_extu(ot, t0);
1673 tcg_gen_mov_tl(t1, t0);
1674
1675 op2 &= mask;
1676 data_bits = 8 << ot;
1677 if (op2 != 0) {
1678 int shift = op2 & ((1 << (3 + ot)) - 1);
1679 if (is_right) {
1680 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1681 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1682 }
1683 else {
1684 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1685 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1686 }
1687 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1688 }
1689
1690 /* store */
1691 if (op1 == OR_TMP0) {
1692 gen_op_st_v(ot + s->mem_index, t0, a0);
1693 } else {
1694 gen_op_mov_reg_v(ot, op1, t0);
1695 }
1696
1697 if (op2 != 0) {
1698 /* update eflags */
1699 if (s->cc_op != CC_OP_DYNAMIC)
1700 gen_op_set_cc_op(s->cc_op);
1701
1702 gen_compute_eflags(cpu_cc_src);
1703 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1704 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1705 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1706 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1707 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1708 if (is_right) {
1709 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1710 }
1711 tcg_gen_andi_tl(t0, t0, CC_C);
1712 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1713
1714 tcg_gen_discard_tl(cpu_cc_dst);
1715 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1716 s->cc_op = CC_OP_EFLAGS;
1717 }
1718
1719 tcg_temp_free(t0);
1720 tcg_temp_free(t1);
1721 tcg_temp_free(a0);
1722 }
1723
1724 /* XXX: add faster immediate = 1 case */
1725 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1726 int is_right)
1727 {
1728 int label1;
1729
1730 if (s->cc_op != CC_OP_DYNAMIC)
1731 gen_op_set_cc_op(s->cc_op);
1732
1733 /* load */
1734 if (op1 == OR_TMP0)
1735 gen_op_ld_T0_A0(ot + s->mem_index);
1736 else
1737 gen_op_mov_TN_reg(ot, 0, op1);
1738
1739 if (is_right) {
1740 switch (ot) {
1741 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1742 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1743 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1744 #ifdef TARGET_X86_64
1745 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1746 #endif
1747 }
1748 } else {
1749 switch (ot) {
1750 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1751 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1752 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1753 #ifdef TARGET_X86_64
1754 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1755 #endif
1756 }
1757 }
1758 /* store */
1759 if (op1 == OR_TMP0)
1760 gen_op_st_T0_A0(ot + s->mem_index);
1761 else
1762 gen_op_mov_reg_T0(ot, op1);
1763
1764 /* update eflags */
1765 label1 = gen_new_label();
1766 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1767
1768 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1769 tcg_gen_discard_tl(cpu_cc_dst);
1770 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1771
1772 gen_set_label(label1);
1773 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1774 }
1775
1776 /* XXX: add faster immediate case */
1777 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1778 int is_right)
1779 {
1780 int label1, label2, data_bits;
1781 target_ulong mask;
1782 TCGv t0, t1, t2, a0;
1783
1784 t0 = tcg_temp_local_new();
1785 t1 = tcg_temp_local_new();
1786 t2 = tcg_temp_local_new();
1787 a0 = tcg_temp_local_new();
1788
1789 if (ot == OT_QUAD)
1790 mask = 0x3f;
1791 else
1792 mask = 0x1f;
1793
1794 /* load */
1795 if (op1 == OR_TMP0) {
1796 tcg_gen_mov_tl(a0, cpu_A0);
1797 gen_op_ld_v(ot + s->mem_index, t0, a0);
1798 } else {
1799 gen_op_mov_v_reg(ot, t0, op1);
1800 }
1801
1802 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1803
1804 tcg_gen_mov_tl(t1, cpu_T[1]);
1805 tcg_gen_mov_tl(t2, cpu_T3);
1806
1807 /* Must test zero case to avoid using undefined behaviour in TCG
1808 shifts. */
1809 label1 = gen_new_label();
1810 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1811
1812 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1813 if (ot == OT_WORD) {
1814 /* Note: we implement the Intel behaviour for shift count > 16 */
1815 if (is_right) {
1816 tcg_gen_andi_tl(t0, t0, 0xffff);
1817 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1818 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1819 tcg_gen_ext32u_tl(t0, t0);
1820
1821 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1822
1823 /* only needed if count > 16, but a test would complicate */
1824 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1825 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1826
1827 tcg_gen_shr_tl(t0, t0, t2);
1828
1829 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1830 } else {
1831 /* XXX: not optimal */
1832 tcg_gen_andi_tl(t0, t0, 0xffff);
1833 tcg_gen_shli_tl(t1, t1, 16);
1834 tcg_gen_or_tl(t1, t1, t0);
1835 tcg_gen_ext32u_tl(t1, t1);
1836
1837 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1838 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1839 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1840 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1841
1842 tcg_gen_shl_tl(t0, t0, t2);
1843 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1844 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1845 tcg_gen_or_tl(t0, t0, t1);
1846 }
1847 } else {
1848 data_bits = 8 << ot;
1849 if (is_right) {
1850 if (ot == OT_LONG)
1851 tcg_gen_ext32u_tl(t0, t0);
1852
1853 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1854
1855 tcg_gen_shr_tl(t0, t0, t2);
1856 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1857 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1858 tcg_gen_or_tl(t0, t0, t1);
1859
1860 } else {
1861 if (ot == OT_LONG)
1862 tcg_gen_ext32u_tl(t1, t1);
1863
1864 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1865
1866 tcg_gen_shl_tl(t0, t0, t2);
1867 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1868 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1869 tcg_gen_or_tl(t0, t0, t1);
1870 }
1871 }
1872 tcg_gen_mov_tl(t1, cpu_tmp4);
1873
1874 gen_set_label(label1);
1875 /* store */
1876 if (op1 == OR_TMP0) {
1877 gen_op_st_v(ot + s->mem_index, t0, a0);
1878 } else {
1879 gen_op_mov_reg_v(ot, op1, t0);
1880 }
1881
1882 /* update eflags */
1883 if (s->cc_op != CC_OP_DYNAMIC)
1884 gen_op_set_cc_op(s->cc_op);
1885
1886 label2 = gen_new_label();
1887 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1888
1889 tcg_gen_mov_tl(cpu_cc_src, t1);
1890 tcg_gen_mov_tl(cpu_cc_dst, t0);
1891 if (is_right) {
1892 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1893 } else {
1894 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1895 }
1896 gen_set_label(label2);
1897 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1898
1899 tcg_temp_free(t0);
1900 tcg_temp_free(t1);
1901 tcg_temp_free(t2);
1902 tcg_temp_free(a0);
1903 }
1904
1905 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1906 {
1907 if (s != OR_TMP1)
1908 gen_op_mov_TN_reg(ot, 1, s);
1909 switch(op) {
1910 case OP_ROL:
1911 gen_rot_rm_T1(s1, ot, d, 0);
1912 break;
1913 case OP_ROR:
1914 gen_rot_rm_T1(s1, ot, d, 1);
1915 break;
1916 case OP_SHL:
1917 case OP_SHL1:
1918 gen_shift_rm_T1(s1, ot, d, 0, 0);
1919 break;
1920 case OP_SHR:
1921 gen_shift_rm_T1(s1, ot, d, 1, 0);
1922 break;
1923 case OP_SAR:
1924 gen_shift_rm_T1(s1, ot, d, 1, 1);
1925 break;
1926 case OP_RCL:
1927 gen_rotc_rm_T1(s1, ot, d, 0);
1928 break;
1929 case OP_RCR:
1930 gen_rotc_rm_T1(s1, ot, d, 1);
1931 break;
1932 }
1933 }
1934
1935 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1936 {
1937 switch(op) {
1938 case OP_ROL:
1939 gen_rot_rm_im(s1, ot, d, c, 0);
1940 break;
1941 case OP_ROR:
1942 gen_rot_rm_im(s1, ot, d, c, 1);
1943 break;
1944 case OP_SHL:
1945 case OP_SHL1:
1946 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1947 break;
1948 case OP_SHR:
1949 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1950 break;
1951 case OP_SAR:
1952 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1953 break;
1954 default:
1955 /* currently not optimized */
1956 gen_op_movl_T1_im(c);
1957 gen_shift(s1, op, ot, d, OR_TMP1);
1958 break;
1959 }
1960 }
1961
1962 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1963 {
1964 target_long disp;
1965 int havesib;
1966 int base;
1967 int index;
1968 int scale;
1969 int opreg;
1970 int mod, rm, code, override, must_add_seg;
1971
1972 override = s->override;
1973 must_add_seg = s->addseg;
1974 if (override >= 0)
1975 must_add_seg = 1;
1976 mod = (modrm >> 6) & 3;
1977 rm = modrm & 7;
1978
1979 if (s->aflag) {
1980
1981 havesib = 0;
1982 base = rm;
1983 index = 0;
1984 scale = 0;
1985
1986 if (base == 4) {
1987 havesib = 1;
1988 code = ldub_code(s->pc++);
1989 scale = (code >> 6) & 3;
1990 index = ((code >> 3) & 7) | REX_X(s);
1991 base = (code & 7);
1992 }
1993 base |= REX_B(s);
1994
1995 switch (mod) {
1996 case 0:
1997 if ((base & 7) == 5) {
1998 base = -1;
1999 disp = (int32_t)ldl_code(s->pc);
2000 s->pc += 4;
2001 if (CODE64(s) && !havesib) {
2002 disp += s->pc + s->rip_offset;
2003 }
2004 } else {
2005 disp = 0;
2006 }
2007 break;
2008 case 1:
2009 disp = (int8_t)ldub_code(s->pc++);
2010 break;
2011 default:
2012 case 2:
2013 disp = (int32_t)ldl_code(s->pc);
2014 s->pc += 4;
2015 break;
2016 }
2017
2018 if (base >= 0) {
2019 /* for correct popl handling with esp */
2020 if (base == 4 && s->popl_esp_hack)
2021 disp += s->popl_esp_hack;
2022 #ifdef TARGET_X86_64
2023 if (s->aflag == 2) {
2024 gen_op_movq_A0_reg(base);
2025 if (disp != 0) {
2026 gen_op_addq_A0_im(disp);
2027 }
2028 } else
2029 #endif
2030 {
2031 gen_op_movl_A0_reg(base);
2032 if (disp != 0)
2033 gen_op_addl_A0_im(disp);
2034 }
2035 } else {
2036 #ifdef TARGET_X86_64
2037 if (s->aflag == 2) {
2038 gen_op_movq_A0_im(disp);
2039 } else
2040 #endif
2041 {
2042 gen_op_movl_A0_im(disp);
2043 }
2044 }
2045 /* index == 4 means no index */
2046 if (havesib && (index != 4)) {
2047 #ifdef TARGET_X86_64
2048 if (s->aflag == 2) {
2049 gen_op_addq_A0_reg_sN(scale, index);
2050 } else
2051 #endif
2052 {
2053 gen_op_addl_A0_reg_sN(scale, index);
2054 }
2055 }
2056 if (must_add_seg) {
2057 if (override < 0) {
2058 if (base == R_EBP || base == R_ESP)
2059 override = R_SS;
2060 else
2061 override = R_DS;
2062 }
2063 #ifdef TARGET_X86_64
2064 if (s->aflag == 2) {
2065 gen_op_addq_A0_seg(override);
2066 } else
2067 #endif
2068 {
2069 gen_op_addl_A0_seg(override);
2070 }
2071 }
2072 } else {
2073 switch (mod) {
2074 case 0:
2075 if (rm == 6) {
2076 disp = lduw_code(s->pc);
2077 s->pc += 2;
2078 gen_op_movl_A0_im(disp);
2079 rm = 0; /* avoid SS override */
2080 goto no_rm;
2081 } else {
2082 disp = 0;
2083 }
2084 break;
2085 case 1:
2086 disp = (int8_t)ldub_code(s->pc++);
2087 break;
2088 default:
2089 case 2:
2090 disp = lduw_code(s->pc);
2091 s->pc += 2;
2092 break;
2093 }
2094 switch(rm) {
2095 case 0:
2096 gen_op_movl_A0_reg(R_EBX);
2097 gen_op_addl_A0_reg_sN(0, R_ESI);
2098 break;
2099 case 1:
2100 gen_op_movl_A0_reg(R_EBX);
2101 gen_op_addl_A0_reg_sN(0, R_EDI);
2102 break;
2103 case 2:
2104 gen_op_movl_A0_reg(R_EBP);
2105 gen_op_addl_A0_reg_sN(0, R_ESI);
2106 break;
2107 case 3:
2108 gen_op_movl_A0_reg(R_EBP);
2109 gen_op_addl_A0_reg_sN(0, R_EDI);
2110 break;
2111 case 4:
2112 gen_op_movl_A0_reg(R_ESI);
2113 break;
2114 case 5:
2115 gen_op_movl_A0_reg(R_EDI);
2116 break;
2117 case 6:
2118 gen_op_movl_A0_reg(R_EBP);
2119 break;
2120 default:
2121 case 7:
2122 gen_op_movl_A0_reg(R_EBX);
2123 break;
2124 }
2125 if (disp != 0)
2126 gen_op_addl_A0_im(disp);
2127 gen_op_andl_A0_ffff();
2128 no_rm:
2129 if (must_add_seg) {
2130 if (override < 0) {
2131 if (rm == 2 || rm == 3 || rm == 6)
2132 override = R_SS;
2133 else
2134 override = R_DS;
2135 }
2136 gen_op_addl_A0_seg(override);
2137 }
2138 }
2139
2140 opreg = OR_A0;
2141 disp = 0;
2142 *reg_ptr = opreg;
2143 *offset_ptr = disp;
2144 }
2145
2146 static void gen_nop_modrm(DisasContext *s, int modrm)
2147 {
2148 int mod, rm, base, code;
2149
2150 mod = (modrm >> 6) & 3;
2151 if (mod == 3)
2152 return;
2153 rm = modrm & 7;
2154
2155 if (s->aflag) {
2156
2157 base = rm;
2158
2159 if (base == 4) {
2160 code = ldub_code(s->pc++);
2161 base = (code & 7);
2162 }
2163
2164 switch (mod) {
2165 case 0:
2166 if (base == 5) {
2167 s->pc += 4;
2168 }
2169 break;
2170 case 1:
2171 s->pc++;
2172 break;
2173 default:
2174 case 2:
2175 s->pc += 4;
2176 break;
2177 }
2178 } else {
2179 switch (mod) {
2180 case 0:
2181 if (rm == 6) {
2182 s->pc += 2;
2183 }
2184 break;
2185 case 1:
2186 s->pc++;
2187 break;
2188 default:
2189 case 2:
2190 s->pc += 2;
2191 break;
2192 }
2193 }
2194 }
2195
2196 /* used for LEA and MOV AX, mem */
2197 static void gen_add_A0_ds_seg(DisasContext *s)
2198 {
2199 int override, must_add_seg;
2200 must_add_seg = s->addseg;
2201 override = R_DS;
2202 if (s->override >= 0) {
2203 override = s->override;
2204 must_add_seg = 1;
2205 }
2206 if (must_add_seg) {
2207 #ifdef TARGET_X86_64
2208 if (CODE64(s)) {
2209 gen_op_addq_A0_seg(override);
2210 } else
2211 #endif
2212 {
2213 gen_op_addl_A0_seg(override);
2214 }
2215 }
2216 }
2217
2218 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2219 OR_TMP0 */
2220 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2221 {
2222 int mod, rm, opreg, disp;
2223
2224 mod = (modrm >> 6) & 3;
2225 rm = (modrm & 7) | REX_B(s);
2226 if (mod == 3) {
2227 if (is_store) {
2228 if (reg != OR_TMP0)
2229 gen_op_mov_TN_reg(ot, 0, reg);
2230 gen_op_mov_reg_T0(ot, rm);
2231 } else {
2232 gen_op_mov_TN_reg(ot, 0, rm);
2233 if (reg != OR_TMP0)
2234 gen_op_mov_reg_T0(ot, reg);
2235 }
2236 } else {
2237 gen_lea_modrm(s, modrm, &opreg, &disp);
2238 if (is_store) {
2239 if (reg != OR_TMP0)
2240 gen_op_mov_TN_reg(ot, 0, reg);
2241 gen_op_st_T0_A0(ot + s->mem_index);
2242 } else {
2243 gen_op_ld_T0_A0(ot + s->mem_index);
2244 if (reg != OR_TMP0)
2245 gen_op_mov_reg_T0(ot, reg);
2246 }
2247 }
2248 }
2249
2250 static inline uint32_t insn_get(DisasContext *s, int ot)
2251 {
2252 uint32_t ret;
2253
2254 switch(ot) {
2255 case OT_BYTE:
2256 ret = ldub_code(s->pc);
2257 s->pc++;
2258 break;
2259 case OT_WORD:
2260 ret = lduw_code(s->pc);
2261 s->pc += 2;
2262 break;
2263 default:
2264 case OT_LONG:
2265 ret = ldl_code(s->pc);
2266 s->pc += 4;
2267 break;
2268 }
2269 return ret;
2270 }
2271
2272 static inline int insn_const_size(unsigned int ot)
2273 {
2274 if (ot <= OT_LONG)
2275 return 1 << ot;
2276 else
2277 return 4;
2278 }
2279
2280 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2281 {
2282 TranslationBlock *tb;
2283 target_ulong pc;
2284
2285 pc = s->cs_base + eip;
2286 tb = s->tb;
2287 /* NOTE: we handle the case where the TB spans two pages here */
2288 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2289 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2290 /* jump to same page: we can use a direct jump */
2291 tcg_gen_goto_tb(tb_num);
2292 gen_jmp_im(eip);
2293 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2294 } else {
2295 /* jump to another page: currently not optimized */
2296 gen_jmp_im(eip);
2297 gen_eob(s);
2298 }
2299 }
2300
2301 static inline void gen_jcc(DisasContext *s, int b,
2302 target_ulong val, target_ulong next_eip)
2303 {
2304 int l1, l2, cc_op;
2305
2306 cc_op = s->cc_op;
2307 gen_update_cc_op(s);
2308 if (s->jmp_opt) {
2309 l1 = gen_new_label();
2310 gen_jcc1(s, cc_op, b, l1);
2311
2312 gen_goto_tb(s, 0, next_eip);
2313
2314 gen_set_label(l1);
2315 gen_goto_tb(s, 1, val);
2316 s->is_jmp = DISAS_TB_JUMP;
2317 } else {
2318
2319 l1 = gen_new_label();
2320 l2 = gen_new_label();
2321 gen_jcc1(s, cc_op, b, l1);
2322
2323 gen_jmp_im(next_eip);
2324 tcg_gen_br(l2);
2325
2326 gen_set_label(l1);
2327 gen_jmp_im(val);
2328 gen_set_label(l2);
2329 gen_eob(s);
2330 }
2331 }
2332
2333 static void gen_setcc(DisasContext *s, int b)
2334 {
2335 int inv, jcc_op, l1;
2336 TCGv t0;
2337
2338 if (is_fast_jcc_case(s, b)) {
2339 /* nominal case: we use a jump */
2340 /* XXX: make it faster by adding new instructions in TCG */
2341 t0 = tcg_temp_local_new();
2342 tcg_gen_movi_tl(t0, 0);
2343 l1 = gen_new_label();
2344 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2345 tcg_gen_movi_tl(t0, 1);
2346 gen_set_label(l1);
2347 tcg_gen_mov_tl(cpu_T[0], t0);
2348 tcg_temp_free(t0);
2349 } else {
2350 /* slow case: it is more efficient not to generate a jump,
2351 although it is questionnable whether this optimization is
2352 worth to */
2353 inv = b & 1;
2354 jcc_op = (b >> 1) & 7;
2355 gen_setcc_slow_T0(s, jcc_op);
2356 if (inv) {
2357 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2358 }
2359 }
2360 }
2361
2362 static inline void gen_op_movl_T0_seg(int seg_reg)
2363 {
2364 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2365 offsetof(CPUX86State,segs[seg_reg].selector));
2366 }
2367
2368 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2369 {
2370 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2371 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2372 offsetof(CPUX86State,segs[seg_reg].selector));
2373 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2374 tcg_gen_st_tl(cpu_T[0], cpu_env,
2375 offsetof(CPUX86State,segs[seg_reg].base));
2376 }
2377
2378 /* move T0 to seg_reg and compute if the CPU state may change. Never
2379 call this function with seg_reg == R_CS */
2380 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2381 {
2382 if (s->pe && !s->vm86) {
2383 /* XXX: optimize by finding processor state dynamically */
2384 if (s->cc_op != CC_OP_DYNAMIC)
2385 gen_op_set_cc_op(s->cc_op);
2386 gen_jmp_im(cur_eip);
2387 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2388 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2389 /* abort translation because the addseg value may change or
2390 because ss32 may change. For R_SS, translation must always
2391 stop as a special handling must be done to disable hardware
2392 interrupts for the next instruction */
2393 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2394 s->is_jmp = DISAS_TB_JUMP;
2395 } else {
2396 gen_op_movl_seg_T0_vm(seg_reg);
2397 if (seg_reg == R_SS)
2398 s->is_jmp = DISAS_TB_JUMP;
2399 }
2400 }
2401
2402 static inline int svm_is_rep(int prefixes)
2403 {
2404 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2405 }
2406
2407 static inline void
2408 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2409 uint32_t type, uint64_t param)
2410 {
2411 /* no SVM activated; fast case */
2412 if (likely(!(s->flags & HF_SVMI_MASK)))
2413 return;
2414 if (s->cc_op != CC_OP_DYNAMIC)
2415 gen_op_set_cc_op(s->cc_op);
2416 gen_jmp_im(pc_start - s->cs_base);
2417 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2418 tcg_const_i64(param));
2419 }
2420
2421 static inline void
2422 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2423 {
2424 gen_svm_check_intercept_param(s, pc_start, type, 0);
2425 }
2426
2427 static inline void gen_stack_update(DisasContext *s, int addend)
2428 {
2429 #ifdef TARGET_X86_64
2430 if (CODE64(s)) {
2431 gen_op_add_reg_im(2, R_ESP, addend);
2432 } else
2433 #endif
2434 if (s->ss32) {
2435 gen_op_add_reg_im(1, R_ESP, addend);
2436 } else {
2437 gen_op_add_reg_im(0, R_ESP, addend);
2438 }
2439 }
2440
2441 /* generate a push. It depends on ss32, addseg and dflag */
2442 static void gen_push_T0(DisasContext *s)
2443 {
2444 #ifdef TARGET_X86_64
2445 if (CODE64(s)) {
2446 gen_op_movq_A0_reg(R_ESP);
2447 if (s->dflag) {
2448 gen_op_addq_A0_im(-8);
2449 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2450 } else {
2451 gen_op_addq_A0_im(-2);
2452 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2453 }
2454 gen_op_mov_reg_A0(2, R_ESP);
2455 } else
2456 #endif
2457 {
2458 gen_op_movl_A0_reg(R_ESP);
2459 if (!s->dflag)
2460 gen_op_addl_A0_im(-2);
2461 else
2462 gen_op_addl_A0_im(-4);
2463 if (s->ss32) {
2464 if (s->addseg) {
2465 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2466 gen_op_addl_A0_seg(R_SS);
2467 }
2468 } else {
2469 gen_op_andl_A0_ffff();
2470 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2471 gen_op_addl_A0_seg(R_SS);
2472 }
2473 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2474 if (s->ss32 && !s->addseg)
2475 gen_op_mov_reg_A0(1, R_ESP);
2476 else
2477 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2478 }
2479 }
2480
2481 /* generate a push. It depends on ss32, addseg and dflag */
2482 /* slower version for T1, only used for call Ev */
2483 static void gen_push_T1(DisasContext *s)
2484 {
2485 #ifdef TARGET_X86_64
2486 if (CODE64(s)) {
2487 gen_op_movq_A0_reg(R_ESP);
2488 if (s->dflag) {
2489 gen_op_addq_A0_im(-8);
2490 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2491 } else {
2492 gen_op_addq_A0_im(-2);
2493 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2494 }
2495 gen_op_mov_reg_A0(2, R_ESP);
2496 } else
2497 #endif
2498 {
2499 gen_op_movl_A0_reg(R_ESP);
2500 if (!s->dflag)
2501 gen_op_addl_A0_im(-2);
2502 else
2503 gen_op_addl_A0_im(-4);
2504 if (s->ss32) {
2505 if (s->addseg) {
2506 gen_op_addl_A0_seg(R_SS);
2507 }
2508 } else {
2509 gen_op_andl_A0_ffff();
2510 gen_op_addl_A0_seg(R_SS);
2511 }
2512 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2513
2514 if (s->ss32 && !s->addseg)
2515 gen_op_mov_reg_A0(1, R_ESP);
2516 else
2517 gen_stack_update(s, (-2) << s->dflag);
2518 }
2519 }
2520
2521 /* two step pop is necessary for precise exceptions */
2522 static void gen_pop_T0(DisasContext *s)
2523 {
2524 #ifdef TARGET_X86_64
2525 if (CODE64(s)) {
2526 gen_op_movq_A0_reg(R_ESP);
2527 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2528 } else
2529 #endif
2530 {
2531 gen_op_movl_A0_reg(R_ESP);
2532 if (s->ss32) {
2533 if (s->addseg)
2534 gen_op_addl_A0_seg(R_SS);
2535 } else {
2536 gen_op_andl_A0_ffff();
2537 gen_op_addl_A0_seg(R_SS);
2538 }
2539 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2540 }
2541 }
2542
2543 static void gen_pop_update(DisasContext *s)
2544 {
2545 #ifdef TARGET_X86_64
2546 if (CODE64(s) && s->dflag) {
2547 gen_stack_update(s, 8);
2548 } else
2549 #endif
2550 {
2551 gen_stack_update(s, 2 << s->dflag);
2552 }
2553 }
2554
2555 static void gen_stack_A0(DisasContext *s)
2556 {
2557 gen_op_movl_A0_reg(R_ESP);
2558 if (!s->ss32)
2559 gen_op_andl_A0_ffff();
2560 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2561 if (s->addseg)
2562 gen_op_addl_A0_seg(R_SS);
2563 }
2564
2565 /* NOTE: wrap around in 16 bit not fully handled */
2566 static void gen_pusha(DisasContext *s)
2567 {
2568 int i;
2569 gen_op_movl_A0_reg(R_ESP);
2570 gen_op_addl_A0_im(-16 << s->dflag);
2571 if (!s->ss32)
2572 gen_op_andl_A0_ffff();
2573 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2574 if (s->addseg)
2575 gen_op_addl_A0_seg(R_SS);
2576 for(i = 0;i < 8; i++) {
2577 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2578 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2579 gen_op_addl_A0_im(2 << s->dflag);
2580 }
2581 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2582 }
2583
2584 /* NOTE: wrap around in 16 bit not fully handled */
2585 static void gen_popa(DisasContext *s)
2586 {
2587 int i;
2588 gen_op_movl_A0_reg(R_ESP);
2589 if (!s->ss32)
2590 gen_op_andl_A0_ffff();
2591 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2592 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2593 if (s->addseg)
2594 gen_op_addl_A0_seg(R_SS);
2595 for(i = 0;i < 8; i++) {
2596 /* ESP is not reloaded */
2597 if (i != 3) {
2598 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2599 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2600 }
2601 gen_op_addl_A0_im(2 << s->dflag);
2602 }
2603 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2604 }
2605
2606 static void gen_enter(DisasContext *s, int esp_addend, int level)
2607 {
2608 int ot, opsize;
2609
2610 level &= 0x1f;
2611 #ifdef TARGET_X86_64
2612 if (CODE64(s)) {
2613 ot = s->dflag ? OT_QUAD : OT_WORD;
2614 opsize = 1 << ot;
2615
2616 gen_op_movl_A0_reg(R_ESP);
2617 gen_op_addq_A0_im(-opsize);
2618 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2619
2620 /* push bp */
2621 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2622 gen_op_st_T0_A0(ot + s->mem_index);
2623 if (level) {
2624 /* XXX: must save state */
2625 gen_helper_enter64_level(tcg_const_i32(level),
2626 tcg_const_i32((ot == OT_QUAD)),
2627 cpu_T[1]);
2628 }
2629 gen_op_mov_reg_T1(ot, R_EBP);
2630 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2631 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2632 } else
2633 #endif
2634 {
2635 ot = s->dflag + OT_WORD;
2636 opsize = 2 << s->dflag;
2637
2638 gen_op_movl_A0_reg(R_ESP);
2639 gen_op_addl_A0_im(-opsize);
2640 if (!s->ss32)
2641 gen_op_andl_A0_ffff();
2642 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2643 if (s->addseg)
2644 gen_op_addl_A0_seg(R_SS);
2645 /* push bp */
2646 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2647 gen_op_st_T0_A0(ot + s->mem_index);
2648 if (level) {
2649 /* XXX: must save state */
2650 gen_helper_enter_level(tcg_const_i32(level),
2651 tcg_const_i32(s->dflag),
2652 cpu_T[1]);
2653 }
2654 gen_op_mov_reg_T1(ot, R_EBP);
2655 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2656 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2657 }
2658 }
2659
2660 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2661 {
2662 if (s->cc_op != CC_OP_DYNAMIC)
2663 gen_op_set_cc_op(s->cc_op);
2664 gen_jmp_im(cur_eip);
2665 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2666 s->is_jmp = DISAS_TB_JUMP;
2667 }
2668
2669 /* an interrupt is different from an exception because of the
2670 privilege checks */
2671 static void gen_interrupt(DisasContext *s, int intno,
2672 target_ulong cur_eip, target_ulong next_eip)
2673 {
2674 if (s->cc_op != CC_OP_DYNAMIC)
2675 gen_op_set_cc_op(s->cc_op);
2676 gen_jmp_im(cur_eip);
2677 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2678 tcg_const_i32(next_eip - cur_eip));
2679 s->is_jmp = DISAS_TB_JUMP;
2680 }
2681
2682 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2683 {
2684 if (s->cc_op != CC_OP_DYNAMIC)
2685 gen_op_set_cc_op(s->cc_op);
2686 gen_jmp_im(cur_eip);
2687 gen_helper_debug();
2688 s->is_jmp = DISAS_TB_JUMP;
2689 }
2690
2691 /* generate a generic end of block. Trace exception is also generated
2692 if needed */
2693 static void gen_eob(DisasContext *s)
2694 {
2695 if (s->cc_op != CC_OP_DYNAMIC)
2696 gen_op_set_cc_op(s->cc_op);
2697 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2698 gen_helper_reset_inhibit_irq();
2699 }
2700 if (s->tb->flags & HF_RF_MASK) {
2701 gen_helper_reset_rf();
2702 }
2703 if (s->singlestep_enabled) {
2704 gen_helper_debug();
2705 } else if (s->tf) {
2706 gen_helper_single_step();
2707 } else {
2708 tcg_gen_exit_tb(0);
2709 }
2710 s->is_jmp = DISAS_TB_JUMP;
2711 }
2712
2713 /* generate a jump to eip. No segment change must happen before as a
2714 direct call to the next block may occur */
2715 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2716 {
2717 if (s->jmp_opt) {
2718 gen_update_cc_op(s);
2719 gen_goto_tb(s, tb_num, eip);
2720 s->is_jmp = DISAS_TB_JUMP;
2721 } else {
2722 gen_jmp_im(eip);
2723 gen_eob(s);
2724 }
2725 }
2726
2727 static void gen_jmp(DisasContext *s, target_ulong eip)
2728 {
2729 gen_jmp_tb(s, eip, 0);
2730 }
2731
2732 static inline void gen_ldq_env_A0(int idx, int offset)
2733 {
2734 int mem_index = (idx >> 2) - 1;
2735 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2736 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2737 }
2738
2739 static inline void gen_stq_env_A0(int idx, int offset)
2740 {
2741 int mem_index = (idx >> 2) - 1;
2742 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2743 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2744 }
2745
2746 static inline void gen_ldo_env_A0(int idx, int offset)
2747 {
2748 int mem_index = (idx >> 2) - 1;
2749 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2750 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2751 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2752 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2753 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2754 }
2755
2756 static inline void gen_sto_env_A0(int idx, int offset)
2757 {
2758 int mem_index = (idx >> 2) - 1;
2759 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2760 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2761 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2762 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2763 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2764 }
2765
2766 static inline void gen_op_movo(int d_offset, int s_offset)
2767 {
2768 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2769 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2770 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2771 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2772 }
2773
2774 static inline void gen_op_movq(int d_offset, int s_offset)
2775 {
2776 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2777 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2778 }
2779
2780 static inline void gen_op_movl(int d_offset, int s_offset)
2781 {
2782 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2783 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2784 }
2785
2786 static inline void gen_op_movq_env_0(int d_offset)
2787 {
2788 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2789 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2790 }
2791
2792 typedef void (*SSEFunc_i_p)(TCGv_i32 val, TCGv_ptr reg);
2793 typedef void (*SSEFunc_l_p)(TCGv_i64 val, TCGv_ptr reg);
2794 typedef void (*SSEFunc_0_pi)(TCGv_ptr reg, TCGv_i32 val);
2795 typedef void (*SSEFunc_0_pl)(TCGv_ptr reg, TCGv_i64 val);
2796 typedef void (*SSEFunc_0_pp)(TCGv_ptr reg_a, TCGv_ptr reg_b);
2797 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2798 typedef void (*SSEFunc_0_ppt)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv val);
2799
2800 #define SSE_SPECIAL ((void *)1)
2801 #define SSE_DUMMY ((void *)2)
2802
2803 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2804 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2805 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2806
2807 static const SSEFunc_0_pp sse_op_table1[256][4] = {
2808 /* 3DNow! extensions */
2809 [0x0e] = { SSE_DUMMY }, /* femms */
2810 [0x0f] = { SSE_DUMMY }, /* pf... */
2811 /* pure SSE operations */
2812 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2813 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2814 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2815 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2816 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2817 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2818 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2819 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2820
2821 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2822 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2823 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2824 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2825 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2826 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2827 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2828 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2829 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2830 [0x51] = SSE_FOP(sqrt),
2831 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2832 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2833 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2834 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2835 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2836 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2837 [0x58] = SSE_FOP(add),
2838 [0x59] = SSE_FOP(mul),
2839 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2840 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2841 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2842 [0x5c] = SSE_FOP(sub),
2843 [0x5d] = SSE_FOP(min),
2844 [0x5e] = SSE_FOP(div),
2845 [0x5f] = SSE_FOP(max),
2846
2847 [0xc2] = SSE_FOP(cmpeq),
2848 [0xc6] = { (SSEFunc_0_pp)gen_helper_shufps,
2849 (SSEFunc_0_pp)gen_helper_shufpd }, /* XXX: casts */
2850
2851 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2852 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2853
2854 /* MMX ops and their SSE extensions */
2855 [0x60] = MMX_OP2(punpcklbw),
2856 [0x61] = MMX_OP2(punpcklwd),
2857 [0x62] = MMX_OP2(punpckldq),
2858 [0x63] = MMX_OP2(packsswb),
2859 [0x64] = MMX_OP2(pcmpgtb),
2860 [0x65] = MMX_OP2(pcmpgtw),
2861 [0x66] = MMX_OP2(pcmpgtl),
2862 [0x67] = MMX_OP2(packuswb),
2863 [0x68] = MMX_OP2(punpckhbw),
2864 [0x69] = MMX_OP2(punpckhwd),
2865 [0x6a] = MMX_OP2(punpckhdq),
2866 [0x6b] = MMX_OP2(packssdw),
2867 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2868 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2869 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2870 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2871 [0x70] = { (SSEFunc_0_pp)gen_helper_pshufw_mmx,
2872 (SSEFunc_0_pp)gen_helper_pshufd_xmm,
2873 (SSEFunc_0_pp)gen_helper_pshufhw_xmm,
2874 (SSEFunc_0_pp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2875 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2876 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2877 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2878 [0x74] = MMX_OP2(pcmpeqb),
2879 [0x75] = MMX_OP2(pcmpeqw),
2880 [0x76] = MMX_OP2(pcmpeql),
2881 [0x77] = { SSE_DUMMY }, /* emms */
2882 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2883 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2884 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2885 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2886 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2887 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2888 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2889 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2890 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2891 [0xd1] = MMX_OP2(psrlw),
2892 [0xd2] = MMX_OP2(psrld),
2893 [0xd3] = MMX_OP2(psrlq),
2894 [0xd4] = MMX_OP2(paddq),
2895 [0xd5] = MMX_OP2(pmullw),
2896 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2897 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2898 [0xd8] = MMX_OP2(psubusb),
2899 [0xd9] = MMX_OP2(psubusw),
2900 [0xda] = MMX_OP2(pminub),
2901 [0xdb] = MMX_OP2(pand),
2902 [0xdc] = MMX_OP2(paddusb),
2903 [0xdd] = MMX_OP2(paddusw),
2904 [0xde] = MMX_OP2(pmaxub),
2905 [0xdf] = MMX_OP2(pandn),
2906 [0xe0] = MMX_OP2(pavgb),
2907 [0xe1] = MMX_OP2(psraw),
2908 [0xe2] = MMX_OP2(psrad),
2909 [0xe3] = MMX_OP2(pavgw),
2910 [0xe4] = MMX_OP2(pmulhuw),
2911 [0xe5] = MMX_OP2(pmulhw),
2912 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2913 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2914 [0xe8] = MMX_OP2(psubsb),
2915 [0xe9] = MMX_OP2(psubsw),
2916 [0xea] = MMX_OP2(pminsw),
2917 [0xeb] = MMX_OP2(por),
2918 [0xec] = MMX_OP2(paddsb),
2919 [0xed] = MMX_OP2(paddsw),
2920 [0xee] = MMX_OP2(pmaxsw),
2921 [0xef] = MMX_OP2(pxor),
2922 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2923 [0xf1] = MMX_OP2(psllw),
2924 [0xf2] = MMX_OP2(pslld),
2925 [0xf3] = MMX_OP2(psllq),
2926 [0xf4] = MMX_OP2(pmuludq),
2927 [0xf5] = MMX_OP2(pmaddwd),
2928 [0xf6] = MMX_OP2(psadbw),
2929 [0xf7] = { (SSEFunc_0_pp)gen_helper_maskmov_mmx,
2930 (SSEFunc_0_pp)gen_helper_maskmov_xmm }, /* XXX: casts */
2931 [0xf8] = MMX_OP2(psubb),
2932 [0xf9] = MMX_OP2(psubw),
2933 [0xfa] = MMX_OP2(psubl),
2934 [0xfb] = MMX_OP2(psubq),
2935 [0xfc] = MMX_OP2(paddb),
2936 [0xfd] = MMX_OP2(paddw),
2937 [0xfe] = MMX_OP2(paddl),
2938 };
2939
2940 static const SSEFunc_0_pp sse_op_table2[3 * 8][2] = {
2941 [0 + 2] = MMX_OP2(psrlw),
2942 [0 + 4] = MMX_OP2(psraw),
2943 [0 + 6] = MMX_OP2(psllw),
2944 [8 + 2] = MMX_OP2(psrld),
2945 [8 + 4] = MMX_OP2(psrad),
2946 [8 + 6] = MMX_OP2(pslld),
2947 [16 + 2] = MMX_OP2(psrlq),
2948 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2949 [16 + 6] = MMX_OP2(psllq),
2950 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2951 };
2952
2953 static const SSEFunc_0_pi sse_op_table3ai[] = {
2954 gen_helper_cvtsi2ss,
2955 gen_helper_cvtsi2sd
2956 };
2957
2958 #ifdef TARGET_X86_64
2959 static const SSEFunc_0_pl sse_op_table3aq[] = {
2960 gen_helper_cvtsq2ss,
2961 gen_helper_cvtsq2sd
2962 };
2963 #endif
2964
2965 static const SSEFunc_i_p sse_op_table3bi[] = {
2966 gen_helper_cvttss2si,
2967 gen_helper_cvtss2si,
2968 gen_helper_cvttsd2si,
2969 gen_helper_cvtsd2si
2970 };
2971
2972 #ifdef TARGET_X86_64
2973 static const SSEFunc_l_p sse_op_table3bq[] = {
2974 gen_helper_cvttss2sq,
2975 gen_helper_cvtss2sq,
2976 gen_helper_cvttsd2sq,
2977 gen_helper_cvtsd2sq
2978 };
2979 #endif
2980
2981 static const SSEFunc_0_pp sse_op_table4[8][4] = {
2982 SSE_FOP(cmpeq),
2983 SSE_FOP(cmplt),
2984 SSE_FOP(cmple),
2985 SSE_FOP(cmpunord),
2986 SSE_FOP(cmpneq),
2987 SSE_FOP(cmpnlt),
2988 SSE_FOP(cmpnle),
2989 SSE_FOP(cmpord),
2990 };
2991
2992 static const SSEFunc_0_pp sse_op_table5[256] = {
2993 [0x0c] = gen_helper_pi2fw,
2994 [0x0d] = gen_helper_pi2fd,
2995 [0x1c] = gen_helper_pf2iw,
2996 [0x1d] = gen_helper_pf2id,
2997 [0x8a] = gen_helper_pfnacc,
2998 [0x8e] = gen_helper_pfpnacc,
2999 [0x90] = gen_helper_pfcmpge,
3000 [0x94] = gen_helper_pfmin,
3001 [0x96] = gen_helper_pfrcp,
3002 [0x97] = gen_helper_pfrsqrt,
3003 [0x9a] = gen_helper_pfsub,
3004 [0x9e] = gen_helper_pfadd,
3005 [0xa0] = gen_helper_pfcmpgt,
3006 [0xa4] = gen_helper_pfmax,
3007 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3008 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3009 [0xaa] = gen_helper_pfsubr,
3010 [0xae] = gen_helper_pfacc,
3011 [0xb0] = gen_helper_pfcmpeq,
3012 [0xb4] = gen_helper_pfmul,
3013 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3014 [0xb7] = gen_helper_pmulhrw_mmx,
3015 [0xbb] = gen_helper_pswapd,
3016 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3017 };
3018
3019 struct SSEOpHelper_pp {
3020 SSEFunc_0_pp op[2];
3021 uint32_t ext_mask;
3022 };
3023
3024 struct SSEOpHelper_ppi {
3025 SSEFunc_0_ppi op[2];
3026 uint32_t ext_mask;
3027 };
3028
3029 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3030 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3031 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3032 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3033
3034 static const struct SSEOpHelper_pp sse_op_table6[256] = {
3035 [0x00] = SSSE3_OP(pshufb),
3036 [0x01] = SSSE3_OP(phaddw),
3037 [0x02] = SSSE3_OP(phaddd),
3038 [0x03] = SSSE3_OP(phaddsw),
3039 [0x04] = SSSE3_OP(pmaddubsw),
3040 [0x05] = SSSE3_OP(phsubw),
3041 [0x06] = SSSE3_OP(phsubd),
3042 [0x07] = SSSE3_OP(phsubsw),
3043 [0x08] = SSSE3_OP(psignb),
3044 [0x09] = SSSE3_OP(psignw),
3045 [0x0a] = SSSE3_OP(psignd),
3046 [0x0b] = SSSE3_OP(pmulhrsw),
3047 [0x10] = SSE41_OP(pblendvb),
3048 [0x14] = SSE41_OP(blendvps),
3049 [0x15] = SSE41_OP(blendvpd),
3050 [0x17] = SSE41_OP(ptest),
3051 [0x1c] = SSSE3_OP(pabsb),
3052 [0x1d] = SSSE3_OP(pabsw),
3053 [0x1e] = SSSE3_OP(pabsd),
3054 [0x20] = SSE41_OP(pmovsxbw),
3055 [0x21] = SSE41_OP(pmovsxbd),
3056 [0x22] = SSE41_OP(pmovsxbq),
3057 [0x23] = SSE41_OP(pmovsxwd),
3058 [0x24] = SSE41_OP(pmovsxwq),
3059 [0x25] = SSE41_OP(pmovsxdq),
3060 [0x28] = SSE41_OP(pmuldq),
3061 [0x29] = SSE41_OP(pcmpeqq),
3062 [0x2a] = SSE41_SPECIAL, /* movntqda */
3063 [0x2b] = SSE41_OP(packusdw),
3064 [0x30] = SSE41_OP(pmovzxbw),
3065 [0x31] = SSE41_OP(pmovzxbd),
3066 [0x32] = SSE41_OP(pmovzxbq),
3067 [0x33] = SSE41_OP(pmovzxwd),
3068 [0x34] = SSE41_OP(pmovzxwq),
3069 [0x35] = SSE41_OP(pmovzxdq),
3070 [0x37] = SSE42_OP(pcmpgtq),
3071 [0x38] = SSE41_OP(pminsb),
3072 [0x39] = SSE41_OP(pminsd),
3073 [0x3a] = SSE41_OP(pminuw),
3074 [0x3b] = SSE41_OP(pminud),
3075 [0x3c] = SSE41_OP(pmaxsb),
3076 [0x3d] = SSE41_OP(pmaxsd),
3077 [0x3e] = SSE41_OP(pmaxuw),
3078 [0x3f] = SSE41_OP(pmaxud),
3079 [0x40] = SSE41_OP(pmulld),
3080 [0x41] = SSE41_OP(phminposuw),
3081 };
3082
3083 static const struct SSEOpHelper_ppi sse_op_table7[256] = {
3084 [0x08] = SSE41_OP(roundps),
3085 [0x09] = SSE41_OP(roundpd),
3086 [0x0a] = SSE41_OP(roundss),
3087 [0x0b] = SSE41_OP(roundsd),
3088 [0x0c] = SSE41_OP(blendps),
3089 [0x0d] = SSE41_OP(blendpd),
3090 [0x0e] = SSE41_OP(pblendw),
3091 [0x0f] = SSSE3_OP(palignr),
3092 [0x14] = SSE41_SPECIAL, /* pextrb */
3093 [0x15] = SSE41_SPECIAL, /* pextrw */
3094 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3095 [0x17] = SSE41_SPECIAL, /* extractps */
3096 [0x20] = SSE41_SPECIAL, /* pinsrb */
3097 [0x21] = SSE41_SPECIAL, /* insertps */
3098 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3099 [0x40] = SSE41_OP(dpps),
3100 [0x41] = SSE41_OP(dppd),
3101 [0x42] = SSE41_OP(mpsadbw),
3102 [0x60] = SSE42_OP(pcmpestrm),
3103 [0x61] = SSE42_OP(pcmpestri),
3104 [0x62] = SSE42_OP(pcmpistrm),
3105 [0x63] = SSE42_OP(pcmpistri),
3106 };
3107
3108 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3109 {
3110 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3111 int modrm, mod, rm, reg, reg_addr, offset_addr;
3112 SSEFunc_0_pp sse_fn_pp;
3113 SSEFunc_0_ppi sse_fn_ppi;
3114 SSEFunc_0_ppt sse_fn_ppt;
3115
3116 b &= 0xff;
3117 if (s->prefix & PREFIX_DATA)
3118 b1 = 1;
3119 else if (s->prefix & PREFIX_REPZ)
3120 b1 = 2;
3121 else if (s->prefix & PREFIX_REPNZ)
3122 b1 = 3;
3123 else
3124 b1 = 0;
3125 sse_fn_pp = sse_op_table1[b][b1];
3126 if (!sse_fn_pp) {
3127 goto illegal_op;
3128 }
3129 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3130 is_xmm = 1;
3131 } else {
3132 if (b1 == 0) {
3133 /* MMX case */
3134 is_xmm = 0;
3135 } else {
3136 is_xmm = 1;
3137 }
3138 }
3139 /* simple MMX/SSE operation */
3140 if (s->flags & HF_TS_MASK) {
3141 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3142 return;
3143 }
3144 if (s->flags & HF_EM_MASK) {
3145 illegal_op:
3146 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3147 return;
3148 }
3149 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3150 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3151 goto illegal_op;
3152 if (b == 0x0e) {
3153 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3154 goto illegal_op;
3155 /* femms */
3156 gen_helper_emms();
3157 return;
3158 }
3159 if (b == 0x77) {
3160 /* emms */
3161 gen_helper_emms();
3162 return;
3163 }
3164 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3165 the static cpu state) */
3166 if (!is_xmm) {
3167 gen_helper_enter_mmx();
3168 }
3169
3170 modrm = ldub_code(s->pc++);
3171 reg = ((modrm >> 3) & 7);
3172 if (is_xmm)
3173 reg |= rex_r;
3174 mod = (modrm >> 6) & 3;
3175 if (sse_fn_pp == SSE_SPECIAL) {
3176 b |= (b1 << 8);
3177 switch(b) {
3178 case 0x0e7: /* movntq */
3179 if (mod == 3)
3180 goto illegal_op;
3181 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3182 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3183 break;
3184 case 0x1e7: /* movntdq */
3185 case 0x02b: /* movntps */
3186 case 0x12b: /* movntps */
3187 if (mod == 3)
3188 goto illegal_op;
3189 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3190 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3191 break;
3192 case 0x3f0: /* lddqu */
3193 if (mod == 3)
3194 goto illegal_op;
3195 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3196 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3197 break;
3198 case 0x22b: /* movntss */
3199 case 0x32b: /* movntsd */
3200 if (mod == 3)
3201 goto illegal_op;
3202 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3203 if (b1 & 1) {
3204 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3205 xmm_regs[reg]));
3206 } else {
3207 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3208 xmm_regs[reg].XMM_L(0)));
3209 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3210 }
3211 break;
3212 case 0x6e: /* movd mm, ea */
3213 #ifdef TARGET_X86_64
3214 if (s->dflag == 2) {
3215 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3216 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3217 } else
3218 #endif
3219 {
3220 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3221 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3222 offsetof(CPUX86State,fpregs[reg].mmx));
3223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3224 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3225 }
3226 break;
3227 case 0x16e: /* movd xmm, ea */
3228 #ifdef TARGET_X86_64
3229 if (s->dflag == 2) {
3230 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3231 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3232 offsetof(CPUX86State,xmm_regs[reg]));
3233 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3234 } else
3235 #endif
3236 {
3237 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3238 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3239 offsetof(CPUX86State,xmm_regs[reg]));
3240 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3241 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3242 }
3243 break;
3244 case 0x6f: /* movq mm, ea */
3245 if (mod != 3) {
3246 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3247 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3248 } else {
3249 rm = (modrm & 7);
3250 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3251 offsetof(CPUX86State,fpregs[rm].mmx));
3252 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3253 offsetof(CPUX86State,fpregs[reg].mmx));
3254 }
3255 break;
3256 case 0x010: /* movups */
3257 case 0x110: /* movupd */
3258 case 0x028: /* movaps */
3259 case 0x128: /* movapd */
3260 case 0x16f: /* movdqa xmm, ea */
3261 case 0x26f: /* movdqu xmm, ea */
3262 if (mod != 3) {
3263 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3264 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3265 } else {
3266 rm = (modrm & 7) | REX_B(s);
3267 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3268 offsetof(CPUX86State,xmm_regs[rm]));
3269 }
3270 break;
3271 case 0x210: /* movss xmm, ea */
3272 if (mod != 3) {
3273 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3274 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3275 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3276 gen_op_movl_T0_0();
3277 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3278 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3279 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3280 } else {
3281 rm = (modrm & 7) | REX_B(s);
3282 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3283 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3284 }
3285 break;
3286 case 0x310: /* movsd xmm, ea */
3287 if (mod != 3) {
3288 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3289 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3290 gen_op_movl_T0_0();
3291 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3292 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3293 } else {
3294 rm = (modrm & 7) | REX_B(s);
3295 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3296 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3297 }
3298 break;
3299 case 0x012: /* movlps */
3300 case 0x112: /* movlpd */
3301 if (mod != 3) {
3302 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3303 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3304 } else {
3305 /* movhlps */
3306 rm = (modrm & 7) | REX_B(s);
3307 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3308 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3309 }
3310 break;
3311 case 0x212: /* movsldup */
3312 if (mod != 3) {
3313 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3314 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3315 } else {
3316 rm = (modrm & 7) | REX_B(s);
3317 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3318 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3319 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3320 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3321 }
3322 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3323 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3324 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3325 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3326 break;
3327 case 0x312: /* movddup */
3328 if (mod != 3) {
3329 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3330 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3331 } else {
3332 rm = (modrm & 7) | REX_B(s);
3333 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3334 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3335 }
3336 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3337 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3338 break;
3339 case 0x016: /* movhps */
3340 case 0x116: /* movhpd */
3341 if (mod != 3) {
3342 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3343 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3344 } else {
3345 /* movlhps */
3346 rm = (modrm & 7) | REX_B(s);
3347 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3348 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3349 }
3350 break;
3351 case 0x216: /* movshdup */
3352 if (mod != 3) {
3353 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3354 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3355 } else {
3356 rm = (modrm & 7) | REX_B(s);
3357 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3358 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3359 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3360 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3361 }
3362 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3363 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3364 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3365 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3366 break;
3367 case 0x178:
3368 case 0x378:
3369 {
3370 int bit_index, field_length;
3371
3372 if (b1 == 1 && reg != 0)
3373 goto illegal_op;
3374 field_length = ldub_code(s->pc++) & 0x3F;
3375 bit_index = ldub_code(s->pc++) & 0x3F;
3376 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3377 offsetof(CPUX86State,xmm_regs[reg]));
3378 if (b1 == 1)
3379 gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3380 tcg_const_i32(field_length));
3381 else
3382 gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3383 tcg_const_i32(field_length));
3384 }
3385 break;
3386 case 0x7e: /* movd ea, mm */
3387 #ifdef TARGET_X86_64
3388 if (s->dflag == 2) {
3389 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3390 offsetof(CPUX86State,fpregs[reg].mmx));
3391 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3392 } else
3393 #endif
3394 {
3395 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3396 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3397 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3398 }
3399 break;
3400 case 0x17e: /* movd ea, xmm */
3401 #ifdef TARGET_X86_64
3402 if (s->dflag == 2) {
3403 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3404 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3405 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3406 } else
3407 #endif
3408 {
3409 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3410 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3411 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3412 }
3413 break;
3414 case 0x27e: /* movq xmm, ea */
3415 if (mod != 3) {
3416 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3417 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3418 } else {
3419 rm = (modrm & 7) | REX_B(s);
3420 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3421 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3422 }
3423 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3424 break;
3425 case 0x7f: /* movq ea, mm */
3426 if (mod != 3) {
3427 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3428 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3429 } else {
3430 rm = (modrm & 7);
3431 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3432 offsetof(CPUX86State,fpregs[reg].mmx));
3433 }
3434 break;
3435 case 0x011: /* movups */
3436 case 0x111: /* movupd */
3437 case 0x029: /* movaps */
3438 case 0x129: /* movapd */
3439 case 0x17f: /* movdqa ea, xmm */
3440 case 0x27f: /* movdqu ea, xmm */
3441 if (mod != 3) {
3442 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3443 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3444 } else {
3445 rm = (modrm & 7) | REX_B(s);
3446 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3447 offsetof(CPUX86State,xmm_regs[reg]));
3448 }
3449 break;
3450 case 0x211: /* movss ea, xmm */
3451 if (mod != 3) {
3452 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3453 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3454 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3455 } else {
3456 rm = (modrm & 7) | REX_B(s);
3457 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3458 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3459 }
3460 break;
3461 case 0x311: /* movsd ea, xmm */
3462 if (mod != 3) {
3463 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3464 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3465 } else {
3466 rm = (modrm & 7) | REX_B(s);
3467 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3468 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3469 }
3470 break;
3471 case 0x013: /* movlps */
3472 case 0x113: /* movlpd */
3473 if (mod != 3) {
3474 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3475 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3476 } else {
3477 goto illegal_op;
3478 }
3479 break;
3480 case 0x017: /* movhps */
3481 case 0x117: /* movhpd */
3482 if (mod != 3) {
3483 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3484 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3485 } else {
3486 goto illegal_op;
3487 }
3488 break;
3489 case 0x71: /* shift mm, im */
3490 case 0x72:
3491 case 0x73:
3492 case 0x171: /* shift xmm, im */
3493 case 0x172:
3494 case 0x173:
3495 if (b1 >= 2) {
3496 goto illegal_op;
3497 }
3498 val = ldub_code(s->pc++);
3499 if (is_xmm) {
3500 gen_op_movl_T0_im(val);
3501 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3502 gen_op_movl_T0_0();
3503 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3504 op1_offset = offsetof(CPUX86State,xmm_t0);
3505 } else {
3506 gen_op_movl_T0_im(val);
3507 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3508 gen_op_movl_T0_0();
3509 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3510 op1_offset = offsetof(CPUX86State,mmx_t0);
3511 }
3512 sse_fn_pp = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3513 if (!sse_fn_pp) {
3514 goto illegal_op;
3515 }
3516 if (is_xmm) {
3517 rm = (modrm & 7) | REX_B(s);
3518 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3519 } else {
3520 rm = (modrm & 7);
3521 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3522 }
3523 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3524 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3525 sse_fn_pp(cpu_ptr0, cpu_ptr1);
3526 break;
3527 case 0x050: /* movmskps */
3528 rm = (modrm & 7) | REX_B(s);
3529 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3530 offsetof(CPUX86State,xmm_regs[rm]));
3531 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3532 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3533 gen_op_mov_reg_T0(OT_LONG, reg);
3534 break;
3535 case 0x150: /* movmskpd */
3536 rm = (modrm & 7) | REX_B(s);
3537 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3538 offsetof(CPUX86State,xmm_regs[rm]));
3539 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3540 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3541 gen_op_mov_reg_T0(OT_LONG, reg);
3542 break;
3543 case 0x02a: /* cvtpi2ps */
3544 case 0x12a: /* cvtpi2pd */
3545 gen_helper_enter_mmx();
3546 if (mod != 3) {
3547 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3548 op2_offset = offsetof(CPUX86State,mmx_t0);
3549 gen_ldq_env_A0(s->mem_index, op2_offset);
3550 } else {
3551 rm = (modrm & 7);
3552 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3553 }
3554 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3555 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3556 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3557 switch(b >> 8) {
3558 case 0x0:
3559 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3560 break;
3561 default:
3562 case 0x1:
3563 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3564 break;
3565 }
3566 break;
3567 case 0x22a: /* cvtsi2ss */
3568 case 0x32a: /* cvtsi2sd */
3569 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3570 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3571 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3572 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3573 if (ot == OT_LONG) {
3574 SSEFunc_0_pi sse_fn_pi = sse_op_table3ai[(b >> 8) & 1];
3575 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3576 sse_fn_pi(cpu_ptr0, cpu_tmp2_i32);
3577 } else {
3578 #ifdef TARGET_X86_64
3579 SSEFunc_0_pl sse_fn_pl = sse_op_table3aq[(b >> 8) & 1];
3580 sse_fn_pl(cpu_ptr0, cpu_T[0]);
3581 #else
3582 goto illegal_op;
3583 #endif
3584 }
3585 break;
3586 case 0x02c: /* cvttps2pi */
3587 case 0x12c: /* cvttpd2pi */
3588 case 0x02d: /* cvtps2pi */
3589 case 0x12d: /* cvtpd2pi */
3590 gen_helper_enter_mmx();
3591 if (mod != 3) {
3592 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3593 op2_offset = offsetof(CPUX86State,xmm_t0);
3594 gen_ldo_env_A0(s->mem_index, op2_offset);
3595 } else {
3596 rm = (modrm & 7) | REX_B(s);
3597 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3598 }
3599 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3600 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3601 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3602 switch(b) {
3603 case 0x02c:
3604 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3605 break;
3606 case 0x12c:
3607 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3608 break;
3609 case 0x02d:
3610 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3611 break;
3612 case 0x12d:
3613 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3614 break;
3615 }
3616 break;
3617 case 0x22c: /* cvttss2si */
3618 case 0x32c: /* cvttsd2si */
3619 case 0x22d: /* cvtss2si */
3620 case 0x32d: /* cvtsd2si */
3621 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3622 if (mod != 3) {
3623 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3624 if ((b >> 8) & 1) {
3625 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3626 } else {
3627 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3628 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3629 }
3630 op2_offset = offsetof(CPUX86State,xmm_t0);
3631 } else {
3632 rm = (modrm & 7) | REX_B(s);
3633 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3634 }
3635 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3636 if (ot == OT_LONG) {
3637 SSEFunc_i_p sse_fn_i_p =
3638 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3639 sse_fn_i_p(cpu_tmp2_i32, cpu_ptr0);
3640 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3641 } else {
3642 #ifdef TARGET_X86_64
3643 SSEFunc_l_p sse_fn_l_p =
3644 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3645 sse_fn_l_p(cpu_T[0], cpu_ptr0);
3646 #else
3647 goto illegal_op;
3648 #endif
3649 }
3650 gen_op_mov_reg_T0(ot, reg);
3651 break;
3652 case 0xc4: /* pinsrw */
3653 case 0x1c4:
3654 s->rip_offset = 1;
3655 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3656 val = ldub_code(s->pc++);
3657 if (b1) {
3658 val &= 7;
3659 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3660 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3661 } else {
3662 val &= 3;
3663 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3664 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3665 }
3666 break;
3667 case 0xc5: /* pextrw */
3668 case 0x1c5:
3669 if (mod != 3)
3670 goto illegal_op;
3671 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3672 val = ldub_code(s->pc++);
3673 if (b1) {
3674 val &= 7;
3675 rm = (modrm & 7) | REX_B(s);
3676 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3677 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3678 } else {
3679 val &= 3;
3680 rm = (modrm & 7);
3681 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3682 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3683 }
3684 reg = ((modrm >> 3) & 7) | rex_r;
3685 gen_op_mov_reg_T0(ot, reg);
3686 break;
3687 case 0x1d6: /* movq ea, xmm */
3688 if (mod != 3) {
3689 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3690 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3691 } else {
3692 rm = (modrm & 7) | REX_B(s);
3693 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3694 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3695 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3696 }
3697 break;
3698 case 0x2d6: /* movq2dq */
3699 gen_helper_enter_mmx();
3700 rm = (modrm & 7);
3701 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3702 offsetof(CPUX86State,fpregs[rm].mmx));
3703 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3704 break;
3705 case 0x3d6: /* movdq2q */
3706 gen_helper_enter_mmx();
3707 rm = (modrm & 7) | REX_B(s);
3708 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3709 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3710 break;
3711 case 0xd7: /* pmovmskb */
3712 case 0x1d7:
3713 if (mod != 3)
3714 goto illegal_op;
3715 if (b1) {
3716 rm = (modrm & 7) | REX_B(s);
3717 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3718 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3719 } else {
3720 rm = (modrm & 7);
3721 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3722 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3723 }
3724 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3725 reg = ((modrm >> 3) & 7) | rex_r;
3726 gen_op_mov_reg_T0(OT_LONG, reg);
3727 break;
3728 case 0x138:
3729 if (s->prefix & PREFIX_REPNZ)
3730 goto crc32;
3731 case 0x038:
3732 b = modrm;
3733 modrm = ldub_code(s->pc++);
3734 rm = modrm & 7;
3735 reg = ((modrm >> 3) & 7) | rex_r;
3736 mod = (modrm >> 6) & 3;
3737 if (b1 >= 2) {
3738 goto illegal_op;
3739 }
3740
3741 sse_fn_pp = sse_op_table6[b].op[b1];
3742 if (!sse_fn_pp) {
3743 goto illegal_op;
3744 }
3745 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3746 goto illegal_op;
3747
3748 if (b1) {
3749 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3750 if (mod == 3) {
3751 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3752 } else {
3753 op2_offset = offsetof(CPUX86State,xmm_t0);
3754 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3755 switch (b) {
3756 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3757 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3758 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3759 gen_ldq_env_A0(s->mem_index, op2_offset +
3760 offsetof(XMMReg, XMM_Q(0)));
3761 break;
3762 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3763 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3764 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3765 (s->mem_index >> 2) - 1);
3766 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3767 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3768 offsetof(XMMReg, XMM_L(0)));
3769 break;
3770 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3771 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3772 (s->mem_index >> 2) - 1);
3773 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3774 offsetof(XMMReg, XMM_W(0)));
3775 break;
3776 case 0x2a: /* movntqda */
3777 gen_ldo_env_A0(s->mem_index, op1_offset);
3778 return;
3779 default:
3780 gen_ldo_env_A0(s->mem_index, op2_offset);
3781 }
3782 }
3783 } else {
3784 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3785 if (mod == 3) {
3786 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3787 } else {
3788 op2_offset = offsetof(CPUX86State,mmx_t0);
3789 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3790 gen_ldq_env_A0(s->mem_index, op2_offset);
3791 }
3792 }
3793 if (sse_fn_pp == SSE_SPECIAL) {
3794 goto illegal_op;
3795 }
3796
3797 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3798 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3799 sse_fn_pp(cpu_ptr0, cpu_ptr1);
3800
3801 if (b == 0x17)
3802 s->cc_op = CC_OP_EFLAGS;
3803 break;
3804 case 0x338: /* crc32 */
3805 crc32:
3806 b = modrm;
3807 modrm = ldub_code(s->pc++);
3808 reg = ((modrm >> 3) & 7) | rex_r;
3809
3810 if (b != 0xf0 && b != 0xf1)
3811 goto illegal_op;
3812 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3813 goto illegal_op;
3814
3815 if (b == 0xf0)
3816 ot = OT_BYTE;
3817 else if (b == 0xf1 && s->dflag != 2)
3818 if (s->prefix & PREFIX_DATA)
3819 ot = OT_WORD;
3820 else
3821 ot = OT_LONG;
3822 else
3823 ot = OT_QUAD;
3824
3825 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3826 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3827 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3828 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3829 cpu_T[0], tcg_const_i32(8 << ot));
3830
3831 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3832 gen_op_mov_reg_T0(ot, reg);
3833 break;
3834 case 0x03a:
3835 case 0x13a:
3836 b = modrm;
3837 modrm = ldub_code(s->pc++);
3838 rm = modrm & 7;
3839 reg = ((modrm >> 3) & 7) | rex_r;
3840 mod = (modrm >> 6) & 3;
3841 if (b1 >= 2) {
3842 goto illegal_op;
3843 }
3844
3845 sse_fn_ppi = sse_op_table7[b].op[b1];
3846 if (!sse_fn_ppi) {
3847 goto illegal_op;
3848 }
3849 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3850 goto illegal_op;
3851
3852 if (sse_fn_ppi == SSE_SPECIAL) {
3853 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3854 rm = (modrm & 7) | REX_B(s);
3855 if (mod != 3)
3856 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3857 reg = ((modrm >> 3) & 7) | rex_r;
3858 val = ldub_code(s->pc++);
3859 switch (b) {
3860 case 0x14: /* pextrb */
3861 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3862 xmm_regs[reg].XMM_B(val & 15)));
3863 if (mod == 3)
3864 gen_op_mov_reg_T0(ot, rm);
3865 else
3866 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3867 (s->mem_index >> 2) - 1);
3868 break;
3869 case 0x15: /* pextrw */
3870 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3871 xmm_regs[reg].XMM_W(val & 7)));
3872 if (mod == 3)
3873 gen_op_mov_reg_T0(ot, rm);
3874 else
3875 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3876 (s->mem_index >> 2) - 1);
3877 break;
3878 case 0x16:
3879 if (ot == OT_LONG) { /* pextrd */
3880 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3881 offsetof(CPUX86State,
3882 xmm_regs[reg].XMM_L(val & 3)));
3883 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3884 if (mod == 3)
3885 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3886 else
3887 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3888 (s->mem_index >> 2) - 1);
3889 } else { /* pextrq */
3890 #ifdef TARGET_X86_64
3891 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3892 offsetof(CPUX86State,
3893 xmm_regs[reg].XMM_Q(val & 1)));
3894 if (mod == 3)
3895 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3896 else
3897 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3898 (s->mem_index >> 2) - 1);
3899 #else
3900 goto illegal_op;
3901 #endif
3902 }
3903 break;
3904 case 0x17: /* extractps */
3905 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3906 xmm_regs[reg].XMM_L(val & 3)));
3907 if (mod == 3)
3908 gen_op_mov_reg_T0(ot, rm);
3909 else
3910 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3911 (s->mem_index >> 2) - 1);
3912 break;
3913 case 0x20: /* pinsrb */
3914 if (mod == 3)
3915 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3916 else
3917 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3918 (s->mem_index >> 2) - 1);
3919 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3920 xmm_regs[reg].XMM_B(val & 15)));
3921 break;
3922 case 0x21: /* insertps */
3923 if (mod == 3) {
3924 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3925 offsetof(CPUX86State,xmm_regs[rm]
3926 .XMM_L((val >> 6) & 3)));
3927 } else {
3928 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3929 (s->mem_index >> 2) - 1);
3930 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3931 }
3932 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3933 offsetof(CPUX86State,xmm_regs[reg]
3934 .XMM_L((val >> 4) & 3)));
3935 if ((val >> 0) & 1)
3936 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3937 cpu_env, offsetof(CPUX86State,
3938 xmm_regs[reg].XMM_L(0)));
3939 if ((val >> 1) & 1)
3940 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3941 cpu_env, offsetof(CPUX86State,
3942 xmm_regs[reg].XMM_L(1)));
3943 if ((val >> 2) & 1)
3944 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3945 cpu_env, offsetof(CPUX86State,
3946 xmm_regs[reg].XMM_L(2)));
3947 if ((val >> 3) & 1)
3948 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3949 cpu_env, offsetof(CPUX86State,
3950 xmm_regs[reg].XMM_L(3)));
3951 break;
3952 case 0x22:
3953 if (ot == OT_LONG) { /* pinsrd */
3954 if (mod == 3)
3955 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3956 else
3957 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3958 (s->mem_index >> 2) - 1);
3959 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3960 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3961 offsetof(CPUX86State,
3962 xmm_regs[reg].XMM_L(val & 3)));
3963 } else { /* pinsrq */
3964 #ifdef TARGET_X86_64
3965 if (mod == 3)
3966 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3967 else
3968 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3969 (s->mem_index >> 2) - 1);
3970 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3971 offsetof(CPUX86State,
3972 xmm_regs[reg].XMM_Q(val & 1)));
3973 #else
3974 goto illegal_op;
3975 #endif
3976 }
3977 break;
3978 }
3979 return;
3980 }
3981
3982 if (b1) {
3983 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3984 if (mod == 3) {
3985 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3986 } else {
3987 op2_offset = offsetof(CPUX86State,xmm_t0);
3988 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3989 gen_ldo_env_A0(s->mem_index, op2_offset);
3990 }
3991 } else {
3992 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3993 if (mod == 3) {
3994 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3995 } else {
3996 op2_offset = offsetof(CPUX86State,mmx_t0);
3997 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3998 gen_ldq_env_A0(s->mem_index, op2_offset);
3999 }
4000 }
4001 val = ldub_code(s->pc++);
4002
4003 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4004 s->cc_op = CC_OP_EFLAGS;
4005
4006 if (s->dflag == 2)
4007 /* The helper must use entire 64-bit gp registers */
4008 val |= 1 << 8;
4009 }
4010
4011 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4012 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4013 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4014 break;
4015 default:
4016 goto illegal_op;
4017 }
4018 } else {
4019 /* generic MMX or SSE operation */
4020 switch(b) {
4021 case 0x70: /* pshufx insn */
4022 case 0xc6: /* pshufx insn */
4023 case 0xc2: /* compare insns */
4024 s->rip_offset = 1;
4025 break;
4026 default:
4027 break;
4028 }
4029 if (is_xmm) {
4030 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4031 if (mod != 3) {
4032 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4033 op2_offset = offsetof(CPUX86State,xmm_t0);
4034 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4035 b == 0xc2)) {
4036 /* specific case for SSE single instructions */
4037 if (b1 == 2) {
4038 /* 32 bit access */
4039 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4040 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4041 } else {
4042 /* 64 bit access */
4043 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4044 }
4045 } else {
4046 gen_ldo_env_A0(s->mem_index, op2_offset);
4047 }
4048 } else {
4049 rm = (modrm & 7) | REX_B(s);
4050 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4051 }
4052 } else {
4053 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4054 if (mod != 3) {
4055 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4056 op2_offset = offsetof(CPUX86State,mmx_t0);
4057 gen_ldq_env_A0(s->mem_index, op2_offset);
4058 } else {
4059 rm = (modrm & 7);
4060 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4061 }
4062 }
4063 switch(b) {
4064 case 0x0f: /* 3DNow! data insns */
4065 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4066 goto illegal_op;
4067 val = ldub_code(s->pc++);
4068 sse_fn_pp = sse_op_table5[val];
4069 if (!sse_fn_pp) {
4070 goto illegal_op;
4071 }
4072 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4073 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4074 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4075 break;
4076 case 0x70: /* pshufx insn */
4077 case 0xc6: /* pshufx insn */
4078 val = ldub_code(s->pc++);
4079 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4080 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4081 /* XXX: introduce a new table? */
4082 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_pp;
4083 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4084 break;
4085 case 0xc2:
4086 /* compare insns */
4087 val = ldub_code(s->pc++);
4088 if (val >= 8)
4089 goto illegal_op;
4090 sse_fn_pp = sse_op_table4[val][b1];
4091
4092 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4093 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4094 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4095 break;
4096 case 0xf7:
4097 /* maskmov : we must prepare A0 */
4098 if (mod != 3)
4099 goto illegal_op;
4100 #ifdef TARGET_X86_64
4101 if (s->aflag == 2) {
4102 gen_op_movq_A0_reg(R_EDI);
4103 } else
4104 #endif
4105 {
4106 gen_op_movl_A0_reg(R_EDI);
4107 if (s->aflag == 0)
4108 gen_op_andl_A0_ffff();
4109 }
4110 gen_add_A0_ds_seg(s);
4111
4112 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4113 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4114 /* XXX: introduce a new table? */
4115 sse_fn_ppt = (SSEFunc_0_ppt)sse_fn_pp;
4116 sse_fn_ppt(cpu_ptr0, cpu_ptr1, cpu_A0);
4117 break;
4118 default:
4119 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4120 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4121 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4122 break;
4123 }
4124 if (b == 0x2e || b == 0x2f) {
4125 s->cc_op = CC_OP_EFLAGS;
4126 }
4127 }
4128 }
4129
4130 /* convert one instruction. s->is_jmp is set if the translation must
4131 be stopped. Return the next pc value */
4132 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4133 {
4134 int b, prefixes, aflag, dflag;
4135 int shift, ot;
4136 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4137 target_ulong next_eip, tval;
4138 int rex_w, rex_r;
4139
4140 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4141 tcg_gen_debug_insn_start(pc_start);
4142 s->pc = pc_start;
4143 prefixes = 0;
4144 aflag = s->code32;
4145 dflag = s->code32;
4146 s->override = -1;
4147 rex_w = -1;
4148 rex_r = 0;
4149 #ifdef TARGET_X86_64
4150 s->rex_x = 0;
4151 s->rex_b = 0;
4152 x86_64_hregs = 0;
4153 #endif
4154 s->rip_offset = 0; /* for relative ip address */
4155 next_byte:
4156 b = ldub_code(s->pc);
4157 s->pc++;
4158 /* check prefixes */
4159 #ifdef TARGET_X86_64
4160 if (CODE64(s)) {
4161 switch (b) {
4162 case 0xf3:
4163 prefixes |= PREFIX_REPZ;
4164 goto next_byte;
4165 case 0xf2:
4166 prefixes |= PREFIX_REPNZ;
4167 goto next_byte;
4168 case 0xf0:
4169 prefixes |= PREFIX_LOCK;
4170 goto next_byte;
4171 case 0x2e:
4172 s->override = R_CS;
4173 goto next_byte;
4174 case 0x36:
4175 s->override = R_SS;
4176 goto next_byte;
4177 case 0x3e:
4178 s->override = R_DS;
4179 goto next_byte;
4180 case 0x26:
4181 s->override = R_ES;
4182 goto next_byte;
4183 case 0x64:
4184 s->override = R_FS;
4185 goto next_byte;
4186 case 0x65:
4187 s->override = R_GS;
4188 goto next_byte;
4189 case 0x66:
4190 prefixes |= PREFIX_DATA;
4191 goto next_byte;
4192 case 0x67:
4193 prefixes |= PREFIX_ADR;
4194 goto next_byte;
4195 case 0x40 ... 0x4f:
4196 /* REX prefix */
4197 rex_w = (b >> 3) & 1;
4198 rex_r = (b & 0x4) << 1;
4199 s->rex_x = (b & 0x2) << 2;
4200 REX_B(s) = (b & 0x1) << 3;
4201 x86_64_hregs = 1; /* select uniform byte register addressing */
4202 goto next_byte;
4203 }
4204 if (rex_w == 1) {
4205 /* 0x66 is ignored if rex.w is set */
4206 dflag = 2;
4207 } else {
4208 if (prefixes & PREFIX_DATA)
4209 dflag ^= 1;
4210 }
4211 if (!(prefixes & PREFIX_ADR))
4212 aflag = 2;
4213 } else
4214 #endif
4215 {
4216 switch (b) {
4217 case 0xf3:
4218 prefixes |= PREFIX_REPZ;
4219 goto next_byte;
4220 case 0xf2:
4221 prefixes |= PREFIX_REPNZ;
4222 goto next_byte;
4223 case 0xf0:
4224 prefixes |= PREFIX_LOCK;
4225 goto next_byte;
4226 case 0x2e:
4227 s->override = R_CS;
4228 goto next_byte;
4229 case 0x36:
4230 s->override = R_SS;
4231 goto next_byte;
4232 case 0x3e:
4233 s->override = R_DS;
4234 goto next_byte;
4235 case 0x26:
4236 s->override = R_ES;
4237 goto next_byte;
4238 case 0x64:
4239 s->override = R_FS;
4240 goto next_byte;
4241 case 0x65:
4242 s->override = R_GS;
4243 goto next_byte;
4244 case 0x66:
4245 prefixes |= PREFIX_DATA;
4246 goto next_byte;
4247 case 0x67:
4248 prefixes |= PREFIX_ADR;
4249 goto next_byte;
4250 }
4251 if (prefixes & PREFIX_DATA)
4252 dflag ^= 1;
4253 if (prefixes & PREFIX_ADR)
4254 aflag ^= 1;
4255 }
4256
4257 s->prefix = prefixes;
4258 s->aflag = aflag;
4259 s->dflag = dflag;
4260
4261 /* lock generation */
4262 if (prefixes & PREFIX_LOCK)
4263 gen_helper_lock();
4264
4265 /* now check op code */
4266 reswitch:
4267 switch(b) {
4268 case 0x0f:
4269 /**************************/
4270 /* extended op code */
4271 b = ldub_code(s->pc++) | 0x100;
4272 goto reswitch;
4273
4274 /**************************/
4275 /* arith & logic */
4276 case 0x00 ... 0x05:
4277 case 0x08 ... 0x0d:
4278 case 0x10 ... 0x15:
4279 case 0x18 ... 0x1d:
4280 case 0x20 ... 0x25:
4281 case 0x28 ... 0x2d:
4282 case 0x30 ... 0x35:
4283 case 0x38 ... 0x3d:
4284 {
4285 int op, f, val;
4286 op = (b >> 3) & 7;
4287 f = (b >> 1) & 3;
4288
4289 if ((b & 1) == 0)
4290 ot = OT_BYTE;
4291 else
4292 ot = dflag + OT_WORD;
4293
4294 switch(f) {
4295 case 0: /* OP Ev, Gv */
4296 modrm = ldub_code(s->pc++);
4297 reg = ((modrm >> 3) & 7) | rex_r;
4298 mod = (modrm >> 6) & 3;
4299 rm = (modrm & 7) | REX_B(s);
4300 if (mod != 3) {
4301 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4302 opreg = OR_TMP0;
4303 } else if (op == OP_XORL && rm == reg) {
4304 xor_zero:
4305 /* xor reg, reg optimisation */
4306 gen_op_movl_T0_0();
4307 s->cc_op = CC_OP_LOGICB + ot;
4308 gen_op_mov_reg_T0(ot, reg);
4309 gen_op_update1_cc();
4310 break;
4311 } else {
4312 opreg = rm;
4313 }
4314 gen_op_mov_TN_reg(ot, 1, reg);
4315 gen_op(s, op, ot, opreg);
4316 break;
4317 case 1: /* OP Gv, Ev */
4318 modrm = ldub_code(s->pc++);
4319 mod = (modrm >> 6) & 3;
4320 reg = ((modrm >> 3) & 7) | rex_r;
4321 rm = (modrm & 7) | REX_B(s);
4322 if (mod != 3) {
4323 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4324 gen_op_ld_T1_A0(ot + s->mem_index);
4325 } else if (op == OP_XORL && rm == reg) {
4326 goto xor_zero;
4327 } else {
4328 gen_op_mov_TN_reg(ot, 1, rm);
4329 }
4330 gen_op(s, op, ot, reg);
4331 break;
4332 case 2: /* OP A, Iv */
4333 val = insn_get(s, ot);
4334 gen_op_movl_T1_im(val);
4335 gen_op(s, op, ot, OR_EAX);
4336 break;
4337 }
4338 }
4339 break;
4340
4341 case 0x82:
4342 if (CODE64(s))
4343 goto illegal_op;
4344 case 0x80: /* GRP1 */
4345 case 0x81:
4346 case 0x83:
4347 {
4348 int val;
4349
4350 if ((b & 1) == 0)
4351 ot = OT_BYTE;
4352 else
4353 ot = dflag + OT_WORD;
4354
4355 modrm = ldub_code(s->pc++);
4356 mod = (modrm >> 6) & 3;
4357 rm = (modrm & 7) | REX_B(s);
4358 op = (modrm >> 3) & 7;
4359
4360 if (mod != 3) {
4361 if (b == 0x83)
4362 s->rip_offset = 1;
4363 else
4364 s->rip_offset = insn_const_size(ot);
4365 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4366 opreg = OR_TMP0;
4367 } else {
4368 opreg = rm;
4369 }
4370
4371 switch(b) {
4372 default:
4373 case 0x80:
4374 case 0x81:
4375 case 0x82:
4376 val = insn_get(s, ot);
4377 break;
4378 case 0x83:
4379 val = (int8_t)insn_get(s, OT_BYTE);
4380 break;
4381 }
4382 gen_op_movl_T1_im(val);
4383 gen_op(s, op, ot, opreg);
4384 }
4385 break;
4386
4387 /**************************/
4388 /* inc, dec, and other misc arith */
4389 case 0x40 ... 0x47: /* inc Gv */
4390 ot = dflag ? OT_LONG : OT_WORD;
4391 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4392 break;
4393 case 0x48 ... 0x4f: /* dec Gv */
4394 ot = dflag ? OT_LONG : OT_WORD;
4395 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4396 break;
4397 case 0xf6: /* GRP3 */
4398 case 0xf7:
4399 if ((b & 1) == 0)
4400 ot = OT_BYTE;
4401 else
4402 ot = dflag + OT_WORD;
4403
4404 modrm = ldub_code(s->pc++);
4405 mod = (modrm >> 6) & 3;
4406 rm = (modrm & 7) | REX_B(s);
4407 op = (modrm >> 3) & 7;
4408 if (mod != 3) {
4409 if (op == 0)
4410 s->rip_offset = insn_const_size(ot);
4411 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4412 gen_op_ld_T0_A0(ot + s->mem_index);
4413 } else {
4414 gen_op_mov_TN_reg(ot, 0, rm);
4415 }
4416
4417 switch(op) {
4418 case 0: /* test */
4419 val = insn_get(s, ot);
4420 gen_op_movl_T1_im(val);
4421 gen_op_testl_T0_T1_cc();
4422 s->cc_op = CC_OP_LOGICB + ot;
4423 break;
4424 case 2: /* not */
4425 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4426 if (mod != 3) {
4427 gen_op_st_T0_A0(ot + s->mem_index);
4428 } else {
4429 gen_op_mov_reg_T0(ot, rm);
4430 }
4431 break;
4432 case 3: /* neg */
4433 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4434 if (mod != 3) {
4435 gen_op_st_T0_A0(ot + s->mem_index);
4436 } else {
4437 gen_op_mov_reg_T0(ot, rm);
4438 }
4439 gen_op_update_neg_cc();
4440 s->cc_op = CC_OP_SUBB + ot;
4441 break;
4442 case 4: /* mul */
4443 switch(ot) {
4444 case OT_BYTE:
4445 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4446 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4447 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4448 /* XXX: use 32 bit mul which could be faster */
4449 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4450 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4451 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4452 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4453 s->cc_op = CC_OP_MULB;
4454 break;
4455 case OT_WORD:
4456 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4457 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4458 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4459 /* XXX: use 32 bit mul which could be faster */
4460 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4461 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4462 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4463 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4464 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4465 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4466 s->cc_op = CC_OP_MULW;
4467 break;
4468 default:
4469 case OT_LONG:
4470 #ifdef TARGET_X86_64
4471 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4472 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4473 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4474 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4475 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4476 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4477 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4478 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4479 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4480 #else
4481 {
4482 TCGv_i64 t0, t1;
4483 t0 = tcg_temp_new_i64();
4484 t1 = tcg_temp_new_i64();
4485 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4486 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4487 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4488 tcg_gen_mul_i64(t0, t0, t1);
4489 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4490 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4491 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4492 tcg_gen_shri_i64(t0, t0, 32);
4493 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4494 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4495 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4496 }
4497 #endif
4498 s->cc_op = CC_OP_MULL;
4499 break;
4500 #ifdef TARGET_X86_64
4501 case OT_QUAD:
4502 gen_helper_mulq_EAX_T0(cpu_T[0]);
4503 s->cc_op = CC_OP_MULQ;
4504 break;
4505 #endif
4506 }
4507 break;
4508 case 5: /* imul */
4509 switch(ot) {
4510 case OT_BYTE:
4511 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4512 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4513 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4514 /* XXX: use 32 bit mul which could be faster */
4515 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4516 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4517 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4518 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4519 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4520 s->cc_op = CC_OP_MULB;
4521 break;
4522 case OT_WORD:
4523 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4524 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4525 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4526 /* XXX: use 32 bit mul which could be faster */
4527 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4528 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4529 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4530 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4531 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4532 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4533 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4534 s->cc_op = CC_OP_MULW;
4535 break;
4536 default:
4537 case OT_LONG:
4538 #ifdef TARGET_X86_64
4539 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4540 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4541 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4542 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4543 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4544 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4545 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4546 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4547 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4548 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4549 #else
4550 {
4551 TCGv_i64 t0, t1;
4552 t0 = tcg_temp_new_i64();
4553 t1 = tcg_temp_new_i64();
4554 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4555 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4556 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4557 tcg_gen_mul_i64(t0, t0, t1);
4558 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4559 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4560 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4561 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4562 tcg_gen_shri_i64(t0, t0, 32);
4563 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4564 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4565 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4566 }
4567 #endif
4568 s->cc_op = CC_OP_MULL;
4569 break;
4570 #ifdef TARGET_X86_64
4571 case OT_QUAD:
4572 gen_helper_imulq_EAX_T0(cpu_T[0]);
4573 s->cc_op = CC_OP_MULQ;
4574 break;
4575 #endif
4576 }
4577 break;
4578 case 6: /* div */
4579 switch(ot) {
4580 case OT_BYTE:
4581 gen_jmp_im(pc_start - s->cs_base);
4582 gen_helper_divb_AL(cpu_T[0]);
4583 break;
4584 case OT_WORD:
4585 gen_jmp_im(pc_start - s->cs_base);
4586 gen_helper_divw_AX(cpu_T[0]);
4587 break;
4588 default:
4589 case OT_LONG:
4590 gen_jmp_im(pc_start - s->cs_base);
4591 gen_helper_divl_EAX(cpu_T[0]);
4592 break;
4593 #ifdef TARGET_X86_64
4594 case OT_QUAD:
4595 gen_jmp_im(pc_start - s->cs_base);
4596 gen_helper_divq_EAX(cpu_T[0]);
4597 break;
4598 #endif
4599 }
4600 break;
4601 case 7: /* idiv */
4602 switch(ot) {
4603 case OT_BYTE:
4604 gen_jmp_im(pc_start - s->cs_base);
4605 gen_helper_idivb_AL(cpu_T[0]);
4606 break;
4607 case OT_WORD:
4608 gen_jmp_im(pc_start - s->cs_base);
4609 gen_helper_idivw_AX(cpu_T[0]);
4610 break;
4611 default:
4612 case OT_LONG:
4613 gen_jmp_im(pc_start - s->cs_base);
4614 gen_helper_idivl_EAX(cpu_T[0]);
4615 break;
4616 #ifdef TARGET_X86_64
4617 case OT_QUAD:
4618 gen_jmp_im(pc_start - s->cs_base);
4619 gen_helper_idivq_EAX(cpu_T[0]);
4620 break;
4621 #endif
4622 }
4623 break;
4624 default:
4625 goto illegal_op;
4626 }
4627 break;
4628
4629 case 0xfe: /* GRP4 */
4630 case 0xff: /* GRP5 */
4631 if ((b & 1) == 0)
4632 ot = OT_BYTE;
4633 else
4634 ot = dflag + OT_WORD;
4635
4636 modrm = ldub_code(s->pc++);
4637 mod = (modrm >> 6) & 3;
4638 rm = (modrm & 7) | REX_B(s);
4639 op = (modrm >> 3) & 7;
4640 if (op >= 2 && b == 0xfe) {
4641 goto illegal_op;
4642 }
4643 if (CODE64(s)) {
4644 if (op == 2 || op == 4) {
4645 /* operand size for jumps is 64 bit */
4646 ot = OT_QUAD;
4647 } else if (op == 3 || op == 5) {
4648 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4649 } else if (op == 6) {
4650 /* default push size is 64 bit */
4651 ot = dflag ? OT_QUAD : OT_WORD;
4652 }
4653 }
4654 if (mod != 3) {
4655 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4656 if (op >= 2 && op != 3 && op != 5)
4657 gen_op_ld_T0_A0(ot + s->mem_index);
4658 } else {
4659 gen_op_mov_TN_reg(ot, 0, rm);
4660 }
4661
4662 switch(op) {
4663 case 0: /* inc Ev */
4664 if (mod != 3)
4665 opreg = OR_TMP0;
4666 else
4667 opreg = rm;
4668 gen_inc(s, ot, opreg, 1);
4669 break;
4670 case 1: /* dec Ev */
4671 if (mod != 3)
4672 opreg = OR_TMP0;
4673 else
4674 opreg = rm;
4675 gen_inc(s, ot, opreg, -1);
4676 break;
4677 case 2: /* call Ev */
4678 /* XXX: optimize if memory (no 'and' is necessary) */
4679 if (s->dflag == 0)
4680 gen_op_andl_T0_ffff();
4681 next_eip = s->pc - s->cs_base;
4682 gen_movtl_T1_im(next_eip);
4683 gen_push_T1(s);
4684 gen_op_jmp_T0();
4685 gen_eob(s);
4686 break;
4687 case 3: /* lcall Ev */
4688 gen_op_ld_T1_A0(ot + s->mem_index);
4689 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4690 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4691 do_lcall:
4692 if (s->pe && !s->vm86) {
4693 if (s->cc_op != CC_OP_DYNAMIC)
4694 gen_op_set_cc_op(s->cc_op);
4695 gen_jmp_im(pc_start - s->cs_base);
4696 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4697 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4698 tcg_const_i32(dflag),
4699 tcg_const_i32(s->pc - pc_start));
4700 } else {
4701 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4702 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4703 tcg_const_i32(dflag),
4704 tcg_const_i32(s->pc - s->cs_base));
4705 }
4706 gen_eob(s);
4707 break;
4708 case 4: /* jmp Ev */
4709 if (s->dflag == 0)
4710 gen_op_andl_T0_ffff();
4711 gen_op_jmp_T0();
4712 gen_eob(s);
4713 break;
4714 case 5: /* ljmp Ev */
4715 gen_op_ld_T1_A0(ot + s->mem_index);
4716 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4717 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4718 do_ljmp:
4719 if (s->pe && !s->vm86) {
4720 if (s->cc_op != CC_OP_DYNAMIC)
4721 gen_op_set_cc_op(s->cc_op);
4722 gen_jmp_im(pc_start - s->cs_base);
4723 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4724 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4725 tcg_const_i32(s->pc - pc_start));
4726 } else {
4727 gen_op_movl_seg_T0_vm(R_CS);
4728 gen_op_movl_T0_T1();
4729 gen_op_jmp_T0();
4730 }
4731 gen_eob(s);
4732 break;
4733 case 6: /* push Ev */
4734 gen_push_T0(s);
4735 break;
4736 default:
4737 goto illegal_op;
4738 }
4739 break;
4740
4741 case 0x84: /* test Ev, Gv */
4742 case 0x85:
4743 if ((b & 1) == 0)
4744 ot = OT_BYTE;
4745 else
4746 ot = dflag + OT_WORD;
4747
4748 modrm = ldub_code(s->pc++);
4749 reg = ((modrm >> 3) & 7) | rex_r;
4750
4751 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4752 gen_op_mov_TN_reg(ot, 1, reg);
4753 gen_op_testl_T0_T1_cc();
4754 s->cc_op = CC_OP_LOGICB + ot;
4755 break;
4756
4757 case 0xa8: /* test eAX, Iv */
4758 case 0xa9:
4759 if ((b & 1) == 0)
4760 ot = OT_BYTE;
4761 else
4762 ot = dflag + OT_WORD;
4763 val = insn_get(s, ot);
4764
4765 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4766 gen_op_movl_T1_im(val);
4767 gen_op_testl_T0_T1_cc();
4768 s->cc_op = CC_OP_LOGICB + ot;
4769 break;
4770
4771 case 0x98: /* CWDE/CBW */
4772 #ifdef TARGET_X86_64
4773 if (dflag == 2) {
4774 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4775 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4776 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4777 } else
4778 #endif
4779 if (dflag == 1) {
4780 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4781 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4782 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4783 } else {
4784 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4785 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4786 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4787 }
4788 break;
4789 case 0x99: /* CDQ/CWD */
4790 #ifdef TARGET_X86_64
4791 if (dflag == 2) {
4792 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4793 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4794 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4795 } else
4796 #endif
4797 if (dflag == 1) {
4798 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4799 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4800 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4801 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4802 } else {
4803 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4804 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4805 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4806 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4807 }
4808 break;
4809 case 0x1af: /* imul Gv, Ev */
4810 case 0x69: /* imul Gv, Ev, I */
4811 case 0x6b:
4812 ot = dflag + OT_WORD;
4813 modrm = ldub_code(s->pc++);
4814 reg = ((modrm >> 3) & 7) | rex_r;
4815 if (b == 0x69)
4816 s->rip_offset = insn_const_size(ot);
4817 else if (b == 0x6b)
4818 s->rip_offset = 1;
4819 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4820 if (b == 0x69) {
4821 val = insn_get(s, ot);
4822 gen_op_movl_T1_im(val);
4823 } else if (b == 0x6b) {
4824 val = (int8_t)insn_get(s, OT_BYTE);
4825 gen_op_movl_T1_im(val);
4826 } else {
4827 gen_op_mov_TN_reg(ot, 1, reg);
4828 }
4829
4830 #ifdef TARGET_X86_64
4831 if (ot == OT_QUAD) {
4832 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4833 } else
4834 #endif
4835 if (ot == OT_LONG) {
4836 #ifdef TARGET_X86_64
4837 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4838 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4839 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4840 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4841 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4842 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4843 #else
4844 {
4845 TCGv_i64 t0, t1;
4846 t0 = tcg_temp_new_i64();
4847 t1 = tcg_temp_new_i64();
4848 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4849 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4850 tcg_gen_mul_i64(t0, t0, t1);
4851 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4852 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4853 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4854 tcg_gen_shri_i64(t0, t0, 32);
4855 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4856 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4857 }
4858 #endif
4859 } else {
4860 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4861 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4862 /* XXX: use 32 bit mul which could be faster */
4863 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4864 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4865 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4866 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4867 }
4868 gen_op_mov_reg_T0(ot, reg);
4869 s->cc_op = CC_OP_MULB + ot;
4870 break;
4871 case 0x1c0:
4872 case 0x1c1: /* xadd Ev, Gv */
4873 if ((b & 1) == 0)
4874 ot = OT_BYTE;
4875 else
4876 ot = dflag + OT_WORD;
4877 modrm = ldub_code(s->pc++);
4878 reg = ((modrm >> 3) & 7) | rex_r;
4879 mod = (modrm >> 6) & 3;
4880 if (mod == 3) {
4881 rm = (modrm & 7) | REX_B(s);
4882 gen_op_mov_TN_reg(ot, 0, reg);
4883 gen_op_mov_TN_reg(ot, 1, rm);
4884 gen_op_addl_T0_T1();
4885 gen_op_mov_reg_T1(ot, reg);
4886 gen_op_mov_reg_T0(ot, rm);
4887 } else {
4888 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4889 gen_op_mov_TN_reg(ot, 0, reg);
4890 gen_op_ld_T1_A0(ot + s->mem_index);
4891 gen_op_addl_T0_T1();
4892 gen_op_st_T0_A0(ot + s->mem_index);
4893 gen_op_mov_reg_T1(ot, reg);
4894 }
4895 gen_op_update2_cc();
4896 s->cc_op = CC_OP_ADDB + ot;
4897 break;
4898 case 0x1b0:
4899 case 0x1b1: /* cmpxchg Ev, Gv */
4900 {
4901 int label1, label2;
4902 TCGv t0, t1, t2, a0;
4903
4904 if ((b & 1) == 0)
4905 ot = OT_BYTE;
4906 else
4907 ot = dflag + OT_WORD;
4908 modrm = ldub_code(s->pc++);
4909 reg = ((modrm >> 3) & 7) | rex_r;
4910 mod = (modrm >> 6) & 3;
4911 t0 = tcg_temp_local_new();
4912 t1 = tcg_temp_local_new();
4913 t2 = tcg_temp_local_new();
4914 a0 = tcg_temp_local_new();
4915 gen_op_mov_v_reg(ot, t1, reg);
4916 if (mod == 3) {
4917 rm = (modrm & 7) | REX_B(s);
4918 gen_op_mov_v_reg(ot, t0, rm);
4919 } else {
4920 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4921 tcg_gen_mov_tl(a0, cpu_A0);
4922 gen_op_ld_v(ot + s->mem_index, t0, a0);
4923 rm = 0; /* avoid warning */
4924 }
4925 label1 = gen_new_label();
4926 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4927 gen_extu(ot, t2);
4928 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4929 label2 = gen_new_label();
4930 if (mod == 3) {
4931 gen_op_mov_reg_v(ot, R_EAX, t0);
4932 tcg_gen_br(label2);
4933 gen_set_label(label1);
4934 gen_op_mov_reg_v(ot, rm, t1);
4935 } else {
4936 /* perform no-op store cycle like physical cpu; must be
4937 before changing accumulator to ensure idempotency if
4938 the store faults and the instruction is restarted */
4939 gen_op_st_v(ot + s->mem_index, t0, a0);
4940 gen_op_mov_reg_v(ot, R_EAX, t0);
4941 tcg_gen_br(label2);
4942 gen_set_label(label1);
4943 gen_op_st_v(ot + s->mem_index, t1, a0);
4944 }
4945 gen_set_label(label2);
4946 tcg_gen_mov_tl(cpu_cc_src, t0);
4947 tcg_gen_mov_tl(cpu_cc_dst, t2);
4948 s->cc_op = CC_OP_SUBB + ot;
4949 tcg_temp_free(t0);
4950 tcg_temp_free(t1);
4951 tcg_temp_free(t2);
4952 tcg_temp_free(a0);
4953 }
4954 break;
4955 case 0x1c7: /* cmpxchg8b */
4956 modrm = ldub_code(s->pc++);
4957 mod = (modrm >> 6) & 3;
4958 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4959 goto illegal_op;
4960 #ifdef TARGET_X86_64
4961 if (dflag == 2) {
4962 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4963 goto illegal_op;
4964 gen_jmp_im(pc_start - s->cs_base);
4965 if (s->cc_op != CC_OP_DYNAMIC)
4966 gen_op_set_cc_op(s->cc_op);
4967 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4968 gen_helper_cmpxchg16b(cpu_A0);
4969 } else
4970 #endif
4971 {
4972 if (!(s->cpuid_features & CPUID_CX8))
4973 goto illegal_op;
4974 gen_jmp_im(pc_start - s->cs_base);
4975 if (s->cc_op != CC_OP_DYNAMIC)
4976 gen_op_set_cc_op(s->cc_op);
4977 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4978 gen_helper_cmpxchg8b(cpu_A0);
4979 }
4980 s->cc_op = CC_OP_EFLAGS;
4981 break;
4982
4983 /**************************/
4984 /* push/pop */
4985 case 0x50 ... 0x57: /* push */
4986 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4987 gen_push_T0(s);
4988 break;
4989 case 0x58 ... 0x5f: /* pop */
4990 if (CODE64(s)) {
4991 ot = dflag ? OT_QUAD : OT_WORD;
4992 } else {
4993 ot = dflag + OT_WORD;
4994 }
4995 gen_pop_T0(s);
4996 /* NOTE: order is important for pop %sp */
4997 gen_pop_update(s);
4998 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4999 break;
5000 case 0x60: /* pusha */
5001 if (CODE64(s))
5002 goto illegal_op;
5003 gen_pusha(s);
5004 break;
5005 case 0x61: /* popa */
5006 if (CODE64(s))
5007 goto illegal_op;
5008 gen_popa(s);
5009 break;
5010 case 0x68: /* push Iv */
5011 case 0x6a:
5012 if (CODE64(s)) {
5013 ot = dflag ? OT_QUAD : OT_WORD;
5014 } else {
5015 ot = dflag + OT_WORD;
5016 }
5017 if (b == 0x68)
5018 val = insn_get(s, ot);
5019 else
5020 val = (int8_t)insn_get(s, OT_BYTE);
5021 gen_op_movl_T0_im(val);
5022 gen_push_T0(s);
5023 break;
5024 case 0x8f: /* pop Ev */
5025 if (CODE64(s)) {
5026 ot = dflag ? OT_QUAD : OT_WORD;
5027 } else {
5028 ot = dflag + OT_WORD;
5029 }
5030 modrm = ldub_code(s->pc++);
5031 mod = (modrm >> 6) & 3;
5032 gen_pop_T0(s);
5033 if (mod == 3) {
5034 /* NOTE: order is important for pop %sp */
5035 gen_pop_update(s);
5036 rm = (modrm & 7) | REX_B(s);
5037 gen_op_mov_reg_T0(ot, rm);
5038 } else {
5039 /* NOTE: order is important too for MMU exceptions */
5040 s->popl_esp_hack = 1 << ot;
5041 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5042 s->popl_esp_hack = 0;
5043 gen_pop_update(s);
5044 }
5045 break;
5046 case 0xc8: /* enter */
5047 {
5048 int level;
5049 val = lduw_code(s->pc);
5050 s->pc += 2;
5051 level = ldub_code(s->pc++);
5052 gen_enter(s, val, level);
5053 }
5054 break;
5055 case 0xc9: /* leave */
5056 /* XXX: exception not precise (ESP is updated before potential exception) */
5057 if (CODE64(s)) {
5058 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5059 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5060 } else if (s->ss32) {
5061 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5062 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5063 } else {
5064 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5065 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5066 }
5067 gen_pop_T0(s);
5068 if (CODE64(s)) {
5069 ot = dflag ? OT_QUAD : OT_WORD;
5070 } else {
5071 ot = dflag + OT_WORD;
5072 }
5073 gen_op_mov_reg_T0(ot, R_EBP);
5074 gen_pop_update(s);
5075 break;
5076 case 0x06: /* push es */
5077 case 0x0e: /* push cs */
5078 case 0x16: /* push ss */
5079 case 0x1e: /* push ds */
5080 if (CODE64(s))
5081 goto illegal_op;
5082 gen_op_movl_T0_seg(b >> 3);
5083 gen_push_T0(s);
5084 break;
5085 case 0x1a0: /* push fs */
5086 case 0x1a8: /* push gs */
5087 gen_op_movl_T0_seg((b >> 3) & 7);
5088 gen_push_T0(s);
5089 break;
5090 case 0x07: /* pop es */
5091 case 0x17: /* pop ss */
5092 case 0x1f: /* pop ds */
5093 if (CODE64(s))
5094 goto illegal_op;
5095 reg = b >> 3;
5096 gen_pop_T0(s);
5097 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5098 gen_pop_update(s);
5099 if (reg == R_SS) {
5100 /* if reg == SS, inhibit interrupts/trace. */
5101 /* If several instructions disable interrupts, only the
5102 _first_ does it */
5103 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5104 gen_helper_set_inhibit_irq();
5105 s->tf = 0;
5106 }
5107 if (s->is_jmp) {
5108 gen_jmp_im(s->pc - s->cs_base);
5109 gen_eob(s);
5110 }
5111 break;
5112 case 0x1a1: /* pop fs */
5113 case 0x1a9: /* pop gs */
5114 gen_pop_T0(s);
5115 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5116 gen_pop_update(s);
5117 if (s->is_jmp) {
5118 gen_jmp_im(s->pc - s->cs_base);
5119 gen_eob(s);
5120 }
5121 break;
5122
5123 /**************************/
5124 /* mov */
5125 case 0x88:
5126 case 0x89: /* mov Gv, Ev */
5127 if ((b & 1) == 0)
5128 ot = OT_BYTE;
5129 else
5130 ot = dflag + OT_WORD;
5131 modrm = ldub_code(s->pc++);
5132 reg = ((modrm >> 3) & 7) | rex_r;
5133
5134 /* generate a generic store */
5135 gen_ldst_modrm(s, modrm, ot, reg, 1);
5136 break;
5137 case 0xc6:
5138 case 0xc7: /* mov Ev, Iv */
5139 if ((b & 1) == 0)
5140 ot = OT_BYTE;
5141 else
5142 ot = dflag + OT_WORD;
5143 modrm = ldub_code(s->pc++);
5144 mod = (modrm >> 6) & 3;
5145 if (mod != 3) {
5146 s->rip_offset = insn_const_size(ot);
5147 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5148 }
5149 val = insn_get(s, ot);
5150 gen_op_movl_T0_im(val);
5151 if (mod != 3)
5152 gen_op_st_T0_A0(ot + s->mem_index);
5153 else
5154 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5155 break;
5156 case 0x8a:
5157 case 0x8b: /* mov Ev, Gv */
5158 if ((b & 1) == 0)
5159 ot = OT_BYTE;
5160 else
5161 ot = OT_WORD + dflag;
5162 modrm = ldub_code(s->pc++);
5163 reg = ((modrm >> 3) & 7) | rex_r;
5164
5165 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5166 gen_op_mov_reg_T0(ot, reg);
5167 break;
5168 case 0x8e: /* mov seg, Gv */
5169 modrm = ldub_code(s->pc++);
5170 reg = (modrm >> 3) & 7;
5171 if (reg >= 6 || reg == R_CS)
5172 goto illegal_op;
5173 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5174 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5175 if (reg == R_SS) {
5176 /* if reg == SS, inhibit interrupts/trace */
5177 /* If several instructions disable interrupts, only the
5178 _first_ does it */
5179 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5180 gen_helper_set_inhibit_irq();
5181 s->tf = 0;
5182 }
5183 if (s->is_jmp) {
5184 gen_jmp_im(s->pc - s->cs_base);
5185 gen_eob(s);
5186 }
5187 break;
5188 case 0x8c: /* mov Gv, seg */
5189 modrm = ldub_code(s->pc++);
5190 reg = (modrm >> 3) & 7;
5191 mod = (modrm >> 6) & 3;
5192 if (reg >= 6)
5193 goto illegal_op;
5194 gen_op_movl_T0_seg(reg);
5195 if (mod == 3)
5196 ot = OT_WORD + dflag;
5197 else
5198 ot = OT_WORD;
5199 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5200 break;
5201
5202 case 0x1b6: /* movzbS Gv, Eb */
5203 case 0x1b7: /* movzwS Gv, Eb */
5204 case 0x1be: /* movsbS Gv, Eb */
5205 case 0x1bf: /* movswS Gv, Eb */
5206 {
5207 int d_ot;
5208 /* d_ot is the size of destination */
5209 d_ot = dflag + OT_WORD;
5210 /* ot is the size of source */
5211 ot = (b & 1) + OT_BYTE;
5212 modrm = ldub_code(s->pc++);
5213 reg = ((modrm >> 3) & 7) | rex_r;
5214 mod = (modrm >> 6) & 3;
5215 rm = (modrm & 7) | REX_B(s);
5216
5217 if (mod == 3) {
5218 gen_op_mov_TN_reg(ot, 0, rm);
5219 switch(ot | (b & 8)) {
5220 case OT_BYTE:
5221 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5222 break;
5223 case OT_BYTE | 8:
5224 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5225 break;
5226 case OT_WORD:
5227 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5228 break;
5229 default:
5230 case OT_WORD | 8:
5231 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5232 break;
5233 }
5234 gen_op_mov_reg_T0(d_ot, reg);
5235 } else {
5236 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5237 if (b & 8) {
5238 gen_op_lds_T0_A0(ot + s->mem_index);
5239 } else {
5240 gen_op_ldu_T0_A0(ot + s->mem_index);
5241 }
5242 gen_op_mov_reg_T0(d_ot, reg);
5243 }
5244 }
5245 break;
5246
5247 case 0x8d: /* lea */
5248 ot = dflag + OT_WORD;
5249 modrm = ldub_code(s->pc++);
5250 mod = (modrm >> 6) & 3;
5251 if (mod == 3)
5252 goto illegal_op;
5253 reg = ((modrm >> 3) & 7) | rex_r;
5254 /* we must ensure that no segment is added */
5255 s->override = -1;
5256 val = s->addseg;
5257 s->addseg = 0;
5258 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5259 s->addseg = val;
5260 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5261 break;
5262
5263 case 0xa0: /* mov EAX, Ov */
5264 case 0xa1:
5265 case 0xa2: /* mov Ov, EAX */
5266 case 0xa3:
5267 {
5268 target_ulong offset_addr;
5269
5270 if ((b & 1) == 0)
5271 ot = OT_BYTE;
5272 else
5273 ot = dflag + OT_WORD;
5274 #ifdef TARGET_X86_64
5275 if (s->aflag == 2) {
5276 offset_addr = ldq_code(s->pc);
5277 s->pc += 8;
5278 gen_op_movq_A0_im(offset_addr);
5279 } else
5280 #endif
5281 {
5282 if (s->aflag) {
5283 offset_addr = insn_get(s, OT_LONG);
5284 } else {
5285 offset_addr = insn_get(s, OT_WORD);
5286 }
5287 gen_op_movl_A0_im(offset_addr);
5288 }
5289 gen_add_A0_ds_seg(s);
5290 if ((b & 2) == 0) {
5291 gen_op_ld_T0_A0(ot + s->mem_index);
5292 gen_op_mov_reg_T0(ot, R_EAX);
5293 } else {
5294 gen_op_mov_TN_reg(ot, 0, R_EAX);
5295 gen_op_st_T0_A0(ot + s->mem_index);
5296 }
5297 }
5298 break;
5299 case 0xd7: /* xlat */
5300 #ifdef TARGET_X86_64
5301 if (s->aflag == 2) {
5302 gen_op_movq_A0_reg(R_EBX);
5303 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5304 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5305 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5306 } else
5307 #endif
5308 {
5309 gen_op_movl_A0_reg(R_EBX);
5310 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5311 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5312 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5313 if (s->aflag == 0)
5314 gen_op_andl_A0_ffff();
5315 else
5316 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5317 }
5318 gen_add_A0_ds_seg(s);
5319 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5320 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5321 break;
5322 case 0xb0 ... 0xb7: /* mov R, Ib */
5323 val = insn_get(s, OT_BYTE);
5324 gen_op_movl_T0_im(val);
5325 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5326 break;
5327 case 0xb8 ... 0xbf: /* mov R, Iv */
5328 #ifdef TARGET_X86_64
5329 if (dflag == 2) {
5330 uint64_t tmp;
5331 /* 64 bit case */
5332 tmp = ldq_code(s->pc);
5333 s->pc += 8;
5334 reg = (b & 7) | REX_B(s);
5335 gen_movtl_T0_im(tmp);
5336 gen_op_mov_reg_T0(OT_QUAD, reg);
5337 } else
5338 #endif
5339 {
5340 ot = dflag ? OT_LONG : OT_WORD;
5341 val = insn_get(s, ot);
5342 reg = (b & 7) | REX_B(s);
5343 gen_op_movl_T0_im(val);
5344 gen_op_mov_reg_T0(ot, reg);
5345 }
5346 break;
5347
5348 case 0x91 ... 0x97: /* xchg R, EAX */
5349 do_xchg_reg_eax:
5350 ot = dflag + OT_WORD;
5351 reg = (b & 7) | REX_B(s);
5352 rm = R_EAX;
5353 goto do_xchg_reg;
5354 case 0x86:
5355 case 0x87: /* xchg Ev, Gv */
5356 if ((b & 1) == 0)
5357 ot = OT_BYTE;
5358 else
5359 ot = dflag + OT_WORD;
5360 modrm = ldub_code(s->pc++);
5361 reg = ((modrm >> 3) & 7) | rex_r;
5362 mod = (modrm >> 6) & 3;
5363 if (mod == 3) {
5364 rm = (modrm & 7) | REX_B(s);
5365 do_xchg_reg:
5366 gen_op_mov_TN_reg(ot, 0, reg);
5367 gen_op_mov_TN_reg(ot, 1, rm);
5368 gen_op_mov_reg_T0(ot, rm);
5369 gen_op_mov_reg_T1(ot, reg);
5370 } else {
5371 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5372 gen_op_mov_TN_reg(ot, 0, reg);
5373 /* for xchg, lock is implicit */
5374 if (!(prefixes & PREFIX_LOCK))
5375 gen_helper_lock();
5376 gen_op_ld_T1_A0(ot + s->mem_index);
5377 gen_op_st_T0_A0(ot + s->mem_index);
5378 if (!(prefixes & PREFIX_LOCK))
5379 gen_helper_unlock();
5380 gen_op_mov_reg_T1(ot, reg);
5381 }
5382 break;
5383 case 0xc4: /* les Gv */
5384 if (CODE64(s))
5385 goto illegal_op;
5386 op = R_ES;
5387 goto do_lxx;
5388 case 0xc5: /* lds Gv */
5389 if (CODE64(s))
5390 goto illegal_op;
5391 op = R_DS;
5392 goto do_lxx;
5393 case 0x1b2: /* lss Gv */
5394 op = R_SS;
5395 goto do_lxx;
5396 case 0x1b4: /* lfs Gv */
5397 op = R_FS;
5398 goto do_lxx;
5399 case 0x1b5: /* lgs Gv */
5400 op = R_GS;
5401 do_lxx:
5402 ot = dflag ? OT_LONG : OT_WORD;
5403 modrm = ldub_code(s->pc++);
5404 reg = ((modrm >> 3) & 7) | rex_r;
5405 mod = (modrm >> 6) & 3;
5406 if (mod == 3)
5407 goto illegal_op;
5408 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5409 gen_op_ld_T1_A0(ot + s->mem_index);
5410 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5411 /* load the segment first to handle exceptions properly */
5412 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5413 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5414 /* then put the data */
5415 gen_op_mov_reg_T1(ot, reg);
5416 if (s->is_jmp) {
5417 gen_jmp_im(s->pc - s->cs_base);
5418 gen_eob(s);
5419 }
5420 break;
5421
5422 /************************/
5423 /* shifts */
5424 case 0xc0:
5425 case 0xc1:
5426 /* shift Ev,Ib */
5427 shift = 2;
5428 grp2:
5429 {
5430 if ((b & 1) == 0)
5431 ot = OT_BYTE;
5432 else
5433 ot = dflag + OT_WORD;
5434
5435 modrm = ldub_code(s->pc++);
5436 mod = (modrm >> 6) & 3;
5437 op = (modrm >> 3) & 7;
5438
5439 if (mod != 3) {
5440 if (shift == 2) {
5441 s->rip_offset = 1;
5442 }
5443 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5444 opreg = OR_TMP0;
5445 } else {
5446 opreg = (modrm & 7) | REX_B(s);
5447 }
5448
5449 /* simpler op */
5450 if (shift == 0) {
5451 gen_shift(s, op, ot, opreg, OR_ECX);
5452 } else {
5453 if (shift == 2) {
5454 shift = ldub_code(s->pc++);
5455 }
5456 gen_shifti(s, op, ot, opreg, shift);
5457 }
5458 }
5459 break;
5460 case 0xd0:
5461 case 0xd1:
5462 /* shift Ev,1 */
5463 shift = 1;
5464 goto grp2;
5465 case 0xd2:
5466 case 0xd3:
5467 /* shift Ev,cl */
5468 shift = 0;
5469 goto grp2;
5470
5471 case 0x1a4: /* shld imm */
5472 op = 0;
5473 shift = 1;
5474 goto do_shiftd;
5475 case 0x1a5: /* shld cl */
5476 op = 0;
5477 shift = 0;
5478 goto do_shiftd;
5479 case 0x1ac: /* shrd imm */
5480 op = 1;
5481 shift = 1;
5482 goto do_shiftd;
5483 case 0x1ad: /* shrd cl */
5484 op = 1;
5485 shift = 0;
5486 do_shiftd:
5487 ot = dflag + OT_WORD;
5488 modrm = ldub_code(s->pc++);
5489 mod = (modrm >> 6) & 3;
5490 rm = (modrm & 7) | REX_B(s);
5491 reg = ((modrm >> 3) & 7) | rex_r;
5492 if (mod != 3) {
5493 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5494 opreg = OR_TMP0;
5495 } else {
5496 opreg = rm;
5497 }
5498 gen_op_mov_TN_reg(ot, 1, reg);
5499
5500 if (shift) {
5501 val = ldub_code(s->pc++);
5502 tcg_gen_movi_tl(cpu_T3, val);
5503 } else {
5504 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5505 }
5506 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5507 break;
5508
5509 /************************/
5510 /* floats */
5511 case 0xd8 ... 0xdf:
5512 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5513 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5514 /* XXX: what to do if illegal op ? */
5515 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5516 break;
5517 }
5518 modrm = ldub_code(s->pc++);
5519 mod = (modrm >> 6) & 3;
5520 rm = modrm & 7;
5521 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5522 if (mod != 3) {
5523 /* memory op */
5524 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5525 switch(op) {
5526 case 0x00 ... 0x07: /* fxxxs */
5527 case 0x10 ... 0x17: /* fixxxl */
5528 case 0x20 ... 0x27: /* fxxxl */
5529 case 0x30 ... 0x37: /* fixxx */
5530 {
5531 int op1;
5532 op1 = op & 7;
5533
5534 switch(op >> 4) {
5535 case 0:
5536 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5537 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5538 gen_helper_flds_FT0(cpu_tmp2_i32);
5539 break;
5540 case 1:
5541 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5542 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5543 gen_helper_fildl_FT0(cpu_tmp2_i32);
5544 break;
5545 case 2:
5546 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5547 (s->mem_index >> 2) - 1);
5548 gen_helper_fldl_FT0(cpu_tmp1_i64);
5549 break;
5550 case 3:
5551 default:
5552 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5553 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5554 gen_helper_fildl_FT0(cpu_tmp2_i32);
5555 break;
5556 }
5557
5558 gen_helper_fp_arith_ST0_FT0(op1);
5559 if (op1 == 3) {
5560 /* fcomp needs pop */
5561 gen_helper_fpop();
5562 }
5563 }
5564 break;
5565 case 0x08: /* flds */
5566 case 0x0a: /* fsts */
5567 case 0x0b: /* fstps */
5568 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5569 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5570 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5571 switch(op & 7) {
5572 case 0:
5573 switch(op >> 4) {
5574 case 0:
5575 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5576 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5577 gen_helper_flds_ST0(cpu_tmp2_i32);
5578 break;
5579 case 1:
5580 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5581 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5582 gen_helper_fildl_ST0(cpu_tmp2_i32);
5583 break;
5584 case 2:
5585 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5586 (s->mem_index >> 2) - 1);
5587 gen_helper_fldl_ST0(cpu_tmp1_i64);
5588 break;
5589 case 3:
5590 default:
5591 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5592 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5593 gen_helper_fildl_ST0(cpu_tmp2_i32);
5594 break;
5595 }
5596 break;
5597 case 1:
5598 /* XXX: the corresponding CPUID bit must be tested ! */
5599 switch(op >> 4) {
5600 case 1:
5601 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5602 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5603 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5604 break;
5605 case 2:
5606 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5607 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5608 (s->mem_index >> 2) - 1);
5609 break;
5610 case 3:
5611 default:
5612 gen_helper_fistt_ST0(cpu_tmp2_i32);
5613 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5614 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5615 break;
5616 }
5617 gen_helper_fpop();
5618 break;
5619 default:
5620 switch(op >> 4) {
5621 case 0:
5622 gen_helper_fsts_ST0(cpu_tmp2_i32);
5623 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5624 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5625 break;
5626 case 1:
5627 gen_helper_fistl_ST0(cpu_tmp2_i32);
5628 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5629 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5630 break;
5631 case 2:
5632 gen_helper_fstl_ST0(cpu_tmp1_i64);
5633 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5634 (s->mem_index >> 2) - 1);
5635 break;
5636 case 3:
5637 default:
5638 gen_helper_fist_ST0(cpu_tmp2_i32);
5639 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5640 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5641 break;
5642 }
5643 if ((op & 7) == 3)
5644 gen_helper_fpop();
5645 break;
5646 }
5647 break;
5648 case 0x0c: /* fldenv mem */
5649 if (s->cc_op != CC_OP_DYNAMIC)
5650 gen_op_set_cc_op(s->cc_op);
5651 gen_jmp_im(pc_start - s->cs_base);
5652 gen_helper_fldenv(
5653 cpu_A0, tcg_const_i32(s->dflag));
5654 break;
5655 case 0x0d: /* fldcw mem */
5656 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5657 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5658 gen_helper_fldcw(cpu_tmp2_i32);
5659 break;
5660 case 0x0e: /* fnstenv mem */
5661 if (s->cc_op != CC_OP_DYNAMIC)
5662 gen_op_set_cc_op(s->cc_op);
5663 gen_jmp_im(pc_start - s->cs_base);
5664 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5665 break;
5666 case 0x0f: /* fnstcw mem */
5667 gen_helper_fnstcw(cpu_tmp2_i32);
5668 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5669 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5670 break;
5671 case 0x1d: /* fldt mem */
5672 if (s->cc_op != CC_OP_DYNAMIC)
5673 gen_op_set_cc_op(s->cc_op);
5674 gen_jmp_im(pc_start - s->cs_base);
5675 gen_helper_fldt_ST0(cpu_A0);
5676 break;
5677 case 0x1f: /* fstpt mem */
5678 if (s->cc_op != CC_OP_DYNAMIC)
5679 gen_op_set_cc_op(s->cc_op);
5680 gen_jmp_im(pc_start - s->cs_base);
5681 gen_helper_fstt_ST0(cpu_A0);
5682 gen_helper_fpop();
5683 break;
5684 case 0x2c: /* frstor mem */
5685 if (s->cc_op != CC_OP_DYNAMIC)
5686 gen_op_set_cc_op(s->cc_op);
5687 gen_jmp_im(pc_start - s->cs_base);
5688 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5689 break;
5690 case 0x2e: /* fnsave mem */
5691 if (s->cc_op != CC_OP_DYNAMIC)
5692 gen_op_set_cc_op(s->cc_op);
5693 gen_jmp_im(pc_start - s->cs_base);
5694 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5695 break;
5696 case 0x2f: /* fnstsw mem */
5697 gen_helper_fnstsw(cpu_tmp2_i32);
5698 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5699 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5700 break;
5701 case 0x3c: /* fbld */
5702 if (s->cc_op != CC_OP_DYNAMIC)
5703 gen_op_set_cc_op(s->cc_op);
5704 gen_jmp_im(pc_start - s->cs_base);
5705 gen_helper_fbld_ST0(cpu_A0);
5706 break;
5707 case 0x3e: /* fbstp */
5708 if (s->cc_op != CC_OP_DYNAMIC)
5709 gen_op_set_cc_op(s->cc_op);
5710 gen_jmp_im(pc_start - s->cs_base);
5711 gen_helper_fbst_ST0(cpu_A0);
5712 gen_helper_fpop();
5713 break;
5714 case 0x3d: /* fildll */
5715 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5716 (s->mem_index >> 2) - 1);
5717 gen_helper_fildll_ST0(cpu_tmp1_i64);
5718 break;
5719 case 0x3f: /* fistpll */
5720 gen_helper_fistll_ST0(cpu_tmp1_i64);
5721 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5722 (s->mem_index >> 2) - 1);
5723 gen_helper_fpop();
5724 break;
5725 default:
5726 goto illegal_op;
5727 }
5728 } else {
5729 /* register float ops */
5730 opreg = rm;
5731
5732 switch(op) {
5733 case 0x08: /* fld sti */
5734 gen_helper_fpush();
5735 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5736 break;
5737 case 0x09: /* fxchg sti */
5738 case 0x29: /* fxchg4 sti, undocumented op */
5739 case 0x39: /* fxchg7 sti, undocumented op */
5740 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5741 break;
5742 case 0x0a: /* grp d9/2 */
5743 switch(rm) {
5744 case 0: /* fnop */
5745 /* check exceptions (FreeBSD FPU probe) */
5746 if (s->cc_op != CC_OP_DYNAMIC)
5747 gen_op_set_cc_op(s->cc_op);
5748 gen_jmp_im(pc_start - s->cs_base);
5749 gen_helper_fwait();
5750 break;
5751 default:
5752 goto illegal_op;
5753 }
5754 break;
5755 case 0x0c: /* grp d9/4 */
5756 switch(rm) {
5757 case 0: /* fchs */
5758 gen_helper_fchs_ST0();
5759 break;
5760 case 1: /* fabs */
5761 gen_helper_fabs_ST0();
5762 break;
5763 case 4: /* ftst */
5764 gen_helper_fldz_FT0();
5765 gen_helper_fcom_ST0_FT0();
5766 break;
5767 case 5: /* fxam */
5768 gen_helper_fxam_ST0();
5769 break;
5770 default:
5771 goto illegal_op;
5772 }
5773 break;
5774 case 0x0d: /* grp d9/5 */
5775 {
5776 switch(rm) {
5777 case 0:
5778 gen_helper_fpush();
5779 gen_helper_fld1_ST0();
5780 break;
5781 case 1:
5782 gen_helper_fpush();
5783 gen_helper_fldl2t_ST0();
5784 break;
5785 case 2:
5786 gen_helper_fpush();
5787 gen_helper_fldl2e_ST0();
5788 break;
5789 case 3:
5790 gen_helper_fpush();
5791 gen_helper_fldpi_ST0();
5792 break;
5793 case 4:
5794 gen_helper_fpush();
5795 gen_helper_fldlg2_ST0();
5796 break;
5797 case 5:
5798 gen_helper_fpush();
5799 gen_helper_fldln2_ST0();
5800 break;
5801 case 6:
5802 gen_helper_fpush();
5803 gen_helper_fldz_ST0();
5804 break;
5805 default:
5806 goto illegal_op;
5807 }
5808 }
5809 break;
5810 case 0x0e: /* grp d9/6 */
5811 switch(rm) {
5812 case 0: /* f2xm1 */
5813 gen_helper_f2xm1();
5814 break;
5815 case 1: /* fyl2x */
5816 gen_helper_fyl2x();
5817 break;
5818 case 2: /* fptan */
5819 gen_helper_fptan();
5820 break;
5821 case 3: /* fpatan */
5822 gen_helper_fpatan();
5823 break;
5824 case 4: /* fxtract */
5825 gen_helper_fxtract();
5826 break;
5827 case 5: /* fprem1 */
5828 gen_helper_fprem1();
5829 break;
5830 case 6: /* fdecstp */
5831 gen_helper_fdecstp();
5832 break;
5833 default:
5834 case 7: /* fincstp */
5835 gen_helper_fincstp();
5836 break;
5837 }
5838 break;
5839 case 0x0f: /* grp d9/7 */
5840 switch(rm) {
5841 case 0: /* fprem */
5842 gen_helper_fprem();
5843 break;
5844 case 1: /* fyl2xp1 */
5845 gen_helper_fyl2xp1();
5846 break;
5847 case 2: /* fsqrt */
5848 gen_helper_fsqrt();
5849 break;
5850 case 3: /* fsincos */
5851 gen_helper_fsincos();
5852 break;
5853 case 5: /* fscale */
5854 gen_helper_fscale();
5855 break;
5856 case 4: /* frndint */
5857 gen_helper_frndint();
5858 break;
5859 case 6: /* fsin */
5860 gen_helper_fsin();
5861 break;
5862 default:
5863 case 7: /* fcos */
5864 gen_helper_fcos();
5865 break;
5866 }
5867 break;
5868 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5869 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5870 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5871 {
5872 int op1;
5873
5874 op1 = op & 7;
5875 if (op >= 0x20) {
5876 gen_helper_fp_arith_STN_ST0(op1, opreg);
5877 if (op >= 0x30)
5878 gen_helper_fpop();
5879 } else {
5880 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5881 gen_helper_fp_arith_ST0_FT0(op1);
5882 }
5883 }
5884 break;
5885 case 0x02: /* fcom */
5886 case 0x22: /* fcom2, undocumented op */
5887 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5888 gen_helper_fcom_ST0_FT0();
5889 break;
5890 case 0x03: /* fcomp */
5891 case 0x23: /* fcomp3, undocumented op */
5892 case 0x32: /* fcomp5, undocumented op */
5893 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5894 gen_helper_fcom_ST0_FT0();
5895 gen_helper_fpop();
5896 break;
5897 case 0x15: /* da/5 */
5898 switch(rm) {
5899 case 1: /* fucompp */
5900 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5901 gen_helper_fucom_ST0_FT0();
5902 gen_helper_fpop();
5903 gen_helper_fpop();
5904 break;
5905 default:
5906 goto illegal_op;
5907 }
5908 break;
5909 case 0x1c:
5910 switch(rm) {
5911 case 0: /* feni (287 only, just do nop here) */
5912 break;
5913 case 1: /* fdisi (287 only, just do nop here) */
5914 break;
5915 case 2: /* fclex */
5916 gen_helper_fclex();
5917 break;
5918 case 3: /* fninit */
5919 gen_helper_fninit();
5920 break;
5921 case 4: /* fsetpm (287 only, just do nop here) */
5922 break;
5923 default:
5924 goto illegal_op;
5925 }
5926 break;
5927 case 0x1d: /* fucomi */
5928 if (s->cc_op != CC_OP_DYNAMIC)
5929 gen_op_set_cc_op(s->cc_op);
5930 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5931 gen_helper_fucomi_ST0_FT0();
5932 s->cc_op = CC_OP_EFLAGS;
5933 break;
5934 case 0x1e: /* fcomi */
5935 if (s->cc_op != CC_OP_DYNAMIC)
5936 gen_op_set_cc_op(s->cc_op);
5937 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5938 gen_helper_fcomi_ST0_FT0();
5939 s->cc_op = CC_OP_EFLAGS;
5940 break;
5941 case 0x28: /* ffree sti */
5942 gen_helper_ffree_STN(tcg_const_i32(opreg));
5943 break;
5944 case 0x2a: /* fst sti */
5945 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5946 break;
5947 case 0x2b: /* fstp sti */
5948 case 0x0b: /* fstp1 sti, undocumented op */
5949 case 0x3a: /* fstp8 sti, undocumented op */
5950 case 0x3b: /* fstp9 sti, undocumented op */
5951 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5952 gen_helper_fpop();
5953 break;
5954 case 0x2c: /* fucom st(i) */
5955 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5956 gen_helper_fucom_ST0_FT0();
5957 break;
5958 case 0x2d: /* fucomp st(i) */
5959 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5960 gen_helper_fucom_ST0_FT0();
5961 gen_helper_fpop();
5962 break;
5963 case 0x33: /* de/3 */
5964 switch(rm) {
5965 case 1: /* fcompp */
5966 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5967 gen_helper_fcom_ST0_FT0();
5968 gen_helper_fpop();
5969 gen_helper_fpop();
5970 break;
5971 default:
5972 goto illegal_op;
5973 }
5974 break;
5975 case 0x38: /* ffreep sti, undocumented op */
5976 gen_helper_ffree_STN(tcg_const_i32(opreg));
5977 gen_helper_fpop();
5978 break;
5979 case 0x3c: /* df/4 */
5980 switch(rm) {
5981 case 0:
5982 gen_helper_fnstsw(cpu_tmp2_i32);
5983 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5984 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5985 break;
5986 default:
5987 goto illegal_op;
5988 }
5989 break;
5990 case 0x3d: /* fucomip */
5991 if (s->cc_op != CC_OP_DYNAMIC)
5992 gen_op_set_cc_op(s->cc_op);
5993 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5994 gen_helper_fucomi_ST0_FT0();
5995 gen_helper_fpop();
5996 s->cc_op = CC_OP_EFLAGS;
5997 break;
5998 case 0x3e: /* fcomip */
5999 if (s->cc_op != CC_OP_DYNAMIC)
6000 gen_op_set_cc_op(s->cc_op);
6001 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
6002 gen_helper_fcomi_ST0_FT0();
6003 gen_helper_fpop();
6004 s->cc_op = CC_OP_EFLAGS;
6005 break;
6006 case 0x10 ... 0x13: /* fcmovxx */
6007 case 0x18 ... 0x1b:
6008 {
6009 int op1, l1;
6010 static const uint8_t fcmov_cc[8] = {
6011 (JCC_B << 1),
6012 (JCC_Z << 1),
6013 (JCC_BE << 1),
6014 (JCC_P << 1),
6015 };
6016 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6017 l1 = gen_new_label();
6018 gen_jcc1(s, s->cc_op, op1, l1);
6019 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
6020 gen_set_label(l1);
6021 }
6022 break;
6023 default:
6024 goto illegal_op;
6025 }
6026 }
6027 break;
6028 /************************/
6029 /* string ops */
6030
6031 case 0xa4: /* movsS */
6032 case 0xa5:
6033 if ((b & 1) == 0)
6034 ot = OT_BYTE;
6035 else
6036 ot = dflag + OT_WORD;
6037
6038 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6039 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6040 } else {
6041 gen_movs(s, ot);
6042 }
6043 break;
6044
6045 case 0xaa: /* stosS */
6046 case 0xab:
6047 if ((b & 1) == 0)
6048 ot = OT_BYTE;
6049 else
6050 ot = dflag + OT_WORD;
6051
6052 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6053 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6054 } else {
6055 gen_stos(s, ot);
6056 }
6057 break;
6058 case 0xac: /* lodsS */
6059 case 0xad:
6060 if ((b & 1) == 0)
6061 ot = OT_BYTE;
6062 else
6063 ot = dflag + OT_WORD;
6064 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6065 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6066 } else {
6067 gen_lods(s, ot);
6068 }
6069 break;
6070 case 0xae: /* scasS */
6071 case 0xaf:
6072 if ((b & 1) == 0)
6073 ot = OT_BYTE;
6074 else
6075 ot = dflag + OT_WORD;
6076 if (prefixes & PREFIX_REPNZ) {
6077 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6078 } else if (prefixes & PREFIX_REPZ) {
6079 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6080 } else {
6081 gen_scas(s, ot);
6082 s->cc_op = CC_OP_SUBB + ot;
6083 }
6084 break;
6085
6086 case 0xa6: /* cmpsS */
6087 case 0xa7:
6088 if ((b & 1) == 0)
6089 ot = OT_BYTE;
6090 else
6091 ot = dflag + OT_WORD;
6092 if (prefixes & PREFIX_REPNZ) {
6093 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6094 } else if (prefixes & PREFIX_REPZ) {
6095 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6096 } else {
6097 gen_cmps(s, ot);
6098 s->cc_op = CC_OP_SUBB + ot;
6099 }
6100 break;
6101 case 0x6c: /* insS */
6102 case 0x6d:
6103 if ((b & 1) == 0)
6104 ot = OT_BYTE;
6105 else
6106 ot = dflag ? OT_LONG : OT_WORD;
6107 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6108 gen_op_andl_T0_ffff();
6109 gen_check_io(s, ot, pc_start - s->cs_base,
6110 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6111 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6112 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6113 } else {
6114 gen_ins(s, ot);
6115 if (use_icount) {
6116 gen_jmp(s, s->pc - s->cs_base);
6117 }
6118 }
6119 break;
6120 case 0x6e: /* outsS */
6121 case 0x6f:
6122 if ((b & 1) == 0)
6123 ot = OT_BYTE;
6124 else
6125 ot = dflag ? OT_LONG : OT_WORD;
6126 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6127 gen_op_andl_T0_ffff();
6128 gen_check_io(s, ot, pc_start - s->cs_base,
6129 svm_is_rep(prefixes) | 4);
6130 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6131 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6132 } else {
6133 gen_outs(s, ot);
6134 if (use_icount) {
6135 gen_jmp(s, s->pc - s->cs_base);
6136 }
6137 }
6138 break;
6139
6140 /************************/
6141 /* port I/O */
6142
6143 case 0xe4:
6144 case 0xe5:
6145 if ((b & 1) == 0)
6146 ot = OT_BYTE;
6147 else
6148 ot = dflag ? OT_LONG : OT_WORD;
6149 val = ldub_code(s->pc++);
6150 gen_op_movl_T0_im(val);
6151 gen_check_io(s, ot, pc_start - s->cs_base,
6152 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6153 if (use_icount)
6154 gen_io_start();
6155 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6156 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6157 gen_op_mov_reg_T1(ot, R_EAX);
6158 if (use_icount) {
6159 gen_io_end();
6160 gen_jmp(s, s->pc - s->cs_base);
6161 }
6162 break;
6163 case 0xe6:
6164 case 0xe7:
6165 if ((b & 1) == 0)
6166 ot = OT_BYTE;
6167 else
6168 ot = dflag ? OT_LONG : OT_WORD;
6169 val = ldub_code(s->pc++);
6170 gen_op_movl_T0_im(val);
6171 gen_check_io(s, ot, pc_start - s->cs_base,
6172 svm_is_rep(prefixes));
6173 gen_op_mov_TN_reg(ot, 1, R_EAX);
6174
6175 if (use_icount)
6176 gen_io_start();
6177 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6178 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6179 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6180 if (use_icount) {
6181 gen_io_end();
6182 gen_jmp(s, s->pc - s->cs_base);
6183 }
6184 break;
6185 case 0xec:
6186 case 0xed:
6187 if ((b & 1) == 0)
6188 ot = OT_BYTE;
6189 else
6190 ot = dflag ? OT_LONG : OT_WORD;
6191 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6192 gen_op_andl_T0_ffff();
6193 gen_check_io(s, ot, pc_start - s->cs_base,
6194 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6195 if (use_icount)
6196 gen_io_start();
6197 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6198 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6199 gen_op_mov_reg_T1(ot, R_EAX);
6200 if (use_icount) {
6201 gen_io_end();
6202 gen_jmp(s, s->pc - s->cs_base);
6203 }
6204 break;
6205 case 0xee:
6206 case 0xef:
6207 if ((b & 1) == 0)
6208 ot = OT_BYTE;
6209 else
6210 ot = dflag ? OT_LONG : OT_WORD;
6211 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6212 gen_op_andl_T0_ffff();
6213 gen_check_io(s, ot, pc_start - s->cs_base,
6214 svm_is_rep(prefixes));
6215 gen_op_mov_TN_reg(ot, 1, R_EAX);
6216
6217 if (use_icount)
6218 gen_io_start();
6219 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6220 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6221 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6222 if (use_icount) {
6223 gen_io_end();
6224 gen_jmp(s, s->pc - s->cs_base);
6225 }
6226 break;
6227
6228 /************************/
6229 /* control */
6230 case 0xc2: /* ret im */
6231 val = ldsw_code(s->pc);
6232 s->pc += 2;
6233 gen_pop_T0(s);
6234 if (CODE64(s) && s->dflag)
6235 s->dflag = 2;
6236 gen_stack_update(s, val + (2 << s->dflag));
6237 if (s->dflag == 0)
6238 gen_op_andl_T0_ffff();
6239 gen_op_jmp_T0();
6240 gen_eob(s);
6241 break;
6242 case 0xc3: /* ret */
6243 gen_pop_T0(s);
6244 gen_pop_update(s);
6245 if (s->dflag == 0)
6246 gen_op_andl_T0_ffff();
6247 gen_op_jmp_T0();
6248 gen_eob(s);
6249 break;
6250 case 0xca: /* lret im */
6251 val = ldsw_code(s->pc);
6252 s->pc += 2;
6253 do_lret:
6254 if (s->pe && !s->vm86) {
6255 if (s->cc_op != CC_OP_DYNAMIC)
6256 gen_op_set_cc_op(s->cc_op);
6257 gen_jmp_im(pc_start - s->cs_base);
6258 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6259 tcg_const_i32(val));
6260 } else {
6261 gen_stack_A0(s);
6262 /* pop offset */
6263 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6264 if (s->dflag == 0)
6265 gen_op_andl_T0_ffff();
6266 /* NOTE: keeping EIP updated is not a problem in case of
6267 exception */
6268 gen_op_jmp_T0();
6269 /* pop selector */
6270 gen_op_addl_A0_im(2 << s->dflag);
6271 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6272 gen_op_movl_seg_T0_vm(R_CS);
6273 /* add stack offset */
6274 gen_stack_update(s, val + (4 << s->dflag));
6275 }
6276 gen_eob(s);
6277 break;
6278 case 0xcb: /* lret */
6279 val = 0;
6280 goto do_lret;
6281 case 0xcf: /* iret */
6282 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6283 if (!s->pe) {
6284 /* real mode */
6285 gen_helper_iret_real(tcg_const_i32(s->dflag));
6286 s->cc_op = CC_OP_EFLAGS;
6287 } else if (s->vm86) {
6288 if (s->iopl != 3) {
6289 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6290 } else {
6291 gen_helper_iret_real(tcg_const_i32(s->dflag));
6292 s->cc_op = CC_OP_EFLAGS;
6293 }
6294 } else {
6295 if (s->cc_op != CC_OP_DYNAMIC)
6296 gen_op_set_cc_op(s->cc_op);
6297 gen_jmp_im(pc_start - s->cs_base);
6298 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6299 tcg_const_i32(s->pc - s->cs_base));
6300 s->cc_op = CC_OP_EFLAGS;
6301 }
6302 gen_eob(s);
6303 break;
6304 case 0xe8: /* call im */
6305 {
6306 if (dflag)
6307 tval = (int32_t)insn_get(s, OT_LONG);
6308 else
6309 tval = (int16_t)insn_get(s, OT_WORD);
6310 next_eip = s->pc - s->cs_base;
6311 tval += next_eip;
6312 if (s->dflag == 0)
6313 tval &= 0xffff;
6314 else if(!CODE64(s))
6315 tval &= 0xffffffff;
6316 gen_movtl_T0_im(next_eip);
6317 gen_push_T0(s);
6318 gen_jmp(s, tval);
6319 }
6320 break;
6321 case 0x9a: /* lcall im */
6322 {
6323 unsigned int selector, offset;
6324
6325 if (CODE64(s))
6326 goto illegal_op;
6327 ot = dflag ? OT_LONG : OT_WORD;
6328 offset = insn_get(s, ot);
6329 selector = insn_get(s, OT_WORD);
6330
6331 gen_op_movl_T0_im(selector);
6332 gen_op_movl_T1_imu(offset);
6333 }
6334 goto do_lcall;
6335 case 0xe9: /* jmp im */
6336 if (dflag)
6337 tval = (int32_t)insn_get(s, OT_LONG);
6338 else
6339 tval = (int16_t)insn_get(s, OT_WORD);
6340 tval += s->pc - s->cs_base;
6341 if (s->dflag == 0)
6342 tval &= 0xffff;
6343 else if(!CODE64(s))
6344 tval &= 0xffffffff;
6345 gen_jmp(s, tval);
6346 break;
6347 case 0xea: /* ljmp im */
6348 {
6349 unsigned int selector, offset;
6350
6351 if (CODE64(s))
6352 goto illegal_op;
6353 ot = dflag ? OT_LONG : OT_WORD;
6354 offset = insn_get(s, ot);
6355 selector = insn_get(s, OT_WORD);
6356
6357 gen_op_movl_T0_im(selector);
6358 gen_op_movl_T1_imu(offset);
6359 }
6360 goto do_ljmp;
6361 case 0xeb: /* jmp Jb */
6362 tval = (int8_t)insn_get(s, OT_BYTE);
6363 tval += s->pc - s->cs_base;
6364 if (s->dflag == 0)
6365 tval &= 0xffff;
6366 gen_jmp(s, tval);
6367 break;
6368 case 0x70 ... 0x7f: /* jcc Jb */
6369 tval = (int8_t)insn_get(s, OT_BYTE);
6370 goto do_jcc;
6371 case 0x180 ... 0x18f: /* jcc Jv */
6372 if (dflag) {
6373 tval = (int32_t)insn_get(s, OT_LONG);
6374 } else {
6375 tval = (int16_t)insn_get(s, OT_WORD);
6376 }
6377 do_jcc:
6378 next_eip = s->pc - s->cs_base;
6379 tval += next_eip;
6380 if (s->dflag == 0)
6381 tval &= 0xffff;
6382 gen_jcc(s, b, tval, next_eip);
6383 break;
6384
6385 case 0x190 ... 0x19f: /* setcc Gv */
6386 modrm = ldub_code(s->pc++);
6387 gen_setcc(s, b);
6388 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6389 break;
6390 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6391 {
6392 int l1;
6393 TCGv t0;
6394
6395 ot = dflag + OT_WORD;
6396 modrm = ldub_code(s->pc++);
6397 reg = ((modrm >> 3) & 7) | rex_r;
6398 mod = (modrm >> 6) & 3;
6399 t0 = tcg_temp_local_new();
6400 if (mod != 3) {
6401 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6402 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6403 } else {
6404 rm = (modrm & 7) | REX_B(s);
6405 gen_op_mov_v_reg(ot, t0, rm);
6406 }
6407 #ifdef TARGET_X86_64
6408 if (ot == OT_LONG) {
6409 /* XXX: specific Intel behaviour ? */
6410 l1 = gen_new_label();
6411 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6412 tcg_gen_mov_tl(cpu_regs[reg], t0);
6413 gen_set_label(l1);
6414 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6415 } else
6416 #endif
6417 {
6418 l1 = gen_new_label();
6419 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6420 gen_op_mov_reg_v(ot, reg, t0);
6421 gen_set_label(l1);
6422 }
6423 tcg_temp_free(t0);
6424 }
6425 break;
6426
6427 /************************/
6428 /* flags */
6429 case 0x9c: /* pushf */
6430 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6431 if (s->vm86 && s->iopl != 3) {
6432 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6433 } else {
6434 if (s->cc_op != CC_OP_DYNAMIC)
6435 gen_op_set_cc_op(s->cc_op);
6436 gen_helper_read_eflags(cpu_T[0]);
6437 gen_push_T0(s);
6438 }
6439 break;
6440 case 0x9d: /* popf */
6441 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6442 if (s->vm86 && s->iopl != 3) {
6443 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6444 } else {
6445 gen_pop_T0(s);
6446 if (s->cpl == 0) {
6447 if (s->dflag) {
6448 gen_helper_write_eflags(cpu_T[0],
6449 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6450 } else {
6451 gen_helper_write_eflags(cpu_T[0],
6452 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6453 }
6454 } else {
6455 if (s->cpl <= s->iopl) {
6456 if (s->dflag) {
6457 gen_helper_write_eflags(cpu_T[0],
6458 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6459 } else {
6460 gen_helper_write_eflags(cpu_T[0],
6461 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6462 }
6463 } else {
6464 if (s->dflag) {
6465 gen_helper_write_eflags(cpu_T[0],
6466 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6467 } else {
6468 gen_helper_write_eflags(cpu_T[0],
6469 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6470 }
6471 }
6472 }
6473 gen_pop_update(s);
6474 s->cc_op = CC_OP_EFLAGS;
6475 /* abort translation because TF flag may change */
6476 gen_jmp_im(s->pc - s->cs_base);
6477 gen_eob(s);
6478 }
6479 break;
6480 case 0x9e: /* sahf */
6481 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6482 goto illegal_op;
6483 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6484 if (s->cc_op != CC_OP_DYNAMIC)
6485 gen_op_set_cc_op(s->cc_op);
6486 gen_compute_eflags(cpu_cc_src);
6487 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6488 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6489 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6490 s->cc_op = CC_OP_EFLAGS;
6491 break;
6492 case 0x9f: /* lahf */
6493 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6494 goto illegal_op;
6495 if (s->cc_op != CC_OP_DYNAMIC)
6496 gen_op_set_cc_op(s->cc_op);
6497 gen_compute_eflags(cpu_T[0]);
6498 /* Note: gen_compute_eflags() only gives the condition codes */
6499 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6500 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6501 break;
6502 case 0xf5: /* cmc */
6503 if (s->cc_op != CC_OP_DYNAMIC)
6504 gen_op_set_cc_op(s->cc_op);
6505 gen_compute_eflags(cpu_cc_src);
6506 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6507 s->cc_op = CC_OP_EFLAGS;
6508 break;
6509 case 0xf8: /* clc */
6510 if (s->cc_op != CC_OP_DYNAMIC)
6511 gen_op_set_cc_op(s->cc_op);
6512 gen_compute_eflags(cpu_cc_src);
6513 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6514 s->cc_op = CC_OP_EFLAGS;
6515 break;
6516 case 0xf9: /* stc */
6517 if (s->cc_op != CC_OP_DYNAMIC)
6518 gen_op_set_cc_op(s->cc_op);
6519 gen_compute_eflags(cpu_cc_src);
6520 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6521 s->cc_op = CC_OP_EFLAGS;
6522 break;
6523 case 0xfc: /* cld */
6524 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6525 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6526 break;
6527 case 0xfd: /* std */
6528 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6529 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6530 break;
6531
6532 /************************/
6533 /* bit operations */
6534 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6535 ot = dflag + OT_WORD;
6536 modrm = ldub_code(s->pc++);
6537 op = (modrm >> 3) & 7;
6538 mod = (modrm >> 6) & 3;
6539 rm = (modrm & 7) | REX_B(s);
6540 if (mod != 3) {
6541 s->rip_offset = 1;
6542 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6543 gen_op_ld_T0_A0(ot + s->mem_index);
6544 } else {
6545 gen_op_mov_TN_reg(ot, 0, rm);
6546 }
6547 /* load shift */
6548 val = ldub_code(s->pc++);
6549 gen_op_movl_T1_im(val);
6550 if (op < 4)
6551 goto illegal_op;
6552 op -= 4;
6553 goto bt_op;
6554 case 0x1a3: /* bt Gv, Ev */
6555 op = 0;
6556 goto do_btx;
6557 case 0x1ab: /* bts */
6558 op = 1;
6559 goto do_btx;
6560 case 0x1b3: /* btr */
6561 op = 2;
6562 goto do_btx;
6563 case 0x1bb: /* btc */
6564 op = 3;
6565 do_btx:
6566 ot = dflag + OT_WORD;
6567 modrm = ldub_code(s->pc++);
6568 reg = ((modrm >> 3) & 7) | rex_r;
6569 mod = (modrm >> 6) & 3;
6570 rm = (modrm & 7) | REX_B(s);
6571 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6572 if (mod != 3) {
6573 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6574 /* specific case: we need to add a displacement */
6575 gen_exts(ot, cpu_T[1]);
6576 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6577 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6578 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6579 gen_op_ld_T0_A0(ot + s->mem_index);
6580 } else {
6581 gen_op_mov_TN_reg(ot, 0, rm);
6582 }
6583 bt_op:
6584 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6585 switch(op) {
6586 case 0:
6587 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6588 tcg_gen_movi_tl(cpu_cc_dst, 0);
6589 break;
6590 case 1:
6591 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6592 tcg_gen_movi_tl(cpu_tmp0, 1);
6593 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6594 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6595 break;
6596 case 2:
6597 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6598 tcg_gen_movi_tl(cpu_tmp0, 1);
6599 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6600 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6601 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6602 break;
6603 default:
6604 case 3:
6605 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6606 tcg_gen_movi_tl(cpu_tmp0, 1);
6607 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6608 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6609 break;
6610 }
6611 s->cc_op = CC_OP_SARB + ot;
6612 if (op != 0) {
6613 if (mod != 3)
6614 gen_op_st_T0_A0(ot + s->mem_index);
6615 else
6616 gen_op_mov_reg_T0(ot, rm);
6617 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6618 tcg_gen_movi_tl(cpu_cc_dst, 0);
6619 }
6620 break;
6621 case 0x1bc: /* bsf */
6622 case 0x1bd: /* bsr */
6623 {
6624 int label1;
6625 TCGv t0;
6626
6627 ot = dflag + OT_WORD;
6628 modrm = ldub_code(s->pc++);
6629 reg = ((modrm >> 3) & 7) | rex_r;
6630 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6631 gen_extu(ot, cpu_T[0]);
6632 t0 = tcg_temp_local_new();
6633 tcg_gen_mov_tl(t0, cpu_T[0]);
6634 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6635 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6636 switch(ot) {
6637 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6638 tcg_const_i32(16)); break;
6639 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6640 tcg_const_i32(32)); break;
6641 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6642 tcg_const_i32(64)); break;
6643 }
6644 gen_op_mov_reg_T0(ot, reg);
6645 } else {
6646 label1 = gen_new_label();
6647 tcg_gen_movi_tl(cpu_cc_dst, 0);
6648 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6649 if (b & 1) {
6650 gen_helper_bsr(cpu_T[0], t0);
6651 } else {
6652 gen_helper_bsf(cpu_T[0], t0);
6653 }
6654 gen_op_mov_reg_T0(ot, reg);
6655 tcg_gen_movi_tl(cpu_cc_dst, 1);
6656 gen_set_label(label1);
6657 tcg_gen_discard_tl(cpu_cc_src);
6658 s->cc_op = CC_OP_LOGICB + ot;
6659 }
6660 tcg_temp_free(t0);
6661 }
6662 break;
6663 /************************/
6664 /* bcd */
6665 case 0x27: /* daa */
6666 if (CODE64(s))
6667 goto illegal_op;
6668 if (s->cc_op != CC_OP_DYNAMIC)
6669 gen_op_set_cc_op(s->cc_op);
6670 gen_helper_daa();
6671 s->cc_op = CC_OP_EFLAGS;
6672 break;
6673 case 0x2f: /* das */
6674 if (CODE64(s))
6675 goto illegal_op;
6676 if (s->cc_op != CC_OP_DYNAMIC)
6677 gen_op_set_cc_op(s->cc_op);
6678 gen_helper_das();
6679 s->cc_op = CC_OP_EFLAGS;
6680 break;
6681 case 0x37: /* aaa */
6682 if (CODE64(s))
6683 goto illegal_op;
6684 if (s->cc_op != CC_OP_DYNAMIC)
6685 gen_op_set_cc_op(s->cc_op);
6686 gen_helper_aaa();
6687 s->cc_op = CC_OP_EFLAGS;
6688 break;
6689 case 0x3f: /* aas */
6690 if (CODE64(s))
6691 goto illegal_op;
6692 if (s->cc_op != CC_OP_DYNAMIC)
6693 gen_op_set_cc_op(s->cc_op);
6694 gen_helper_aas();
6695 s->cc_op = CC_OP_EFLAGS;
6696 break;
6697 case 0xd4: /* aam */
6698 if (CODE64(s))
6699 goto illegal_op;
6700 val = ldub_code(s->pc++);
6701 if (val == 0) {
6702 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6703 } else {
6704 gen_helper_aam(tcg_const_i32(val));
6705 s->cc_op = CC_OP_LOGICB;
6706 }
6707 break;
6708 case 0xd5: /* aad */
6709 if (CODE64(s))
6710 goto illegal_op;
6711 val = ldub_code(s->pc++);
6712 gen_helper_aad(tcg_const_i32(val));
6713 s->cc_op = CC_OP_LOGICB;
6714 break;
6715 /************************/
6716 /* misc */
6717 case 0x90: /* nop */
6718 /* XXX: correct lock test for all insn */
6719 if (prefixes & PREFIX_LOCK) {
6720 goto illegal_op;
6721 }
6722 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6723 if (REX_B(s)) {
6724 goto do_xchg_reg_eax;
6725 }
6726 if (prefixes & PREFIX_REPZ) {
6727 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6728 }
6729 break;
6730 case 0x9b: /* fwait */
6731 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6732 (HF_MP_MASK | HF_TS_MASK)) {
6733 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6734 } else {
6735 if (s->cc_op != CC_OP_DYNAMIC)
6736 gen_op_set_cc_op(s->cc_op);
6737 gen_jmp_im(pc_start - s->cs_base);
6738 gen_helper_fwait();
6739 }
6740 break;
6741 case 0xcc: /* int3 */
6742 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6743 break;
6744 case 0xcd: /* int N */
6745 val = ldub_code(s->pc++);
6746 if (s->vm86 && s->iopl != 3) {
6747 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6748 } else {
6749 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6750 }
6751 break;
6752 case 0xce: /* into */
6753 if (CODE64(s))
6754 goto illegal_op;
6755 if (s->cc_op != CC_OP_DYNAMIC)
6756 gen_op_set_cc_op(s->cc_op);
6757 gen_jmp_im(pc_start - s->cs_base);
6758 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6759 break;
6760 #ifdef WANT_ICEBP
6761 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6762 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6763 #if 1
6764 gen_debug(s, pc_start - s->cs_base);
6765 #else
6766 /* start debug */
6767 tb_flush(cpu_single_env);
6768 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6769 #endif
6770 break;
6771 #endif
6772 case 0xfa: /* cli */
6773 if (!s->vm86) {
6774 if (s->cpl <= s->iopl) {
6775 gen_helper_cli();
6776 } else {
6777 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6778 }
6779 } else {
6780 if (s->iopl == 3) {
6781 gen_helper_cli();
6782 } else {
6783 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6784 }
6785 }
6786 break;
6787 case 0xfb: /* sti */
6788 if (!s->vm86) {
6789 if (s->cpl <= s->iopl) {
6790 gen_sti:
6791 gen_helper_sti();
6792 /* interruptions are enabled only the first insn after sti */
6793 /* If several instructions disable interrupts, only the
6794 _first_ does it */
6795 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6796 gen_helper_set_inhibit_irq();
6797 /* give a chance to handle pending irqs */
6798 gen_jmp_im(s->pc - s->cs_base);
6799 gen_eob(s);
6800 } else {
6801 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6802 }
6803 } else {
6804 if (s->iopl == 3) {
6805 goto gen_sti;
6806 } else {
6807 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6808 }
6809 }
6810 break;
6811 case 0x62: /* bound */
6812 if (CODE64(s))
6813 goto illegal_op;
6814 ot = dflag ? OT_LONG : OT_WORD;
6815 modrm = ldub_code(s->pc++);
6816 reg = (modrm >> 3) & 7;
6817 mod = (modrm >> 6) & 3;
6818 if (mod == 3)
6819 goto illegal_op;
6820 gen_op_mov_TN_reg(ot, 0, reg);
6821 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6822 gen_jmp_im(pc_start - s->cs_base);
6823 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6824 if (ot == OT_WORD)
6825 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6826 else
6827 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6828 break;
6829 case 0x1c8 ... 0x1cf: /* bswap reg */
6830 reg = (b & 7) | REX_B(s);
6831 #ifdef TARGET_X86_64
6832 if (dflag == 2) {
6833 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6834 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6835 gen_op_mov_reg_T0(OT_QUAD, reg);
6836 } else
6837 #endif
6838 {
6839 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6840 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6841 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6842 gen_op_mov_reg_T0(OT_LONG, reg);
6843 }
6844 break;
6845 case 0xd6: /* salc */
6846 if (CODE64(s))
6847 goto illegal_op;
6848 if (s->cc_op != CC_OP_DYNAMIC)
6849 gen_op_set_cc_op(s->cc_op);
6850 gen_compute_eflags_c(cpu_T[0]);
6851 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6852 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6853 break;
6854 case 0xe0: /* loopnz */
6855 case 0xe1: /* loopz */
6856 case 0xe2: /* loop */
6857 case 0xe3: /* jecxz */
6858 {
6859 int l1, l2, l3;
6860
6861 tval = (int8_t)insn_get(s, OT_BYTE);
6862 next_eip = s->pc - s->cs_base;
6863 tval += next_eip;
6864 if (s->dflag == 0)
6865 tval &= 0xffff;
6866
6867 l1 = gen_new_label();
6868 l2 = gen_new_label();
6869 l3 = gen_new_label();
6870 b &= 3;
6871 switch(b) {
6872 case 0: /* loopnz */
6873 case 1: /* loopz */
6874 if (s->cc_op != CC_OP_DYNAMIC)
6875 gen_op_set_cc_op(s->cc_op);
6876 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6877 gen_op_jz_ecx(s->aflag, l3);
6878 gen_compute_eflags(cpu_tmp0);
6879 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6880 if (b == 0) {
6881 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6882 } else {
6883 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6884 }
6885 break;
6886 case 2: /* loop */
6887 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6888 gen_op_jnz_ecx(s->aflag, l1);
6889 break;
6890 default:
6891 case 3: /* jcxz */
6892 gen_op_jz_ecx(s->aflag, l1);
6893 break;
6894 }
6895
6896 gen_set_label(l3);
6897 gen_jmp_im(next_eip);
6898 tcg_gen_br(l2);
6899
6900 gen_set_label(l1);
6901 gen_jmp_im(tval);
6902 gen_set_label(l2);
6903 gen_eob(s);
6904 }
6905 break;
6906 case 0x130: /* wrmsr */
6907 case 0x132: /* rdmsr */
6908 if (s->cpl != 0) {
6909 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6910 } else {
6911 if (s->cc_op != CC_OP_DYNAMIC)
6912 gen_op_set_cc_op(s->cc_op);
6913 gen_jmp_im(pc_start - s->cs_base);
6914 if (b & 2) {
6915 gen_helper_rdmsr();
6916 } else {
6917 gen_helper_wrmsr();
6918 }
6919 }
6920 break;
6921 case 0x131: /* rdtsc */
6922 if (s->cc_op != CC_OP_DYNAMIC)
6923 gen_op_set_cc_op(s->cc_op);
6924 gen_jmp_im(pc_start - s->cs_base);
6925 if (use_icount)
6926 gen_io_start();
6927 gen_helper_rdtsc();
6928 if (use_icount) {
6929 gen_io_end();
6930 gen_jmp(s, s->pc - s->cs_base);
6931 }
6932 break;
6933 case 0x133: /* rdpmc */
6934 if (s->cc_op != CC_OP_DYNAMIC)
6935 gen_op_set_cc_op(s->cc_op);
6936 gen_jmp_im(pc_start - s->cs_base);
6937 gen_helper_rdpmc();
6938 break;
6939 case 0x134: /* sysenter */
6940 /* For Intel SYSENTER is valid on 64-bit */
6941 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6942 goto illegal_op;
6943 if (!s->pe) {
6944 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6945 } else {
6946 gen_update_cc_op(s);
6947 gen_jmp_im(pc_start - s->cs_base);
6948 gen_helper_sysenter();
6949 gen_eob(s);
6950 }
6951 break;
6952 case 0x135: /* sysexit */
6953 /* For Intel SYSEXIT is valid on 64-bit */
6954 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6955 goto illegal_op;
6956 if (!s->pe) {
6957 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6958 } else {
6959 gen_update_cc_op(s);
6960 gen_jmp_im(pc_start - s->cs_base);
6961 gen_helper_sysexit(tcg_const_i32(dflag));
6962 gen_eob(s);
6963 }
6964 break;
6965 #ifdef TARGET_X86_64
6966 case 0x105: /* syscall */
6967 /* XXX: is it usable in real mode ? */
6968 gen_update_cc_op(s);
6969 gen_jmp_im(pc_start - s->cs_base);
6970 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6971 gen_eob(s);
6972 break;
6973 case 0x107: /* sysret */
6974 if (!s->pe) {
6975 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6976 } else {
6977 gen_update_cc_op(s);
6978 gen_jmp_im(pc_start - s->cs_base);
6979 gen_helper_sysret(tcg_const_i32(s->dflag));
6980 /* condition codes are modified only in long mode */
6981 if (s->lma)
6982 s->cc_op = CC_OP_EFLAGS;
6983 gen_eob(s);
6984 }
6985 break;
6986 #endif
6987 case 0x1a2: /* cpuid */
6988 if (s->cc_op != CC_OP_DYNAMIC)
6989 gen_op_set_cc_op(s->cc_op);
6990 gen_jmp_im(pc_start - s->cs_base);
6991 gen_helper_cpuid();
6992 break;
6993 case 0xf4: /* hlt */
6994 if (s->cpl != 0) {
6995 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6996 } else {
6997 if (s->cc_op != CC_OP_DYNAMIC)
6998 gen_op_set_cc_op(s->cc_op);
6999 gen_jmp_im(pc_start - s->cs_base);
7000 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
7001 s->is_jmp = DISAS_TB_JUMP;
7002 }
7003 break;
7004 case 0x100:
7005 modrm = ldub_code(s->pc++);
7006 mod = (modrm >> 6) & 3;
7007 op = (modrm >> 3) & 7;
7008 switch(op) {
7009 case 0: /* sldt */
7010 if (!s->pe || s->vm86)
7011 goto illegal_op;
7012 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7013 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7014 ot = OT_WORD;
7015 if (mod == 3)
7016 ot += s->dflag;
7017 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7018 break;
7019 case 2: /* lldt */
7020 if (!s->pe || s->vm86)
7021 goto illegal_op;
7022 if (s->cpl != 0) {
7023 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7024 } else {
7025 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7026 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7027 gen_jmp_im(pc_start - s->cs_base);
7028 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7029 gen_helper_lldt(cpu_tmp2_i32);
7030 }
7031 break;
7032 case 1: /* str */
7033 if (!s->pe || s->vm86)
7034 goto illegal_op;
7035 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7036 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7037 ot = OT_WORD;
7038 if (mod == 3)
7039 ot += s->dflag;
7040 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7041 break;
7042 case 3: /* ltr */
7043 if (!s->pe || s->vm86)
7044 goto illegal_op;
7045 if (s->cpl != 0) {
7046 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7047 } else {
7048 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7049 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7050 gen_jmp_im(pc_start - s->cs_base);
7051 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7052 gen_helper_ltr(cpu_tmp2_i32);
7053 }
7054 break;
7055 case 4: /* verr */
7056 case 5: /* verw */
7057 if (!s->pe || s->vm86)
7058 goto illegal_op;
7059 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7060 if (s->cc_op != CC_OP_DYNAMIC)
7061 gen_op_set_cc_op(s->cc_op);
7062 if (op == 4)
7063 gen_helper_verr(cpu_T[0]);
7064 else
7065 gen_helper_verw(cpu_T[0]);
7066 s->cc_op = CC_OP_EFLAGS;
7067 break;
7068 default:
7069 goto illegal_op;
7070 }
7071 break;
7072 case 0x101:
7073 modrm = ldub_code(s->pc++);
7074 mod = (modrm >> 6) & 3;
7075 op = (modrm >> 3) & 7;
7076 rm = modrm & 7;
7077 switch(op) {
7078 case 0: /* sgdt */
7079 if (mod == 3)
7080 goto illegal_op;
7081 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7082 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7083 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7084 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7085 gen_add_A0_im(s, 2);
7086 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7087 if (!s->dflag)
7088 gen_op_andl_T0_im(0xffffff);
7089 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7090 break;
7091 case 1:
7092 if (mod == 3) {
7093 switch (rm) {
7094 case 0: /* monitor */
7095 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7096 s->cpl != 0)
7097 goto illegal_op;
7098 if (s->cc_op != CC_OP_DYNAMIC)
7099 gen_op_set_cc_op(s->cc_op);
7100 gen_jmp_im(pc_start - s->cs_base);
7101 #ifdef TARGET_X86_64
7102 if (s->aflag == 2) {
7103 gen_op_movq_A0_reg(R_EAX);
7104 } else
7105 #endif
7106 {
7107 gen_op_movl_A0_reg(R_EAX);
7108 if (s->aflag == 0)
7109 gen_op_andl_A0_ffff();
7110 }
7111 gen_add_A0_ds_seg(s);
7112 gen_helper_monitor(cpu_A0);
7113 break;
7114 case 1: /* mwait */
7115 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7116 s->cpl != 0)
7117 goto illegal_op;
7118 gen_update_cc_op(s);
7119 gen_jmp_im(pc_start - s->cs_base);
7120 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7121 gen_eob(s);
7122 break;
7123 default:
7124 goto illegal_op;
7125 }
7126 } else { /* sidt */
7127 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7128 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7129 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7130 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7131 gen_add_A0_im(s, 2);
7132 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7133 if (!s->dflag)
7134 gen_op_andl_T0_im(0xffffff);
7135 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7136 }
7137 break;
7138 case 2: /* lgdt */
7139 case 3: /* lidt */
7140 if (mod == 3) {
7141 if (s->cc_op != CC_OP_DYNAMIC)
7142 gen_op_set_cc_op(s->cc_op);
7143 gen_jmp_im(pc_start - s->cs_base);
7144 switch(rm) {
7145 case 0: /* VMRUN */
7146 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7147 goto illegal_op;
7148 if (s->cpl != 0) {
7149 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7150 break;
7151 } else {
7152 gen_helper_vmrun(tcg_const_i32(s->aflag),
7153 tcg_const_i32(s->pc - pc_start));
7154 tcg_gen_exit_tb(0);
7155 s->is_jmp = DISAS_TB_JUMP;
7156 }
7157 break;
7158 case 1: /* VMMCALL */
7159 if (!(s->flags & HF_SVME_MASK))
7160 goto illegal_op;
7161 gen_helper_vmmcall();
7162 break;
7163 case 2: /* VMLOAD */
7164 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7165 goto illegal_op;
7166 if (s->cpl != 0) {
7167 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7168 break;
7169 } else {
7170 gen_helper_vmload(tcg_const_i32(s->aflag));
7171 }
7172 break;
7173 case 3: /* VMSAVE */
7174 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7175 goto illegal_op;
7176 if (s->cpl != 0) {
7177 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7178 break;
7179 } else {
7180 gen_helper_vmsave(tcg_const_i32(s->aflag));
7181 }
7182 break;
7183 case 4: /* STGI */
7184 if ((!(s->flags & HF_SVME_MASK) &&
7185 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7186 !s->pe)
7187 goto illegal_op;
7188 if (s->cpl != 0) {
7189 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7190 break;
7191 } else {
7192 gen_helper_stgi();
7193 }
7194 break;
7195 case 5: /* CLGI */
7196 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7197 goto illegal_op;
7198 if (s->cpl != 0) {
7199 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7200 break;
7201 } else {
7202 gen_helper_clgi();
7203 }
7204 break;
7205 case 6: /* SKINIT */
7206 if ((!(s->flags & HF_SVME_MASK) &&
7207 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7208 !s->pe)
7209 goto illegal_op;
7210 gen_helper_skinit();
7211 break;
7212 case 7: /* INVLPGA */
7213 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7214 goto illegal_op;
7215 if (s->cpl != 0) {
7216 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7217 break;
7218 } else {
7219 gen_helper_invlpga(tcg_const_i32(s->aflag));
7220 }
7221 break;
7222 default:
7223 goto illegal_op;
7224 }
7225 } else if (s->cpl != 0) {
7226 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7227 } else {
7228 gen_svm_check_intercept(s, pc_start,
7229 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7230 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7231 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7232 gen_add_A0_im(s, 2);
7233 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7234 if (!s->dflag)
7235 gen_op_andl_T0_im(0xffffff);
7236 if (op == 2) {
7237 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7238 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7239 } else {
7240 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7241 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7242 }
7243 }
7244 break;
7245 case 4: /* smsw */
7246 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7247 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7248 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7249 #else
7250 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7251 #endif
7252 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7253 break;
7254 case 6: /* lmsw */
7255 if (s->cpl != 0) {
7256 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7257 } else {
7258 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7259 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7260 gen_helper_lmsw(cpu_T[0]);
7261 gen_jmp_im(s->pc - s->cs_base);
7262 gen_eob(s);
7263 }
7264 break;
7265 case 7:
7266 if (mod != 3) { /* invlpg */
7267 if (s->cpl != 0) {
7268 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7269 } else {
7270 if (s->cc_op != CC_OP_DYNAMIC)
7271 gen_op_set_cc_op(s->cc_op);
7272 gen_jmp_im(pc_start - s->cs_base);
7273 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7274 gen_helper_invlpg(cpu_A0);
7275 gen_jmp_im(s->pc - s->cs_base);
7276 gen_eob(s);
7277 }
7278 } else {
7279 switch (rm) {
7280 case 0: /* swapgs */
7281 #ifdef TARGET_X86_64
7282 if (CODE64(s)) {
7283 if (s->cpl != 0) {
7284 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7285 } else {
7286 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7287 offsetof(CPUX86State,segs[R_GS].base));
7288 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7289 offsetof(CPUX86State,kernelgsbase));
7290 tcg_gen_st_tl(cpu_T[1], cpu_env,
7291 offsetof(CPUX86State,segs[R_GS].base));
7292 tcg_gen_st_tl(cpu_T[0], cpu_env,
7293 offsetof(CPUX86State,kernelgsbase));
7294 }
7295 } else
7296 #endif
7297 {
7298 goto illegal_op;
7299 }
7300 break;
7301 case 1: /* rdtscp */
7302 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7303 goto illegal_op;
7304 if (s->cc_op != CC_OP_DYNAMIC)
7305 gen_op_set_cc_op(s->cc_op);
7306 gen_jmp_im(pc_start - s->cs_base);
7307 if (use_icount)
7308 gen_io_start();
7309 gen_helper_rdtscp();
7310 if (use_icount) {
7311 gen_io_end();
7312 gen_jmp(s, s->pc - s->cs_base);
7313 }
7314 break;
7315 default:
7316 goto illegal_op;
7317 }
7318 }
7319 break;
7320 default:
7321 goto illegal_op;
7322 }
7323 break;
7324 case 0x108: /* invd */
7325 case 0x109: /* wbinvd */
7326 if (s->cpl != 0) {
7327 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7328 } else {
7329 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7330 /* nothing to do */
7331 }
7332 break;
7333 case 0x63: /* arpl or movslS (x86_64) */
7334 #ifdef TARGET_X86_64
7335 if (CODE64(s)) {
7336 int d_ot;
7337 /* d_ot is the size of destination */
7338 d_ot = dflag + OT_WORD;
7339
7340 modrm = ldub_code(s->pc++);
7341 reg = ((modrm >> 3) & 7) | rex_r;
7342 mod = (modrm >> 6) & 3;
7343 rm = (modrm & 7) | REX_B(s);
7344
7345 if (mod == 3) {
7346 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7347 /* sign extend */
7348 if (d_ot == OT_QUAD)
7349 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7350 gen_op_mov_reg_T0(d_ot, reg);
7351 } else {
7352 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7353 if (d_ot == OT_QUAD) {
7354 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7355 } else {
7356 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7357 }
7358 gen_op_mov_reg_T0(d_ot, reg);
7359 }
7360 } else
7361 #endif
7362 {
7363 int label1;
7364 TCGv t0, t1, t2, a0;
7365
7366 if (!s->pe || s->vm86)
7367 goto illegal_op;
7368 t0 = tcg_temp_local_new();
7369 t1 = tcg_temp_local_new();
7370 t2 = tcg_temp_local_new();
7371 ot = OT_WORD;
7372 modrm = ldub_code(s->pc++);
7373 reg = (modrm >> 3) & 7;
7374 mod = (modrm >> 6) & 3;
7375 rm = modrm & 7;
7376 if (mod != 3) {
7377 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7378 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7379 a0 = tcg_temp_local_new();
7380 tcg_gen_mov_tl(a0, cpu_A0);
7381 } else {
7382 gen_op_mov_v_reg(ot, t0, rm);
7383 TCGV_UNUSED(a0);
7384 }
7385 gen_op_mov_v_reg(ot, t1, reg);
7386 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7387 tcg_gen_andi_tl(t1, t1, 3);
7388 tcg_gen_movi_tl(t2, 0);
7389 label1 = gen_new_label();
7390 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7391 tcg_gen_andi_tl(t0, t0, ~3);
7392 tcg_gen_or_tl(t0, t0, t1);
7393 tcg_gen_movi_tl(t2, CC_Z);
7394 gen_set_label(label1);
7395 if (mod != 3) {
7396 gen_op_st_v(ot + s->mem_index, t0, a0);
7397 tcg_temp_free(a0);
7398 } else {
7399 gen_op_mov_reg_v(ot, rm, t0);
7400 }
7401 if (s->cc_op != CC_OP_DYNAMIC)
7402 gen_op_set_cc_op(s->cc_op);
7403 gen_compute_eflags(cpu_cc_src);
7404 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7405 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7406 s->cc_op = CC_OP_EFLAGS;
7407 tcg_temp_free(t0);
7408 tcg_temp_free(t1);
7409 tcg_temp_free(t2);
7410 }
7411 break;
7412 case 0x102: /* lar */
7413 case 0x103: /* lsl */
7414 {
7415 int label1;
7416 TCGv t0;
7417 if (!s->pe || s->vm86)
7418 goto illegal_op;
7419 ot = dflag ? OT_LONG : OT_WORD;
7420 modrm = ldub_code(s->pc++);
7421 reg = ((modrm >> 3) & 7) | rex_r;
7422 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7423 t0 = tcg_temp_local_new();
7424 if (s->cc_op != CC_OP_DYNAMIC)
7425 gen_op_set_cc_op(s->cc_op);
7426 if (b == 0x102)
7427 gen_helper_lar(t0, cpu_T[0]);
7428 else
7429 gen_helper_lsl(t0, cpu_T[0]);
7430 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7431 label1 = gen_new_label();
7432 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7433 gen_op_mov_reg_v(ot, reg, t0);
7434 gen_set_label(label1);
7435 s->cc_op = CC_OP_EFLAGS;
7436 tcg_temp_free(t0);
7437 }
7438 break;
7439 case 0x118:
7440 modrm = ldub_code(s->pc++);
7441 mod = (modrm >> 6) & 3;
7442 op = (modrm >> 3) & 7;
7443 switch(op) {
7444 case 0: /* prefetchnta */
7445 case 1: /* prefetchnt0 */
7446 case 2: /* prefetchnt0 */
7447 case 3: /* prefetchnt0 */
7448 if (mod == 3)
7449 goto illegal_op;
7450 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7451 /* nothing more to do */
7452 break;
7453 default: /* nop (multi byte) */
7454 gen_nop_modrm(s, modrm);
7455 break;
7456 }
7457 break;
7458 case 0x119 ... 0x11f: /* nop (multi byte) */
7459 modrm = ldub_code(s->pc++);
7460 gen_nop_modrm(s, modrm);
7461 break;
7462 case 0x120: /* mov reg, crN */
7463 case 0x122: /* mov crN, reg */
7464 if (s->cpl != 0) {
7465 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7466 } else {
7467 modrm = ldub_code(s->pc++);
7468 if ((modrm & 0xc0) != 0xc0)
7469 goto illegal_op;
7470 rm = (modrm & 7) | REX_B(s);
7471 reg = ((modrm >> 3) & 7) | rex_r;
7472 if (CODE64(s))
7473 ot = OT_QUAD;
7474 else
7475 ot = OT_LONG;
7476 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7477 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7478 reg = 8;
7479 }
7480 switch(reg) {
7481 case 0:
7482 case 2:
7483 case 3:
7484 case 4:
7485 case 8:
7486 if (s->cc_op != CC_OP_DYNAMIC)
7487 gen_op_set_cc_op(s->cc_op);
7488 gen_jmp_im(pc_start - s->cs_base);
7489 if (b & 2) {
7490 gen_op_mov_TN_reg(ot, 0, rm);
7491 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7492 gen_jmp_im(s->pc - s->cs_base);
7493 gen_eob(s);
7494 } else {
7495 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7496 gen_op_mov_reg_T0(ot, rm);
7497 }
7498 break;
7499 default:
7500 goto illegal_op;
7501 }
7502 }
7503 break;
7504 case 0x121: /* mov reg, drN */
7505 case 0x123: /* mov drN, reg */
7506 if (s->cpl != 0) {
7507 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7508 } else {
7509 modrm = ldub_code(s->pc++);
7510 if ((modrm & 0xc0) != 0xc0)
7511 goto illegal_op;
7512 rm = (modrm & 7) | REX_B(s);
7513 reg = ((modrm >> 3) & 7) | rex_r;
7514 if (CODE64(s))
7515 ot = OT_QUAD;
7516 else
7517 ot = OT_LONG;
7518 /* XXX: do it dynamically with CR4.DE bit */
7519 if (reg == 4 || reg == 5 || reg >= 8)
7520 goto illegal_op;
7521 if (b & 2) {
7522 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7523 gen_op_mov_TN_reg(ot, 0, rm);
7524 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7525 gen_jmp_im(s->pc - s->cs_base);
7526 gen_eob(s);
7527 } else {
7528 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7529 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7530 gen_op_mov_reg_T0(ot, rm);
7531 }
7532 }
7533 break;
7534 case 0x106: /* clts */
7535 if (s->cpl != 0) {
7536 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7537 } else {
7538 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7539 gen_helper_clts();
7540 /* abort block because static cpu state changed */
7541 gen_jmp_im(s->pc - s->cs_base);
7542 gen_eob(s);
7543 }
7544 break;
7545 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7546 case 0x1c3: /* MOVNTI reg, mem */
7547 if (!(s->cpuid_features & CPUID_SSE2))
7548 goto illegal_op;
7549 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7550 modrm = ldub_code(s->pc++);
7551 mod = (modrm >> 6) & 3;
7552 if (mod == 3)
7553 goto illegal_op;
7554 reg = ((modrm >> 3) & 7) | rex_r;
7555 /* generate a generic store */
7556 gen_ldst_modrm(s, modrm, ot, reg, 1);
7557 break;
7558 case 0x1ae:
7559 modrm = ldub_code(s->pc++);
7560 mod = (modrm >> 6) & 3;
7561 op = (modrm >> 3) & 7;
7562 switch(op) {
7563 case 0: /* fxsave */
7564 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7565 (s->prefix & PREFIX_LOCK))
7566 goto illegal_op;
7567 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7568 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7569 break;
7570 }
7571 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7572 if (s->cc_op != CC_OP_DYNAMIC)
7573 gen_op_set_cc_op(s->cc_op);
7574 gen_jmp_im(pc_start - s->cs_base);
7575 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7576 break;
7577 case 1: /* fxrstor */
7578 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7579 (s->prefix & PREFIX_LOCK))
7580 goto illegal_op;
7581 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7582 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7583 break;
7584 }
7585 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7586 if (s->cc_op != CC_OP_DYNAMIC)
7587 gen_op_set_cc_op(s->cc_op);
7588 gen_jmp_im(pc_start - s->cs_base);
7589 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7590 break;
7591 case 2: /* ldmxcsr */
7592 case 3: /* stmxcsr */
7593 if (s->flags & HF_TS_MASK) {
7594 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7595 break;
7596 }
7597 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7598 mod == 3)
7599 goto illegal_op;
7600 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7601 if (op == 2) {
7602 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7603 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7604 gen_helper_ldmxcsr(cpu_tmp2_i32);
7605 } else {
7606 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7607 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7608 }
7609 break;
7610 case 5: /* lfence */
7611 case 6: /* mfence */
7612 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7613 goto illegal_op;
7614 break;
7615 case 7: /* sfence / clflush */
7616 if ((modrm & 0xc7) == 0xc0) {
7617 /* sfence */
7618 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7619 if (!(s->cpuid_features & CPUID_SSE))
7620 goto illegal_op;
7621 } else {
7622 /* clflush */
7623 if (!(s->cpuid_features & CPUID_CLFLUSH))
7624 goto illegal_op;
7625 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7626 }
7627 break;
7628 default:
7629 goto illegal_op;
7630 }
7631 break;
7632 case 0x10d: /* 3DNow! prefetch(w) */
7633 modrm = ldub_code(s->pc++);
7634 mod = (modrm >> 6) & 3;
7635 if (mod == 3)
7636 goto illegal_op;
7637 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7638 /* ignore for now */
7639 break;
7640 case 0x1aa: /* rsm */
7641 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7642 if (!(s->flags & HF_SMM_MASK))
7643 goto illegal_op;
7644 gen_update_cc_op(s);
7645 gen_jmp_im(s->pc - s->cs_base);
7646 gen_helper_rsm();
7647 gen_eob(s);
7648 break;
7649 case 0x1b8: /* SSE4.2 popcnt */
7650 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7651 PREFIX_REPZ)
7652 goto illegal_op;
7653 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7654 goto illegal_op;
7655
7656 modrm = ldub_code(s->pc++);
7657 reg = ((modrm >> 3) & 7);
7658
7659 if (s->prefix & PREFIX_DATA)
7660 ot = OT_WORD;
7661 else if (s->dflag != 2)
7662 ot = OT_LONG;
7663 else
7664 ot = OT_QUAD;
7665
7666 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7667 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7668 gen_op_mov_reg_T0(ot, reg);
7669
7670 s->cc_op = CC_OP_EFLAGS;
7671 break;
7672 case 0x10e ... 0x10f:
7673 /* 3DNow! instructions, ignore prefixes */
7674 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7675 case 0x110 ... 0x117:
7676 case 0x128 ... 0x12f:
7677 case 0x138 ... 0x13a:
7678 case 0x150 ... 0x179:
7679 case 0x17c ... 0x17f:
7680 case 0x1c2:
7681 case 0x1c4 ... 0x1c6:
7682 case 0x1d0 ... 0x1fe:
7683 gen_sse(s, b, pc_start, rex_r);
7684 break;
7685 default:
7686 goto illegal_op;
7687 }
7688 /* lock generation */
7689 if (s->prefix & PREFIX_LOCK)
7690 gen_helper_unlock();
7691 return s->pc;
7692 illegal_op:
7693 if (s->prefix & PREFIX_LOCK)
7694 gen_helper_unlock();
7695 /* XXX: ensure that no lock was generated */
7696 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7697 return s->pc;
7698 }
7699
7700 void optimize_flags_init(void)
7701 {
7702 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7703 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7704 offsetof(CPUX86State, cc_op), "cc_op");
7705 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7706 "cc_src");
7707 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7708 "cc_dst");
7709 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_tmp),
7710 "cc_tmp");
7711
7712 #ifdef TARGET_X86_64
7713 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7714 offsetof(CPUX86State, regs[R_EAX]), "rax");
7715 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7716 offsetof(CPUX86State, regs[R_ECX]), "rcx");
7717 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7718 offsetof(CPUX86State, regs[R_EDX]), "rdx");
7719 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7720 offsetof(CPUX86State, regs[R_EBX]), "rbx");
7721 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7722 offsetof(CPUX86State, regs[R_ESP]), "rsp");
7723 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7724 offsetof(CPUX86State, regs[R_EBP]), "rbp");
7725 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7726 offsetof(CPUX86State, regs[R_ESI]), "rsi");
7727 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7728 offsetof(CPUX86State, regs[R_EDI]), "rdi");
7729 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7730 offsetof(CPUX86State, regs[8]), "r8");
7731 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7732 offsetof(CPUX86State, regs[9]), "r9");
7733 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7734 offsetof(CPUX86State, regs[10]), "r10");
7735 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7736 offsetof(CPUX86State, regs[11]), "r11");
7737 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7738 offsetof(CPUX86State, regs[12]), "r12");
7739 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7740 offsetof(CPUX86State, regs[13]), "r13");
7741 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7742 offsetof(CPUX86State, regs[14]), "r14");
7743 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7744 offsetof(CPUX86State, regs[15]), "r15");
7745 #else
7746 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7747 offsetof(CPUX86State, regs[R_EAX]), "eax");
7748 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7749 offsetof(CPUX86State, regs[R_ECX]), "ecx");
7750 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7751 offsetof(CPUX86State, regs[R_EDX]), "edx");
7752 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7753 offsetof(CPUX86State, regs[R_EBX]), "ebx");
7754 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7755 offsetof(CPUX86State, regs[R_ESP]), "esp");
7756 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7757 offsetof(CPUX86State, regs[R_EBP]), "ebp");
7758 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7759 offsetof(CPUX86State, regs[R_ESI]), "esi");
7760 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7761 offsetof(CPUX86State, regs[R_EDI]), "edi");
7762 #endif
7763
7764 /* register helpers */
7765 #define GEN_HELPER 2
7766 #include "helper.h"
7767 }
7768
7769 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7770 basic block 'tb'. If search_pc is TRUE, also generate PC
7771 information for each intermediate instruction. */
7772 static inline void gen_intermediate_code_internal(CPUX86State *env,
7773 TranslationBlock *tb,
7774 int search_pc)
7775 {
7776 DisasContext dc1, *dc = &dc1;
7777 target_ulong pc_ptr;
7778 uint16_t *gen_opc_end;
7779 CPUBreakpoint *bp;
7780 int j, lj;
7781 uint64_t flags;
7782 target_ulong pc_start;
7783 target_ulong cs_base;
7784 int num_insns;
7785 int max_insns;
7786
7787 /* generate intermediate code */
7788 pc_start = tb->pc;
7789 cs_base = tb->cs_base;
7790 flags = tb->flags;
7791
7792 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7793 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7794 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7795 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7796 dc->f_st = 0;
7797 dc->vm86 = (flags >> VM_SHIFT) & 1;
7798 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7799 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7800 dc->tf = (flags >> TF_SHIFT) & 1;
7801 dc->singlestep_enabled = env->singlestep_enabled;
7802 dc->cc_op = CC_OP_DYNAMIC;
7803 dc->cs_base = cs_base;
7804 dc->tb = tb;
7805 dc->popl_esp_hack = 0;
7806 /* select memory access functions */
7807 dc->mem_index = 0;
7808 if (flags & HF_SOFTMMU_MASK) {
7809 if (dc->cpl == 3)
7810 dc->mem_index = 2 * 4;
7811 else
7812 dc->mem_index = 1 * 4;
7813 }
7814 dc->cpuid_features = env->cpuid_features;
7815 dc->cpuid_ext_features = env->cpuid_ext_features;
7816 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7817 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7818 #ifdef TARGET_X86_64
7819 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7820 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7821 #endif
7822 dc->flags = flags;
7823 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7824 (flags & HF_INHIBIT_IRQ_MASK)
7825 #ifndef CONFIG_SOFTMMU
7826 || (flags & HF_SOFTMMU_MASK)
7827 #endif
7828 );
7829 #if 0
7830 /* check addseg logic */
7831 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7832 printf("ERROR addseg\n");
7833 #endif
7834
7835 cpu_T[0] = tcg_temp_new();
7836 cpu_T[1] = tcg_temp_new();
7837 cpu_A0 = tcg_temp_new();
7838 cpu_T3 = tcg_temp_new();
7839
7840 cpu_tmp0 = tcg_temp_new();
7841 cpu_tmp1_i64 = tcg_temp_new_i64();
7842 cpu_tmp2_i32 = tcg_temp_new_i32();
7843 cpu_tmp3_i32 = tcg_temp_new_i32();
7844 cpu_tmp4 = tcg_temp_new();
7845 cpu_tmp5 = tcg_temp_new();
7846 cpu_ptr0 = tcg_temp_new_ptr();
7847 cpu_ptr1 = tcg_temp_new_ptr();
7848
7849 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7850
7851 dc->is_jmp = DISAS_NEXT;
7852 pc_ptr = pc_start;
7853 lj = -1;
7854 num_insns = 0;
7855 max_insns = tb->cflags & CF_COUNT_MASK;
7856 if (max_insns == 0)
7857 max_insns = CF_COUNT_MASK;
7858
7859 gen_icount_start();
7860 for(;;) {
7861 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7862 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7863 if (bp->pc == pc_ptr &&
7864 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7865 gen_debug(dc, pc_ptr - dc->cs_base);
7866 break;
7867 }
7868 }
7869 }
7870 if (search_pc) {
7871 j = gen_opc_ptr - gen_opc_buf;
7872 if (lj < j) {
7873 lj++;
7874 while (lj < j)
7875 gen_opc_instr_start[lj++] = 0;
7876 }
7877 gen_opc_pc[lj] = pc_ptr;
7878 gen_opc_cc_op[lj] = dc->cc_op;
7879 gen_opc_instr_start[lj] = 1;
7880 gen_opc_icount[lj] = num_insns;
7881 }
7882 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7883 gen_io_start();
7884
7885 pc_ptr = disas_insn(dc, pc_ptr);
7886 num_insns++;
7887 /* stop translation if indicated */
7888 if (dc->is_jmp)
7889 break;
7890 /* if single step mode, we generate only one instruction and
7891 generate an exception */
7892 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7893 the flag and abort the translation to give the irqs a
7894 change to be happen */
7895 if (dc->tf || dc->singlestep_enabled ||
7896 (flags & HF_INHIBIT_IRQ_MASK)) {
7897 gen_jmp_im(pc_ptr - dc->cs_base);
7898 gen_eob(dc);
7899 break;
7900 }
7901 /* if too long translation, stop generation too */
7902 if (gen_opc_ptr >= gen_opc_end ||
7903 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7904 num_insns >= max_insns) {
7905 gen_jmp_im(pc_ptr - dc->cs_base);
7906 gen_eob(dc);
7907 break;
7908 }
7909 if (singlestep) {
7910 gen_jmp_im(pc_ptr - dc->cs_base);
7911 gen_eob(dc);
7912 break;
7913 }
7914 }
7915 if (tb->cflags & CF_LAST_IO)
7916 gen_io_end();
7917 gen_icount_end(tb, num_insns);
7918 *gen_opc_ptr = INDEX_op_end;
7919 /* we don't forget to fill the last values */
7920 if (search_pc) {
7921 j = gen_opc_ptr - gen_opc_buf;
7922 lj++;
7923 while (lj <= j)
7924 gen_opc_instr_start[lj++] = 0;
7925 }
7926
7927 #ifdef DEBUG_DISAS
7928 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7929 int disas_flags;
7930 qemu_log("----------------\n");
7931 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7932 #ifdef TARGET_X86_64
7933 if (dc->code64)
7934 disas_flags = 2;
7935 else
7936 #endif
7937 disas_flags = !dc->code32;
7938 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7939 qemu_log("\n");
7940 }
7941 #endif
7942
7943 if (!search_pc) {
7944 tb->size = pc_ptr - pc_start;
7945 tb->icount = num_insns;
7946 }
7947 }
7948
7949 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
7950 {
7951 gen_intermediate_code_internal(env, tb, 0);
7952 }
7953
7954 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
7955 {
7956 gen_intermediate_code_internal(env, tb, 1);
7957 }
7958
7959 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
7960 {
7961 int cc_op;
7962 #ifdef DEBUG_DISAS
7963 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7964 int i;
7965 qemu_log("RESTORE:\n");
7966 for(i = 0;i <= pc_pos; i++) {
7967 if (gen_opc_instr_start[i]) {
7968 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7969 }
7970 }
7971 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7972 pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7973 (uint32_t)tb->cs_base);
7974 }
7975 #endif
7976 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7977 cc_op = gen_opc_cc_op[pc_pos];
7978 if (cc_op != CC_OP_DYNAMIC)
7979 env->cc_op = cc_op;
7980 }
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