2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/memop.h"
27 #include "fpu_helper.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 /* 64 bits arithmetic for 32 bits hosts */
54 static inline uint64_t get_HILO(CPUMIPSState
*env
)
56 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) |
57 (uint32_t)env
->active_tc
.LO
[0];
60 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
62 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
63 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
66 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
68 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
69 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
73 /* Multiplication variants of the vr54xx. */
74 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
77 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
78 (int64_t)(int32_t)arg2
));
81 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
84 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
85 (uint64_t)(uint32_t)arg2
);
88 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
91 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
92 (int64_t)(int32_t)arg2
);
95 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
98 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
99 (int64_t)(int32_t)arg2
);
102 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
105 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
106 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
109 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
112 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
113 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
116 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
119 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
120 (int64_t)(int32_t)arg2
);
123 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
126 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
127 (int64_t)(int32_t)arg2
);
130 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
133 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
134 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
137 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
140 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
141 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
144 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
147 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
150 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
153 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
154 (uint64_t)(uint32_t)arg2
);
157 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
160 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
161 (int64_t)(int32_t)arg2
);
164 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
167 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
168 (uint64_t)(uint32_t)arg2
);
171 static inline target_ulong
bitswap(target_ulong v
)
173 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
174 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
175 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
176 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
177 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
178 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
183 target_ulong
helper_dbitswap(target_ulong rt
)
189 target_ulong
helper_bitswap(target_ulong rt
)
191 return (int32_t)bitswap(rt
);
194 target_ulong
helper_rotx(target_ulong rs
, uint32_t shift
, uint32_t shiftx
,
198 uint64_t tmp0
= ((uint64_t)rs
) << 32 | ((uint64_t)rs
& 0xffffffff);
199 uint64_t tmp1
= tmp0
;
200 for (i
= 0; i
<= 46; i
++) {
208 if (stripe
!= 0 && !(i
& 0x4)) {
212 if (tmp0
& (1LL << (i
+ 16))) {
220 uint64_t tmp2
= tmp1
;
221 for (i
= 0; i
<= 38; i
++) {
230 if (tmp1
& (1LL << (i
+ 8))) {
238 uint64_t tmp3
= tmp2
;
239 for (i
= 0; i
<= 34; i
++) {
247 if (tmp2
& (1LL << (i
+ 4))) {
255 uint64_t tmp4
= tmp3
;
256 for (i
= 0; i
<= 32; i
++) {
264 if (tmp3
& (1LL << (i
+ 2))) {
272 uint64_t tmp5
= tmp4
;
273 for (i
= 0; i
<= 31; i
++) {
277 if (tmp4
& (1LL << (i
+ 1))) {
285 return (int64_t)(int32_t)(uint32_t)tmp5
;
288 #ifndef CONFIG_USER_ONLY
290 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
291 target_ulong address
,
292 int rw
, uintptr_t retaddr
)
295 CPUState
*cs
= env_cpu(env
);
297 paddr
= cpu_mips_translate_address(env
, address
, rw
);
300 cpu_loop_exit_restore(cs
, retaddr
);
306 #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
307 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
309 if (arg & almask) { \
310 if (!(env->hflags & MIPS_HFLAG_DM)) { \
311 env->CP0_BadVAddr = arg; \
313 do_raise_exception(env, EXCP_AdEL, GETPC()); \
315 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
317 env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
320 HELPER_LD_ATOMIC(ll
, ldl
, 0x3, (target_long
)(int32_t))
322 HELPER_LD_ATOMIC(lld
, ldq
, 0x7, (target_ulong
))
324 #undef HELPER_LD_ATOMIC
327 #ifdef TARGET_WORDS_BIGENDIAN
328 #define GET_LMASK(v) ((v) & 3)
329 #define GET_OFFSET(addr, offset) (addr + (offset))
331 #define GET_LMASK(v) (((v) & 3) ^ 3)
332 #define GET_OFFSET(addr, offset) (addr - (offset))
335 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
338 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
340 if (GET_LMASK(arg2
) <= 2) {
341 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16),
345 if (GET_LMASK(arg2
) <= 1) {
346 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8),
350 if (GET_LMASK(arg2
) == 0) {
351 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
,
356 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
359 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
361 if (GET_LMASK(arg2
) >= 1) {
362 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8),
366 if (GET_LMASK(arg2
) >= 2) {
367 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16),
371 if (GET_LMASK(arg2
) == 3) {
372 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24),
377 #if defined(TARGET_MIPS64)
379 * "half" load and stores. We must do the memory access inline,
380 * or fault handling won't work.
382 #ifdef TARGET_WORDS_BIGENDIAN
383 #define GET_LMASK64(v) ((v) & 7)
385 #define GET_LMASK64(v) (((v) & 7) ^ 7)
388 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
391 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
393 if (GET_LMASK64(arg2
) <= 6) {
394 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48),
398 if (GET_LMASK64(arg2
) <= 5) {
399 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40),
403 if (GET_LMASK64(arg2
) <= 4) {
404 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32),
408 if (GET_LMASK64(arg2
) <= 3) {
409 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24),
413 if (GET_LMASK64(arg2
) <= 2) {
414 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16),
418 if (GET_LMASK64(arg2
) <= 1) {
419 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8),
423 if (GET_LMASK64(arg2
) <= 0) {
424 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
,
429 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
432 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
434 if (GET_LMASK64(arg2
) >= 1) {
435 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8),
439 if (GET_LMASK64(arg2
) >= 2) {
440 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16),
444 if (GET_LMASK64(arg2
) >= 3) {
445 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24),
449 if (GET_LMASK64(arg2
) >= 4) {
450 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32),
454 if (GET_LMASK64(arg2
) >= 5) {
455 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40),
459 if (GET_LMASK64(arg2
) >= 6) {
460 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48),
464 if (GET_LMASK64(arg2
) == 7) {
465 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56),
469 #endif /* TARGET_MIPS64 */
471 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
473 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
476 target_ulong base_reglist
= reglist
& 0xf;
477 target_ulong do_r31
= reglist
& 0x10;
479 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
482 for (i
= 0; i
< base_reglist
; i
++) {
483 env
->active_tc
.gpr
[multiple_regs
[i
]] =
484 (target_long
)cpu_ldl_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
490 env
->active_tc
.gpr
[31] =
491 (target_long
)cpu_ldl_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
495 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
498 target_ulong base_reglist
= reglist
& 0xf;
499 target_ulong do_r31
= reglist
& 0x10;
501 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
504 for (i
= 0; i
< base_reglist
; i
++) {
505 cpu_stw_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]],
512 cpu_stw_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
516 #if defined(TARGET_MIPS64)
517 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
520 target_ulong base_reglist
= reglist
& 0xf;
521 target_ulong do_r31
= reglist
& 0x10;
523 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
526 for (i
= 0; i
< base_reglist
; i
++) {
527 env
->active_tc
.gpr
[multiple_regs
[i
]] =
528 cpu_ldq_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
534 env
->active_tc
.gpr
[31] =
535 cpu_ldq_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
539 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
542 target_ulong base_reglist
= reglist
& 0xf;
543 target_ulong do_r31
= reglist
& 0x10;
545 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
548 for (i
= 0; i
< base_reglist
; i
++) {
549 cpu_stq_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]],
556 cpu_stq_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
562 void helper_fork(target_ulong arg1
, target_ulong arg2
)
565 * arg1 = rt, arg2 = rs
566 * TODO: store to TC register
570 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
572 target_long arg1
= arg
;
575 /* No scheduling policy implemented. */
577 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
578 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
579 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
580 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
581 do_raise_exception(env
, EXCP_THREAD
, GETPC());
584 } else if (arg1
== 0) {
586 /* TODO: TC underflow */
587 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
588 do_raise_exception(env
, EXCP_THREAD
, GETPC());
590 /* TODO: Deallocate TC */
592 } else if (arg1
> 0) {
593 /* Yield qualifier inputs not implemented. */
594 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
595 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
596 do_raise_exception(env
, EXCP_THREAD
, GETPC());
598 return env
->CP0_YQMask
;
601 #ifndef CONFIG_USER_ONLY
603 static void r4k_mips_tlb_flush_extra(CPUMIPSState
*env
, int first
)
605 /* Discard entries from env->tlb[first] onwards. */
606 while (env
->tlb
->tlb_in_use
> first
) {
607 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
611 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
613 #if defined(TARGET_MIPS64)
614 return extract64(entrylo
, 6, 54);
616 return extract64(entrylo
, 6, 24) | /* PFN */
617 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
621 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
624 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
626 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
627 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
628 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
633 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
634 #if defined(TARGET_MIPS64)
635 tlb
->VPN
&= env
->SEGMask
;
637 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
638 tlb
->MMID
= env
->CP0_MemoryMapID
;
639 tlb
->PageMask
= env
->CP0_PageMask
;
640 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
641 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
642 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
643 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
644 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
645 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
646 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
647 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
648 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
649 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
650 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
651 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
652 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
655 void r4k_helper_tlbinv(CPUMIPSState
*env
)
657 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
658 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
659 uint32_t MMID
= env
->CP0_MemoryMapID
;
664 MMID
= mi
? MMID
: (uint32_t) ASID
;
665 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
666 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
667 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
668 if (!tlb
->G
&& tlb_mmid
== MMID
) {
672 cpu_mips_tlb_flush(env
);
675 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
679 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
680 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
682 cpu_mips_tlb_flush(env
);
685 void r4k_helper_tlbwi(CPUMIPSState
*env
)
687 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
689 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
690 uint32_t MMID
= env
->CP0_MemoryMapID
;
692 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
696 MMID
= mi
? MMID
: (uint32_t) ASID
;
698 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
699 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
700 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
701 #if defined(TARGET_MIPS64)
704 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
705 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
706 V0
= (env
->CP0_EntryLo0
& 2) != 0;
707 D0
= (env
->CP0_EntryLo0
& 4) != 0;
708 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
709 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
710 V1
= (env
->CP0_EntryLo1
& 2) != 0;
711 D1
= (env
->CP0_EntryLo1
& 4) != 0;
712 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
713 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
715 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
717 * Discard cached TLB entries, unless tlbwi is just upgrading access
718 * permissions on the current entry.
720 if (tlb
->VPN
!= VPN
|| tlb_mmid
!= MMID
|| tlb
->G
!= G
||
721 (!tlb
->EHINV
&& EHINV
) ||
722 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
723 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
724 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
725 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
726 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
729 r4k_invalidate_tlb(env
, idx
, 0);
730 r4k_fill_tlb(env
, idx
);
733 void r4k_helper_tlbwr(CPUMIPSState
*env
)
735 int r
= cpu_mips_get_random(env
);
737 r4k_invalidate_tlb(env
, r
, 1);
738 r4k_fill_tlb(env
, r
);
741 void r4k_helper_tlbp(CPUMIPSState
*env
)
743 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
748 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
749 uint32_t MMID
= env
->CP0_MemoryMapID
;
753 MMID
= mi
? MMID
: (uint32_t) ASID
;
754 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
755 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
756 /* 1k pages are not supported. */
757 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
758 tag
= env
->CP0_EntryHi
& ~mask
;
759 VPN
= tlb
->VPN
& ~mask
;
760 #if defined(TARGET_MIPS64)
763 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
764 /* Check ASID/MMID, virtual page number & size */
765 if ((tlb
->G
== 1 || tlb_mmid
== MMID
) && VPN
== tag
&& !tlb
->EHINV
) {
771 if (i
== env
->tlb
->nb_tlb
) {
772 /* No match. Discard any shadow entries, if any of them match. */
773 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
774 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
775 /* 1k pages are not supported. */
776 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
777 tag
= env
->CP0_EntryHi
& ~mask
;
778 VPN
= tlb
->VPN
& ~mask
;
779 #if defined(TARGET_MIPS64)
782 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
783 /* Check ASID/MMID, virtual page number & size */
784 if ((tlb
->G
== 1 || tlb_mmid
== MMID
) && VPN
== tag
) {
785 r4k_mips_tlb_flush_extra(env
, i
);
790 env
->CP0_Index
|= 0x80000000;
794 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
796 #if defined(TARGET_MIPS64)
799 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
800 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
804 void r4k_helper_tlbr(CPUMIPSState
*env
)
806 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
807 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
808 uint32_t MMID
= env
->CP0_MemoryMapID
;
813 MMID
= mi
? MMID
: (uint32_t) ASID
;
814 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
815 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
817 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
818 /* If this will change the current ASID/MMID, flush qemu's TLB. */
819 if (MMID
!= tlb_mmid
) {
820 cpu_mips_tlb_flush(env
);
823 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
826 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
827 env
->CP0_PageMask
= 0;
828 env
->CP0_EntryLo0
= 0;
829 env
->CP0_EntryLo1
= 0;
831 env
->CP0_EntryHi
= mi
? tlb
->VPN
: tlb
->VPN
| tlb
->ASID
;
832 env
->CP0_MemoryMapID
= tlb
->MMID
;
833 env
->CP0_PageMask
= tlb
->PageMask
;
834 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
835 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
836 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
837 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
838 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
839 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
840 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
841 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
845 void helper_tlbwi(CPUMIPSState
*env
)
847 env
->tlb
->helper_tlbwi(env
);
850 void helper_tlbwr(CPUMIPSState
*env
)
852 env
->tlb
->helper_tlbwr(env
);
855 void helper_tlbp(CPUMIPSState
*env
)
857 env
->tlb
->helper_tlbp(env
);
860 void helper_tlbr(CPUMIPSState
*env
)
862 env
->tlb
->helper_tlbr(env
);
865 void helper_tlbinv(CPUMIPSState
*env
)
867 env
->tlb
->helper_tlbinv(env
);
870 void helper_tlbinvf(CPUMIPSState
*env
)
872 env
->tlb
->helper_tlbinvf(env
);
875 static void global_invalidate_tlb(CPUMIPSState
*env
,
890 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
891 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
893 (((tlb
->VPN
& ~tlb
->PageMask
) == (invMsgVPN2
& ~tlb
->PageMask
))
896 (extract64(env
->CP0_EntryHi
, 62, 2) == invMsgR
)
899 MMidMatch
= tlb
->MMID
== invMsgMMid
;
900 if ((invAll
&& (idx
> env
->CP0_Wired
)) ||
901 (VAMatch
&& invVAMMid
&& (tlb
->G
|| MMidMatch
)) ||
902 (VAMatch
&& invVA
) ||
903 (MMidMatch
&& !(tlb
->G
) && invMMid
)) {
907 cpu_mips_tlb_flush(env
);
910 void helper_ginvt(CPUMIPSState
*env
, target_ulong arg
, uint32_t type
)
912 bool invAll
= type
== 0;
913 bool invVA
= type
== 1;
914 bool invMMid
= type
== 2;
915 bool invVAMMid
= type
== 3;
916 uint32_t invMsgVPN2
= arg
& (TARGET_PAGE_MASK
<< 1);
918 uint32_t invMsgMMid
= env
->CP0_MemoryMapID
;
919 CPUState
*other_cs
= first_cpu
;
922 invMsgR
= extract64(arg
, 62, 2);
925 CPU_FOREACH(other_cs
) {
926 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
927 global_invalidate_tlb(&other_cpu
->env
, invMsgVPN2
, invMsgR
, invMsgMMid
,
928 invAll
, invVAMMid
, invMMid
, invVA
);
933 target_ulong
helper_di(CPUMIPSState
*env
)
935 target_ulong t0
= env
->CP0_Status
;
937 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
941 target_ulong
helper_ei(CPUMIPSState
*env
)
943 target_ulong t0
= env
->CP0_Status
;
945 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
949 static void debug_pre_eret(CPUMIPSState
*env
)
951 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
952 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
953 env
->active_tc
.PC
, env
->CP0_EPC
);
954 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
955 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
957 if (env
->hflags
& MIPS_HFLAG_DM
) {
958 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
964 static void debug_post_eret(CPUMIPSState
*env
)
966 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
967 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
968 env
->active_tc
.PC
, env
->CP0_EPC
);
969 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
970 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
972 if (env
->hflags
& MIPS_HFLAG_DM
) {
973 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
975 switch (cpu_mmu_index(env
, false)) {
989 cpu_abort(env_cpu(env
), "Invalid MMU mode!\n");
995 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
997 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
999 env
->hflags
|= MIPS_HFLAG_M16
;
1001 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1005 static inline void exception_return(CPUMIPSState
*env
)
1007 debug_pre_eret(env
);
1008 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
1009 set_pc(env
, env
->CP0_ErrorEPC
);
1010 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1012 set_pc(env
, env
->CP0_EPC
);
1013 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
1015 compute_hflags(env
);
1016 debug_post_eret(env
);
1019 void helper_eret(CPUMIPSState
*env
)
1021 exception_return(env
);
1022 env
->CP0_LLAddr
= 1;
1026 void helper_eretnc(CPUMIPSState
*env
)
1028 exception_return(env
);
1031 void helper_deret(CPUMIPSState
*env
)
1033 debug_pre_eret(env
);
1035 env
->hflags
&= ~MIPS_HFLAG_DM
;
1036 compute_hflags(env
);
1038 set_pc(env
, env
->CP0_DEPC
);
1040 debug_post_eret(env
);
1042 #endif /* !CONFIG_USER_ONLY */
1044 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
1046 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
1049 do_raise_exception(env
, EXCP_RI
, pc
);
1052 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
1054 check_hwrena(env
, 0, GETPC());
1055 return env
->CP0_EBase
& 0x3ff;
1058 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
1060 check_hwrena(env
, 1, GETPC());
1061 return env
->SYNCI_Step
;
1064 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
1066 check_hwrena(env
, 2, GETPC());
1067 #ifdef CONFIG_USER_ONLY
1068 return env
->CP0_Count
;
1070 return (int32_t)cpu_mips_get_count(env
);
1074 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
1076 check_hwrena(env
, 3, GETPC());
1080 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
1082 check_hwrena(env
, 4, GETPC());
1083 return env
->CP0_Performance0
;
1086 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
1088 check_hwrena(env
, 5, GETPC());
1089 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
1092 void helper_pmon(CPUMIPSState
*env
, int function
)
1096 case 2: /* TODO: char inbyte(int waitflag); */
1097 if (env
->active_tc
.gpr
[4] == 0) {
1098 env
->active_tc
.gpr
[2] = -1;
1101 case 11: /* TODO: char inbyte (void); */
1102 env
->active_tc
.gpr
[2] = -1;
1106 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
1112 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
1119 void helper_wait(CPUMIPSState
*env
)
1121 CPUState
*cs
= env_cpu(env
);
1124 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
1126 * Last instruction in the block, PC was updated before
1127 * - no need to recover PC and icount.
1129 raise_exception(env
, EXCP_HLT
);
1132 #if !defined(CONFIG_USER_ONLY)
1134 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
1135 MMUAccessType access_type
,
1136 int mmu_idx
, uintptr_t retaddr
)
1138 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1139 CPUMIPSState
*env
= &cpu
->env
;
1143 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
1144 env
->CP0_BadVAddr
= addr
;
1147 if (access_type
== MMU_DATA_STORE
) {
1151 if (access_type
== MMU_INST_FETCH
) {
1152 error_code
|= EXCP_INST_NOTAVAIL
;
1156 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
1159 void mips_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1160 vaddr addr
, unsigned size
,
1161 MMUAccessType access_type
,
1162 int mmu_idx
, MemTxAttrs attrs
,
1163 MemTxResult response
, uintptr_t retaddr
)
1165 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1166 CPUMIPSState
*env
= &cpu
->env
;
1168 if (access_type
== MMU_INST_FETCH
) {
1169 do_raise_exception(env
, EXCP_IBE
, retaddr
);
1171 do_raise_exception(env
, EXCP_DBE
, retaddr
);
1174 #endif /* !CONFIG_USER_ONLY */
1178 /* Data format min and max values */
1179 #define DF_BITS(df) (1 << ((df) + 3))
1181 /* Element-by-element access macros */
1182 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
1184 #if !defined(CONFIG_USER_ONLY)
1185 #define MEMOP_IDX(DF) \
1186 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
1187 cpu_mmu_index(env, false));
1189 #define MEMOP_IDX(DF)
1192 void helper_msa_ld_b(CPUMIPSState
*env
, uint32_t wd
,
1195 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1197 #if !defined(CONFIG_USER_ONLY)
1198 #if !defined(HOST_WORDS_BIGENDIAN)
1199 pwd
->b
[0] = helper_ret_ldub_mmu(env
, addr
+ (0 << DF_BYTE
), oi
, GETPC());
1200 pwd
->b
[1] = helper_ret_ldub_mmu(env
, addr
+ (1 << DF_BYTE
), oi
, GETPC());
1201 pwd
->b
[2] = helper_ret_ldub_mmu(env
, addr
+ (2 << DF_BYTE
), oi
, GETPC());
1202 pwd
->b
[3] = helper_ret_ldub_mmu(env
, addr
+ (3 << DF_BYTE
), oi
, GETPC());
1203 pwd
->b
[4] = helper_ret_ldub_mmu(env
, addr
+ (4 << DF_BYTE
), oi
, GETPC());
1204 pwd
->b
[5] = helper_ret_ldub_mmu(env
, addr
+ (5 << DF_BYTE
), oi
, GETPC());
1205 pwd
->b
[6] = helper_ret_ldub_mmu(env
, addr
+ (6 << DF_BYTE
), oi
, GETPC());
1206 pwd
->b
[7] = helper_ret_ldub_mmu(env
, addr
+ (7 << DF_BYTE
), oi
, GETPC());
1207 pwd
->b
[8] = helper_ret_ldub_mmu(env
, addr
+ (8 << DF_BYTE
), oi
, GETPC());
1208 pwd
->b
[9] = helper_ret_ldub_mmu(env
, addr
+ (9 << DF_BYTE
), oi
, GETPC());
1209 pwd
->b
[10] = helper_ret_ldub_mmu(env
, addr
+ (10 << DF_BYTE
), oi
, GETPC());
1210 pwd
->b
[11] = helper_ret_ldub_mmu(env
, addr
+ (11 << DF_BYTE
), oi
, GETPC());
1211 pwd
->b
[12] = helper_ret_ldub_mmu(env
, addr
+ (12 << DF_BYTE
), oi
, GETPC());
1212 pwd
->b
[13] = helper_ret_ldub_mmu(env
, addr
+ (13 << DF_BYTE
), oi
, GETPC());
1213 pwd
->b
[14] = helper_ret_ldub_mmu(env
, addr
+ (14 << DF_BYTE
), oi
, GETPC());
1214 pwd
->b
[15] = helper_ret_ldub_mmu(env
, addr
+ (15 << DF_BYTE
), oi
, GETPC());
1216 pwd
->b
[0] = helper_ret_ldub_mmu(env
, addr
+ (7 << DF_BYTE
), oi
, GETPC());
1217 pwd
->b
[1] = helper_ret_ldub_mmu(env
, addr
+ (6 << DF_BYTE
), oi
, GETPC());
1218 pwd
->b
[2] = helper_ret_ldub_mmu(env
, addr
+ (5 << DF_BYTE
), oi
, GETPC());
1219 pwd
->b
[3] = helper_ret_ldub_mmu(env
, addr
+ (4 << DF_BYTE
), oi
, GETPC());
1220 pwd
->b
[4] = helper_ret_ldub_mmu(env
, addr
+ (3 << DF_BYTE
), oi
, GETPC());
1221 pwd
->b
[5] = helper_ret_ldub_mmu(env
, addr
+ (2 << DF_BYTE
), oi
, GETPC());
1222 pwd
->b
[6] = helper_ret_ldub_mmu(env
, addr
+ (1 << DF_BYTE
), oi
, GETPC());
1223 pwd
->b
[7] = helper_ret_ldub_mmu(env
, addr
+ (0 << DF_BYTE
), oi
, GETPC());
1224 pwd
->b
[8] = helper_ret_ldub_mmu(env
, addr
+ (15 << DF_BYTE
), oi
, GETPC());
1225 pwd
->b
[9] = helper_ret_ldub_mmu(env
, addr
+ (14 << DF_BYTE
), oi
, GETPC());
1226 pwd
->b
[10] = helper_ret_ldub_mmu(env
, addr
+ (13 << DF_BYTE
), oi
, GETPC());
1227 pwd
->b
[11] = helper_ret_ldub_mmu(env
, addr
+ (12 << DF_BYTE
), oi
, GETPC());
1228 pwd
->b
[12] = helper_ret_ldub_mmu(env
, addr
+ (11 << DF_BYTE
), oi
, GETPC());
1229 pwd
->b
[13] = helper_ret_ldub_mmu(env
, addr
+ (10 << DF_BYTE
), oi
, GETPC());
1230 pwd
->b
[14] = helper_ret_ldub_mmu(env
, addr
+ (9 << DF_BYTE
), oi
, GETPC());
1231 pwd
->b
[15] = helper_ret_ldub_mmu(env
, addr
+ (8 << DF_BYTE
), oi
, GETPC());
1234 #if !defined(HOST_WORDS_BIGENDIAN)
1235 pwd
->b
[0] = cpu_ldub_data(env
, addr
+ (0 << DF_BYTE
));
1236 pwd
->b
[1] = cpu_ldub_data(env
, addr
+ (1 << DF_BYTE
));
1237 pwd
->b
[2] = cpu_ldub_data(env
, addr
+ (2 << DF_BYTE
));
1238 pwd
->b
[3] = cpu_ldub_data(env
, addr
+ (3 << DF_BYTE
));
1239 pwd
->b
[4] = cpu_ldub_data(env
, addr
+ (4 << DF_BYTE
));
1240 pwd
->b
[5] = cpu_ldub_data(env
, addr
+ (5 << DF_BYTE
));
1241 pwd
->b
[6] = cpu_ldub_data(env
, addr
+ (6 << DF_BYTE
));
1242 pwd
->b
[7] = cpu_ldub_data(env
, addr
+ (7 << DF_BYTE
));
1243 pwd
->b
[8] = cpu_ldub_data(env
, addr
+ (8 << DF_BYTE
));
1244 pwd
->b
[9] = cpu_ldub_data(env
, addr
+ (9 << DF_BYTE
));
1245 pwd
->b
[10] = cpu_ldub_data(env
, addr
+ (10 << DF_BYTE
));
1246 pwd
->b
[11] = cpu_ldub_data(env
, addr
+ (11 << DF_BYTE
));
1247 pwd
->b
[12] = cpu_ldub_data(env
, addr
+ (12 << DF_BYTE
));
1248 pwd
->b
[13] = cpu_ldub_data(env
, addr
+ (13 << DF_BYTE
));
1249 pwd
->b
[14] = cpu_ldub_data(env
, addr
+ (14 << DF_BYTE
));
1250 pwd
->b
[15] = cpu_ldub_data(env
, addr
+ (15 << DF_BYTE
));
1252 pwd
->b
[0] = cpu_ldub_data(env
, addr
+ (7 << DF_BYTE
));
1253 pwd
->b
[1] = cpu_ldub_data(env
, addr
+ (6 << DF_BYTE
));
1254 pwd
->b
[2] = cpu_ldub_data(env
, addr
+ (5 << DF_BYTE
));
1255 pwd
->b
[3] = cpu_ldub_data(env
, addr
+ (4 << DF_BYTE
));
1256 pwd
->b
[4] = cpu_ldub_data(env
, addr
+ (3 << DF_BYTE
));
1257 pwd
->b
[5] = cpu_ldub_data(env
, addr
+ (2 << DF_BYTE
));
1258 pwd
->b
[6] = cpu_ldub_data(env
, addr
+ (1 << DF_BYTE
));
1259 pwd
->b
[7] = cpu_ldub_data(env
, addr
+ (0 << DF_BYTE
));
1260 pwd
->b
[8] = cpu_ldub_data(env
, addr
+ (15 << DF_BYTE
));
1261 pwd
->b
[9] = cpu_ldub_data(env
, addr
+ (14 << DF_BYTE
));
1262 pwd
->b
[10] = cpu_ldub_data(env
, addr
+ (13 << DF_BYTE
));
1263 pwd
->b
[11] = cpu_ldub_data(env
, addr
+ (12 << DF_BYTE
));
1264 pwd
->b
[12] = cpu_ldub_data(env
, addr
+ (11 << DF_BYTE
));
1265 pwd
->b
[13] = cpu_ldub_data(env
, addr
+ (10 << DF_BYTE
));
1266 pwd
->b
[14] = cpu_ldub_data(env
, addr
+ (9 << DF_BYTE
));
1267 pwd
->b
[15] = cpu_ldub_data(env
, addr
+ (8 << DF_BYTE
));
1272 void helper_msa_ld_h(CPUMIPSState
*env
, uint32_t wd
,
1275 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1277 #if !defined(CONFIG_USER_ONLY)
1278 #if !defined(HOST_WORDS_BIGENDIAN)
1279 pwd
->h
[0] = helper_ret_lduw_mmu(env
, addr
+ (0 << DF_HALF
), oi
, GETPC());
1280 pwd
->h
[1] = helper_ret_lduw_mmu(env
, addr
+ (1 << DF_HALF
), oi
, GETPC());
1281 pwd
->h
[2] = helper_ret_lduw_mmu(env
, addr
+ (2 << DF_HALF
), oi
, GETPC());
1282 pwd
->h
[3] = helper_ret_lduw_mmu(env
, addr
+ (3 << DF_HALF
), oi
, GETPC());
1283 pwd
->h
[4] = helper_ret_lduw_mmu(env
, addr
+ (4 << DF_HALF
), oi
, GETPC());
1284 pwd
->h
[5] = helper_ret_lduw_mmu(env
, addr
+ (5 << DF_HALF
), oi
, GETPC());
1285 pwd
->h
[6] = helper_ret_lduw_mmu(env
, addr
+ (6 << DF_HALF
), oi
, GETPC());
1286 pwd
->h
[7] = helper_ret_lduw_mmu(env
, addr
+ (7 << DF_HALF
), oi
, GETPC());
1288 pwd
->h
[0] = helper_ret_lduw_mmu(env
, addr
+ (3 << DF_HALF
), oi
, GETPC());
1289 pwd
->h
[1] = helper_ret_lduw_mmu(env
, addr
+ (2 << DF_HALF
), oi
, GETPC());
1290 pwd
->h
[2] = helper_ret_lduw_mmu(env
, addr
+ (1 << DF_HALF
), oi
, GETPC());
1291 pwd
->h
[3] = helper_ret_lduw_mmu(env
, addr
+ (0 << DF_HALF
), oi
, GETPC());
1292 pwd
->h
[4] = helper_ret_lduw_mmu(env
, addr
+ (7 << DF_HALF
), oi
, GETPC());
1293 pwd
->h
[5] = helper_ret_lduw_mmu(env
, addr
+ (6 << DF_HALF
), oi
, GETPC());
1294 pwd
->h
[6] = helper_ret_lduw_mmu(env
, addr
+ (5 << DF_HALF
), oi
, GETPC());
1295 pwd
->h
[7] = helper_ret_lduw_mmu(env
, addr
+ (4 << DF_HALF
), oi
, GETPC());
1298 #if !defined(HOST_WORDS_BIGENDIAN)
1299 pwd
->h
[0] = cpu_lduw_data(env
, addr
+ (0 << DF_HALF
));
1300 pwd
->h
[1] = cpu_lduw_data(env
, addr
+ (1 << DF_HALF
));
1301 pwd
->h
[2] = cpu_lduw_data(env
, addr
+ (2 << DF_HALF
));
1302 pwd
->h
[3] = cpu_lduw_data(env
, addr
+ (3 << DF_HALF
));
1303 pwd
->h
[4] = cpu_lduw_data(env
, addr
+ (4 << DF_HALF
));
1304 pwd
->h
[5] = cpu_lduw_data(env
, addr
+ (5 << DF_HALF
));
1305 pwd
->h
[6] = cpu_lduw_data(env
, addr
+ (6 << DF_HALF
));
1306 pwd
->h
[7] = cpu_lduw_data(env
, addr
+ (7 << DF_HALF
));
1308 pwd
->h
[0] = cpu_lduw_data(env
, addr
+ (3 << DF_HALF
));
1309 pwd
->h
[1] = cpu_lduw_data(env
, addr
+ (2 << DF_HALF
));
1310 pwd
->h
[2] = cpu_lduw_data(env
, addr
+ (1 << DF_HALF
));
1311 pwd
->h
[3] = cpu_lduw_data(env
, addr
+ (0 << DF_HALF
));
1312 pwd
->h
[4] = cpu_lduw_data(env
, addr
+ (7 << DF_HALF
));
1313 pwd
->h
[5] = cpu_lduw_data(env
, addr
+ (6 << DF_HALF
));
1314 pwd
->h
[6] = cpu_lduw_data(env
, addr
+ (5 << DF_HALF
));
1315 pwd
->h
[7] = cpu_lduw_data(env
, addr
+ (4 << DF_HALF
));
1320 void helper_msa_ld_w(CPUMIPSState
*env
, uint32_t wd
,
1323 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1325 #if !defined(CONFIG_USER_ONLY)
1326 #if !defined(HOST_WORDS_BIGENDIAN)
1327 pwd
->w
[0] = helper_ret_ldul_mmu(env
, addr
+ (0 << DF_WORD
), oi
, GETPC());
1328 pwd
->w
[1] = helper_ret_ldul_mmu(env
, addr
+ (1 << DF_WORD
), oi
, GETPC());
1329 pwd
->w
[2] = helper_ret_ldul_mmu(env
, addr
+ (2 << DF_WORD
), oi
, GETPC());
1330 pwd
->w
[3] = helper_ret_ldul_mmu(env
, addr
+ (3 << DF_WORD
), oi
, GETPC());
1332 pwd
->w
[0] = helper_ret_ldul_mmu(env
, addr
+ (1 << DF_WORD
), oi
, GETPC());
1333 pwd
->w
[1] = helper_ret_ldul_mmu(env
, addr
+ (0 << DF_WORD
), oi
, GETPC());
1334 pwd
->w
[2] = helper_ret_ldul_mmu(env
, addr
+ (3 << DF_WORD
), oi
, GETPC());
1335 pwd
->w
[3] = helper_ret_ldul_mmu(env
, addr
+ (2 << DF_WORD
), oi
, GETPC());
1338 #if !defined(HOST_WORDS_BIGENDIAN)
1339 pwd
->w
[0] = cpu_ldl_data(env
, addr
+ (0 << DF_WORD
));
1340 pwd
->w
[1] = cpu_ldl_data(env
, addr
+ (1 << DF_WORD
));
1341 pwd
->w
[2] = cpu_ldl_data(env
, addr
+ (2 << DF_WORD
));
1342 pwd
->w
[3] = cpu_ldl_data(env
, addr
+ (3 << DF_WORD
));
1344 pwd
->w
[0] = cpu_ldl_data(env
, addr
+ (1 << DF_WORD
));
1345 pwd
->w
[1] = cpu_ldl_data(env
, addr
+ (0 << DF_WORD
));
1346 pwd
->w
[2] = cpu_ldl_data(env
, addr
+ (3 << DF_WORD
));
1347 pwd
->w
[3] = cpu_ldl_data(env
, addr
+ (2 << DF_WORD
));
1352 void helper_msa_ld_d(CPUMIPSState
*env
, uint32_t wd
,
1355 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1356 MEMOP_IDX(DF_DOUBLE
)
1357 #if !defined(CONFIG_USER_ONLY)
1358 pwd
->d
[0] = helper_ret_ldq_mmu(env
, addr
+ (0 << DF_DOUBLE
), oi
, GETPC());
1359 pwd
->d
[1] = helper_ret_ldq_mmu(env
, addr
+ (1 << DF_DOUBLE
), oi
, GETPC());
1361 pwd
->d
[0] = cpu_ldq_data(env
, addr
+ (0 << DF_DOUBLE
));
1362 pwd
->d
[1] = cpu_ldq_data(env
, addr
+ (1 << DF_DOUBLE
));
1366 #define MSA_PAGESPAN(x) \
1367 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
1369 static inline void ensure_writable_pages(CPUMIPSState
*env
,
1374 /* FIXME: Probe the actual accesses (pass and use a size) */
1375 if (unlikely(MSA_PAGESPAN(addr
))) {
1377 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
1379 addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1380 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
1384 void helper_msa_st_b(CPUMIPSState
*env
, uint32_t wd
,
1387 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1388 int mmu_idx
= cpu_mmu_index(env
, false);
1391 ensure_writable_pages(env
, addr
, mmu_idx
, GETPC());
1392 #if !defined(CONFIG_USER_ONLY)
1393 #if !defined(HOST_WORDS_BIGENDIAN)
1394 helper_ret_stb_mmu(env
, addr
+ (0 << DF_BYTE
), pwd
->b
[0], oi
, GETPC());
1395 helper_ret_stb_mmu(env
, addr
+ (1 << DF_BYTE
), pwd
->b
[1], oi
, GETPC());
1396 helper_ret_stb_mmu(env
, addr
+ (2 << DF_BYTE
), pwd
->b
[2], oi
, GETPC());
1397 helper_ret_stb_mmu(env
, addr
+ (3 << DF_BYTE
), pwd
->b
[3], oi
, GETPC());
1398 helper_ret_stb_mmu(env
, addr
+ (4 << DF_BYTE
), pwd
->b
[4], oi
, GETPC());
1399 helper_ret_stb_mmu(env
, addr
+ (5 << DF_BYTE
), pwd
->b
[5], oi
, GETPC());
1400 helper_ret_stb_mmu(env
, addr
+ (6 << DF_BYTE
), pwd
->b
[6], oi
, GETPC());
1401 helper_ret_stb_mmu(env
, addr
+ (7 << DF_BYTE
), pwd
->b
[7], oi
, GETPC());
1402 helper_ret_stb_mmu(env
, addr
+ (8 << DF_BYTE
), pwd
->b
[8], oi
, GETPC());
1403 helper_ret_stb_mmu(env
, addr
+ (9 << DF_BYTE
), pwd
->b
[9], oi
, GETPC());
1404 helper_ret_stb_mmu(env
, addr
+ (10 << DF_BYTE
), pwd
->b
[10], oi
, GETPC());
1405 helper_ret_stb_mmu(env
, addr
+ (11 << DF_BYTE
), pwd
->b
[11], oi
, GETPC());
1406 helper_ret_stb_mmu(env
, addr
+ (12 << DF_BYTE
), pwd
->b
[12], oi
, GETPC());
1407 helper_ret_stb_mmu(env
, addr
+ (13 << DF_BYTE
), pwd
->b
[13], oi
, GETPC());
1408 helper_ret_stb_mmu(env
, addr
+ (14 << DF_BYTE
), pwd
->b
[14], oi
, GETPC());
1409 helper_ret_stb_mmu(env
, addr
+ (15 << DF_BYTE
), pwd
->b
[15], oi
, GETPC());
1411 helper_ret_stb_mmu(env
, addr
+ (7 << DF_BYTE
), pwd
->b
[0], oi
, GETPC());
1412 helper_ret_stb_mmu(env
, addr
+ (6 << DF_BYTE
), pwd
->b
[1], oi
, GETPC());
1413 helper_ret_stb_mmu(env
, addr
+ (5 << DF_BYTE
), pwd
->b
[2], oi
, GETPC());
1414 helper_ret_stb_mmu(env
, addr
+ (4 << DF_BYTE
), pwd
->b
[3], oi
, GETPC());
1415 helper_ret_stb_mmu(env
, addr
+ (3 << DF_BYTE
), pwd
->b
[4], oi
, GETPC());
1416 helper_ret_stb_mmu(env
, addr
+ (2 << DF_BYTE
), pwd
->b
[5], oi
, GETPC());
1417 helper_ret_stb_mmu(env
, addr
+ (1 << DF_BYTE
), pwd
->b
[6], oi
, GETPC());
1418 helper_ret_stb_mmu(env
, addr
+ (0 << DF_BYTE
), pwd
->b
[7], oi
, GETPC());
1419 helper_ret_stb_mmu(env
, addr
+ (15 << DF_BYTE
), pwd
->b
[8], oi
, GETPC());
1420 helper_ret_stb_mmu(env
, addr
+ (14 << DF_BYTE
), pwd
->b
[9], oi
, GETPC());
1421 helper_ret_stb_mmu(env
, addr
+ (13 << DF_BYTE
), pwd
->b
[10], oi
, GETPC());
1422 helper_ret_stb_mmu(env
, addr
+ (12 << DF_BYTE
), pwd
->b
[11], oi
, GETPC());
1423 helper_ret_stb_mmu(env
, addr
+ (11 << DF_BYTE
), pwd
->b
[12], oi
, GETPC());
1424 helper_ret_stb_mmu(env
, addr
+ (10 << DF_BYTE
), pwd
->b
[13], oi
, GETPC());
1425 helper_ret_stb_mmu(env
, addr
+ (9 << DF_BYTE
), pwd
->b
[14], oi
, GETPC());
1426 helper_ret_stb_mmu(env
, addr
+ (8 << DF_BYTE
), pwd
->b
[15], oi
, GETPC());
1429 #if !defined(HOST_WORDS_BIGENDIAN)
1430 cpu_stb_data(env
, addr
+ (0 << DF_BYTE
), pwd
->b
[0]);
1431 cpu_stb_data(env
, addr
+ (1 << DF_BYTE
), pwd
->b
[1]);
1432 cpu_stb_data(env
, addr
+ (2 << DF_BYTE
), pwd
->b
[2]);
1433 cpu_stb_data(env
, addr
+ (3 << DF_BYTE
), pwd
->b
[3]);
1434 cpu_stb_data(env
, addr
+ (4 << DF_BYTE
), pwd
->b
[4]);
1435 cpu_stb_data(env
, addr
+ (5 << DF_BYTE
), pwd
->b
[5]);
1436 cpu_stb_data(env
, addr
+ (6 << DF_BYTE
), pwd
->b
[6]);
1437 cpu_stb_data(env
, addr
+ (7 << DF_BYTE
), pwd
->b
[7]);
1438 cpu_stb_data(env
, addr
+ (8 << DF_BYTE
), pwd
->b
[8]);
1439 cpu_stb_data(env
, addr
+ (9 << DF_BYTE
), pwd
->b
[9]);
1440 cpu_stb_data(env
, addr
+ (10 << DF_BYTE
), pwd
->b
[10]);
1441 cpu_stb_data(env
, addr
+ (11 << DF_BYTE
), pwd
->b
[11]);
1442 cpu_stb_data(env
, addr
+ (12 << DF_BYTE
), pwd
->b
[12]);
1443 cpu_stb_data(env
, addr
+ (13 << DF_BYTE
), pwd
->b
[13]);
1444 cpu_stb_data(env
, addr
+ (14 << DF_BYTE
), pwd
->b
[14]);
1445 cpu_stb_data(env
, addr
+ (15 << DF_BYTE
), pwd
->b
[15]);
1447 cpu_stb_data(env
, addr
+ (7 << DF_BYTE
), pwd
->b
[0]);
1448 cpu_stb_data(env
, addr
+ (6 << DF_BYTE
), pwd
->b
[1]);
1449 cpu_stb_data(env
, addr
+ (5 << DF_BYTE
), pwd
->b
[2]);
1450 cpu_stb_data(env
, addr
+ (4 << DF_BYTE
), pwd
->b
[3]);
1451 cpu_stb_data(env
, addr
+ (3 << DF_BYTE
), pwd
->b
[4]);
1452 cpu_stb_data(env
, addr
+ (2 << DF_BYTE
), pwd
->b
[5]);
1453 cpu_stb_data(env
, addr
+ (1 << DF_BYTE
), pwd
->b
[6]);
1454 cpu_stb_data(env
, addr
+ (0 << DF_BYTE
), pwd
->b
[7]);
1455 cpu_stb_data(env
, addr
+ (15 << DF_BYTE
), pwd
->b
[8]);
1456 cpu_stb_data(env
, addr
+ (14 << DF_BYTE
), pwd
->b
[9]);
1457 cpu_stb_data(env
, addr
+ (13 << DF_BYTE
), pwd
->b
[10]);
1458 cpu_stb_data(env
, addr
+ (12 << DF_BYTE
), pwd
->b
[11]);
1459 cpu_stb_data(env
, addr
+ (11 << DF_BYTE
), pwd
->b
[12]);
1460 cpu_stb_data(env
, addr
+ (10 << DF_BYTE
), pwd
->b
[13]);
1461 cpu_stb_data(env
, addr
+ (9 << DF_BYTE
), pwd
->b
[14]);
1462 cpu_stb_data(env
, addr
+ (8 << DF_BYTE
), pwd
->b
[15]);
1467 void helper_msa_st_h(CPUMIPSState
*env
, uint32_t wd
,
1470 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1471 int mmu_idx
= cpu_mmu_index(env
, false);
1474 ensure_writable_pages(env
, addr
, mmu_idx
, GETPC());
1475 #if !defined(CONFIG_USER_ONLY)
1476 #if !defined(HOST_WORDS_BIGENDIAN)
1477 helper_ret_stw_mmu(env
, addr
+ (0 << DF_HALF
), pwd
->h
[0], oi
, GETPC());
1478 helper_ret_stw_mmu(env
, addr
+ (1 << DF_HALF
), pwd
->h
[1], oi
, GETPC());
1479 helper_ret_stw_mmu(env
, addr
+ (2 << DF_HALF
), pwd
->h
[2], oi
, GETPC());
1480 helper_ret_stw_mmu(env
, addr
+ (3 << DF_HALF
), pwd
->h
[3], oi
, GETPC());
1481 helper_ret_stw_mmu(env
, addr
+ (4 << DF_HALF
), pwd
->h
[4], oi
, GETPC());
1482 helper_ret_stw_mmu(env
, addr
+ (5 << DF_HALF
), pwd
->h
[5], oi
, GETPC());
1483 helper_ret_stw_mmu(env
, addr
+ (6 << DF_HALF
), pwd
->h
[6], oi
, GETPC());
1484 helper_ret_stw_mmu(env
, addr
+ (7 << DF_HALF
), pwd
->h
[7], oi
, GETPC());
1486 helper_ret_stw_mmu(env
, addr
+ (3 << DF_HALF
), pwd
->h
[0], oi
, GETPC());
1487 helper_ret_stw_mmu(env
, addr
+ (2 << DF_HALF
), pwd
->h
[1], oi
, GETPC());
1488 helper_ret_stw_mmu(env
, addr
+ (1 << DF_HALF
), pwd
->h
[2], oi
, GETPC());
1489 helper_ret_stw_mmu(env
, addr
+ (0 << DF_HALF
), pwd
->h
[3], oi
, GETPC());
1490 helper_ret_stw_mmu(env
, addr
+ (7 << DF_HALF
), pwd
->h
[4], oi
, GETPC());
1491 helper_ret_stw_mmu(env
, addr
+ (6 << DF_HALF
), pwd
->h
[5], oi
, GETPC());
1492 helper_ret_stw_mmu(env
, addr
+ (5 << DF_HALF
), pwd
->h
[6], oi
, GETPC());
1493 helper_ret_stw_mmu(env
, addr
+ (4 << DF_HALF
), pwd
->h
[7], oi
, GETPC());
1496 #if !defined(HOST_WORDS_BIGENDIAN)
1497 cpu_stw_data(env
, addr
+ (0 << DF_HALF
), pwd
->h
[0]);
1498 cpu_stw_data(env
, addr
+ (1 << DF_HALF
), pwd
->h
[1]);
1499 cpu_stw_data(env
, addr
+ (2 << DF_HALF
), pwd
->h
[2]);
1500 cpu_stw_data(env
, addr
+ (3 << DF_HALF
), pwd
->h
[3]);
1501 cpu_stw_data(env
, addr
+ (4 << DF_HALF
), pwd
->h
[4]);
1502 cpu_stw_data(env
, addr
+ (5 << DF_HALF
), pwd
->h
[5]);
1503 cpu_stw_data(env
, addr
+ (6 << DF_HALF
), pwd
->h
[6]);
1504 cpu_stw_data(env
, addr
+ (7 << DF_HALF
), pwd
->h
[7]);
1506 cpu_stw_data(env
, addr
+ (3 << DF_HALF
), pwd
->h
[0]);
1507 cpu_stw_data(env
, addr
+ (2 << DF_HALF
), pwd
->h
[1]);
1508 cpu_stw_data(env
, addr
+ (1 << DF_HALF
), pwd
->h
[2]);
1509 cpu_stw_data(env
, addr
+ (0 << DF_HALF
), pwd
->h
[3]);
1510 cpu_stw_data(env
, addr
+ (7 << DF_HALF
), pwd
->h
[4]);
1511 cpu_stw_data(env
, addr
+ (6 << DF_HALF
), pwd
->h
[5]);
1512 cpu_stw_data(env
, addr
+ (5 << DF_HALF
), pwd
->h
[6]);
1513 cpu_stw_data(env
, addr
+ (4 << DF_HALF
), pwd
->h
[7]);
1518 void helper_msa_st_w(CPUMIPSState
*env
, uint32_t wd
,
1521 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1522 int mmu_idx
= cpu_mmu_index(env
, false);
1525 ensure_writable_pages(env
, addr
, mmu_idx
, GETPC());
1526 #if !defined(CONFIG_USER_ONLY)
1527 #if !defined(HOST_WORDS_BIGENDIAN)
1528 helper_ret_stl_mmu(env
, addr
+ (0 << DF_WORD
), pwd
->w
[0], oi
, GETPC());
1529 helper_ret_stl_mmu(env
, addr
+ (1 << DF_WORD
), pwd
->w
[1], oi
, GETPC());
1530 helper_ret_stl_mmu(env
, addr
+ (2 << DF_WORD
), pwd
->w
[2], oi
, GETPC());
1531 helper_ret_stl_mmu(env
, addr
+ (3 << DF_WORD
), pwd
->w
[3], oi
, GETPC());
1533 helper_ret_stl_mmu(env
, addr
+ (1 << DF_WORD
), pwd
->w
[0], oi
, GETPC());
1534 helper_ret_stl_mmu(env
, addr
+ (0 << DF_WORD
), pwd
->w
[1], oi
, GETPC());
1535 helper_ret_stl_mmu(env
, addr
+ (3 << DF_WORD
), pwd
->w
[2], oi
, GETPC());
1536 helper_ret_stl_mmu(env
, addr
+ (2 << DF_WORD
), pwd
->w
[3], oi
, GETPC());
1539 #if !defined(HOST_WORDS_BIGENDIAN)
1540 cpu_stl_data(env
, addr
+ (0 << DF_WORD
), pwd
->w
[0]);
1541 cpu_stl_data(env
, addr
+ (1 << DF_WORD
), pwd
->w
[1]);
1542 cpu_stl_data(env
, addr
+ (2 << DF_WORD
), pwd
->w
[2]);
1543 cpu_stl_data(env
, addr
+ (3 << DF_WORD
), pwd
->w
[3]);
1545 cpu_stl_data(env
, addr
+ (1 << DF_WORD
), pwd
->w
[0]);
1546 cpu_stl_data(env
, addr
+ (0 << DF_WORD
), pwd
->w
[1]);
1547 cpu_stl_data(env
, addr
+ (3 << DF_WORD
), pwd
->w
[2]);
1548 cpu_stl_data(env
, addr
+ (2 << DF_WORD
), pwd
->w
[3]);
1553 void helper_msa_st_d(CPUMIPSState
*env
, uint32_t wd
,
1556 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1557 int mmu_idx
= cpu_mmu_index(env
, false);
1559 MEMOP_IDX(DF_DOUBLE
)
1560 ensure_writable_pages(env
, addr
, mmu_idx
, GETPC());
1561 #if !defined(CONFIG_USER_ONLY)
1562 helper_ret_stq_mmu(env
, addr
+ (0 << DF_DOUBLE
), pwd
->d
[0], oi
, GETPC());
1563 helper_ret_stq_mmu(env
, addr
+ (1 << DF_DOUBLE
), pwd
->d
[1], oi
, GETPC());
1565 cpu_stq_data(env
, addr
+ (0 << DF_DOUBLE
), pwd
->d
[0]);
1566 cpu_stq_data(env
, addr
+ (1 << DF_DOUBLE
), pwd
->d
[1]);
1570 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
1572 #ifndef CONFIG_USER_ONLY
1573 static const char *const type_name
[] = {
1574 "Primary Instruction",
1575 "Primary Data or Unified Primary",
1579 uint32_t cache_type
= extract32(op
, 0, 2);
1580 uint32_t cache_operation
= extract32(op
, 2, 3);
1581 target_ulong index
= addr
& 0x1fffffff;
1583 switch (cache_operation
) {
1584 case 0b010: /* Index Store Tag */
1585 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
1586 MO_64
, MEMTXATTRS_UNSPECIFIED
);
1588 case 0b001: /* Index Load Tag */
1589 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
1590 MO_64
, MEMTXATTRS_UNSPECIFIED
);
1592 case 0b000: /* Index Invalidate */
1593 case 0b100: /* Hit Invalidate */
1594 case 0b110: /* Hit Writeback */
1598 qemu_log_mask(LOG_UNIMP
, "cache operation:%u (type: %s cache)\n",
1599 cache_operation
, type_name
[cache_type
]);