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target-arm: Fix reset and migration of TTBCR(S)
[qemu/kevin.git] / hw / net / xilinx_axienet.c
blobde23ab5dcd0038a09d24873c75fccbd3cc34ac02
1 /*
2 * QEMU model of Xilinx AXI-Ethernet.
3 *
4 * Copyright (c) 2011 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "qapi/error.h"
28 #include "qemu/log.h"
29 #include "net/net.h"
30 #include "net/checksum.h"
31
32 #include "hw/stream.h"
33
34 #define DPHY(x)
35
36 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
37 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
38 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
39
40 #define XILINX_AXI_ENET(obj) \
41 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
42
43 #define XILINX_AXI_ENET_DATA_STREAM(obj) \
44 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
45 TYPE_XILINX_AXI_ENET_DATA_STREAM)
46
47 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
48 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
49 TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
50
51 /* Advertisement control register. */
52 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
53 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
54 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
55 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
56
57 #define CONTROL_PAYLOAD_WORDS 5
58 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
59
60 struct PHY {
61 uint32_t regs[32];
62
63 int link;
64
65 unsigned int (*read)(struct PHY *phy, unsigned int req);
66 void (*write)(struct PHY *phy, unsigned int req,
67 unsigned int data);
68 };
69
70 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
71 {
72 int regnum;
73 unsigned r = 0;
74
75 regnum = req & 0x1f;
76
77 switch (regnum) {
78 case 1:
79 if (!phy->link) {
80 break;
81 }
82 /* MR1. */
83 /* Speeds and modes. */
84 r |= (1 << 13) | (1 << 14);
85 r |= (1 << 11) | (1 << 12);
86 r |= (1 << 5); /* Autoneg complete. */
87 r |= (1 << 3); /* Autoneg able. */
88 r |= (1 << 2); /* link. */
89 r |= (1 << 1); /* link. */
90 break;
91 case 5:
92 /* Link partner ability.
93 We are kind; always agree with whatever best mode
94 the guest advertises. */
95 r = 1 << 14; /* Success. */
96 /* Copy advertised modes. */
97 r |= phy->regs[4] & (15 << 5);
98 /* Autoneg support. */
99 r |= 1;
100 break;
101 case 17:
102 /* Marvell PHY on many xilinx boards. */
103 r = 0x8000; /* 1000Mb */
104 break;
105 case 18:
106 {
107 /* Diagnostics reg. */
108 int duplex = 0;
109 int speed_100 = 0;
110
111 if (!phy->link) {
112 break;
113 }
114
115 /* Are we advertising 100 half or 100 duplex ? */
116 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
117 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
118
119 /* Are we advertising 10 duplex or 100 duplex ? */
120 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
121 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
122 r = (speed_100 << 10) | (duplex << 11);
123 }
124 break;
125
126 default:
127 r = phy->regs[regnum];
128 break;
129 }
130 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
131 return r;
132 }
133
134 static void
135 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
136 {
137 int regnum;
138
139 regnum = req & 0x1f;
140 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
141 switch (regnum) {
142 default:
143 phy->regs[regnum] = data;
144 break;
145 }
146
147 /* Unconditionally clear regs[BMCR][BMCR_RESET] */
148 phy->regs[0] &= ~0x8000;
149 }
150
151 static void
152 tdk_init(struct PHY *phy)
153 {
154 phy->regs[0] = 0x3100;
155 /* PHY Id. */
156 phy->regs[2] = 0x0300;
157 phy->regs[3] = 0xe400;
158 /* Autonegotiation advertisement reg. */
159 phy->regs[4] = 0x01E1;
160 phy->link = 1;
161
162 phy->read = tdk_read;
163 phy->write = tdk_write;
164 }
165
166 struct MDIOBus {
167 /* bus. */
168 int mdc;
169 int mdio;
170
171 /* decoder. */
172 enum {
173 PREAMBLE,
174 SOF,
175 OPC,
176 ADDR,
177 REQ,
178 TURNAROUND,
179 DATA
180 } state;
181 unsigned int drive;
182
183 unsigned int cnt;
184 unsigned int addr;
185 unsigned int opc;
186 unsigned int req;
187 unsigned int data;
188
189 struct PHY *devs[32];
190 };
191
192 static void
193 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
194 {
195 bus->devs[addr & 0x1f] = phy;
196 }
197
198 #ifdef USE_THIS_DEAD_CODE
199 static void
200 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
201 {
202 bus->devs[addr & 0x1f] = NULL;
203 }
204 #endif
205
206 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
207 unsigned int reg)
208 {
209 struct PHY *phy;
210 uint16_t data;
211
212 phy = bus->devs[addr];
213 if (phy && phy->read) {
214 data = phy->read(phy, reg);
215 } else {
216 data = 0xffff;
217 }
218 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
219 return data;
220 }
221
222 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
223 unsigned int reg, uint16_t data)
224 {
225 struct PHY *phy;
226
227 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
228 phy = bus->devs[addr];
229 if (phy && phy->write) {
230 phy->write(phy, reg, data);
231 }
232 }
233
234 #define DENET(x)
235
236 #define R_RAF (0x000 / 4)
237 enum {
238 RAF_MCAST_REJ = (1 << 1),
239 RAF_BCAST_REJ = (1 << 2),
240 RAF_EMCF_EN = (1 << 12),
241 RAF_NEWFUNC_EN = (1 << 11)
242 };
243
244 #define R_IS (0x00C / 4)
245 enum {
246 IS_HARD_ACCESS_COMPLETE = 1,
247 IS_AUTONEG = (1 << 1),
248 IS_RX_COMPLETE = (1 << 2),
249 IS_RX_REJECT = (1 << 3),
250 IS_TX_COMPLETE = (1 << 5),
251 IS_RX_DCM_LOCK = (1 << 6),
252 IS_MGM_RDY = (1 << 7),
253 IS_PHY_RST_DONE = (1 << 8),
254 };
255
256 #define R_IP (0x010 / 4)
257 #define R_IE (0x014 / 4)
258 #define R_UAWL (0x020 / 4)
259 #define R_UAWU (0x024 / 4)
260 #define R_PPST (0x030 / 4)
261 enum {
262 PPST_LINKSTATUS = (1 << 0),
263 PPST_PHY_LINKSTATUS = (1 << 7),
264 };
265
266 #define R_STATS_RX_BYTESL (0x200 / 4)
267 #define R_STATS_RX_BYTESH (0x204 / 4)
268 #define R_STATS_TX_BYTESL (0x208 / 4)
269 #define R_STATS_TX_BYTESH (0x20C / 4)
270 #define R_STATS_RXL (0x290 / 4)
271 #define R_STATS_RXH (0x294 / 4)
272 #define R_STATS_RX_BCASTL (0x2a0 / 4)
273 #define R_STATS_RX_BCASTH (0x2a4 / 4)
274 #define R_STATS_RX_MCASTL (0x2a8 / 4)
275 #define R_STATS_RX_MCASTH (0x2ac / 4)
276
277 #define R_RCW0 (0x400 / 4)
278 #define R_RCW1 (0x404 / 4)
279 enum {
280 RCW1_VLAN = (1 << 27),
281 RCW1_RX = (1 << 28),
282 RCW1_FCS = (1 << 29),
283 RCW1_JUM = (1 << 30),
284 RCW1_RST = (1 << 31),
285 };
286
287 #define R_TC (0x408 / 4)
288 enum {
289 TC_VLAN = (1 << 27),
290 TC_TX = (1 << 28),
291 TC_FCS = (1 << 29),
292 TC_JUM = (1 << 30),
293 TC_RST = (1 << 31),
294 };
295
296 #define R_EMMC (0x410 / 4)
297 enum {
298 EMMC_LINKSPEED_10MB = (0 << 30),
299 EMMC_LINKSPEED_100MB = (1 << 30),
300 EMMC_LINKSPEED_1000MB = (2 << 30),
301 };
302
303 #define R_PHYC (0x414 / 4)
304
305 #define R_MC (0x500 / 4)
306 #define MC_EN (1 << 6)
307
308 #define R_MCR (0x504 / 4)
309 #define R_MWD (0x508 / 4)
310 #define R_MRD (0x50c / 4)
311 #define R_MIS (0x600 / 4)
312 #define R_MIP (0x620 / 4)
313 #define R_MIE (0x640 / 4)
314 #define R_MIC (0x640 / 4)
315
316 #define R_UAW0 (0x700 / 4)
317 #define R_UAW1 (0x704 / 4)
318 #define R_FMI (0x708 / 4)
319 #define R_AF0 (0x710 / 4)
320 #define R_AF1 (0x714 / 4)
321 #define R_MAX (0x34 / 4)
322
323 /* Indirect registers. */
324 struct TEMAC {
325 struct MDIOBus mdio_bus;
326 struct PHY phy;
327
328 void *parent;
329 };
330
331 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
332 typedef struct XilinxAXIEnet XilinxAXIEnet;
333
334 struct XilinxAXIEnetStreamSlave {
335 Object parent;
336
337 struct XilinxAXIEnet *enet;
338 } ;
339
340 struct XilinxAXIEnet {
341 SysBusDevice busdev;
342 MemoryRegion iomem;
343 qemu_irq irq;
344 StreamSlave *tx_data_dev;
345 StreamSlave *tx_control_dev;
346 XilinxAXIEnetStreamSlave rx_data_dev;
347 XilinxAXIEnetStreamSlave rx_control_dev;
348 NICState *nic;
349 NICConf conf;
350
351
352 uint32_t c_rxmem;
353 uint32_t c_txmem;
354 uint32_t c_phyaddr;
355
356 struct TEMAC TEMAC;
357
358 /* MII regs. */
359 union {
360 uint32_t regs[4];
361 struct {
362 uint32_t mc;
363 uint32_t mcr;
364 uint32_t mwd;
365 uint32_t mrd;
366 };
367 } mii;
368
369 struct {
370 uint64_t rx_bytes;
371 uint64_t tx_bytes;
372
373 uint64_t rx;
374 uint64_t rx_bcast;
375 uint64_t rx_mcast;
376 } stats;
377
378 /* Receive configuration words. */
379 uint32_t rcw[2];
380 /* Transmit config. */
381 uint32_t tc;
382 uint32_t emmc;
383 uint32_t phyc;
384
385 /* Unicast Address Word. */
386 uint32_t uaw[2];
387 /* Unicast address filter used with extended mcast. */
388 uint32_t ext_uaw[2];
389 uint32_t fmi;
390
391 uint32_t regs[R_MAX];
392
393 /* Multicast filter addrs. */
394 uint32_t maddr[4][2];
395 /* 32K x 1 lookup filter. */
396 uint32_t ext_mtable[1024];
397
398 uint32_t hdr[CONTROL_PAYLOAD_WORDS];
399
400 uint8_t *rxmem;
401 uint32_t rxsize;
402 uint32_t rxpos;
403
404 uint8_t rxapp[CONTROL_PAYLOAD_SIZE];
405 uint32_t rxappsize;
406
407 /* Whether axienet_eth_rx_notify should flush incoming queue. */
408 bool need_flush;
409 };
410
411 static void axienet_rx_reset(XilinxAXIEnet *s)
412 {
413 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
414 }
415
416 static void axienet_tx_reset(XilinxAXIEnet *s)
417 {
418 s->tc = TC_JUM | TC_TX | TC_VLAN;
419 }
420
421 static inline int axienet_rx_resetting(XilinxAXIEnet *s)
422 {
423 return s->rcw[1] & RCW1_RST;
424 }
425
426 static inline int axienet_rx_enabled(XilinxAXIEnet *s)
427 {
428 return s->rcw[1] & RCW1_RX;
429 }
430
431 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
432 {
433 return !!(s->regs[R_RAF] & RAF_EMCF_EN);
434 }
435
436 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
437 {
438 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
439 }
440
441 static void xilinx_axienet_reset(DeviceState *d)
442 {
443 XilinxAXIEnet *s = XILINX_AXI_ENET(d);
444
445 axienet_rx_reset(s);
446 axienet_tx_reset(s);
447
448 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
449 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
450
451 s->emmc = EMMC_LINKSPEED_100MB;
452 }
453
454 static void enet_update_irq(XilinxAXIEnet *s)
455 {
456 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
457 qemu_set_irq(s->irq, !!s->regs[R_IP]);
458 }
459
460 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
461 {
462 XilinxAXIEnet *s = opaque;
463 uint32_t r = 0;
464 addr >>= 2;
465
466 switch (addr) {
467 case R_RCW0:
468 case R_RCW1:
469 r = s->rcw[addr & 1];
470 break;
471
472 case R_TC:
473 r = s->tc;
474 break;
475
476 case R_EMMC:
477 r = s->emmc;
478 break;
479
480 case R_PHYC:
481 r = s->phyc;
482 break;
483
484 case R_MCR:
485 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */
486 break;
487
488 case R_STATS_RX_BYTESL:
489 case R_STATS_RX_BYTESH:
490 r = s->stats.rx_bytes >> (32 * (addr & 1));
491 break;
492
493 case R_STATS_TX_BYTESL:
494 case R_STATS_TX_BYTESH:
495 r = s->stats.tx_bytes >> (32 * (addr & 1));
496 break;
497
498 case R_STATS_RXL:
499 case R_STATS_RXH:
500 r = s->stats.rx >> (32 * (addr & 1));
501 break;
502 case R_STATS_RX_BCASTL:
503 case R_STATS_RX_BCASTH:
504 r = s->stats.rx_bcast >> (32 * (addr & 1));
505 break;
506 case R_STATS_RX_MCASTL:
507 case R_STATS_RX_MCASTH:
508 r = s->stats.rx_mcast >> (32 * (addr & 1));
509 break;
510
511 case R_MC:
512 case R_MWD:
513 case R_MRD:
514 r = s->mii.regs[addr & 3];
515 break;
516
517 case R_UAW0:
518 case R_UAW1:
519 r = s->uaw[addr & 1];
520 break;
521
522 case R_UAWU:
523 case R_UAWL:
524 r = s->ext_uaw[addr & 1];
525 break;
526
527 case R_FMI:
528 r = s->fmi;
529 break;
530
531 case R_AF0:
532 case R_AF1:
533 r = s->maddr[s->fmi & 3][addr & 1];
534 break;
535
536 case 0x8000 ... 0x83ff:
537 r = s->ext_mtable[addr - 0x8000];
538 break;
539
540 default:
541 if (addr < ARRAY_SIZE(s->regs)) {
542 r = s->regs[addr];
543 }
544 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
545 __func__, addr * 4, r));
546 break;
547 }
548 return r;
549 }
550
551 static void enet_write(void *opaque, hwaddr addr,
552 uint64_t value, unsigned size)
553 {
554 XilinxAXIEnet *s = opaque;
555 struct TEMAC *t = &s->TEMAC;
556
557 addr >>= 2;
558 switch (addr) {
559 case R_RCW0:
560 case R_RCW1:
561 s->rcw[addr & 1] = value;
562 if ((addr & 1) && value & RCW1_RST) {
563 axienet_rx_reset(s);
564 } else {
565 qemu_flush_queued_packets(qemu_get_queue(s->nic));
566 }
567 break;
568
569 case R_TC:
570 s->tc = value;
571 if (value & TC_RST) {
572 axienet_tx_reset(s);
573 }
574 break;
575
576 case R_EMMC:
577 s->emmc = value;
578 break;
579
580 case R_PHYC:
581 s->phyc = value;
582 break;
583
584 case R_MC:
585 value &= ((1 << 7) - 1);
586
587 /* Enable the MII. */
588 if (value & MC_EN) {
589 unsigned int miiclkdiv = value & ((1 << 6) - 1);
590 if (!miiclkdiv) {
591 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
592 }
593 }
594 s->mii.mc = value;
595 break;
596
597 case R_MCR: {
598 unsigned int phyaddr = (value >> 24) & 0x1f;
599 unsigned int regaddr = (value >> 16) & 0x1f;
600 unsigned int op = (value >> 14) & 3;
601 unsigned int initiate = (value >> 11) & 1;
602
603 if (initiate) {
604 if (op == 1) {
605 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
606 } else if (op == 2) {
607 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
608 } else {
609 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
610 }
611 }
612 s->mii.mcr = value;
613 break;
614 }
615
616 case R_MWD:
617 case R_MRD:
618 s->mii.regs[addr & 3] = value;
619 break;
620
621
622 case R_UAW0:
623 case R_UAW1:
624 s->uaw[addr & 1] = value;
625 break;
626
627 case R_UAWL:
628 case R_UAWU:
629 s->ext_uaw[addr & 1] = value;
630 break;
631
632 case R_FMI:
633 s->fmi = value;
634 break;
635
636 case R_AF0:
637 case R_AF1:
638 s->maddr[s->fmi & 3][addr & 1] = value;
639 break;
640
641 case R_IS:
642 s->regs[addr] &= ~value;
643 break;
644
645 case 0x8000 ... 0x83ff:
646 s->ext_mtable[addr - 0x8000] = value;
647 break;
648
649 default:
650 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
651 __func__, addr * 4, (unsigned)value));
652 if (addr < ARRAY_SIZE(s->regs)) {
653 s->regs[addr] = value;
654 }
655 break;
656 }
657 enet_update_irq(s);
658 }
659
660 static const MemoryRegionOps enet_ops = {
661 .read = enet_read,
662 .write = enet_write,
663 .endianness = DEVICE_LITTLE_ENDIAN,
664 };
665
666 static int eth_can_rx(XilinxAXIEnet *s)
667 {
668 /* RX enabled? */
669 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
670 }
671
672 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
673 {
674 int match = 1;
675
676 if (memcmp(buf, &f0, 4)) {
677 match = 0;
678 }
679
680 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
681 match = 0;
682 }
683
684 return match;
685 }
686
687 static void axienet_eth_rx_notify(void *opaque)
688 {
689 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque);
690
691 while (s->rxappsize && stream_can_push(s->tx_control_dev,
692 axienet_eth_rx_notify, s)) {
693 size_t ret = stream_push(s->tx_control_dev,
694 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE
695 - s->rxappsize, s->rxappsize);
696 s->rxappsize -= ret;
697 }
698
699 while (s->rxsize && stream_can_push(s->tx_data_dev,
700 axienet_eth_rx_notify, s)) {
701 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
702 s->rxsize);
703 s->rxsize -= ret;
704 s->rxpos += ret;
705 if (!s->rxsize) {
706 s->regs[R_IS] |= IS_RX_COMPLETE;
707 if (s->need_flush) {
708 s->need_flush = false;
709 qemu_flush_queued_packets(qemu_get_queue(s->nic));
710 }
711 }
712 }
713 enet_update_irq(s);
714 }
715
716 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
717 {
718 XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
719 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
720 0xff, 0xff, 0xff};
721 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
722 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
723 int promisc = s->fmi & (1 << 31);
724 int unicast, broadcast, multicast, ip_multicast = 0;
725 uint32_t csum32;
726 uint16_t csum16;
727 int i;
728
729 DENET(qemu_log("%s: %zd bytes\n", __func__, size));
730
731 if (!eth_can_rx(s)) {
732 s->need_flush = true;
733 return 0;
734 }
735
736 unicast = ~buf[0] & 0x1;
737 broadcast = memcmp(buf, sa_bcast, 6) == 0;
738 multicast = !unicast && !broadcast;
739 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
740 ip_multicast = 1;
741 }
742
743 /* Jumbo or vlan sizes ? */
744 if (!(s->rcw[1] & RCW1_JUM)) {
745 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
746 return size;
747 }
748 }
749
750 /* Basic Address filters. If you want to use the extended filters
751 you'll generally have to place the ethernet mac into promiscuous mode
752 to avoid the basic filtering from dropping most frames. */
753 if (!promisc) {
754 if (unicast) {
755 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
756 return size;
757 }
758 } else {
759 if (broadcast) {
760 /* Broadcast. */
761 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
762 return size;
763 }
764 } else {
765 int drop = 1;
766
767 /* Multicast. */
768 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
769 return size;
770 }
771
772 for (i = 0; i < 4; i++) {
773 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
774 drop = 0;
775 break;
776 }
777 }
778
779 if (drop) {
780 return size;
781 }
782 }
783 }
784 }
785
786 /* Extended mcast filtering enabled? */
787 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
788 if (unicast) {
789 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
790 return size;
791 }
792 } else {
793 if (broadcast) {
794 /* Broadcast. ??? */
795 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
796 return size;
797 }
798 } else {
799 int idx, bit;
800
801 /* Multicast. */
802 if (!memcmp(buf, sa_ipmcast, 3)) {
803 return size;
804 }
805
806 idx = (buf[4] & 0x7f) << 8;
807 idx |= buf[5];
808
809 bit = 1 << (idx & 0x1f);
810 idx >>= 5;
811
812 if (!(s->ext_mtable[idx] & bit)) {
813 return size;
814 }
815 }
816 }
817 }
818
819 if (size < 12) {
820 s->regs[R_IS] |= IS_RX_REJECT;
821 enet_update_irq(s);
822 return -1;
823 }
824
825 if (size > (s->c_rxmem - 4)) {
826 size = s->c_rxmem - 4;
827 }
828
829 memcpy(s->rxmem, buf, size);
830 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */
831
832 if (s->rcw[1] & RCW1_FCS) {
833 size += 4; /* fcs is inband. */
834 }
835
836 app[0] = 5 << 28;
837 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
838 /* Fold it once. */
839 csum32 = (csum32 & 0xffff) + (csum32 >> 16);
840 /* And twice to get rid of possible carries. */
841 csum16 = (csum32 & 0xffff) + (csum32 >> 16);
842 app[3] = csum16;
843 app[4] = size & 0xffff;
844
845 s->stats.rx_bytes += size;
846 s->stats.rx++;
847 if (multicast) {
848 s->stats.rx_mcast++;
849 app[2] |= 1 | (ip_multicast << 1);
850 } else if (broadcast) {
851 s->stats.rx_bcast++;
852 app[2] |= 1 << 3;
853 }
854
855 /* Good frame. */
856 app[2] |= 1 << 6;
857
858 s->rxsize = size;
859 s->rxpos = 0;
860 for (i = 0; i < ARRAY_SIZE(app); ++i) {
861 app[i] = cpu_to_le32(app[i]);
862 }
863 s->rxappsize = CONTROL_PAYLOAD_SIZE;
864 memcpy(s->rxapp, app, s->rxappsize);
865 axienet_eth_rx_notify(s);
866
867 enet_update_irq(s);
868 return size;
869 }
870
871 static size_t
872 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len)
873 {
874 int i;
875 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
876 XilinxAXIEnet *s = cs->enet;
877
878 if (len != CONTROL_PAYLOAD_SIZE) {
879 hw_error("AXI Enet requires %d byte control stream payload\n",
880 (int)CONTROL_PAYLOAD_SIZE);
881 }
882
883 memcpy(s->hdr, buf, len);
884
885 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) {
886 s->hdr[i] = le32_to_cpu(s->hdr[i]);
887 }
888 return len;
889 }
890
891 static size_t
892 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size)
893 {
894 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
895 XilinxAXIEnet *s = ds->enet;
896
897 /* TX enable ? */
898 if (!(s->tc & TC_TX)) {
899 return size;
900 }
901
902 /* Jumbo or vlan sizes ? */
903 if (!(s->tc & TC_JUM)) {
904 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
905 return size;
906 }
907 }
908
909 if (s->hdr[0] & 1) {
910 unsigned int start_off = s->hdr[1] >> 16;
911 unsigned int write_off = s->hdr[1] & 0xffff;
912 uint32_t tmp_csum;
913 uint16_t csum;
914
915 tmp_csum = net_checksum_add(size - start_off,
916 (uint8_t *)buf + start_off);
917 /* Accumulate the seed. */
918 tmp_csum += s->hdr[2] & 0xffff;
919
920 /* Fold the 32bit partial checksum. */
921 csum = net_checksum_finish(tmp_csum);
922
923 /* Writeback. */
924 buf[write_off] = csum >> 8;
925 buf[write_off + 1] = csum & 0xff;
926 }
927
928 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
929
930 s->stats.tx_bytes += size;
931 s->regs[R_IS] |= IS_TX_COMPLETE;
932 enet_update_irq(s);
933
934 return size;
935 }
936
937 static NetClientInfo net_xilinx_enet_info = {
938 .type = NET_CLIENT_OPTIONS_KIND_NIC,
939 .size = sizeof(NICState),
940 .receive = eth_rx,
941 };
942
943 static void xilinx_enet_realize(DeviceState *dev, Error **errp)
944 {
945 XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
946 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
947 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
948 &s->rx_control_dev);
949 Error *local_err = NULL;
950
951 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
952 (Object **) &ds->enet,
953 object_property_allow_set_link,
954 OBJ_PROP_LINK_UNREF_ON_RELEASE,
955 &local_err);
956 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
957 (Object **) &cs->enet,
958 object_property_allow_set_link,
959 OBJ_PROP_LINK_UNREF_ON_RELEASE,
960 &local_err);
961 if (local_err) {
962 goto xilinx_enet_realize_fail;
963 }
964 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err);
965 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err);
966 if (local_err) {
967 goto xilinx_enet_realize_fail;
968 }
969
970 qemu_macaddr_default_if_unset(&s->conf.macaddr);
971 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
972 object_get_typename(OBJECT(dev)), dev->id, s);
973 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
974
975 tdk_init(&s->TEMAC.phy);
976 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
977
978 s->TEMAC.parent = s;
979
980 s->rxmem = g_malloc(s->c_rxmem);
981 return;
982
983 xilinx_enet_realize_fail:
984 if (!*errp) {
985 *errp = local_err;
986 }
987 }
988
989 static void xilinx_enet_init(Object *obj)
990 {
991 XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
992 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
993
994 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
995 (Object **) &s->tx_data_dev,
996 qdev_prop_allow_set_link_before_realize,
997 OBJ_PROP_LINK_UNREF_ON_RELEASE,
998 &error_abort);
999 object_property_add_link(obj, "axistream-control-connected",
1000 TYPE_STREAM_SLAVE,
1001 (Object **) &s->tx_control_dev,
1002 qdev_prop_allow_set_link_before_realize,
1003 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1004 &error_abort);
1005
1006 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
1007 TYPE_XILINX_AXI_ENET_DATA_STREAM);
1008 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
1009 TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
1010 object_property_add_child(OBJECT(s), "axistream-connected-target",
1011 (Object *)&s->rx_data_dev, &error_abort);
1012 object_property_add_child(OBJECT(s), "axistream-control-connected-target",
1013 (Object *)&s->rx_control_dev, &error_abort);
1014
1015 sysbus_init_irq(sbd, &s->irq);
1016
1017 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
1018 sysbus_init_mmio(sbd, &s->iomem);
1019 }
1020
1021 static Property xilinx_enet_properties[] = {
1022 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
1023 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
1024 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
1025 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
1026 DEFINE_PROP_END_OF_LIST(),
1027 };
1028
1029 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
1030 {
1031 DeviceClass *dc = DEVICE_CLASS(klass);
1032
1033 dc->realize = xilinx_enet_realize;
1034 dc->props = xilinx_enet_properties;
1035 dc->reset = xilinx_axienet_reset;
1036 }
1037
1038 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
1039 {
1040 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
1041
1042 ssc->push = data;
1043 }
1044
1045 static const TypeInfo xilinx_enet_info = {
1046 .name = TYPE_XILINX_AXI_ENET,
1047 .parent = TYPE_SYS_BUS_DEVICE,
1048 .instance_size = sizeof(XilinxAXIEnet),
1049 .class_init = xilinx_enet_class_init,
1050 .instance_init = xilinx_enet_init,
1051 };
1052
1053 static const TypeInfo xilinx_enet_data_stream_info = {
1054 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
1055 .parent = TYPE_OBJECT,
1056 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1057 .class_init = xilinx_enet_stream_class_init,
1058 .class_data = xilinx_axienet_data_stream_push,
1059 .interfaces = (InterfaceInfo[]) {
1060 { TYPE_STREAM_SLAVE },
1061 { }
1062 }
1063 };
1064
1065 static const TypeInfo xilinx_enet_control_stream_info = {
1066 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
1067 .parent = TYPE_OBJECT,
1068 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1069 .class_init = xilinx_enet_stream_class_init,
1070 .class_data = xilinx_axienet_control_stream_push,
1071 .interfaces = (InterfaceInfo[]) {
1072 { TYPE_STREAM_SLAVE },
1073 { }
1074 }
1075 };
1076
1077 static void xilinx_enet_register_types(void)
1078 {
1079 type_register_static(&xilinx_enet_info);
1080 type_register_static(&xilinx_enet_data_stream_info);
1081 type_register_static(&xilinx_enet_control_stream_info);
1082 }
1083
1084 type_init(xilinx_enet_register_types)
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