hw/net/etraxfs_eth.c

   1 /*
   2  * QEMU ETRAX Ethernet Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "net/net.h"
  28 #include "hw/cris/etraxfs.h"
  29 #include "qemu/error-report.h"
  30
  31 #define D(x)
  32
  33 /* Advertisement control register. */
  34 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  35 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  36 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  37 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  38
  39 /*
  40  * The MDIO extensions in the TDK PHY model were reversed engineered from the
  41  * linux driver (PHYID and Diagnostics reg).
  42  * TODO: Add friendly names for the register nums.
  43  */
  44 struct qemu_phy
  45 {
  46     uint32_t regs[32];
  47
  48     int link;
  49
  50     unsigned int (*read)(struct qemu_phy *phy, unsigned int req);
  51     void (*write)(struct qemu_phy *phy, unsigned int req, unsigned int data);
  52 };
  53
  54 static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
  55 {
  56     int regnum;
  57     unsigned r = 0;
  58
  59     regnum = req & 0x1f;
  60
  61     switch (regnum) {
  62     case 1:
  63         if (!phy->link) {
  64             break;
  65         }
  66         /* MR1.     */
  67         /* Speeds and modes.  */
  68         r |= (1 << 13) | (1 << 14);
  69         r |= (1 << 11) | (1 << 12);
  70         r |= (1 << 5); /* Autoneg complete.  */
  71         r |= (1 << 3); /* Autoneg able.     */
  72         r |= (1 << 2); /* link.     */
  73         break;
  74     case 5:
  75         /* Link partner ability.
  76            We are kind; always agree with whatever best mode
  77            the guest advertises.  */
  78         r = 1 << 14; /* Success.  */
  79         /* Copy advertised modes.  */
  80         r |= phy->regs[4] & (15 << 5);
  81         /* Autoneg support.  */
  82         r |= 1;
  83         break;
  84     case 18:
  85     {
  86         /* Diagnostics reg.  */
  87         int duplex = 0;
  88         int speed_100 = 0;
  89
  90         if (!phy->link) {
  91             break;
  92         }
  93
  94         /* Are we advertising 100 half or 100 duplex ? */
  95         speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
  96         speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
  97
  98         /* Are we advertising 10 duplex or 100 duplex ? */
  99         duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
 100         duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
 101         r = (speed_100 << 10) | (duplex << 11);
 102     }
 103     break;
 104
 105     default:
 106         r = phy->regs[regnum];
 107         break;
 108     }
 109     D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
 110     return r;
 111 }
 112
 113 static void
 114 tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
 115 {
 116     int regnum;
 117
 118     regnum = req & 0x1f;
 119     D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
 120     switch (regnum) {
 121     default:
 122         phy->regs[regnum] = data;
 123         break;
 124     }
 125 }
 126
 127 static void
 128 tdk_init(struct qemu_phy *phy)
 129 {
 130     phy->regs[0] = 0x3100;
 131     /* PHY Id.  */
 132     phy->regs[2] = 0x0300;
 133     phy->regs[3] = 0xe400;
 134     /* Autonegotiation advertisement reg.  */
 135     phy->regs[4] = 0x01E1;
 136     phy->link = 1;
 137
 138     phy->read = tdk_read;
 139     phy->write = tdk_write;
 140 }
 141
 142 struct qemu_mdio
 143 {
 144     /* bus.     */
 145     int mdc;
 146     int mdio;
 147
 148     /* decoder.  */
 149     enum {
 150         PREAMBLE,
 151         SOF,
 152         OPC,
 153         ADDR,
 154         REQ,
 155         TURNAROUND,
 156         DATA
 157     } state;
 158     unsigned int drive;
 159
 160     unsigned int cnt;
 161     unsigned int addr;
 162     unsigned int opc;
 163     unsigned int req;
 164     unsigned int data;
 165
 166     struct qemu_phy *devs[32];
 167 };
 168
 169 static void
 170 mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
 171 {
 172     bus->devs[addr & 0x1f] = phy;
 173 }
 174
 175 #ifdef USE_THIS_DEAD_CODE
 176 static void
 177 mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
 178 {
 179     bus->devs[addr & 0x1f] = NULL;
 180 }
 181 #endif
 182
 183 static void mdio_read_req(struct qemu_mdio *bus)
 184 {
 185     struct qemu_phy *phy;
 186
 187     phy = bus->devs[bus->addr];
 188     if (phy && phy->read) {
 189         bus->data = phy->read(phy, bus->req);
 190     } else {
 191         bus->data = 0xffff;
 192     }
 193 }
 194
 195 static void mdio_write_req(struct qemu_mdio *bus)
 196 {
 197     struct qemu_phy *phy;
 198
 199     phy = bus->devs[bus->addr];
 200     if (phy && phy->write) {
 201         phy->write(phy, bus->req, bus->data);
 202     }
 203 }
 204
 205 static void mdio_cycle(struct qemu_mdio *bus)
 206 {
 207     bus->cnt++;
 208
 209     D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
 210         bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
 211 #if 0
 212     if (bus->mdc) {
 213         printf("%d", bus->mdio);
 214     }
 215 #endif
 216     switch (bus->state) {
 217     case PREAMBLE:
 218         if (bus->mdc) {
 219             if (bus->cnt >= (32 * 2) && !bus->mdio) {
 220                 bus->cnt = 0;
 221                 bus->state = SOF;
 222                 bus->data = 0;
 223             }
 224         }
 225         break;
 226     case SOF:
 227         if (bus->mdc) {
 228             if (bus->mdio != 1) {
 229                 printf("WARNING: no SOF\n");
 230             }
 231             if (bus->cnt == 1*2) {
 232                 bus->cnt = 0;
 233                 bus->opc = 0;
 234                 bus->state = OPC;
 235             }
 236         }
 237         break;
 238     case OPC:
 239         if (bus->mdc) {
 240             bus->opc <<= 1;
 241             bus->opc |= bus->mdio & 1;
 242             if (bus->cnt == 2*2) {
 243                 bus->cnt = 0;
 244                 bus->addr = 0;
 245                 bus->state = ADDR;
 246             }
 247         }
 248         break;
 249     case ADDR:
 250         if (bus->mdc) {
 251             bus->addr <<= 1;
 252             bus->addr |= bus->mdio & 1;
 253
 254             if (bus->cnt == 5*2) {
 255                 bus->cnt = 0;
 256                 bus->req = 0;
 257                 bus->state = REQ;
 258             }
 259         }
 260         break;
 261     case REQ:
 262         if (bus->mdc) {
 263             bus->req <<= 1;
 264             bus->req |= bus->mdio & 1;
 265             if (bus->cnt == 5*2) {
 266                 bus->cnt = 0;
 267                 bus->state = TURNAROUND;
 268             }
 269         }
 270         break;
 271     case TURNAROUND:
 272         if (bus->mdc && bus->cnt == 2*2) {
 273             bus->mdio = 0;
 274             bus->cnt = 0;
 275
 276             if (bus->opc == 2) {
 277                 bus->drive = 1;
 278                 mdio_read_req(bus);
 279                 bus->mdio = bus->data & 1;
 280             }
 281             bus->state = DATA;
 282         }
 283         break;
 284     case DATA:
 285         if (!bus->mdc) {
 286             if (bus->drive) {
 287                 bus->mdio = !!(bus->data & (1 << 15));
 288                 bus->data <<= 1;
 289             }
 290         } else {
 291             if (!bus->drive) {
 292                 bus->data <<= 1;
 293                 bus->data |= bus->mdio;
 294             }
 295             if (bus->cnt == 16 * 2) {
 296                 bus->cnt = 0;
 297                 bus->state = PREAMBLE;
 298                 if (!bus->drive) {
 299                     mdio_write_req(bus);
 300                 }
 301                 bus->drive = 0;
 302             }
 303         }
 304         break;
 305     default:
 306         break;
 307     }
 308 }
 309
 310 /* ETRAX-FS Ethernet MAC block starts here.  */
 311
 312 #define RW_MA0_LO      0x00
 313 #define RW_MA0_HI      0x01
 314 #define RW_MA1_LO      0x02
 315 #define RW_MA1_HI      0x03
 316 #define RW_GA_LO      0x04
 317 #define RW_GA_HI      0x05
 318 #define RW_GEN_CTRL      0x06
 319 #define RW_REC_CTRL      0x07
 320 #define RW_TR_CTRL      0x08
 321 #define RW_CLR_ERR      0x09
 322 #define RW_MGM_CTRL      0x0a
 323 #define R_STAT          0x0b
 324 #define FS_ETH_MAX_REGS      0x17
 325
 326 #define TYPE_ETRAX_FS_ETH "etraxfs-eth"
 327 #define ETRAX_FS_ETH(obj) \
 328     OBJECT_CHECK(ETRAXFSEthState, (obj), TYPE_ETRAX_FS_ETH)
 329
 330 typedef struct ETRAXFSEthState
 331 {
 332     SysBusDevice parent_obj;
 333
 334     MemoryRegion mmio;
 335     NICState *nic;
 336     NICConf conf;
 337
 338     /* Two addrs in the filter.  */
 339     uint8_t macaddr[2][6];
 340     uint32_t regs[FS_ETH_MAX_REGS];
 341
 342     union {
 343         void *vdma_out;
 344         struct etraxfs_dma_client *dma_out;
 345     };
 346     union {
 347         void *vdma_in;
 348         struct etraxfs_dma_client *dma_in;
 349     };
 350
 351     /* MDIO bus.  */
 352     struct qemu_mdio mdio_bus;
 353     unsigned int phyaddr;
 354     int duplex_mismatch;
 355
 356     /* PHY.     */
 357     struct qemu_phy phy;
 358 } ETRAXFSEthState;
 359
 360 static void eth_validate_duplex(ETRAXFSEthState *eth)
 361 {
 362     struct qemu_phy *phy;
 363     unsigned int phy_duplex;
 364     unsigned int mac_duplex;
 365     int new_mm = 0;
 366
 367     phy = eth->mdio_bus.devs[eth->phyaddr];
 368     phy_duplex = !!(phy->read(phy, 18) & (1 << 11));
 369     mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
 370
 371     if (mac_duplex != phy_duplex) {
 372         new_mm = 1;
 373     }
 374
 375     if (eth->regs[RW_GEN_CTRL] & 1) {
 376         if (new_mm != eth->duplex_mismatch) {
 377             if (new_mm) {
 378                 printf("HW: WARNING ETH duplex mismatch MAC=%d PHY=%d\n",
 379                        mac_duplex, phy_duplex);
 380             } else {
 381                 printf("HW: ETH duplex ok.\n");
 382             }
 383         }
 384         eth->duplex_mismatch = new_mm;
 385     }
 386 }
 387
 388 static uint64_t
 389 eth_read(void *opaque, hwaddr addr, unsigned int size)
 390 {
 391     ETRAXFSEthState *eth = opaque;
 392     uint32_t r = 0;
 393
 394     addr >>= 2;
 395
 396     switch (addr) {
 397     case R_STAT:
 398         r = eth->mdio_bus.mdio & 1;
 399         break;
 400     default:
 401         r = eth->regs[addr];
 402         D(printf("%s %x\n", __func__, addr * 4));
 403         break;
 404     }
 405     return r;
 406 }
 407
 408 static void eth_update_ma(ETRAXFSEthState *eth, int ma)
 409 {
 410     int reg;
 411     int i = 0;
 412
 413     ma &= 1;
 414
 415     reg = RW_MA0_LO;
 416     if (ma) {
 417         reg = RW_MA1_LO;
 418     }
 419
 420     eth->macaddr[ma][i++] = eth->regs[reg];
 421     eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
 422     eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
 423     eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
 424     eth->macaddr[ma][i++] = eth->regs[reg + 1];
 425     eth->macaddr[ma][i] = eth->regs[reg + 1] >> 8;
 426
 427     D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
 428              eth->macaddr[ma][0], eth->macaddr[ma][1],
 429              eth->macaddr[ma][2], eth->macaddr[ma][3],
 430              eth->macaddr[ma][4], eth->macaddr[ma][5]));
 431 }
 432
 433 static void
 434 eth_write(void *opaque, hwaddr addr,
 435           uint64_t val64, unsigned int size)
 436 {
 437     ETRAXFSEthState *eth = opaque;
 438     uint32_t value = val64;
 439
 440     addr >>= 2;
 441     switch (addr) {
 442     case RW_MA0_LO:
 443     case RW_MA0_HI:
 444         eth->regs[addr] = value;
 445         eth_update_ma(eth, 0);
 446         break;
 447     case RW_MA1_LO:
 448     case RW_MA1_HI:
 449         eth->regs[addr] = value;
 450         eth_update_ma(eth, 1);
 451         break;
 452
 453     case RW_MGM_CTRL:
 454         /* Attach an MDIO/PHY abstraction.  */
 455         if (value & 2) {
 456             eth->mdio_bus.mdio = value & 1;
 457         }
 458         if (eth->mdio_bus.mdc != (value & 4)) {
 459             mdio_cycle(&eth->mdio_bus);
 460             eth_validate_duplex(eth);
 461         }
 462         eth->mdio_bus.mdc = !!(value & 4);
 463         eth->regs[addr] = value;
 464         break;
 465
 466     case RW_REC_CTRL:
 467         eth->regs[addr] = value;
 468         eth_validate_duplex(eth);
 469         break;
 470
 471     default:
 472         eth->regs[addr] = value;
 473         D(printf("%s %x %x\n", __func__, addr, value));
 474         break;
 475     }
 476 }
 477
 478 /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
 479    filter dropping group addresses we have not joined.    The filter has 64
 480    bits (m). The has function is a simple nible xor of the group addr.    */
 481 static int eth_match_groupaddr(ETRAXFSEthState *eth, const unsigned char *sa)
 482 {
 483     unsigned int hsh;
 484     int m_individual = eth->regs[RW_REC_CTRL] & 4;
 485     int match;
 486
 487     /* First bit on the wire of a MAC address signals multicast or
 488        physical address.  */
 489     if (!m_individual && !(sa[0] & 1)) {
 490         return 0;
 491     }
 492
 493     /* Calculate the hash index for the GA registers. */
 494     hsh = 0;
 495     hsh ^= (*sa) & 0x3f;
 496     hsh ^= ((*sa) >> 6) & 0x03;
 497     ++sa;
 498     hsh ^= ((*sa) << 2) & 0x03c;
 499     hsh ^= ((*sa) >> 4) & 0xf;
 500     ++sa;
 501     hsh ^= ((*sa) << 4) & 0x30;
 502     hsh ^= ((*sa) >> 2) & 0x3f;
 503     ++sa;
 504     hsh ^= (*sa) & 0x3f;
 505     hsh ^= ((*sa) >> 6) & 0x03;
 506     ++sa;
 507     hsh ^= ((*sa) << 2) & 0x03c;
 508     hsh ^= ((*sa) >> 4) & 0xf;
 509     ++sa;
 510     hsh ^= ((*sa) << 4) & 0x30;
 511     hsh ^= ((*sa) >> 2) & 0x3f;
 512
 513     hsh &= 63;
 514     if (hsh > 31) {
 515         match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
 516     } else {
 517         match = eth->regs[RW_GA_LO] & (1 << hsh);
 518     }
 519     D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
 520              eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
 521     return match;
 522 }
 523
 524 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 525 {
 526     unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 527     ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
 528     int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
 529     int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
 530     int r_bcast = eth->regs[RW_REC_CTRL] & 8;
 531
 532     if (size < 12) {
 533         return -1;
 534     }
 535
 536     D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
 537          buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
 538          use_ma0, use_ma1, r_bcast));
 539
 540     /* Does the frame get through the address filters?  */
 541     if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
 542         && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
 543         && (!r_bcast || memcmp(buf, sa_bcast, 6))
 544         && !eth_match_groupaddr(eth, buf)) {
 545         return size;
 546     }
 547
 548     /* FIXME: Find another way to pass on the fake csum.  */
 549     etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1);
 550
 551     return size;
 552 }
 553
 554 static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop)
 555 {
 556     ETRAXFSEthState *eth = opaque;
 557
 558     D(printf("%s buf=%p len=%d\n", __func__, buf, len));
 559     qemu_send_packet(qemu_get_queue(eth->nic), buf, len);
 560     return len;
 561 }
 562
 563 static void eth_set_link(NetClientState *nc)
 564 {
 565     ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
 566     D(printf("%s %d\n", __func__, nc->link_down));
 567     eth->phy.link = !nc->link_down;
 568 }
 569
 570 static const MemoryRegionOps eth_ops = {
 571     .read = eth_read,
 572     .write = eth_write,
 573     .endianness = DEVICE_LITTLE_ENDIAN,
 574     .valid = {
 575         .min_access_size = 4,
 576         .max_access_size = 4
 577     }
 578 };
 579
 580 static NetClientInfo net_etraxfs_info = {
 581     .type = NET_CLIENT_DRIVER_NIC,
 582     .size = sizeof(NICState),
 583     .receive = eth_receive,
 584     .link_status_changed = eth_set_link,
 585 };
 586
 587 static int fs_eth_init(SysBusDevice *sbd)
 588 {
 589     DeviceState *dev = DEVICE(sbd);
 590     ETRAXFSEthState *s = ETRAX_FS_ETH(dev);
 591
 592     if (!s->dma_out || !s->dma_in) {
 593         error_report("Unconnected ETRAX-FS Ethernet MAC");
 594         return -1;
 595     }
 596
 597     s->dma_out->client.push = eth_tx_push;
 598     s->dma_out->client.opaque = s;
 599     s->dma_in->client.opaque = s;
 600     s->dma_in->client.pull = NULL;
 601
 602     memory_region_init_io(&s->mmio, OBJECT(dev), &eth_ops, s,
 603                           "etraxfs-eth", 0x5c);
 604     sysbus_init_mmio(sbd, &s->mmio);
 605
 606     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 607     s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
 608                           object_get_typename(OBJECT(s)), dev->id, s);
 609     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 610
 611
 612     tdk_init(&s->phy);
 613     mdio_attach(&s->mdio_bus, &s->phy, s->phyaddr);
 614     return 0;
 615 }
 616
 617 static Property etraxfs_eth_properties[] = {
 618     DEFINE_PROP_UINT32("phyaddr", ETRAXFSEthState, phyaddr, 1),
 619     DEFINE_PROP_PTR("dma_out", ETRAXFSEthState, vdma_out),
 620     DEFINE_PROP_PTR("dma_in", ETRAXFSEthState, vdma_in),
 621     DEFINE_NIC_PROPERTIES(ETRAXFSEthState, conf),
 622     DEFINE_PROP_END_OF_LIST(),
 623 };
 624
 625 static void etraxfs_eth_class_init(ObjectClass *klass, void *data)
 626 {
 627     DeviceClass *dc = DEVICE_CLASS(klass);
 628     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 629
 630     k->init = fs_eth_init;
 631     dc->props = etraxfs_eth_properties;
 632     /* Reason: pointer properties "dma_out", "dma_in" */
 633     dc->user_creatable = false;
 634 }
 635
 636 static const TypeInfo etraxfs_eth_info = {
 637     .name          = TYPE_ETRAX_FS_ETH,
 638     .parent        = TYPE_SYS_BUS_DEVICE,
 639     .instance_size = sizeof(ETRAXFSEthState),
 640     .class_init    = etraxfs_eth_class_init,
 641 };
 642
 643 static void etraxfs_eth_register_types(void)
 644 {
 645     type_register_static(&etraxfs_eth_info);
 646 }
 647
 648 type_init(etraxfs_eth_register_types)