find_ram_offset: Align ram_addr_t allocation on long boundaries
[qemu/kevin.git] / hw / cpu / arm11mpcore.c
blobeb244658b902966535e4df09cd0e39b3e6cae385
1 /*
2 * ARM11MPCore internal peripheral emulation.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/cpu/arm11mpcore.h"
13 #include "hw/intc/realview_gic.h"
16 static void mpcore_priv_set_irq(void *opaque, int irq, int level)
18 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
20 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
23 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
25 int i;
26 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
27 DeviceState *gicdev = DEVICE(&s->gic);
28 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
29 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
30 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
32 memory_region_add_subregion(&s->container, 0,
33 sysbus_mmio_get_region(scubusdev, 0));
34 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
35 * at 0x200, 0x300...
37 for (i = 0; i < (s->num_cpu + 1); i++) {
38 hwaddr offset = 0x100 + (i * 0x100);
39 memory_region_add_subregion(&s->container, offset,
40 sysbus_mmio_get_region(gicbusdev, i + 1));
42 /* Add the regions for timer and watchdog for "current CPU" and
43 * for each specific CPU.
45 for (i = 0; i < (s->num_cpu + 1); i++) {
46 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
47 hwaddr offset = 0x600 + i * 0x100;
48 memory_region_add_subregion(&s->container, offset,
49 sysbus_mmio_get_region(timerbusdev, i));
50 memory_region_add_subregion(&s->container, offset + 0x20,
51 sysbus_mmio_get_region(wdtbusdev, i));
53 memory_region_add_subregion(&s->container, 0x1000,
54 sysbus_mmio_get_region(gicbusdev, 0));
55 /* Wire up the interrupt from each watchdog and timer.
56 * For each core the timer is PPI 29 and the watchdog PPI 30.
58 for (i = 0; i < s->num_cpu; i++) {
59 int ppibase = (s->num_irq - 32) + i * 32;
60 sysbus_connect_irq(timerbusdev, i,
61 qdev_get_gpio_in(gicdev, ppibase + 29));
62 sysbus_connect_irq(wdtbusdev, i,
63 qdev_get_gpio_in(gicdev, ppibase + 30));
67 static void mpcore_priv_realize(DeviceState *dev, Error **errp)
69 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
70 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
71 DeviceState *scudev = DEVICE(&s->scu);
72 DeviceState *gicdev = DEVICE(&s->gic);
73 DeviceState *mptimerdev = DEVICE(&s->mptimer);
74 DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
75 Error *err = NULL;
77 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
78 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
79 if (err != NULL) {
80 error_propagate(errp, err);
81 return;
84 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
85 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
86 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
87 if (err != NULL) {
88 error_propagate(errp, err);
89 return;
92 /* Pass through outbound IRQ lines from the GIC */
93 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
95 /* Pass through inbound GPIO lines to the GIC */
96 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
98 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
99 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
100 if (err != NULL) {
101 error_propagate(errp, err);
102 return;
105 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
106 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
107 if (err != NULL) {
108 error_propagate(errp, err);
109 return;
112 mpcore_priv_map_setup(s);
115 static void mpcore_priv_initfn(Object *obj)
117 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
118 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
120 memory_region_init(&s->container, OBJECT(s),
121 "mpcore-priv-container", 0x2000);
122 sysbus_init_mmio(sbd, &s->container);
124 object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
125 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
127 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
128 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
129 /* Request the legacy 11MPCore GIC behaviour: */
130 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
132 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
133 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
135 object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER);
136 qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
139 static Property mpcore_priv_properties[] = {
140 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
141 /* The ARM11 MPCORE TRM says the on-chip controller may have
142 * anything from 0 to 224 external interrupt IRQ lines (with another
143 * 32 internal). We default to 32+32, which is the number provided by
144 * the ARM11 MPCore test chip in the Realview Versatile Express
145 * coretile. Other boards may differ and should set this property
146 * appropriately. Some Linux kernels may not boot if the hardware
147 * has more IRQ lines than the kernel expects.
149 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
150 DEFINE_PROP_END_OF_LIST(),
153 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
155 DeviceClass *dc = DEVICE_CLASS(klass);
157 dc->realize = mpcore_priv_realize;
158 dc->props = mpcore_priv_properties;
161 static const TypeInfo mpcore_priv_info = {
162 .name = TYPE_ARM11MPCORE_PRIV,
163 .parent = TYPE_SYS_BUS_DEVICE,
164 .instance_size = sizeof(ARM11MPCorePriveState),
165 .instance_init = mpcore_priv_initfn,
166 .class_init = mpcore_priv_class_init,
169 static void arm11mpcore_register_types(void)
171 type_register_static(&mpcore_priv_info);
174 type_init(arm11mpcore_register_types)