hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  * Contributions after 2012-01-13 are licensed under the terms of the
  14  * GNU GPL, version 2 or (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "msix.h"
  19 #include "pci.h"
  20 #include "range.h"
  21
  22 #define MSIX_CAP_LENGTH 12
  23
  24 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  25 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  26 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  27 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  28
  29 /* How much space does an MSIX table need. */
  30 /* The spec requires giving the table structure
  31  * a 4K aligned region all by itself. */
  32 #define MSIX_PAGE_SIZE 0x1000
  33 /* Reserve second half of the page for pending bits */
  34 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  35 #define MSIX_MAX_ENTRIES 32
  36
  37
  38 /* Flag for interrupt controller to declare MSI-X support */
  39 int msix_supported;
  40
  41 /* Add MSI-X capability to the config space for the device. */
  42 /* Given a bar and its size, add MSI-X table on top of it
  43  * and fill MSI-X capability in the config space.
  44  * Original bar size must be a power of 2 or 0.
  45  * New bar size is returned. */
  46 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
  47                            unsigned bar_nr, unsigned bar_size)
  48 {
  49     int config_offset;
  50     uint8_t *config;
  51     uint32_t new_size;
  52
  53     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
  54         return -EINVAL;
  55     if (bar_size > 0x80000000)
  56         return -ENOSPC;
  57
  58     /* Add space for MSI-X structures */
  59     if (!bar_size) {
  60         new_size = MSIX_PAGE_SIZE;
  61     } else if (bar_size < MSIX_PAGE_SIZE) {
  62         bar_size = MSIX_PAGE_SIZE;
  63         new_size = MSIX_PAGE_SIZE * 2;
  64     } else {
  65         new_size = bar_size * 2;
  66     }
  67
  68     pdev->msix_bar_size = new_size;
  69     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
  70                                        0, MSIX_CAP_LENGTH);
  71     if (config_offset < 0)
  72         return config_offset;
  73     config = pdev->config + config_offset;
  74
  75     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
  76     /* Table on top of BAR */
  77     pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
  78     /* Pending bits on top of that */
  79     pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
  80                  bar_nr);
  81     pdev->msix_cap = config_offset;
  82     /* Make flags bit writable. */
  83     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
  84             MSIX_MASKALL_MASK;
  85     pdev->msix_function_masked = true;
  86     return 0;
  87 }
  88
  89 static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
  90                                unsigned size)
  91 {
  92     PCIDevice *dev = opaque;
  93     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
  94     void *page = dev->msix_table_page;
  95
  96     return pci_get_long(page + offset);
  97 }
  98
  99 static uint8_t msix_pending_mask(int vector)
 100 {
 101     return 1 << (vector % 8);
 102 }
 103
 104 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 105 {
 106     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 107 }
 108
 109 static int msix_is_pending(PCIDevice *dev, int vector)
 110 {
 111     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 112 }
 113
 114 static void msix_set_pending(PCIDevice *dev, int vector)
 115 {
 116     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 117 }
 118
 119 static void msix_clr_pending(PCIDevice *dev, int vector)
 120 {
 121     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 122 }
 123
 124 static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
 125 {
 126     unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 127     return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
 128 }
 129
 130 static bool msix_is_masked(PCIDevice *dev, int vector)
 131 {
 132     return msix_vector_masked(dev, vector, dev->msix_function_masked);
 133 }
 134
 135 static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
 136 {
 137     bool is_masked = msix_is_masked(dev, vector);
 138     if (is_masked == was_masked) {
 139         return;
 140     }
 141
 142     if (!is_masked && msix_is_pending(dev, vector)) {
 143         msix_clr_pending(dev, vector);
 144         msix_notify(dev, vector);
 145     }
 146 }
 147
 148 static void msix_update_function_masked(PCIDevice *dev)
 149 {
 150     dev->msix_function_masked = !msix_enabled(dev) ||
 151         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
 152 }
 153
 154 /* Handle MSI-X capability config write. */
 155 void msix_write_config(PCIDevice *dev, uint32_t addr,
 156                        uint32_t val, int len)
 157 {
 158     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 159     int vector;
 160     bool was_masked;
 161
 162     if (!range_covers_byte(addr, len, enable_pos)) {
 163         return;
 164     }
 165
 166     was_masked = dev->msix_function_masked;
 167     msix_update_function_masked(dev);
 168
 169     if (!msix_enabled(dev)) {
 170         return;
 171     }
 172
 173     pci_device_deassert_intx(dev);
 174
 175     if (dev->msix_function_masked == was_masked) {
 176         return;
 177     }
 178
 179     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 180         msix_handle_mask_update(dev, vector,
 181                                 msix_vector_masked(dev, vector, was_masked));
 182     }
 183 }
 184
 185 static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
 186                             uint64_t val, unsigned size)
 187 {
 188     PCIDevice *dev = opaque;
 189     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 190     int vector = offset / PCI_MSIX_ENTRY_SIZE;
 191     bool was_masked;
 192
 193     /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
 194     if (vector >= dev->msix_entries_nr) {
 195         return;
 196     }
 197
 198     was_masked = msix_is_masked(dev, vector);
 199     pci_set_long(dev->msix_table_page + offset, val);
 200     msix_handle_mask_update(dev, vector, was_masked);
 201 }
 202
 203 static const MemoryRegionOps msix_mmio_ops = {
 204     .read = msix_mmio_read,
 205     .write = msix_mmio_write,
 206     .endianness = DEVICE_NATIVE_ENDIAN,
 207     .valid = {
 208         .min_access_size = 4,
 209         .max_access_size = 4,
 210     },
 211 };
 212
 213 static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
 214 {
 215     uint8_t *config = d->config + d->msix_cap;
 216     uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
 217     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 218     /* TODO: for assigned devices, we'll want to make it possible to map
 219      * pending bits separately in case they are in a separate bar. */
 220
 221     memory_region_add_subregion(bar, offset, &d->msix_mmio);
 222 }
 223
 224 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 225 {
 226     int vector;
 227     for (vector = 0; vector < nentries; ++vector) {
 228         unsigned offset =
 229             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 230         dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 231     }
 232 }
 233
 234 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 235  * modified, it should be retrieved with msix_bar_size. */
 236 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 237               MemoryRegion *bar,
 238               unsigned bar_nr, unsigned bar_size)
 239 {
 240     int ret;
 241     /* Nothing to do if MSI is not supported by interrupt controller */
 242     if (!msix_supported)
 243         return -ENOTSUP;
 244
 245     if (nentries > MSIX_MAX_ENTRIES)
 246         return -EINVAL;
 247
 248     dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
 249                                         sizeof *dev->msix_entry_used);
 250
 251     dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
 252     msix_mask_all(dev, nentries);
 253
 254     memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
 255                           "msix", MSIX_PAGE_SIZE);
 256
 257     dev->msix_entries_nr = nentries;
 258     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 259     if (ret)
 260         goto err_config;
 261
 262     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 263     msix_mmio_setup(dev, bar);
 264     return 0;
 265
 266 err_config:
 267     dev->msix_entries_nr = 0;
 268     memory_region_destroy(&dev->msix_mmio);
 269     g_free(dev->msix_table_page);
 270     dev->msix_table_page = NULL;
 271     g_free(dev->msix_entry_used);
 272     dev->msix_entry_used = NULL;
 273     return ret;
 274 }
 275
 276 static void msix_free_irq_entries(PCIDevice *dev)
 277 {
 278     int vector;
 279
 280     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 281         dev->msix_entry_used[vector] = 0;
 282         msix_clr_pending(dev, vector);
 283     }
 284 }
 285
 286 /* Clean up resources for the device. */
 287 int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
 288 {
 289     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 290         return 0;
 291     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 292     dev->msix_cap = 0;
 293     msix_free_irq_entries(dev);
 294     dev->msix_entries_nr = 0;
 295     memory_region_del_subregion(bar, &dev->msix_mmio);
 296     memory_region_destroy(&dev->msix_mmio);
 297     g_free(dev->msix_table_page);
 298     dev->msix_table_page = NULL;
 299     g_free(dev->msix_entry_used);
 300     dev->msix_entry_used = NULL;
 301     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 302     return 0;
 303 }
 304
 305 void msix_save(PCIDevice *dev, QEMUFile *f)
 306 {
 307     unsigned n = dev->msix_entries_nr;
 308
 309     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 310         return;
 311     }
 312
 313     qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 314     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 315 }
 316
 317 /* Should be called after restoring the config space. */
 318 void msix_load(PCIDevice *dev, QEMUFile *f)
 319 {
 320     unsigned n = dev->msix_entries_nr;
 321
 322     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 323         return;
 324     }
 325
 326     msix_free_irq_entries(dev);
 327     qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 328     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 329     msix_update_function_masked(dev);
 330 }
 331
 332 /* Does device support MSI-X? */
 333 int msix_present(PCIDevice *dev)
 334 {
 335     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 336 }
 337
 338 /* Is MSI-X enabled? */
 339 int msix_enabled(PCIDevice *dev)
 340 {
 341     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 342         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 343          MSIX_ENABLE_MASK);
 344 }
 345
 346 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 347 uint32_t msix_bar_size(PCIDevice *dev)
 348 {
 349     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 350         dev->msix_bar_size : 0;
 351 }
 352
 353 /* Send an MSI-X message */
 354 void msix_notify(PCIDevice *dev, unsigned vector)
 355 {
 356     uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
 357     uint64_t address;
 358     uint32_t data;
 359
 360     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 361         return;
 362     if (msix_is_masked(dev, vector)) {
 363         msix_set_pending(dev, vector);
 364         return;
 365     }
 366
 367     address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
 368     data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
 369     stl_le_phys(address, data);
 370 }
 371
 372 void msix_reset(PCIDevice *dev)
 373 {
 374     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 375         return;
 376     msix_free_irq_entries(dev);
 377     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 378             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 379     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 380     msix_mask_all(dev, dev->msix_entries_nr);
 381 }
 382
 383 /* PCI spec suggests that devices make it possible for software to configure
 384  * less vectors than supported by the device, but does not specify a standard
 385  * mechanism for devices to do so.
 386  *
 387  * We support this by asking devices to declare vectors software is going to
 388  * actually use, and checking this on the notification path. Devices that
 389  * don't want to follow the spec suggestion can declare all vectors as used. */
 390
 391 /* Mark vector as used. */
 392 int msix_vector_use(PCIDevice *dev, unsigned vector)
 393 {
 394     if (vector >= dev->msix_entries_nr)
 395         return -EINVAL;
 396     dev->msix_entry_used[vector]++;
 397     return 0;
 398 }
 399
 400 /* Mark vector as unused. */
 401 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 402 {
 403     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 404         return;
 405     }
 406     if (--dev->msix_entry_used[vector]) {
 407         return;
 408     }
 409     msix_clr_pending(dev, vector);
 410 }
 411
 412 void msix_unuse_all_vectors(PCIDevice *dev)
 413 {
 414     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 415         return;
 416     msix_free_irq_entries(dev);
 417 }