hw/ssi/imx_spi.c

   1 /*
   2  * IMX SPI Controller
   3  *
   4  * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "hw/irq.h"
  13 #include "hw/ssi/imx_spi.h"
  14 #include "migration/vmstate.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17
  18 #ifndef DEBUG_IMX_SPI
  19 #define DEBUG_IMX_SPI 0
  20 #endif
  21
  22 #define DPRINTF(fmt, args...) \
  23     do { \
  24         if (DEBUG_IMX_SPI) { \
  25             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
  26                                              __func__, ##args); \
  27         } \
  28     } while (0)
  29
  30 static const char *imx_spi_reg_name(uint32_t reg)
  31 {
  32     static char unknown[20];
  33
  34     switch (reg) {
  35     case ECSPI_RXDATA:
  36         return  "ECSPI_RXDATA";
  37     case ECSPI_TXDATA:
  38         return  "ECSPI_TXDATA";
  39     case ECSPI_CONREG:
  40         return  "ECSPI_CONREG";
  41     case ECSPI_CONFIGREG:
  42         return  "ECSPI_CONFIGREG";
  43     case ECSPI_INTREG:
  44         return  "ECSPI_INTREG";
  45     case ECSPI_DMAREG:
  46         return  "ECSPI_DMAREG";
  47     case ECSPI_STATREG:
  48         return  "ECSPI_STATREG";
  49     case ECSPI_PERIODREG:
  50         return  "ECSPI_PERIODREG";
  51     case ECSPI_TESTREG:
  52         return  "ECSPI_TESTREG";
  53     case ECSPI_MSGDATA:
  54         return  "ECSPI_MSGDATA";
  55     default:
  56         sprintf(unknown, "%u ?", reg);
  57         return unknown;
  58     }
  59 }
  60
  61 static const VMStateDescription vmstate_imx_spi = {
  62     .name = TYPE_IMX_SPI,
  63     .version_id = 1,
  64     .minimum_version_id = 1,
  65     .fields = (VMStateField[]) {
  66         VMSTATE_FIFO32(tx_fifo, IMXSPIState),
  67         VMSTATE_FIFO32(rx_fifo, IMXSPIState),
  68         VMSTATE_INT16(burst_length, IMXSPIState),
  69         VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
  70         VMSTATE_END_OF_LIST()
  71     },
  72 };
  73
  74 static void imx_spi_txfifo_reset(IMXSPIState *s)
  75 {
  76     fifo32_reset(&s->tx_fifo);
  77     s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
  78     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
  79 }
  80
  81 static void imx_spi_rxfifo_reset(IMXSPIState *s)
  82 {
  83     fifo32_reset(&s->rx_fifo);
  84     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
  85     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
  86     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
  87 }
  88
  89 static void imx_spi_update_irq(IMXSPIState *s)
  90 {
  91     int level;
  92
  93     if (fifo32_is_empty(&s->rx_fifo)) {
  94         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
  95     } else {
  96         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
  97     }
  98
  99     if (fifo32_is_full(&s->rx_fifo)) {
 100         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
 101     } else {
 102         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
 103     }
 104
 105     if (fifo32_is_empty(&s->tx_fifo)) {
 106         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
 107     } else {
 108         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
 109     }
 110
 111     if (fifo32_is_full(&s->tx_fifo)) {
 112         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
 113     } else {
 114         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
 115     }
 116
 117     level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
 118
 119     qemu_set_irq(s->irq, level);
 120
 121     DPRINTF("IRQ level is %d\n", level);
 122 }
 123
 124 static uint8_t imx_spi_selected_channel(IMXSPIState *s)
 125 {
 126     return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
 127 }
 128
 129 static uint32_t imx_spi_burst_length(IMXSPIState *s)
 130 {
 131     return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
 132 }
 133
 134 static bool imx_spi_is_enabled(IMXSPIState *s)
 135 {
 136     return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
 137 }
 138
 139 static bool imx_spi_channel_is_master(IMXSPIState *s)
 140 {
 141     uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
 142
 143     return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
 144 }
 145
 146 static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
 147 {
 148     uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
 149
 150     return imx_spi_channel_is_master(s) &&
 151            !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
 152            ((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
 153 }
 154
 155 static void imx_spi_flush_txfifo(IMXSPIState *s)
 156 {
 157     uint32_t tx;
 158     uint32_t rx;
 159
 160     DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
 161             fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
 162
 163     while (!fifo32_is_empty(&s->tx_fifo)) {
 164         int tx_burst = 0;
 165         int index = 0;
 166
 167         if (s->burst_length <= 0) {
 168             s->burst_length = imx_spi_burst_length(s);
 169
 170             DPRINTF("Burst length = %d\n", s->burst_length);
 171
 172             if (imx_spi_is_multiple_master_burst(s)) {
 173                 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
 174             }
 175         }
 176
 177         tx = fifo32_pop(&s->tx_fifo);
 178
 179         DPRINTF("data tx:0x%08x\n", tx);
 180
 181         tx_burst = MIN(s->burst_length, 32);
 182
 183         rx = 0;
 184
 185         while (tx_burst > 0) {
 186             uint8_t byte = tx & 0xff;
 187
 188             DPRINTF("writing 0x%02x\n", (uint32_t)byte);
 189
 190             /* We need to write one byte at a time */
 191             byte = ssi_transfer(s->bus, byte);
 192
 193             DPRINTF("0x%02x read\n", (uint32_t)byte);
 194
 195             tx = tx >> 8;
 196             rx |= (byte << (index * 8));
 197
 198             /* Remove 8 bits from the actual burst */
 199             tx_burst -= 8;
 200             s->burst_length -= 8;
 201             index++;
 202         }
 203
 204         DPRINTF("data rx:0x%08x\n", rx);
 205
 206         if (fifo32_is_full(&s->rx_fifo)) {
 207             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
 208         } else {
 209             fifo32_push(&s->rx_fifo, rx);
 210         }
 211
 212         if (s->burst_length <= 0) {
 213             if (!imx_spi_is_multiple_master_burst(s)) {
 214                 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
 215                 break;
 216             }
 217         }
 218     }
 219
 220     if (fifo32_is_empty(&s->tx_fifo)) {
 221         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
 222         s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
 223     }
 224
 225     /* TODO: We should also use TDR and RDR bits */
 226
 227     DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
 228             fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
 229 }
 230
 231 static void imx_spi_common_reset(IMXSPIState *s)
 232 {
 233     int i;
 234
 235     for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
 236         switch (i) {
 237         case ECSPI_CONREG:
 238             /* CONREG is not updated on soft reset */
 239             break;
 240         case ECSPI_STATREG:
 241             s->regs[i] = 0x00000003;
 242             break;
 243         default:
 244             s->regs[i] = 0;
 245             break;
 246         }
 247     }
 248
 249     imx_spi_rxfifo_reset(s);
 250     imx_spi_txfifo_reset(s);
 251
 252     s->burst_length = 0;
 253 }
 254
 255 static void imx_spi_soft_reset(IMXSPIState *s)
 256 {
 257     imx_spi_common_reset(s);
 258
 259     imx_spi_update_irq(s);
 260 }
 261
 262 static void imx_spi_reset(DeviceState *dev)
 263 {
 264     IMXSPIState *s = IMX_SPI(dev);
 265
 266     imx_spi_common_reset(s);
 267     s->regs[ECSPI_CONREG] = 0;
 268 }
 269
 270 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
 271 {
 272     uint32_t value = 0;
 273     IMXSPIState *s = opaque;
 274     uint32_t index = offset >> 2;
 275
 276     if (index >=  ECSPI_MAX) {
 277         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 278                       HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
 279         return 0;
 280     }
 281
 282     value = s->regs[index];
 283
 284     if (imx_spi_is_enabled(s)) {
 285         switch (index) {
 286         case ECSPI_RXDATA:
 287             if (fifo32_is_empty(&s->rx_fifo)) {
 288                 /* value is undefined */
 289                 value = 0xdeadbeef;
 290             } else {
 291                 /* read from the RX FIFO */
 292                 value = fifo32_pop(&s->rx_fifo);
 293             }
 294             break;
 295         case ECSPI_TXDATA:
 296             qemu_log_mask(LOG_GUEST_ERROR,
 297                           "[%s]%s: Trying to read from TX FIFO\n",
 298                           TYPE_IMX_SPI, __func__);
 299
 300             /* Reading from TXDATA gives 0 */
 301             break;
 302         case ECSPI_MSGDATA:
 303             qemu_log_mask(LOG_GUEST_ERROR,
 304                           "[%s]%s: Trying to read from MSG FIFO\n",
 305                           TYPE_IMX_SPI, __func__);
 306             /* Reading from MSGDATA gives 0 */
 307             break;
 308         default:
 309             break;
 310         }
 311
 312         imx_spi_update_irq(s);
 313     }
 314     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
 315
 316     return (uint64_t)value;
 317 }
 318
 319 static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
 320                            unsigned size)
 321 {
 322     IMXSPIState *s = opaque;
 323     uint32_t index = offset >> 2;
 324     uint32_t change_mask;
 325
 326     if (index >=  ECSPI_MAX) {
 327         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 328                       HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
 329         return;
 330     }
 331
 332     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
 333             (uint32_t)value);
 334
 335     change_mask = s->regs[index] ^ value;
 336
 337     switch (index) {
 338     case ECSPI_RXDATA:
 339         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
 340                       TYPE_IMX_SPI, __func__);
 341         break;
 342     case ECSPI_TXDATA:
 343         if (!imx_spi_is_enabled(s)) {
 344             /* Ignore writes if device is disabled */
 345             break;
 346         } else if (fifo32_is_full(&s->tx_fifo)) {
 347             /* Ignore writes if queue is full */
 348             break;
 349         }
 350
 351         fifo32_push(&s->tx_fifo, (uint32_t)value);
 352
 353         if (imx_spi_channel_is_master(s) &&
 354             (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
 355             /*
 356              * Start emitting if current channel is master and SMC bit is
 357              * set.
 358              */
 359             imx_spi_flush_txfifo(s);
 360         }
 361
 362         break;
 363     case ECSPI_STATREG:
 364         /* the RO and TC bits are write-one-to-clear */
 365         value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
 366         s->regs[ECSPI_STATREG] &= ~value;
 367
 368         break;
 369     case ECSPI_CONREG:
 370         s->regs[ECSPI_CONREG] = value;
 371
 372         if (!imx_spi_is_enabled(s)) {
 373             /* device is disabled, so this is a soft reset */
 374             imx_spi_soft_reset(s);
 375
 376             return;
 377         }
 378
 379         if (imx_spi_channel_is_master(s)) {
 380             int i;
 381
 382             /* We are in master mode */
 383
 384             for (i = 0; i < ECSPI_NUM_CS; i++) {
 385                 qemu_set_irq(s->cs_lines[i],
 386                              i == imx_spi_selected_channel(s) ? 0 : 1);
 387             }
 388
 389             if ((value & change_mask & ECSPI_CONREG_SMC) &&
 390                 !fifo32_is_empty(&s->tx_fifo)) {
 391                 /* SMC bit is set and TX FIFO has some slots filled in */
 392                 imx_spi_flush_txfifo(s);
 393             } else if ((value & change_mask & ECSPI_CONREG_XCH) &&
 394                 !(value & ECSPI_CONREG_SMC)) {
 395                 /* This is a request to start emitting */
 396                 imx_spi_flush_txfifo(s);
 397             }
 398         }
 399
 400         break;
 401     case ECSPI_MSGDATA:
 402         /* it is not clear from the spec what MSGDATA is for */
 403         /* Anyway it is not used by Linux driver */
 404         /* So for now we just ignore it */
 405         qemu_log_mask(LOG_UNIMP,
 406                       "[%s]%s: Trying to write to MSGDATA, ignoring\n",
 407                       TYPE_IMX_SPI, __func__);
 408         break;
 409     default:
 410         s->regs[index] = value;
 411
 412         break;
 413     }
 414
 415     imx_spi_update_irq(s);
 416 }
 417
 418 static const struct MemoryRegionOps imx_spi_ops = {
 419     .read = imx_spi_read,
 420     .write = imx_spi_write,
 421     .endianness = DEVICE_NATIVE_ENDIAN,
 422     .valid = {
 423         /*
 424          * Our device would not work correctly if the guest was doing
 425          * unaligned access. This might not be a limitation on the real
 426          * device but in practice there is no reason for a guest to access
 427          * this device unaligned.
 428          */
 429         .min_access_size = 4,
 430         .max_access_size = 4,
 431         .unaligned = false,
 432     },
 433 };
 434
 435 static void imx_spi_realize(DeviceState *dev, Error **errp)
 436 {
 437     IMXSPIState *s = IMX_SPI(dev);
 438     int i;
 439
 440     s->bus = ssi_create_bus(dev, "spi");
 441
 442     memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
 443                           TYPE_IMX_SPI, 0x1000);
 444     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 445     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 446
 447     for (i = 0; i < ECSPI_NUM_CS; ++i) {
 448         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
 449     }
 450
 451     fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
 452     fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
 453 }
 454
 455 static void imx_spi_class_init(ObjectClass *klass, void *data)
 456 {
 457     DeviceClass *dc = DEVICE_CLASS(klass);
 458
 459     dc->realize = imx_spi_realize;
 460     dc->vmsd = &vmstate_imx_spi;
 461     dc->reset = imx_spi_reset;
 462     dc->desc = "i.MX SPI Controller";
 463 }
 464
 465 static const TypeInfo imx_spi_info = {
 466     .name          = TYPE_IMX_SPI,
 467     .parent        = TYPE_SYS_BUS_DEVICE,
 468     .instance_size = sizeof(IMXSPIState),
 469     .class_init    = imx_spi_class_init,
 470 };
 471
 472 static void imx_spi_register_types(void)
 473 {
 474     type_register_static(&imx_spi_info);
 475 }
 476
 477 type_init(imx_spi_register_types)