docker: update qemu:debian base following stretch release
[qemu/kevin.git] / exec.c
blob42ad1eaedd504df4580a407c4c3e8b0cffadc408
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/boards.h"
32 #include "hw/xen/xen.h"
33 #endif
34 #include "sysemu/kvm.h"
35 #include "sysemu/sysemu.h"
36 #include "qemu/timer.h"
37 #include "qemu/config-file.h"
38 #include "qemu/error-report.h"
39 #if defined(CONFIG_USER_ONLY)
40 #include "qemu.h"
41 #else /* !CONFIG_USER_ONLY */
42 #include "hw/hw.h"
43 #include "exec/memory.h"
44 #include "exec/ioport.h"
45 #include "sysemu/dma.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/hw_accel.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace-root.h"
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <fcntl.h>
54 #include <linux/falloc.h>
55 #endif
57 #endif
58 #include "exec/cpu-all.h"
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
66 #include "exec/log.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
71 #ifndef _WIN32
72 #include "qemu/mmap-alloc.h"
73 #endif
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
85 static MemoryRegion *system_memory;
86 static MemoryRegion *system_io;
88 AddressSpace address_space_io;
89 AddressSpace address_space_memory;
91 MemoryRegion io_mem_rom, io_mem_notdirty;
92 static MemoryRegion io_mem_unassigned;
94 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
95 #define RAM_PREALLOC (1 << 0)
97 /* RAM is mmap-ed with MAP_SHARED */
98 #define RAM_SHARED (1 << 1)
100 /* Only a portion of RAM (used_length) is actually used, and migrated.
101 * This used_length size can change across reboots.
103 #define RAM_RESIZEABLE (1 << 2)
105 #endif
107 #ifdef TARGET_PAGE_BITS_VARY
108 int target_page_bits;
109 bool target_page_bits_decided;
110 #endif
112 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
113 /* current CPU in the current thread. It is only valid inside
114 cpu_exec() */
115 __thread CPUState *current_cpu;
116 /* 0 = Do not count executed instructions.
117 1 = Precise instruction counting.
118 2 = Adaptive rate instruction counting. */
119 int use_icount;
121 bool set_preferred_target_page_bits(int bits)
123 /* The target page size is the lowest common denominator for all
124 * the CPUs in the system, so we can only make it smaller, never
125 * larger. And we can't make it smaller once we've committed to
126 * a particular size.
128 #ifdef TARGET_PAGE_BITS_VARY
129 assert(bits >= TARGET_PAGE_BITS_MIN);
130 if (target_page_bits == 0 || target_page_bits > bits) {
131 if (target_page_bits_decided) {
132 return false;
134 target_page_bits = bits;
136 #endif
137 return true;
140 #if !defined(CONFIG_USER_ONLY)
142 static void finalize_target_page_bits(void)
144 #ifdef TARGET_PAGE_BITS_VARY
145 if (target_page_bits == 0) {
146 target_page_bits = TARGET_PAGE_BITS_MIN;
148 target_page_bits_decided = true;
149 #endif
152 typedef struct PhysPageEntry PhysPageEntry;
154 struct PhysPageEntry {
155 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
156 uint32_t skip : 6;
157 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
158 uint32_t ptr : 26;
161 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
163 /* Size of the L2 (and L3, etc) page tables. */
164 #define ADDR_SPACE_BITS 64
166 #define P_L2_BITS 9
167 #define P_L2_SIZE (1 << P_L2_BITS)
169 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
171 typedef PhysPageEntry Node[P_L2_SIZE];
173 typedef struct PhysPageMap {
174 struct rcu_head rcu;
176 unsigned sections_nb;
177 unsigned sections_nb_alloc;
178 unsigned nodes_nb;
179 unsigned nodes_nb_alloc;
180 Node *nodes;
181 MemoryRegionSection *sections;
182 } PhysPageMap;
184 struct AddressSpaceDispatch {
185 struct rcu_head rcu;
187 MemoryRegionSection *mru_section;
188 /* This is a multi-level map on the physical address space.
189 * The bottom level has pointers to MemoryRegionSections.
191 PhysPageEntry phys_map;
192 PhysPageMap map;
193 AddressSpace *as;
196 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
197 typedef struct subpage_t {
198 MemoryRegion iomem;
199 AddressSpace *as;
200 hwaddr base;
201 uint16_t sub_section[];
202 } subpage_t;
204 #define PHYS_SECTION_UNASSIGNED 0
205 #define PHYS_SECTION_NOTDIRTY 1
206 #define PHYS_SECTION_ROM 2
207 #define PHYS_SECTION_WATCH 3
209 static void io_mem_init(void);
210 static void memory_map_init(void);
211 static void tcg_commit(MemoryListener *listener);
213 static MemoryRegion io_mem_watch;
216 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
217 * @cpu: the CPU whose AddressSpace this is
218 * @as: the AddressSpace itself
219 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
220 * @tcg_as_listener: listener for tracking changes to the AddressSpace
222 struct CPUAddressSpace {
223 CPUState *cpu;
224 AddressSpace *as;
225 struct AddressSpaceDispatch *memory_dispatch;
226 MemoryListener tcg_as_listener;
229 struct DirtyBitmapSnapshot {
230 ram_addr_t start;
231 ram_addr_t end;
232 unsigned long dirty[];
235 #endif
237 #if !defined(CONFIG_USER_ONLY)
239 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
241 static unsigned alloc_hint = 16;
242 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
243 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
244 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
245 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
246 alloc_hint = map->nodes_nb_alloc;
250 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
252 unsigned i;
253 uint32_t ret;
254 PhysPageEntry e;
255 PhysPageEntry *p;
257 ret = map->nodes_nb++;
258 p = map->nodes[ret];
259 assert(ret != PHYS_MAP_NODE_NIL);
260 assert(ret != map->nodes_nb_alloc);
262 e.skip = leaf ? 0 : 1;
263 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
264 for (i = 0; i < P_L2_SIZE; ++i) {
265 memcpy(&p[i], &e, sizeof(e));
267 return ret;
270 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
271 hwaddr *index, hwaddr *nb, uint16_t leaf,
272 int level)
274 PhysPageEntry *p;
275 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
277 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
278 lp->ptr = phys_map_node_alloc(map, level == 0);
280 p = map->nodes[lp->ptr];
281 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
283 while (*nb && lp < &p[P_L2_SIZE]) {
284 if ((*index & (step - 1)) == 0 && *nb >= step) {
285 lp->skip = 0;
286 lp->ptr = leaf;
287 *index += step;
288 *nb -= step;
289 } else {
290 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
292 ++lp;
296 static void phys_page_set(AddressSpaceDispatch *d,
297 hwaddr index, hwaddr nb,
298 uint16_t leaf)
300 /* Wildly overreserve - it doesn't matter much. */
301 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
303 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
306 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
307 * and update our entry so we can skip it and go directly to the destination.
309 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
311 unsigned valid_ptr = P_L2_SIZE;
312 int valid = 0;
313 PhysPageEntry *p;
314 int i;
316 if (lp->ptr == PHYS_MAP_NODE_NIL) {
317 return;
320 p = nodes[lp->ptr];
321 for (i = 0; i < P_L2_SIZE; i++) {
322 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
323 continue;
326 valid_ptr = i;
327 valid++;
328 if (p[i].skip) {
329 phys_page_compact(&p[i], nodes);
333 /* We can only compress if there's only one child. */
334 if (valid != 1) {
335 return;
338 assert(valid_ptr < P_L2_SIZE);
340 /* Don't compress if it won't fit in the # of bits we have. */
341 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
342 return;
345 lp->ptr = p[valid_ptr].ptr;
346 if (!p[valid_ptr].skip) {
347 /* If our only child is a leaf, make this a leaf. */
348 /* By design, we should have made this node a leaf to begin with so we
349 * should never reach here.
350 * But since it's so simple to handle this, let's do it just in case we
351 * change this rule.
353 lp->skip = 0;
354 } else {
355 lp->skip += p[valid_ptr].skip;
359 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
361 if (d->phys_map.skip) {
362 phys_page_compact(&d->phys_map, d->map.nodes);
366 static inline bool section_covers_addr(const MemoryRegionSection *section,
367 hwaddr addr)
369 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
370 * the section must cover the entire address space.
372 return int128_gethi(section->size) ||
373 range_covers_byte(section->offset_within_address_space,
374 int128_getlo(section->size), addr);
377 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
379 PhysPageEntry lp = d->phys_map, *p;
380 Node *nodes = d->map.nodes;
381 MemoryRegionSection *sections = d->map.sections;
382 hwaddr index = addr >> TARGET_PAGE_BITS;
383 int i;
385 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
386 if (lp.ptr == PHYS_MAP_NODE_NIL) {
387 return &sections[PHYS_SECTION_UNASSIGNED];
389 p = nodes[lp.ptr];
390 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
393 if (section_covers_addr(&sections[lp.ptr], addr)) {
394 return &sections[lp.ptr];
395 } else {
396 return &sections[PHYS_SECTION_UNASSIGNED];
400 bool memory_region_is_unassigned(MemoryRegion *mr)
402 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
403 && mr != &io_mem_watch;
406 /* Called from RCU critical section */
407 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
408 hwaddr addr,
409 bool resolve_subpage)
411 MemoryRegionSection *section = atomic_read(&d->mru_section);
412 subpage_t *subpage;
413 bool update;
415 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
416 section_covers_addr(section, addr)) {
417 update = false;
418 } else {
419 section = phys_page_find(d, addr);
420 update = true;
422 if (resolve_subpage && section->mr->subpage) {
423 subpage = container_of(section->mr, subpage_t, iomem);
424 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
426 if (update) {
427 atomic_set(&d->mru_section, section);
429 return section;
432 /* Called from RCU critical section */
433 static MemoryRegionSection *
434 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
435 hwaddr *plen, bool resolve_subpage)
437 MemoryRegionSection *section;
438 MemoryRegion *mr;
439 Int128 diff;
441 section = address_space_lookup_region(d, addr, resolve_subpage);
442 /* Compute offset within MemoryRegionSection */
443 addr -= section->offset_within_address_space;
445 /* Compute offset within MemoryRegion */
446 *xlat = addr + section->offset_within_region;
448 mr = section->mr;
450 /* MMIO registers can be expected to perform full-width accesses based only
451 * on their address, without considering adjacent registers that could
452 * decode to completely different MemoryRegions. When such registers
453 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
454 * regions overlap wildly. For this reason we cannot clamp the accesses
455 * here.
457 * If the length is small (as is the case for address_space_ldl/stl),
458 * everything works fine. If the incoming length is large, however,
459 * the caller really has to do the clamping through memory_access_size.
461 if (memory_region_is_ram(mr)) {
462 diff = int128_sub(section->size, int128_make64(addr));
463 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
465 return section;
468 /* Called from RCU critical section */
469 static MemoryRegionSection address_space_do_translate(AddressSpace *as,
470 hwaddr addr,
471 hwaddr *xlat,
472 hwaddr *plen,
473 bool is_write,
474 bool is_mmio)
476 IOMMUTLBEntry iotlb;
477 MemoryRegionSection *section;
478 MemoryRegion *mr;
480 for (;;) {
481 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
482 section = address_space_translate_internal(d, addr, &addr, plen, is_mmio);
483 mr = section->mr;
485 if (!mr->iommu_ops) {
486 break;
489 iotlb = mr->iommu_ops->translate(mr, addr, is_write ?
490 IOMMU_WO : IOMMU_RO);
491 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
492 | (addr & iotlb.addr_mask));
493 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
494 if (!(iotlb.perm & (1 << is_write))) {
495 goto translate_fail;
498 as = iotlb.target_as;
501 *xlat = addr;
503 return *section;
505 translate_fail:
506 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
509 /* Called from RCU critical section */
510 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
511 bool is_write)
513 MemoryRegionSection section;
514 hwaddr xlat, plen;
516 /* Try to get maximum page mask during translation. */
517 plen = (hwaddr)-1;
519 /* This can never be MMIO. */
520 section = address_space_do_translate(as, addr, &xlat, &plen,
521 is_write, false);
523 /* Illegal translation */
524 if (section.mr == &io_mem_unassigned) {
525 goto iotlb_fail;
528 /* Convert memory region offset into address space offset */
529 xlat += section.offset_within_address_space -
530 section.offset_within_region;
532 if (plen == (hwaddr)-1) {
534 * We use default page size here. Logically it only happens
535 * for identity mappings.
537 plen = TARGET_PAGE_SIZE;
540 /* Convert to address mask */
541 plen -= 1;
543 return (IOMMUTLBEntry) {
544 .target_as = section.address_space,
545 .iova = addr & ~plen,
546 .translated_addr = xlat & ~plen,
547 .addr_mask = plen,
548 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
549 .perm = IOMMU_RW,
552 iotlb_fail:
553 return (IOMMUTLBEntry) {0};
556 /* Called from RCU critical section */
557 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
558 hwaddr *xlat, hwaddr *plen,
559 bool is_write)
561 MemoryRegion *mr;
562 MemoryRegionSection section;
564 /* This can be MMIO, so setup MMIO bit. */
565 section = address_space_do_translate(as, addr, xlat, plen, is_write, true);
566 mr = section.mr;
568 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
569 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
570 *plen = MIN(page, *plen);
573 return mr;
576 /* Called from RCU critical section */
577 MemoryRegionSection *
578 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
579 hwaddr *xlat, hwaddr *plen)
581 MemoryRegionSection *section;
582 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
584 section = address_space_translate_internal(d, addr, xlat, plen, false);
586 assert(!section->mr->iommu_ops);
587 return section;
589 #endif
591 #if !defined(CONFIG_USER_ONLY)
593 static int cpu_common_post_load(void *opaque, int version_id)
595 CPUState *cpu = opaque;
597 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
598 version_id is increased. */
599 cpu->interrupt_request &= ~0x01;
600 tlb_flush(cpu);
602 return 0;
605 static int cpu_common_pre_load(void *opaque)
607 CPUState *cpu = opaque;
609 cpu->exception_index = -1;
611 return 0;
614 static bool cpu_common_exception_index_needed(void *opaque)
616 CPUState *cpu = opaque;
618 return tcg_enabled() && cpu->exception_index != -1;
621 static const VMStateDescription vmstate_cpu_common_exception_index = {
622 .name = "cpu_common/exception_index",
623 .version_id = 1,
624 .minimum_version_id = 1,
625 .needed = cpu_common_exception_index_needed,
626 .fields = (VMStateField[]) {
627 VMSTATE_INT32(exception_index, CPUState),
628 VMSTATE_END_OF_LIST()
632 static bool cpu_common_crash_occurred_needed(void *opaque)
634 CPUState *cpu = opaque;
636 return cpu->crash_occurred;
639 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
640 .name = "cpu_common/crash_occurred",
641 .version_id = 1,
642 .minimum_version_id = 1,
643 .needed = cpu_common_crash_occurred_needed,
644 .fields = (VMStateField[]) {
645 VMSTATE_BOOL(crash_occurred, CPUState),
646 VMSTATE_END_OF_LIST()
650 const VMStateDescription vmstate_cpu_common = {
651 .name = "cpu_common",
652 .version_id = 1,
653 .minimum_version_id = 1,
654 .pre_load = cpu_common_pre_load,
655 .post_load = cpu_common_post_load,
656 .fields = (VMStateField[]) {
657 VMSTATE_UINT32(halted, CPUState),
658 VMSTATE_UINT32(interrupt_request, CPUState),
659 VMSTATE_END_OF_LIST()
661 .subsections = (const VMStateDescription*[]) {
662 &vmstate_cpu_common_exception_index,
663 &vmstate_cpu_common_crash_occurred,
664 NULL
668 #endif
670 CPUState *qemu_get_cpu(int index)
672 CPUState *cpu;
674 CPU_FOREACH(cpu) {
675 if (cpu->cpu_index == index) {
676 return cpu;
680 return NULL;
683 #if !defined(CONFIG_USER_ONLY)
684 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
686 CPUAddressSpace *newas;
688 /* Target code should have set num_ases before calling us */
689 assert(asidx < cpu->num_ases);
691 if (asidx == 0) {
692 /* address space 0 gets the convenience alias */
693 cpu->as = as;
696 /* KVM cannot currently support multiple address spaces. */
697 assert(asidx == 0 || !kvm_enabled());
699 if (!cpu->cpu_ases) {
700 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
703 newas = &cpu->cpu_ases[asidx];
704 newas->cpu = cpu;
705 newas->as = as;
706 if (tcg_enabled()) {
707 newas->tcg_as_listener.commit = tcg_commit;
708 memory_listener_register(&newas->tcg_as_listener, as);
712 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
714 /* Return the AddressSpace corresponding to the specified index */
715 return cpu->cpu_ases[asidx].as;
717 #endif
719 void cpu_exec_unrealizefn(CPUState *cpu)
721 CPUClass *cc = CPU_GET_CLASS(cpu);
723 cpu_list_remove(cpu);
725 if (cc->vmsd != NULL) {
726 vmstate_unregister(NULL, cc->vmsd, cpu);
728 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
729 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
733 void cpu_exec_initfn(CPUState *cpu)
735 cpu->as = NULL;
736 cpu->num_ases = 0;
738 #ifndef CONFIG_USER_ONLY
739 cpu->thread_id = qemu_get_thread_id();
741 /* This is a softmmu CPU object, so create a property for it
742 * so users can wire up its memory. (This can't go in qom/cpu.c
743 * because that file is compiled only once for both user-mode
744 * and system builds.) The default if no link is set up is to use
745 * the system address space.
747 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
748 (Object **)&cpu->memory,
749 qdev_prop_allow_set_link_before_realize,
750 OBJ_PROP_LINK_UNREF_ON_RELEASE,
751 &error_abort);
752 cpu->memory = system_memory;
753 object_ref(OBJECT(cpu->memory));
754 #endif
757 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
759 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
761 cpu_list_add(cpu);
763 #ifndef CONFIG_USER_ONLY
764 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
765 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
767 if (cc->vmsd != NULL) {
768 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
770 #endif
773 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
775 /* Flush the whole TB as this will not have race conditions
776 * even if we don't have proper locking yet.
777 * Ideally we would just invalidate the TBs for the
778 * specified PC.
780 tb_flush(cpu);
783 #if defined(CONFIG_USER_ONLY)
784 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
789 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
790 int flags)
792 return -ENOSYS;
795 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
799 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
800 int flags, CPUWatchpoint **watchpoint)
802 return -ENOSYS;
804 #else
805 /* Add a watchpoint. */
806 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
807 int flags, CPUWatchpoint **watchpoint)
809 CPUWatchpoint *wp;
811 /* forbid ranges which are empty or run off the end of the address space */
812 if (len == 0 || (addr + len - 1) < addr) {
813 error_report("tried to set invalid watchpoint at %"
814 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
815 return -EINVAL;
817 wp = g_malloc(sizeof(*wp));
819 wp->vaddr = addr;
820 wp->len = len;
821 wp->flags = flags;
823 /* keep all GDB-injected watchpoints in front */
824 if (flags & BP_GDB) {
825 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
826 } else {
827 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
830 tlb_flush_page(cpu, addr);
832 if (watchpoint)
833 *watchpoint = wp;
834 return 0;
837 /* Remove a specific watchpoint. */
838 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
839 int flags)
841 CPUWatchpoint *wp;
843 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
844 if (addr == wp->vaddr && len == wp->len
845 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
846 cpu_watchpoint_remove_by_ref(cpu, wp);
847 return 0;
850 return -ENOENT;
853 /* Remove a specific watchpoint by reference. */
854 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
856 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
858 tlb_flush_page(cpu, watchpoint->vaddr);
860 g_free(watchpoint);
863 /* Remove all matching watchpoints. */
864 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
866 CPUWatchpoint *wp, *next;
868 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
869 if (wp->flags & mask) {
870 cpu_watchpoint_remove_by_ref(cpu, wp);
875 /* Return true if this watchpoint address matches the specified
876 * access (ie the address range covered by the watchpoint overlaps
877 * partially or completely with the address range covered by the
878 * access).
880 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
881 vaddr addr,
882 vaddr len)
884 /* We know the lengths are non-zero, but a little caution is
885 * required to avoid errors in the case where the range ends
886 * exactly at the top of the address space and so addr + len
887 * wraps round to zero.
889 vaddr wpend = wp->vaddr + wp->len - 1;
890 vaddr addrend = addr + len - 1;
892 return !(addr > wpend || wp->vaddr > addrend);
895 #endif
897 /* Add a breakpoint. */
898 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
899 CPUBreakpoint **breakpoint)
901 CPUBreakpoint *bp;
903 bp = g_malloc(sizeof(*bp));
905 bp->pc = pc;
906 bp->flags = flags;
908 /* keep all GDB-injected breakpoints in front */
909 if (flags & BP_GDB) {
910 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
911 } else {
912 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
915 breakpoint_invalidate(cpu, pc);
917 if (breakpoint) {
918 *breakpoint = bp;
920 return 0;
923 /* Remove a specific breakpoint. */
924 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
926 CPUBreakpoint *bp;
928 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
929 if (bp->pc == pc && bp->flags == flags) {
930 cpu_breakpoint_remove_by_ref(cpu, bp);
931 return 0;
934 return -ENOENT;
937 /* Remove a specific breakpoint by reference. */
938 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
940 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
942 breakpoint_invalidate(cpu, breakpoint->pc);
944 g_free(breakpoint);
947 /* Remove all matching breakpoints. */
948 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
950 CPUBreakpoint *bp, *next;
952 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
953 if (bp->flags & mask) {
954 cpu_breakpoint_remove_by_ref(cpu, bp);
959 /* enable or disable single step mode. EXCP_DEBUG is returned by the
960 CPU loop after each instruction */
961 void cpu_single_step(CPUState *cpu, int enabled)
963 if (cpu->singlestep_enabled != enabled) {
964 cpu->singlestep_enabled = enabled;
965 if (kvm_enabled()) {
966 kvm_update_guest_debug(cpu, 0);
967 } else {
968 /* must flush all the translated code to avoid inconsistencies */
969 /* XXX: only flush what is necessary */
970 tb_flush(cpu);
975 void cpu_abort(CPUState *cpu, const char *fmt, ...)
977 va_list ap;
978 va_list ap2;
980 va_start(ap, fmt);
981 va_copy(ap2, ap);
982 fprintf(stderr, "qemu: fatal: ");
983 vfprintf(stderr, fmt, ap);
984 fprintf(stderr, "\n");
985 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
986 if (qemu_log_separate()) {
987 qemu_log_lock();
988 qemu_log("qemu: fatal: ");
989 qemu_log_vprintf(fmt, ap2);
990 qemu_log("\n");
991 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
992 qemu_log_flush();
993 qemu_log_unlock();
994 qemu_log_close();
996 va_end(ap2);
997 va_end(ap);
998 replay_finish();
999 #if defined(CONFIG_USER_ONLY)
1001 struct sigaction act;
1002 sigfillset(&act.sa_mask);
1003 act.sa_handler = SIG_DFL;
1004 sigaction(SIGABRT, &act, NULL);
1006 #endif
1007 abort();
1010 #if !defined(CONFIG_USER_ONLY)
1011 /* Called from RCU critical section */
1012 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1014 RAMBlock *block;
1016 block = atomic_rcu_read(&ram_list.mru_block);
1017 if (block && addr - block->offset < block->max_length) {
1018 return block;
1020 RAMBLOCK_FOREACH(block) {
1021 if (addr - block->offset < block->max_length) {
1022 goto found;
1026 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1027 abort();
1029 found:
1030 /* It is safe to write mru_block outside the iothread lock. This
1031 * is what happens:
1033 * mru_block = xxx
1034 * rcu_read_unlock()
1035 * xxx removed from list
1036 * rcu_read_lock()
1037 * read mru_block
1038 * mru_block = NULL;
1039 * call_rcu(reclaim_ramblock, xxx);
1040 * rcu_read_unlock()
1042 * atomic_rcu_set is not needed here. The block was already published
1043 * when it was placed into the list. Here we're just making an extra
1044 * copy of the pointer.
1046 ram_list.mru_block = block;
1047 return block;
1050 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1052 CPUState *cpu;
1053 ram_addr_t start1;
1054 RAMBlock *block;
1055 ram_addr_t end;
1057 end = TARGET_PAGE_ALIGN(start + length);
1058 start &= TARGET_PAGE_MASK;
1060 rcu_read_lock();
1061 block = qemu_get_ram_block(start);
1062 assert(block == qemu_get_ram_block(end - 1));
1063 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1064 CPU_FOREACH(cpu) {
1065 tlb_reset_dirty(cpu, start1, length);
1067 rcu_read_unlock();
1070 /* Note: start and end must be within the same ram block. */
1071 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1072 ram_addr_t length,
1073 unsigned client)
1075 DirtyMemoryBlocks *blocks;
1076 unsigned long end, page;
1077 bool dirty = false;
1079 if (length == 0) {
1080 return false;
1083 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1084 page = start >> TARGET_PAGE_BITS;
1086 rcu_read_lock();
1088 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1090 while (page < end) {
1091 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1092 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1093 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1095 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1096 offset, num);
1097 page += num;
1100 rcu_read_unlock();
1102 if (dirty && tcg_enabled()) {
1103 tlb_reset_dirty_range_all(start, length);
1106 return dirty;
1109 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1110 (ram_addr_t start, ram_addr_t length, unsigned client)
1112 DirtyMemoryBlocks *blocks;
1113 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1114 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1115 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1116 DirtyBitmapSnapshot *snap;
1117 unsigned long page, end, dest;
1119 snap = g_malloc0(sizeof(*snap) +
1120 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1121 snap->start = first;
1122 snap->end = last;
1124 page = first >> TARGET_PAGE_BITS;
1125 end = last >> TARGET_PAGE_BITS;
1126 dest = 0;
1128 rcu_read_lock();
1130 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1132 while (page < end) {
1133 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1134 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1135 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1137 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1138 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1139 offset >>= BITS_PER_LEVEL;
1141 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1142 blocks->blocks[idx] + offset,
1143 num);
1144 page += num;
1145 dest += num >> BITS_PER_LEVEL;
1148 rcu_read_unlock();
1150 if (tcg_enabled()) {
1151 tlb_reset_dirty_range_all(start, length);
1154 return snap;
1157 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1158 ram_addr_t start,
1159 ram_addr_t length)
1161 unsigned long page, end;
1163 assert(start >= snap->start);
1164 assert(start + length <= snap->end);
1166 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1167 page = (start - snap->start) >> TARGET_PAGE_BITS;
1169 while (page < end) {
1170 if (test_bit(page, snap->dirty)) {
1171 return true;
1173 page++;
1175 return false;
1178 /* Called from RCU critical section */
1179 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1180 MemoryRegionSection *section,
1181 target_ulong vaddr,
1182 hwaddr paddr, hwaddr xlat,
1183 int prot,
1184 target_ulong *address)
1186 hwaddr iotlb;
1187 CPUWatchpoint *wp;
1189 if (memory_region_is_ram(section->mr)) {
1190 /* Normal RAM. */
1191 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1192 if (!section->readonly) {
1193 iotlb |= PHYS_SECTION_NOTDIRTY;
1194 } else {
1195 iotlb |= PHYS_SECTION_ROM;
1197 } else {
1198 AddressSpaceDispatch *d;
1200 d = atomic_rcu_read(&section->address_space->dispatch);
1201 iotlb = section - d->map.sections;
1202 iotlb += xlat;
1205 /* Make accesses to pages with watchpoints go via the
1206 watchpoint trap routines. */
1207 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1208 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1209 /* Avoid trapping reads of pages with a write breakpoint. */
1210 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1211 iotlb = PHYS_SECTION_WATCH + paddr;
1212 *address |= TLB_MMIO;
1213 break;
1218 return iotlb;
1220 #endif /* defined(CONFIG_USER_ONLY) */
1222 #if !defined(CONFIG_USER_ONLY)
1224 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1225 uint16_t section);
1226 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1228 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1229 qemu_anon_ram_alloc;
1232 * Set a custom physical guest memory alloator.
1233 * Accelerators with unusual needs may need this. Hopefully, we can
1234 * get rid of it eventually.
1236 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1238 phys_mem_alloc = alloc;
1241 static uint16_t phys_section_add(PhysPageMap *map,
1242 MemoryRegionSection *section)
1244 /* The physical section number is ORed with a page-aligned
1245 * pointer to produce the iotlb entries. Thus it should
1246 * never overflow into the page-aligned value.
1248 assert(map->sections_nb < TARGET_PAGE_SIZE);
1250 if (map->sections_nb == map->sections_nb_alloc) {
1251 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1252 map->sections = g_renew(MemoryRegionSection, map->sections,
1253 map->sections_nb_alloc);
1255 map->sections[map->sections_nb] = *section;
1256 memory_region_ref(section->mr);
1257 return map->sections_nb++;
1260 static void phys_section_destroy(MemoryRegion *mr)
1262 bool have_sub_page = mr->subpage;
1264 memory_region_unref(mr);
1266 if (have_sub_page) {
1267 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1268 object_unref(OBJECT(&subpage->iomem));
1269 g_free(subpage);
1273 static void phys_sections_free(PhysPageMap *map)
1275 while (map->sections_nb > 0) {
1276 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1277 phys_section_destroy(section->mr);
1279 g_free(map->sections);
1280 g_free(map->nodes);
1283 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1285 subpage_t *subpage;
1286 hwaddr base = section->offset_within_address_space
1287 & TARGET_PAGE_MASK;
1288 MemoryRegionSection *existing = phys_page_find(d, base);
1289 MemoryRegionSection subsection = {
1290 .offset_within_address_space = base,
1291 .size = int128_make64(TARGET_PAGE_SIZE),
1293 hwaddr start, end;
1295 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1297 if (!(existing->mr->subpage)) {
1298 subpage = subpage_init(d->as, base);
1299 subsection.address_space = d->as;
1300 subsection.mr = &subpage->iomem;
1301 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1302 phys_section_add(&d->map, &subsection));
1303 } else {
1304 subpage = container_of(existing->mr, subpage_t, iomem);
1306 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1307 end = start + int128_get64(section->size) - 1;
1308 subpage_register(subpage, start, end,
1309 phys_section_add(&d->map, section));
1313 static void register_multipage(AddressSpaceDispatch *d,
1314 MemoryRegionSection *section)
1316 hwaddr start_addr = section->offset_within_address_space;
1317 uint16_t section_index = phys_section_add(&d->map, section);
1318 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1319 TARGET_PAGE_BITS));
1321 assert(num_pages);
1322 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1325 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1327 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1328 AddressSpaceDispatch *d = as->next_dispatch;
1329 MemoryRegionSection now = *section, remain = *section;
1330 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1332 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1333 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1334 - now.offset_within_address_space;
1336 now.size = int128_min(int128_make64(left), now.size);
1337 register_subpage(d, &now);
1338 } else {
1339 now.size = int128_zero();
1341 while (int128_ne(remain.size, now.size)) {
1342 remain.size = int128_sub(remain.size, now.size);
1343 remain.offset_within_address_space += int128_get64(now.size);
1344 remain.offset_within_region += int128_get64(now.size);
1345 now = remain;
1346 if (int128_lt(remain.size, page_size)) {
1347 register_subpage(d, &now);
1348 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1349 now.size = page_size;
1350 register_subpage(d, &now);
1351 } else {
1352 now.size = int128_and(now.size, int128_neg(page_size));
1353 register_multipage(d, &now);
1358 void qemu_flush_coalesced_mmio_buffer(void)
1360 if (kvm_enabled())
1361 kvm_flush_coalesced_mmio_buffer();
1364 void qemu_mutex_lock_ramlist(void)
1366 qemu_mutex_lock(&ram_list.mutex);
1369 void qemu_mutex_unlock_ramlist(void)
1371 qemu_mutex_unlock(&ram_list.mutex);
1374 void ram_block_dump(Monitor *mon)
1376 RAMBlock *block;
1377 char *psize;
1379 rcu_read_lock();
1380 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1381 "Block Name", "PSize", "Offset", "Used", "Total");
1382 RAMBLOCK_FOREACH(block) {
1383 psize = size_to_str(block->page_size);
1384 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1385 " 0x%016" PRIx64 "\n", block->idstr, psize,
1386 (uint64_t)block->offset,
1387 (uint64_t)block->used_length,
1388 (uint64_t)block->max_length);
1389 g_free(psize);
1391 rcu_read_unlock();
1394 #ifdef __linux__
1396 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1397 * may or may not name the same files / on the same filesystem now as
1398 * when we actually open and map them. Iterate over the file
1399 * descriptors instead, and use qemu_fd_getpagesize().
1401 static int find_max_supported_pagesize(Object *obj, void *opaque)
1403 char *mem_path;
1404 long *hpsize_min = opaque;
1406 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1407 mem_path = object_property_get_str(obj, "mem-path", NULL);
1408 if (mem_path) {
1409 long hpsize = qemu_mempath_getpagesize(mem_path);
1410 if (hpsize < *hpsize_min) {
1411 *hpsize_min = hpsize;
1413 } else {
1414 *hpsize_min = getpagesize();
1418 return 0;
1421 long qemu_getrampagesize(void)
1423 long hpsize = LONG_MAX;
1424 long mainrampagesize;
1425 Object *memdev_root;
1427 if (mem_path) {
1428 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1429 } else {
1430 mainrampagesize = getpagesize();
1433 /* it's possible we have memory-backend objects with
1434 * hugepage-backed RAM. these may get mapped into system
1435 * address space via -numa parameters or memory hotplug
1436 * hooks. we want to take these into account, but we
1437 * also want to make sure these supported hugepage
1438 * sizes are applicable across the entire range of memory
1439 * we may boot from, so we take the min across all
1440 * backends, and assume normal pages in cases where a
1441 * backend isn't backed by hugepages.
1443 memdev_root = object_resolve_path("/objects", NULL);
1444 if (memdev_root) {
1445 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1447 if (hpsize == LONG_MAX) {
1448 /* No additional memory regions found ==> Report main RAM page size */
1449 return mainrampagesize;
1452 /* If NUMA is disabled or the NUMA nodes are not backed with a
1453 * memory-backend, then there is at least one node using "normal" RAM,
1454 * so if its page size is smaller we have got to report that size instead.
1456 if (hpsize > mainrampagesize &&
1457 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1458 static bool warned;
1459 if (!warned) {
1460 error_report("Huge page support disabled (n/a for main memory).");
1461 warned = true;
1463 return mainrampagesize;
1466 return hpsize;
1468 #else
1469 long qemu_getrampagesize(void)
1471 return getpagesize();
1473 #endif
1475 #ifdef __linux__
1476 static int64_t get_file_size(int fd)
1478 int64_t size = lseek(fd, 0, SEEK_END);
1479 if (size < 0) {
1480 return -errno;
1482 return size;
1485 static int file_ram_open(const char *path,
1486 const char *region_name,
1487 bool *created,
1488 Error **errp)
1490 char *filename;
1491 char *sanitized_name;
1492 char *c;
1493 int fd = -1;
1495 *created = false;
1496 for (;;) {
1497 fd = open(path, O_RDWR);
1498 if (fd >= 0) {
1499 /* @path names an existing file, use it */
1500 break;
1502 if (errno == ENOENT) {
1503 /* @path names a file that doesn't exist, create it */
1504 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1505 if (fd >= 0) {
1506 *created = true;
1507 break;
1509 } else if (errno == EISDIR) {
1510 /* @path names a directory, create a file there */
1511 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1512 sanitized_name = g_strdup(region_name);
1513 for (c = sanitized_name; *c != '\0'; c++) {
1514 if (*c == '/') {
1515 *c = '_';
1519 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1520 sanitized_name);
1521 g_free(sanitized_name);
1523 fd = mkstemp(filename);
1524 if (fd >= 0) {
1525 unlink(filename);
1526 g_free(filename);
1527 break;
1529 g_free(filename);
1531 if (errno != EEXIST && errno != EINTR) {
1532 error_setg_errno(errp, errno,
1533 "can't open backing store %s for guest RAM",
1534 path);
1535 return -1;
1538 * Try again on EINTR and EEXIST. The latter happens when
1539 * something else creates the file between our two open().
1543 return fd;
1546 static void *file_ram_alloc(RAMBlock *block,
1547 ram_addr_t memory,
1548 int fd,
1549 bool truncate,
1550 Error **errp)
1552 void *area;
1554 block->page_size = qemu_fd_getpagesize(fd);
1555 block->mr->align = block->page_size;
1556 #if defined(__s390x__)
1557 if (kvm_enabled()) {
1558 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1560 #endif
1562 if (memory < block->page_size) {
1563 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1564 "or larger than page size 0x%zx",
1565 memory, block->page_size);
1566 return NULL;
1569 memory = ROUND_UP(memory, block->page_size);
1572 * ftruncate is not supported by hugetlbfs in older
1573 * hosts, so don't bother bailing out on errors.
1574 * If anything goes wrong with it under other filesystems,
1575 * mmap will fail.
1577 * Do not truncate the non-empty backend file to avoid corrupting
1578 * the existing data in the file. Disabling shrinking is not
1579 * enough. For example, the current vNVDIMM implementation stores
1580 * the guest NVDIMM labels at the end of the backend file. If the
1581 * backend file is later extended, QEMU will not be able to find
1582 * those labels. Therefore, extending the non-empty backend file
1583 * is disabled as well.
1585 if (truncate && ftruncate(fd, memory)) {
1586 perror("ftruncate");
1589 area = qemu_ram_mmap(fd, memory, block->mr->align,
1590 block->flags & RAM_SHARED);
1591 if (area == MAP_FAILED) {
1592 error_setg_errno(errp, errno,
1593 "unable to map backing store for guest RAM");
1594 return NULL;
1597 if (mem_prealloc) {
1598 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1599 if (errp && *errp) {
1600 qemu_ram_munmap(area, memory);
1601 return NULL;
1605 block->fd = fd;
1606 return area;
1608 #endif
1610 /* Called with the ramlist lock held. */
1611 static ram_addr_t find_ram_offset(ram_addr_t size)
1613 RAMBlock *block, *next_block;
1614 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1616 assert(size != 0); /* it would hand out same offset multiple times */
1618 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1619 return 0;
1622 RAMBLOCK_FOREACH(block) {
1623 ram_addr_t end, next = RAM_ADDR_MAX;
1625 end = block->offset + block->max_length;
1627 RAMBLOCK_FOREACH(next_block) {
1628 if (next_block->offset >= end) {
1629 next = MIN(next, next_block->offset);
1632 if (next - end >= size && next - end < mingap) {
1633 offset = end;
1634 mingap = next - end;
1638 if (offset == RAM_ADDR_MAX) {
1639 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1640 (uint64_t)size);
1641 abort();
1644 return offset;
1647 unsigned long last_ram_page(void)
1649 RAMBlock *block;
1650 ram_addr_t last = 0;
1652 rcu_read_lock();
1653 RAMBLOCK_FOREACH(block) {
1654 last = MAX(last, block->offset + block->max_length);
1656 rcu_read_unlock();
1657 return last >> TARGET_PAGE_BITS;
1660 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1662 int ret;
1664 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1665 if (!machine_dump_guest_core(current_machine)) {
1666 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1667 if (ret) {
1668 perror("qemu_madvise");
1669 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1670 "but dump_guest_core=off specified\n");
1675 const char *qemu_ram_get_idstr(RAMBlock *rb)
1677 return rb->idstr;
1680 bool qemu_ram_is_shared(RAMBlock *rb)
1682 return rb->flags & RAM_SHARED;
1685 /* Called with iothread lock held. */
1686 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1688 RAMBlock *block;
1690 assert(new_block);
1691 assert(!new_block->idstr[0]);
1693 if (dev) {
1694 char *id = qdev_get_dev_path(dev);
1695 if (id) {
1696 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1697 g_free(id);
1700 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1702 rcu_read_lock();
1703 RAMBLOCK_FOREACH(block) {
1704 if (block != new_block &&
1705 !strcmp(block->idstr, new_block->idstr)) {
1706 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1707 new_block->idstr);
1708 abort();
1711 rcu_read_unlock();
1714 /* Called with iothread lock held. */
1715 void qemu_ram_unset_idstr(RAMBlock *block)
1717 /* FIXME: arch_init.c assumes that this is not called throughout
1718 * migration. Ignore the problem since hot-unplug during migration
1719 * does not work anyway.
1721 if (block) {
1722 memset(block->idstr, 0, sizeof(block->idstr));
1726 size_t qemu_ram_pagesize(RAMBlock *rb)
1728 return rb->page_size;
1731 /* Returns the largest size of page in use */
1732 size_t qemu_ram_pagesize_largest(void)
1734 RAMBlock *block;
1735 size_t largest = 0;
1737 RAMBLOCK_FOREACH(block) {
1738 largest = MAX(largest, qemu_ram_pagesize(block));
1741 return largest;
1744 static int memory_try_enable_merging(void *addr, size_t len)
1746 if (!machine_mem_merge(current_machine)) {
1747 /* disabled by the user */
1748 return 0;
1751 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1754 /* Only legal before guest might have detected the memory size: e.g. on
1755 * incoming migration, or right after reset.
1757 * As memory core doesn't know how is memory accessed, it is up to
1758 * resize callback to update device state and/or add assertions to detect
1759 * misuse, if necessary.
1761 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1763 assert(block);
1765 newsize = HOST_PAGE_ALIGN(newsize);
1767 if (block->used_length == newsize) {
1768 return 0;
1771 if (!(block->flags & RAM_RESIZEABLE)) {
1772 error_setg_errno(errp, EINVAL,
1773 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1774 " in != 0x" RAM_ADDR_FMT, block->idstr,
1775 newsize, block->used_length);
1776 return -EINVAL;
1779 if (block->max_length < newsize) {
1780 error_setg_errno(errp, EINVAL,
1781 "Length too large: %s: 0x" RAM_ADDR_FMT
1782 " > 0x" RAM_ADDR_FMT, block->idstr,
1783 newsize, block->max_length);
1784 return -EINVAL;
1787 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1788 block->used_length = newsize;
1789 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1790 DIRTY_CLIENTS_ALL);
1791 memory_region_set_size(block->mr, newsize);
1792 if (block->resized) {
1793 block->resized(block->idstr, newsize, block->host);
1795 return 0;
1798 /* Called with ram_list.mutex held */
1799 static void dirty_memory_extend(ram_addr_t old_ram_size,
1800 ram_addr_t new_ram_size)
1802 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1803 DIRTY_MEMORY_BLOCK_SIZE);
1804 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1805 DIRTY_MEMORY_BLOCK_SIZE);
1806 int i;
1808 /* Only need to extend if block count increased */
1809 if (new_num_blocks <= old_num_blocks) {
1810 return;
1813 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1814 DirtyMemoryBlocks *old_blocks;
1815 DirtyMemoryBlocks *new_blocks;
1816 int j;
1818 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1819 new_blocks = g_malloc(sizeof(*new_blocks) +
1820 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1822 if (old_num_blocks) {
1823 memcpy(new_blocks->blocks, old_blocks->blocks,
1824 old_num_blocks * sizeof(old_blocks->blocks[0]));
1827 for (j = old_num_blocks; j < new_num_blocks; j++) {
1828 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1831 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1833 if (old_blocks) {
1834 g_free_rcu(old_blocks, rcu);
1839 static void ram_block_add(RAMBlock *new_block, Error **errp)
1841 RAMBlock *block;
1842 RAMBlock *last_block = NULL;
1843 ram_addr_t old_ram_size, new_ram_size;
1844 Error *err = NULL;
1846 old_ram_size = last_ram_page();
1848 qemu_mutex_lock_ramlist();
1849 new_block->offset = find_ram_offset(new_block->max_length);
1851 if (!new_block->host) {
1852 if (xen_enabled()) {
1853 xen_ram_alloc(new_block->offset, new_block->max_length,
1854 new_block->mr, &err);
1855 if (err) {
1856 error_propagate(errp, err);
1857 qemu_mutex_unlock_ramlist();
1858 return;
1860 } else {
1861 new_block->host = phys_mem_alloc(new_block->max_length,
1862 &new_block->mr->align);
1863 if (!new_block->host) {
1864 error_setg_errno(errp, errno,
1865 "cannot set up guest memory '%s'",
1866 memory_region_name(new_block->mr));
1867 qemu_mutex_unlock_ramlist();
1868 return;
1870 memory_try_enable_merging(new_block->host, new_block->max_length);
1874 new_ram_size = MAX(old_ram_size,
1875 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1876 if (new_ram_size > old_ram_size) {
1877 dirty_memory_extend(old_ram_size, new_ram_size);
1879 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1880 * QLIST (which has an RCU-friendly variant) does not have insertion at
1881 * tail, so save the last element in last_block.
1883 RAMBLOCK_FOREACH(block) {
1884 last_block = block;
1885 if (block->max_length < new_block->max_length) {
1886 break;
1889 if (block) {
1890 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1891 } else if (last_block) {
1892 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1893 } else { /* list is empty */
1894 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1896 ram_list.mru_block = NULL;
1898 /* Write list before version */
1899 smp_wmb();
1900 ram_list.version++;
1901 qemu_mutex_unlock_ramlist();
1903 cpu_physical_memory_set_dirty_range(new_block->offset,
1904 new_block->used_length,
1905 DIRTY_CLIENTS_ALL);
1907 if (new_block->host) {
1908 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1909 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1910 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1911 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1912 ram_block_notify_add(new_block->host, new_block->max_length);
1916 #ifdef __linux__
1917 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
1918 bool share, int fd,
1919 Error **errp)
1921 RAMBlock *new_block;
1922 Error *local_err = NULL;
1923 int64_t file_size;
1925 if (xen_enabled()) {
1926 error_setg(errp, "-mem-path not supported with Xen");
1927 return NULL;
1930 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1931 error_setg(errp,
1932 "host lacks kvm mmu notifiers, -mem-path unsupported");
1933 return NULL;
1936 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1938 * file_ram_alloc() needs to allocate just like
1939 * phys_mem_alloc, but we haven't bothered to provide
1940 * a hook there.
1942 error_setg(errp,
1943 "-mem-path not supported with this accelerator");
1944 return NULL;
1947 size = HOST_PAGE_ALIGN(size);
1948 file_size = get_file_size(fd);
1949 if (file_size > 0 && file_size < size) {
1950 error_setg(errp, "backing store %s size 0x%" PRIx64
1951 " does not match 'size' option 0x" RAM_ADDR_FMT,
1952 mem_path, file_size, size);
1953 return NULL;
1956 new_block = g_malloc0(sizeof(*new_block));
1957 new_block->mr = mr;
1958 new_block->used_length = size;
1959 new_block->max_length = size;
1960 new_block->flags = share ? RAM_SHARED : 0;
1961 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
1962 if (!new_block->host) {
1963 g_free(new_block);
1964 return NULL;
1967 ram_block_add(new_block, &local_err);
1968 if (local_err) {
1969 g_free(new_block);
1970 error_propagate(errp, local_err);
1971 return NULL;
1973 return new_block;
1978 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1979 bool share, const char *mem_path,
1980 Error **errp)
1982 int fd;
1983 bool created;
1984 RAMBlock *block;
1986 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
1987 if (fd < 0) {
1988 return NULL;
1991 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1992 if (!block) {
1993 if (created) {
1994 unlink(mem_path);
1996 close(fd);
1997 return NULL;
2000 return block;
2002 #endif
2004 static
2005 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2006 void (*resized)(const char*,
2007 uint64_t length,
2008 void *host),
2009 void *host, bool resizeable,
2010 MemoryRegion *mr, Error **errp)
2012 RAMBlock *new_block;
2013 Error *local_err = NULL;
2015 size = HOST_PAGE_ALIGN(size);
2016 max_size = HOST_PAGE_ALIGN(max_size);
2017 new_block = g_malloc0(sizeof(*new_block));
2018 new_block->mr = mr;
2019 new_block->resized = resized;
2020 new_block->used_length = size;
2021 new_block->max_length = max_size;
2022 assert(max_size >= size);
2023 new_block->fd = -1;
2024 new_block->page_size = getpagesize();
2025 new_block->host = host;
2026 if (host) {
2027 new_block->flags |= RAM_PREALLOC;
2029 if (resizeable) {
2030 new_block->flags |= RAM_RESIZEABLE;
2032 ram_block_add(new_block, &local_err);
2033 if (local_err) {
2034 g_free(new_block);
2035 error_propagate(errp, local_err);
2036 return NULL;
2038 return new_block;
2041 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2042 MemoryRegion *mr, Error **errp)
2044 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
2047 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
2049 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
2052 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2053 void (*resized)(const char*,
2054 uint64_t length,
2055 void *host),
2056 MemoryRegion *mr, Error **errp)
2058 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
2061 static void reclaim_ramblock(RAMBlock *block)
2063 if (block->flags & RAM_PREALLOC) {
2065 } else if (xen_enabled()) {
2066 xen_invalidate_map_cache_entry(block->host);
2067 #ifndef _WIN32
2068 } else if (block->fd >= 0) {
2069 qemu_ram_munmap(block->host, block->max_length);
2070 close(block->fd);
2071 #endif
2072 } else {
2073 qemu_anon_ram_free(block->host, block->max_length);
2075 g_free(block);
2078 void qemu_ram_free(RAMBlock *block)
2080 if (!block) {
2081 return;
2084 if (block->host) {
2085 ram_block_notify_remove(block->host, block->max_length);
2088 qemu_mutex_lock_ramlist();
2089 QLIST_REMOVE_RCU(block, next);
2090 ram_list.mru_block = NULL;
2091 /* Write list before version */
2092 smp_wmb();
2093 ram_list.version++;
2094 call_rcu(block, reclaim_ramblock, rcu);
2095 qemu_mutex_unlock_ramlist();
2098 #ifndef _WIN32
2099 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2101 RAMBlock *block;
2102 ram_addr_t offset;
2103 int flags;
2104 void *area, *vaddr;
2106 RAMBLOCK_FOREACH(block) {
2107 offset = addr - block->offset;
2108 if (offset < block->max_length) {
2109 vaddr = ramblock_ptr(block, offset);
2110 if (block->flags & RAM_PREALLOC) {
2112 } else if (xen_enabled()) {
2113 abort();
2114 } else {
2115 flags = MAP_FIXED;
2116 if (block->fd >= 0) {
2117 flags |= (block->flags & RAM_SHARED ?
2118 MAP_SHARED : MAP_PRIVATE);
2119 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2120 flags, block->fd, offset);
2121 } else {
2123 * Remap needs to match alloc. Accelerators that
2124 * set phys_mem_alloc never remap. If they did,
2125 * we'd need a remap hook here.
2127 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2129 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2130 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2131 flags, -1, 0);
2133 if (area != vaddr) {
2134 fprintf(stderr, "Could not remap addr: "
2135 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2136 length, addr);
2137 exit(1);
2139 memory_try_enable_merging(vaddr, length);
2140 qemu_ram_setup_dump(vaddr, length);
2145 #endif /* !_WIN32 */
2147 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2148 * This should not be used for general purpose DMA. Use address_space_map
2149 * or address_space_rw instead. For local memory (e.g. video ram) that the
2150 * device owns, use memory_region_get_ram_ptr.
2152 * Called within RCU critical section.
2154 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2156 RAMBlock *block = ram_block;
2158 if (block == NULL) {
2159 block = qemu_get_ram_block(addr);
2160 addr -= block->offset;
2163 if (xen_enabled() && block->host == NULL) {
2164 /* We need to check if the requested address is in the RAM
2165 * because we don't want to map the entire memory in QEMU.
2166 * In that case just map until the end of the page.
2168 if (block->offset == 0) {
2169 return xen_map_cache(addr, 0, 0, false);
2172 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2174 return ramblock_ptr(block, addr);
2177 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2178 * but takes a size argument.
2180 * Called within RCU critical section.
2182 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2183 hwaddr *size)
2185 RAMBlock *block = ram_block;
2186 if (*size == 0) {
2187 return NULL;
2190 if (block == NULL) {
2191 block = qemu_get_ram_block(addr);
2192 addr -= block->offset;
2194 *size = MIN(*size, block->max_length - addr);
2196 if (xen_enabled() && block->host == NULL) {
2197 /* We need to check if the requested address is in the RAM
2198 * because we don't want to map the entire memory in QEMU.
2199 * In that case just map the requested area.
2201 if (block->offset == 0) {
2202 return xen_map_cache(addr, *size, 1, true);
2205 block->host = xen_map_cache(block->offset, block->max_length, 1, true);
2208 return ramblock_ptr(block, addr);
2212 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2213 * in that RAMBlock.
2215 * ptr: Host pointer to look up
2216 * round_offset: If true round the result offset down to a page boundary
2217 * *ram_addr: set to result ram_addr
2218 * *offset: set to result offset within the RAMBlock
2220 * Returns: RAMBlock (or NULL if not found)
2222 * By the time this function returns, the returned pointer is not protected
2223 * by RCU anymore. If the caller is not within an RCU critical section and
2224 * does not hold the iothread lock, it must have other means of protecting the
2225 * pointer, such as a reference to the region that includes the incoming
2226 * ram_addr_t.
2228 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2229 ram_addr_t *offset)
2231 RAMBlock *block;
2232 uint8_t *host = ptr;
2234 if (xen_enabled()) {
2235 ram_addr_t ram_addr;
2236 rcu_read_lock();
2237 ram_addr = xen_ram_addr_from_mapcache(ptr);
2238 block = qemu_get_ram_block(ram_addr);
2239 if (block) {
2240 *offset = ram_addr - block->offset;
2242 rcu_read_unlock();
2243 return block;
2246 rcu_read_lock();
2247 block = atomic_rcu_read(&ram_list.mru_block);
2248 if (block && block->host && host - block->host < block->max_length) {
2249 goto found;
2252 RAMBLOCK_FOREACH(block) {
2253 /* This case append when the block is not mapped. */
2254 if (block->host == NULL) {
2255 continue;
2257 if (host - block->host < block->max_length) {
2258 goto found;
2262 rcu_read_unlock();
2263 return NULL;
2265 found:
2266 *offset = (host - block->host);
2267 if (round_offset) {
2268 *offset &= TARGET_PAGE_MASK;
2270 rcu_read_unlock();
2271 return block;
2275 * Finds the named RAMBlock
2277 * name: The name of RAMBlock to find
2279 * Returns: RAMBlock (or NULL if not found)
2281 RAMBlock *qemu_ram_block_by_name(const char *name)
2283 RAMBlock *block;
2285 RAMBLOCK_FOREACH(block) {
2286 if (!strcmp(name, block->idstr)) {
2287 return block;
2291 return NULL;
2294 /* Some of the softmmu routines need to translate from a host pointer
2295 (typically a TLB entry) back to a ram offset. */
2296 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2298 RAMBlock *block;
2299 ram_addr_t offset;
2301 block = qemu_ram_block_from_host(ptr, false, &offset);
2302 if (!block) {
2303 return RAM_ADDR_INVALID;
2306 return block->offset + offset;
2309 /* Called within RCU critical section. */
2310 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2311 uint64_t val, unsigned size)
2313 bool locked = false;
2315 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2316 locked = true;
2317 tb_lock();
2318 tb_invalidate_phys_page_fast(ram_addr, size);
2320 switch (size) {
2321 case 1:
2322 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2323 break;
2324 case 2:
2325 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2326 break;
2327 case 4:
2328 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2329 break;
2330 default:
2331 abort();
2334 if (locked) {
2335 tb_unlock();
2338 /* Set both VGA and migration bits for simplicity and to remove
2339 * the notdirty callback faster.
2341 cpu_physical_memory_set_dirty_range(ram_addr, size,
2342 DIRTY_CLIENTS_NOCODE);
2343 /* we remove the notdirty callback only if the code has been
2344 flushed */
2345 if (!cpu_physical_memory_is_clean(ram_addr)) {
2346 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2350 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2351 unsigned size, bool is_write)
2353 return is_write;
2356 static const MemoryRegionOps notdirty_mem_ops = {
2357 .write = notdirty_mem_write,
2358 .valid.accepts = notdirty_mem_accepts,
2359 .endianness = DEVICE_NATIVE_ENDIAN,
2362 /* Generate a debug exception if a watchpoint has been hit. */
2363 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2365 CPUState *cpu = current_cpu;
2366 CPUClass *cc = CPU_GET_CLASS(cpu);
2367 CPUArchState *env = cpu->env_ptr;
2368 target_ulong pc, cs_base;
2369 target_ulong vaddr;
2370 CPUWatchpoint *wp;
2371 uint32_t cpu_flags;
2373 if (cpu->watchpoint_hit) {
2374 /* We re-entered the check after replacing the TB. Now raise
2375 * the debug interrupt so that is will trigger after the
2376 * current instruction. */
2377 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2378 return;
2380 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2381 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2382 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2383 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2384 && (wp->flags & flags)) {
2385 if (flags == BP_MEM_READ) {
2386 wp->flags |= BP_WATCHPOINT_HIT_READ;
2387 } else {
2388 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2390 wp->hitaddr = vaddr;
2391 wp->hitattrs = attrs;
2392 if (!cpu->watchpoint_hit) {
2393 if (wp->flags & BP_CPU &&
2394 !cc->debug_check_watchpoint(cpu, wp)) {
2395 wp->flags &= ~BP_WATCHPOINT_HIT;
2396 continue;
2398 cpu->watchpoint_hit = wp;
2400 /* Both tb_lock and iothread_mutex will be reset when
2401 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2402 * back into the cpu_exec main loop.
2404 tb_lock();
2405 tb_check_watchpoint(cpu);
2406 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2407 cpu->exception_index = EXCP_DEBUG;
2408 cpu_loop_exit(cpu);
2409 } else {
2410 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2411 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2412 cpu_loop_exit_noexc(cpu);
2415 } else {
2416 wp->flags &= ~BP_WATCHPOINT_HIT;
2421 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2422 so these check for a hit then pass through to the normal out-of-line
2423 phys routines. */
2424 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2425 unsigned size, MemTxAttrs attrs)
2427 MemTxResult res;
2428 uint64_t data;
2429 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2430 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2432 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2433 switch (size) {
2434 case 1:
2435 data = address_space_ldub(as, addr, attrs, &res);
2436 break;
2437 case 2:
2438 data = address_space_lduw(as, addr, attrs, &res);
2439 break;
2440 case 4:
2441 data = address_space_ldl(as, addr, attrs, &res);
2442 break;
2443 default: abort();
2445 *pdata = data;
2446 return res;
2449 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2450 uint64_t val, unsigned size,
2451 MemTxAttrs attrs)
2453 MemTxResult res;
2454 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2455 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2457 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2458 switch (size) {
2459 case 1:
2460 address_space_stb(as, addr, val, attrs, &res);
2461 break;
2462 case 2:
2463 address_space_stw(as, addr, val, attrs, &res);
2464 break;
2465 case 4:
2466 address_space_stl(as, addr, val, attrs, &res);
2467 break;
2468 default: abort();
2470 return res;
2473 static const MemoryRegionOps watch_mem_ops = {
2474 .read_with_attrs = watch_mem_read,
2475 .write_with_attrs = watch_mem_write,
2476 .endianness = DEVICE_NATIVE_ENDIAN,
2479 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2480 unsigned len, MemTxAttrs attrs)
2482 subpage_t *subpage = opaque;
2483 uint8_t buf[8];
2484 MemTxResult res;
2486 #if defined(DEBUG_SUBPAGE)
2487 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2488 subpage, len, addr);
2489 #endif
2490 res = address_space_read(subpage->as, addr + subpage->base,
2491 attrs, buf, len);
2492 if (res) {
2493 return res;
2495 switch (len) {
2496 case 1:
2497 *data = ldub_p(buf);
2498 return MEMTX_OK;
2499 case 2:
2500 *data = lduw_p(buf);
2501 return MEMTX_OK;
2502 case 4:
2503 *data = ldl_p(buf);
2504 return MEMTX_OK;
2505 case 8:
2506 *data = ldq_p(buf);
2507 return MEMTX_OK;
2508 default:
2509 abort();
2513 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2514 uint64_t value, unsigned len, MemTxAttrs attrs)
2516 subpage_t *subpage = opaque;
2517 uint8_t buf[8];
2519 #if defined(DEBUG_SUBPAGE)
2520 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2521 " value %"PRIx64"\n",
2522 __func__, subpage, len, addr, value);
2523 #endif
2524 switch (len) {
2525 case 1:
2526 stb_p(buf, value);
2527 break;
2528 case 2:
2529 stw_p(buf, value);
2530 break;
2531 case 4:
2532 stl_p(buf, value);
2533 break;
2534 case 8:
2535 stq_p(buf, value);
2536 break;
2537 default:
2538 abort();
2540 return address_space_write(subpage->as, addr + subpage->base,
2541 attrs, buf, len);
2544 static bool subpage_accepts(void *opaque, hwaddr addr,
2545 unsigned len, bool is_write)
2547 subpage_t *subpage = opaque;
2548 #if defined(DEBUG_SUBPAGE)
2549 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2550 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2551 #endif
2553 return address_space_access_valid(subpage->as, addr + subpage->base,
2554 len, is_write);
2557 static const MemoryRegionOps subpage_ops = {
2558 .read_with_attrs = subpage_read,
2559 .write_with_attrs = subpage_write,
2560 .impl.min_access_size = 1,
2561 .impl.max_access_size = 8,
2562 .valid.min_access_size = 1,
2563 .valid.max_access_size = 8,
2564 .valid.accepts = subpage_accepts,
2565 .endianness = DEVICE_NATIVE_ENDIAN,
2568 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2569 uint16_t section)
2571 int idx, eidx;
2573 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2574 return -1;
2575 idx = SUBPAGE_IDX(start);
2576 eidx = SUBPAGE_IDX(end);
2577 #if defined(DEBUG_SUBPAGE)
2578 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2579 __func__, mmio, start, end, idx, eidx, section);
2580 #endif
2581 for (; idx <= eidx; idx++) {
2582 mmio->sub_section[idx] = section;
2585 return 0;
2588 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2590 subpage_t *mmio;
2592 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2593 mmio->as = as;
2594 mmio->base = base;
2595 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2596 NULL, TARGET_PAGE_SIZE);
2597 mmio->iomem.subpage = true;
2598 #if defined(DEBUG_SUBPAGE)
2599 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2600 mmio, base, TARGET_PAGE_SIZE);
2601 #endif
2602 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2604 return mmio;
2607 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2608 MemoryRegion *mr)
2610 assert(as);
2611 MemoryRegionSection section = {
2612 .address_space = as,
2613 .mr = mr,
2614 .offset_within_address_space = 0,
2615 .offset_within_region = 0,
2616 .size = int128_2_64(),
2619 return phys_section_add(map, &section);
2622 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2624 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2625 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2626 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2627 MemoryRegionSection *sections = d->map.sections;
2629 return sections[index & ~TARGET_PAGE_MASK].mr;
2632 static void io_mem_init(void)
2634 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2635 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2636 NULL, UINT64_MAX);
2638 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2639 * which can be called without the iothread mutex.
2641 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2642 NULL, UINT64_MAX);
2643 memory_region_clear_global_locking(&io_mem_notdirty);
2645 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2646 NULL, UINT64_MAX);
2649 static void mem_begin(MemoryListener *listener)
2651 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2652 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2653 uint16_t n;
2655 n = dummy_section(&d->map, as, &io_mem_unassigned);
2656 assert(n == PHYS_SECTION_UNASSIGNED);
2657 n = dummy_section(&d->map, as, &io_mem_notdirty);
2658 assert(n == PHYS_SECTION_NOTDIRTY);
2659 n = dummy_section(&d->map, as, &io_mem_rom);
2660 assert(n == PHYS_SECTION_ROM);
2661 n = dummy_section(&d->map, as, &io_mem_watch);
2662 assert(n == PHYS_SECTION_WATCH);
2664 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2665 d->as = as;
2666 as->next_dispatch = d;
2669 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2671 phys_sections_free(&d->map);
2672 g_free(d);
2675 static void mem_commit(MemoryListener *listener)
2677 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2678 AddressSpaceDispatch *cur = as->dispatch;
2679 AddressSpaceDispatch *next = as->next_dispatch;
2681 phys_page_compact_all(next, next->map.nodes_nb);
2683 atomic_rcu_set(&as->dispatch, next);
2684 if (cur) {
2685 call_rcu(cur, address_space_dispatch_free, rcu);
2689 static void tcg_commit(MemoryListener *listener)
2691 CPUAddressSpace *cpuas;
2692 AddressSpaceDispatch *d;
2694 /* since each CPU stores ram addresses in its TLB cache, we must
2695 reset the modified entries */
2696 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2697 cpu_reloading_memory_map();
2698 /* The CPU and TLB are protected by the iothread lock.
2699 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2700 * may have split the RCU critical section.
2702 d = atomic_rcu_read(&cpuas->as->dispatch);
2703 atomic_rcu_set(&cpuas->memory_dispatch, d);
2704 tlb_flush(cpuas->cpu);
2707 void address_space_init_dispatch(AddressSpace *as)
2709 as->dispatch = NULL;
2710 as->dispatch_listener = (MemoryListener) {
2711 .begin = mem_begin,
2712 .commit = mem_commit,
2713 .region_add = mem_add,
2714 .region_nop = mem_add,
2715 .priority = 0,
2717 memory_listener_register(&as->dispatch_listener, as);
2720 void address_space_unregister(AddressSpace *as)
2722 memory_listener_unregister(&as->dispatch_listener);
2725 void address_space_destroy_dispatch(AddressSpace *as)
2727 AddressSpaceDispatch *d = as->dispatch;
2729 atomic_rcu_set(&as->dispatch, NULL);
2730 if (d) {
2731 call_rcu(d, address_space_dispatch_free, rcu);
2735 static void memory_map_init(void)
2737 system_memory = g_malloc(sizeof(*system_memory));
2739 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2740 address_space_init(&address_space_memory, system_memory, "memory");
2742 system_io = g_malloc(sizeof(*system_io));
2743 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2744 65536);
2745 address_space_init(&address_space_io, system_io, "I/O");
2748 MemoryRegion *get_system_memory(void)
2750 return system_memory;
2753 MemoryRegion *get_system_io(void)
2755 return system_io;
2758 #endif /* !defined(CONFIG_USER_ONLY) */
2760 /* physical memory access (slow version, mainly for debug) */
2761 #if defined(CONFIG_USER_ONLY)
2762 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2763 uint8_t *buf, int len, int is_write)
2765 int l, flags;
2766 target_ulong page;
2767 void * p;
2769 while (len > 0) {
2770 page = addr & TARGET_PAGE_MASK;
2771 l = (page + TARGET_PAGE_SIZE) - addr;
2772 if (l > len)
2773 l = len;
2774 flags = page_get_flags(page);
2775 if (!(flags & PAGE_VALID))
2776 return -1;
2777 if (is_write) {
2778 if (!(flags & PAGE_WRITE))
2779 return -1;
2780 /* XXX: this code should not depend on lock_user */
2781 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2782 return -1;
2783 memcpy(p, buf, l);
2784 unlock_user(p, addr, l);
2785 } else {
2786 if (!(flags & PAGE_READ))
2787 return -1;
2788 /* XXX: this code should not depend on lock_user */
2789 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2790 return -1;
2791 memcpy(buf, p, l);
2792 unlock_user(p, addr, 0);
2794 len -= l;
2795 buf += l;
2796 addr += l;
2798 return 0;
2801 #else
2803 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2804 hwaddr length)
2806 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2807 addr += memory_region_get_ram_addr(mr);
2809 /* No early return if dirty_log_mask is or becomes 0, because
2810 * cpu_physical_memory_set_dirty_range will still call
2811 * xen_modified_memory.
2813 if (dirty_log_mask) {
2814 dirty_log_mask =
2815 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2817 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2818 tb_lock();
2819 tb_invalidate_phys_range(addr, addr + length);
2820 tb_unlock();
2821 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2823 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2826 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2828 unsigned access_size_max = mr->ops->valid.max_access_size;
2830 /* Regions are assumed to support 1-4 byte accesses unless
2831 otherwise specified. */
2832 if (access_size_max == 0) {
2833 access_size_max = 4;
2836 /* Bound the maximum access by the alignment of the address. */
2837 if (!mr->ops->impl.unaligned) {
2838 unsigned align_size_max = addr & -addr;
2839 if (align_size_max != 0 && align_size_max < access_size_max) {
2840 access_size_max = align_size_max;
2844 /* Don't attempt accesses larger than the maximum. */
2845 if (l > access_size_max) {
2846 l = access_size_max;
2848 l = pow2floor(l);
2850 return l;
2853 static bool prepare_mmio_access(MemoryRegion *mr)
2855 bool unlocked = !qemu_mutex_iothread_locked();
2856 bool release_lock = false;
2858 if (unlocked && mr->global_locking) {
2859 qemu_mutex_lock_iothread();
2860 unlocked = false;
2861 release_lock = true;
2863 if (mr->flush_coalesced_mmio) {
2864 if (unlocked) {
2865 qemu_mutex_lock_iothread();
2867 qemu_flush_coalesced_mmio_buffer();
2868 if (unlocked) {
2869 qemu_mutex_unlock_iothread();
2873 return release_lock;
2876 /* Called within RCU critical section. */
2877 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2878 MemTxAttrs attrs,
2879 const uint8_t *buf,
2880 int len, hwaddr addr1,
2881 hwaddr l, MemoryRegion *mr)
2883 uint8_t *ptr;
2884 uint64_t val;
2885 MemTxResult result = MEMTX_OK;
2886 bool release_lock = false;
2888 for (;;) {
2889 if (!memory_access_is_direct(mr, true)) {
2890 release_lock |= prepare_mmio_access(mr);
2891 l = memory_access_size(mr, l, addr1);
2892 /* XXX: could force current_cpu to NULL to avoid
2893 potential bugs */
2894 switch (l) {
2895 case 8:
2896 /* 64 bit write access */
2897 val = ldq_p(buf);
2898 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2899 attrs);
2900 break;
2901 case 4:
2902 /* 32 bit write access */
2903 val = (uint32_t)ldl_p(buf);
2904 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2905 attrs);
2906 break;
2907 case 2:
2908 /* 16 bit write access */
2909 val = lduw_p(buf);
2910 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2911 attrs);
2912 break;
2913 case 1:
2914 /* 8 bit write access */
2915 val = ldub_p(buf);
2916 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2917 attrs);
2918 break;
2919 default:
2920 abort();
2922 } else {
2923 /* RAM case */
2924 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2925 memcpy(ptr, buf, l);
2926 invalidate_and_set_dirty(mr, addr1, l);
2929 if (release_lock) {
2930 qemu_mutex_unlock_iothread();
2931 release_lock = false;
2934 len -= l;
2935 buf += l;
2936 addr += l;
2938 if (!len) {
2939 break;
2942 l = len;
2943 mr = address_space_translate(as, addr, &addr1, &l, true);
2946 return result;
2949 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2950 const uint8_t *buf, int len)
2952 hwaddr l;
2953 hwaddr addr1;
2954 MemoryRegion *mr;
2955 MemTxResult result = MEMTX_OK;
2957 if (len > 0) {
2958 rcu_read_lock();
2959 l = len;
2960 mr = address_space_translate(as, addr, &addr1, &l, true);
2961 result = address_space_write_continue(as, addr, attrs, buf, len,
2962 addr1, l, mr);
2963 rcu_read_unlock();
2966 return result;
2969 /* Called within RCU critical section. */
2970 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2971 MemTxAttrs attrs, uint8_t *buf,
2972 int len, hwaddr addr1, hwaddr l,
2973 MemoryRegion *mr)
2975 uint8_t *ptr;
2976 uint64_t val;
2977 MemTxResult result = MEMTX_OK;
2978 bool release_lock = false;
2980 for (;;) {
2981 if (!memory_access_is_direct(mr, false)) {
2982 /* I/O case */
2983 release_lock |= prepare_mmio_access(mr);
2984 l = memory_access_size(mr, l, addr1);
2985 switch (l) {
2986 case 8:
2987 /* 64 bit read access */
2988 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2989 attrs);
2990 stq_p(buf, val);
2991 break;
2992 case 4:
2993 /* 32 bit read access */
2994 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2995 attrs);
2996 stl_p(buf, val);
2997 break;
2998 case 2:
2999 /* 16 bit read access */
3000 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
3001 attrs);
3002 stw_p(buf, val);
3003 break;
3004 case 1:
3005 /* 8 bit read access */
3006 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
3007 attrs);
3008 stb_p(buf, val);
3009 break;
3010 default:
3011 abort();
3013 } else {
3014 /* RAM case */
3015 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3016 memcpy(buf, ptr, l);
3019 if (release_lock) {
3020 qemu_mutex_unlock_iothread();
3021 release_lock = false;
3024 len -= l;
3025 buf += l;
3026 addr += l;
3028 if (!len) {
3029 break;
3032 l = len;
3033 mr = address_space_translate(as, addr, &addr1, &l, false);
3036 return result;
3039 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3040 MemTxAttrs attrs, uint8_t *buf, int len)
3042 hwaddr l;
3043 hwaddr addr1;
3044 MemoryRegion *mr;
3045 MemTxResult result = MEMTX_OK;
3047 if (len > 0) {
3048 rcu_read_lock();
3049 l = len;
3050 mr = address_space_translate(as, addr, &addr1, &l, false);
3051 result = address_space_read_continue(as, addr, attrs, buf, len,
3052 addr1, l, mr);
3053 rcu_read_unlock();
3056 return result;
3059 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3060 uint8_t *buf, int len, bool is_write)
3062 if (is_write) {
3063 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
3064 } else {
3065 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
3069 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3070 int len, int is_write)
3072 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3073 buf, len, is_write);
3076 enum write_rom_type {
3077 WRITE_DATA,
3078 FLUSH_CACHE,
3081 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3082 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3084 hwaddr l;
3085 uint8_t *ptr;
3086 hwaddr addr1;
3087 MemoryRegion *mr;
3089 rcu_read_lock();
3090 while (len > 0) {
3091 l = len;
3092 mr = address_space_translate(as, addr, &addr1, &l, true);
3094 if (!(memory_region_is_ram(mr) ||
3095 memory_region_is_romd(mr))) {
3096 l = memory_access_size(mr, l, addr1);
3097 } else {
3098 /* ROM/RAM case */
3099 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3100 switch (type) {
3101 case WRITE_DATA:
3102 memcpy(ptr, buf, l);
3103 invalidate_and_set_dirty(mr, addr1, l);
3104 break;
3105 case FLUSH_CACHE:
3106 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3107 break;
3110 len -= l;
3111 buf += l;
3112 addr += l;
3114 rcu_read_unlock();
3117 /* used for ROM loading : can write in RAM and ROM */
3118 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3119 const uint8_t *buf, int len)
3121 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3124 void cpu_flush_icache_range(hwaddr start, int len)
3127 * This function should do the same thing as an icache flush that was
3128 * triggered from within the guest. For TCG we are always cache coherent,
3129 * so there is no need to flush anything. For KVM / Xen we need to flush
3130 * the host's instruction cache at least.
3132 if (tcg_enabled()) {
3133 return;
3136 cpu_physical_memory_write_rom_internal(&address_space_memory,
3137 start, NULL, len, FLUSH_CACHE);
3140 typedef struct {
3141 MemoryRegion *mr;
3142 void *buffer;
3143 hwaddr addr;
3144 hwaddr len;
3145 bool in_use;
3146 } BounceBuffer;
3148 static BounceBuffer bounce;
3150 typedef struct MapClient {
3151 QEMUBH *bh;
3152 QLIST_ENTRY(MapClient) link;
3153 } MapClient;
3155 QemuMutex map_client_list_lock;
3156 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3157 = QLIST_HEAD_INITIALIZER(map_client_list);
3159 static void cpu_unregister_map_client_do(MapClient *client)
3161 QLIST_REMOVE(client, link);
3162 g_free(client);
3165 static void cpu_notify_map_clients_locked(void)
3167 MapClient *client;
3169 while (!QLIST_EMPTY(&map_client_list)) {
3170 client = QLIST_FIRST(&map_client_list);
3171 qemu_bh_schedule(client->bh);
3172 cpu_unregister_map_client_do(client);
3176 void cpu_register_map_client(QEMUBH *bh)
3178 MapClient *client = g_malloc(sizeof(*client));
3180 qemu_mutex_lock(&map_client_list_lock);
3181 client->bh = bh;
3182 QLIST_INSERT_HEAD(&map_client_list, client, link);
3183 if (!atomic_read(&bounce.in_use)) {
3184 cpu_notify_map_clients_locked();
3186 qemu_mutex_unlock(&map_client_list_lock);
3189 void cpu_exec_init_all(void)
3191 qemu_mutex_init(&ram_list.mutex);
3192 /* The data structures we set up here depend on knowing the page size,
3193 * so no more changes can be made after this point.
3194 * In an ideal world, nothing we did before we had finished the
3195 * machine setup would care about the target page size, and we could
3196 * do this much later, rather than requiring board models to state
3197 * up front what their requirements are.
3199 finalize_target_page_bits();
3200 io_mem_init();
3201 memory_map_init();
3202 qemu_mutex_init(&map_client_list_lock);
3205 void cpu_unregister_map_client(QEMUBH *bh)
3207 MapClient *client;
3209 qemu_mutex_lock(&map_client_list_lock);
3210 QLIST_FOREACH(client, &map_client_list, link) {
3211 if (client->bh == bh) {
3212 cpu_unregister_map_client_do(client);
3213 break;
3216 qemu_mutex_unlock(&map_client_list_lock);
3219 static void cpu_notify_map_clients(void)
3221 qemu_mutex_lock(&map_client_list_lock);
3222 cpu_notify_map_clients_locked();
3223 qemu_mutex_unlock(&map_client_list_lock);
3226 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3228 MemoryRegion *mr;
3229 hwaddr l, xlat;
3231 rcu_read_lock();
3232 while (len > 0) {
3233 l = len;
3234 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3235 if (!memory_access_is_direct(mr, is_write)) {
3236 l = memory_access_size(mr, l, addr);
3237 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3238 rcu_read_unlock();
3239 return false;
3243 len -= l;
3244 addr += l;
3246 rcu_read_unlock();
3247 return true;
3250 static hwaddr
3251 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3252 MemoryRegion *mr, hwaddr base, hwaddr len,
3253 bool is_write)
3255 hwaddr done = 0;
3256 hwaddr xlat;
3257 MemoryRegion *this_mr;
3259 for (;;) {
3260 target_len -= len;
3261 addr += len;
3262 done += len;
3263 if (target_len == 0) {
3264 return done;
3267 len = target_len;
3268 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3269 if (this_mr != mr || xlat != base + done) {
3270 return done;
3275 /* Map a physical memory region into a host virtual address.
3276 * May map a subset of the requested range, given by and returned in *plen.
3277 * May return NULL if resources needed to perform the mapping are exhausted.
3278 * Use only for reads OR writes - not for read-modify-write operations.
3279 * Use cpu_register_map_client() to know when retrying the map operation is
3280 * likely to succeed.
3282 void *address_space_map(AddressSpace *as,
3283 hwaddr addr,
3284 hwaddr *plen,
3285 bool is_write)
3287 hwaddr len = *plen;
3288 hwaddr l, xlat;
3289 MemoryRegion *mr;
3290 void *ptr;
3292 if (len == 0) {
3293 return NULL;
3296 l = len;
3297 rcu_read_lock();
3298 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3300 if (!memory_access_is_direct(mr, is_write)) {
3301 if (atomic_xchg(&bounce.in_use, true)) {
3302 rcu_read_unlock();
3303 return NULL;
3305 /* Avoid unbounded allocations */
3306 l = MIN(l, TARGET_PAGE_SIZE);
3307 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3308 bounce.addr = addr;
3309 bounce.len = l;
3311 memory_region_ref(mr);
3312 bounce.mr = mr;
3313 if (!is_write) {
3314 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3315 bounce.buffer, l);
3318 rcu_read_unlock();
3319 *plen = l;
3320 return bounce.buffer;
3324 memory_region_ref(mr);
3325 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3326 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3327 rcu_read_unlock();
3329 return ptr;
3332 /* Unmaps a memory region previously mapped by address_space_map().
3333 * Will also mark the memory as dirty if is_write == 1. access_len gives
3334 * the amount of memory that was actually read or written by the caller.
3336 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3337 int is_write, hwaddr access_len)
3339 if (buffer != bounce.buffer) {
3340 MemoryRegion *mr;
3341 ram_addr_t addr1;
3343 mr = memory_region_from_host(buffer, &addr1);
3344 assert(mr != NULL);
3345 if (is_write) {
3346 invalidate_and_set_dirty(mr, addr1, access_len);
3348 if (xen_enabled()) {
3349 xen_invalidate_map_cache_entry(buffer);
3351 memory_region_unref(mr);
3352 return;
3354 if (is_write) {
3355 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3356 bounce.buffer, access_len);
3358 qemu_vfree(bounce.buffer);
3359 bounce.buffer = NULL;
3360 memory_region_unref(bounce.mr);
3361 atomic_mb_set(&bounce.in_use, false);
3362 cpu_notify_map_clients();
3365 void *cpu_physical_memory_map(hwaddr addr,
3366 hwaddr *plen,
3367 int is_write)
3369 return address_space_map(&address_space_memory, addr, plen, is_write);
3372 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3373 int is_write, hwaddr access_len)
3375 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3378 #define ARG1_DECL AddressSpace *as
3379 #define ARG1 as
3380 #define SUFFIX
3381 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3382 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3383 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3384 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3385 #define RCU_READ_LOCK(...) rcu_read_lock()
3386 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3387 #include "memory_ldst.inc.c"
3389 int64_t address_space_cache_init(MemoryRegionCache *cache,
3390 AddressSpace *as,
3391 hwaddr addr,
3392 hwaddr len,
3393 bool is_write)
3395 cache->len = len;
3396 cache->as = as;
3397 cache->xlat = addr;
3398 return len;
3401 void address_space_cache_invalidate(MemoryRegionCache *cache,
3402 hwaddr addr,
3403 hwaddr access_len)
3407 void address_space_cache_destroy(MemoryRegionCache *cache)
3409 cache->as = NULL;
3412 #define ARG1_DECL MemoryRegionCache *cache
3413 #define ARG1 cache
3414 #define SUFFIX _cached
3415 #define TRANSLATE(addr, ...) \
3416 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3417 #define IS_DIRECT(mr, is_write) true
3418 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3419 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3420 #define RCU_READ_LOCK() rcu_read_lock()
3421 #define RCU_READ_UNLOCK() rcu_read_unlock()
3422 #include "memory_ldst.inc.c"
3424 /* virtual memory access for debug (includes writing to ROM) */
3425 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3426 uint8_t *buf, int len, int is_write)
3428 int l;
3429 hwaddr phys_addr;
3430 target_ulong page;
3432 cpu_synchronize_state(cpu);
3433 while (len > 0) {
3434 int asidx;
3435 MemTxAttrs attrs;
3437 page = addr & TARGET_PAGE_MASK;
3438 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3439 asidx = cpu_asidx_from_attrs(cpu, attrs);
3440 /* if no physical page mapped, return an error */
3441 if (phys_addr == -1)
3442 return -1;
3443 l = (page + TARGET_PAGE_SIZE) - addr;
3444 if (l > len)
3445 l = len;
3446 phys_addr += (addr & ~TARGET_PAGE_MASK);
3447 if (is_write) {
3448 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3449 phys_addr, buf, l);
3450 } else {
3451 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3452 MEMTXATTRS_UNSPECIFIED,
3453 buf, l, 0);
3455 len -= l;
3456 buf += l;
3457 addr += l;
3459 return 0;
3463 * Allows code that needs to deal with migration bitmaps etc to still be built
3464 * target independent.
3466 size_t qemu_target_page_size(void)
3468 return TARGET_PAGE_SIZE;
3471 int qemu_target_page_bits(void)
3473 return TARGET_PAGE_BITS;
3476 int qemu_target_page_bits_min(void)
3478 return TARGET_PAGE_BITS_MIN;
3480 #endif
3483 * A helper function for the _utterly broken_ virtio device model to find out if
3484 * it's running on a big endian machine. Don't do this at home kids!
3486 bool target_words_bigendian(void);
3487 bool target_words_bigendian(void)
3489 #if defined(TARGET_WORDS_BIGENDIAN)
3490 return true;
3491 #else
3492 return false;
3493 #endif
3496 #ifndef CONFIG_USER_ONLY
3497 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3499 MemoryRegion*mr;
3500 hwaddr l = 1;
3501 bool res;
3503 rcu_read_lock();
3504 mr = address_space_translate(&address_space_memory,
3505 phys_addr, &phys_addr, &l, false);
3507 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3508 rcu_read_unlock();
3509 return res;
3512 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3514 RAMBlock *block;
3515 int ret = 0;
3517 rcu_read_lock();
3518 RAMBLOCK_FOREACH(block) {
3519 ret = func(block->idstr, block->host, block->offset,
3520 block->used_length, opaque);
3521 if (ret) {
3522 break;
3525 rcu_read_unlock();
3526 return ret;
3530 * Unmap pages of memory from start to start+length such that
3531 * they a) read as 0, b) Trigger whatever fault mechanism
3532 * the OS provides for postcopy.
3533 * The pages must be unmapped by the end of the function.
3534 * Returns: 0 on success, none-0 on failure
3537 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3539 int ret = -1;
3541 uint8_t *host_startaddr = rb->host + start;
3543 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3544 error_report("ram_block_discard_range: Unaligned start address: %p",
3545 host_startaddr);
3546 goto err;
3549 if ((start + length) <= rb->used_length) {
3550 uint8_t *host_endaddr = host_startaddr + length;
3551 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3552 error_report("ram_block_discard_range: Unaligned end address: %p",
3553 host_endaddr);
3554 goto err;
3557 errno = ENOTSUP; /* If we are missing MADVISE etc */
3559 if (rb->page_size == qemu_host_page_size) {
3560 #if defined(CONFIG_MADVISE)
3561 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3562 * freeing the page.
3564 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3565 #endif
3566 } else {
3567 /* Huge page case - unfortunately it can't do DONTNEED, but
3568 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3569 * huge page file.
3571 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3572 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3573 start, length);
3574 #endif
3576 if (ret) {
3577 ret = -errno;
3578 error_report("ram_block_discard_range: Failed to discard range "
3579 "%s:%" PRIx64 " +%zx (%d)",
3580 rb->idstr, start, length, ret);
3582 } else {
3583 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3584 "/%zx/" RAM_ADDR_FMT")",
3585 rb->idstr, start, length, rb->used_length);
3588 err:
3589 return ret;
3592 #endif