2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-timer.h"
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #define DPRINTF(...) do {} while (0)
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
51 /* Very pessimistic, let's hope it's enough for all cases */
52 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
53 /* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
58 #define OFF_OPER LEN_CAP
59 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
60 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
61 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
62 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
63 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
65 /* must be power of 2 */
66 #define LEN_REGS 0x2000
68 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69 # error Increase LEN_REGS
73 # error TODO: only one interrupter supported
77 #define USBCMD_RS (1<<0)
78 #define USBCMD_HCRST (1<<1)
79 #define USBCMD_INTE (1<<2)
80 #define USBCMD_HSEE (1<<3)
81 #define USBCMD_LHCRST (1<<7)
82 #define USBCMD_CSS (1<<8)
83 #define USBCMD_CRS (1<<9)
84 #define USBCMD_EWE (1<<10)
85 #define USBCMD_EU3S (1<<11)
87 #define USBSTS_HCH (1<<0)
88 #define USBSTS_HSE (1<<2)
89 #define USBSTS_EINT (1<<3)
90 #define USBSTS_PCD (1<<4)
91 #define USBSTS_SSS (1<<8)
92 #define USBSTS_RSS (1<<9)
93 #define USBSTS_SRE (1<<10)
94 #define USBSTS_CNR (1<<11)
95 #define USBSTS_HCE (1<<12)
98 #define PORTSC_CCS (1<<0)
99 #define PORTSC_PED (1<<1)
100 #define PORTSC_OCA (1<<3)
101 #define PORTSC_PR (1<<4)
102 #define PORTSC_PLS_SHIFT 5
103 #define PORTSC_PLS_MASK 0xf
104 #define PORTSC_PP (1<<9)
105 #define PORTSC_SPEED_SHIFT 10
106 #define PORTSC_SPEED_MASK 0xf
107 #define PORTSC_SPEED_FULL (1<<10)
108 #define PORTSC_SPEED_LOW (2<<10)
109 #define PORTSC_SPEED_HIGH (3<<10)
110 #define PORTSC_SPEED_SUPER (4<<10)
111 #define PORTSC_PIC_SHIFT 14
112 #define PORTSC_PIC_MASK 0x3
113 #define PORTSC_LWS (1<<16)
114 #define PORTSC_CSC (1<<17)
115 #define PORTSC_PEC (1<<18)
116 #define PORTSC_WRC (1<<19)
117 #define PORTSC_OCC (1<<20)
118 #define PORTSC_PRC (1<<21)
119 #define PORTSC_PLC (1<<22)
120 #define PORTSC_CEC (1<<23)
121 #define PORTSC_CAS (1<<24)
122 #define PORTSC_WCE (1<<25)
123 #define PORTSC_WDE (1<<26)
124 #define PORTSC_WOE (1<<27)
125 #define PORTSC_DR (1<<30)
126 #define PORTSC_WPR (1<<31)
128 #define CRCR_RCS (1<<0)
129 #define CRCR_CS (1<<1)
130 #define CRCR_CA (1<<2)
131 #define CRCR_CRR (1<<3)
133 #define IMAN_IP (1<<0)
134 #define IMAN_IE (1<<1)
136 #define ERDP_EHB (1<<3)
139 typedef struct XHCITRB
{
148 typedef enum TRBType
{
161 CR_CONFIGURE_ENDPOINT
,
169 CR_SET_LATENCY_TOLERANCE
,
170 CR_GET_PORT_BANDWIDTH
,
175 ER_PORT_STATUS_CHANGE
,
176 ER_BANDWIDTH_REQUEST
,
179 ER_DEVICE_NOTIFICATION
,
181 /* vendor specific bits */
182 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
183 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
184 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
187 #define CR_LINK TR_LINK
189 typedef enum TRBCCode
{
192 CC_DATA_BUFFER_ERROR
,
194 CC_USB_TRANSACTION_ERROR
,
200 CC_INVALID_STREAM_TYPE_ERROR
,
201 CC_SLOT_NOT_ENABLED_ERROR
,
202 CC_EP_NOT_ENABLED_ERROR
,
208 CC_BANDWIDTH_OVERRUN
,
209 CC_CONTEXT_STATE_ERROR
,
210 CC_NO_PING_RESPONSE_ERROR
,
211 CC_EVENT_RING_FULL_ERROR
,
212 CC_INCOMPATIBLE_DEVICE_ERROR
,
213 CC_MISSED_SERVICE_ERROR
,
214 CC_COMMAND_RING_STOPPED
,
217 CC_STOPPED_LENGTH_INVALID
,
218 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
219 CC_ISOCH_BUFFER_OVERRUN
= 31,
222 CC_INVALID_STREAM_ID_ERROR
,
223 CC_SECONDARY_BANDWIDTH_ERROR
,
224 CC_SPLIT_TRANSACTION_ERROR
228 #define TRB_TYPE_SHIFT 10
229 #define TRB_TYPE_MASK 0x3f
230 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
232 #define TRB_EV_ED (1<<2)
234 #define TRB_TR_ENT (1<<1)
235 #define TRB_TR_ISP (1<<2)
236 #define TRB_TR_NS (1<<3)
237 #define TRB_TR_CH (1<<4)
238 #define TRB_TR_IOC (1<<5)
239 #define TRB_TR_IDT (1<<6)
240 #define TRB_TR_TBC_SHIFT 7
241 #define TRB_TR_TBC_MASK 0x3
242 #define TRB_TR_BEI (1<<9)
243 #define TRB_TR_TLBPC_SHIFT 16
244 #define TRB_TR_TLBPC_MASK 0xf
245 #define TRB_TR_FRAMEID_SHIFT 20
246 #define TRB_TR_FRAMEID_MASK 0x7ff
247 #define TRB_TR_SIA (1<<31)
249 #define TRB_TR_DIR (1<<16)
251 #define TRB_CR_SLOTID_SHIFT 24
252 #define TRB_CR_SLOTID_MASK 0xff
253 #define TRB_CR_EPID_SHIFT 16
254 #define TRB_CR_EPID_MASK 0x1f
256 #define TRB_CR_BSR (1<<9)
257 #define TRB_CR_DC (1<<9)
259 #define TRB_LK_TC (1<<1)
261 #define EP_TYPE_MASK 0x7
262 #define EP_TYPE_SHIFT 3
264 #define EP_STATE_MASK 0x7
265 #define EP_DISABLED (0<<0)
266 #define EP_RUNNING (1<<0)
267 #define EP_HALTED (2<<0)
268 #define EP_STOPPED (3<<0)
269 #define EP_ERROR (4<<0)
271 #define SLOT_STATE_MASK 0x1f
272 #define SLOT_STATE_SHIFT 27
273 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
274 #define SLOT_ENABLED 0
275 #define SLOT_DEFAULT 1
276 #define SLOT_ADDRESSED 2
277 #define SLOT_CONFIGURED 3
279 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
280 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
282 typedef enum EPType
{
293 typedef struct XHCIRing
{
299 typedef struct XHCIPort
{
305 typedef struct XHCIState XHCIState
;
307 typedef struct XHCITransfer
{
315 unsigned int iso_pkts
;
322 unsigned int trb_count
;
323 unsigned int trb_alloced
;
326 unsigned int data_length
;
327 unsigned int data_alloced
;
333 unsigned int pktsize
;
334 unsigned int cur_pkt
;
337 typedef struct XHCIEPContext
{
339 unsigned int next_xfer
;
340 unsigned int comp_xfer
;
341 XHCITransfer transfers
[TD_QUEUE
];
345 unsigned int next_bg
;
346 XHCITransfer bg_transfers
[BG_XFERS
];
349 unsigned int max_psize
;
354 typedef struct XHCISlot
{
358 unsigned int devaddr
;
359 XHCIEPContext
* eps
[31];
362 typedef struct XHCIEvent
{
379 unsigned int devaddr
;
381 /* Operational Registers */
388 uint32_t dcbaap_high
;
391 XHCIPort ports
[MAXPORTS
];
392 XHCISlot slots
[MAXSLOTS
];
394 /* Runtime Registers */
396 /* note: we only support one interrupter */
401 uint32_t erstba_high
;
408 unsigned int er_ep_idx
;
411 XHCIEvent ev_buffer
[EV_QUEUE
];
412 unsigned int ev_buffer_put
;
413 unsigned int ev_buffer_get
;
418 typedef struct XHCIEvRingSeg
{
425 static const char *TRBType_names
[] = {
426 [TRB_RESERVED
] = "TRB_RESERVED",
427 [TR_NORMAL
] = "TR_NORMAL",
428 [TR_SETUP
] = "TR_SETUP",
429 [TR_DATA
] = "TR_DATA",
430 [TR_STATUS
] = "TR_STATUS",
431 [TR_ISOCH
] = "TR_ISOCH",
432 [TR_LINK
] = "TR_LINK",
433 [TR_EVDATA
] = "TR_EVDATA",
434 [TR_NOOP
] = "TR_NOOP",
435 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
436 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
437 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
438 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
439 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
440 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
441 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
442 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
443 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
444 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
445 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
446 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
447 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
448 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
449 [CR_NOOP
] = "CR_NOOP",
450 [ER_TRANSFER
] = "ER_TRANSFER",
451 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
452 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
453 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
454 [ER_DOORBELL
] = "ER_DOORBELL",
455 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
456 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
457 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
458 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
459 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
460 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
463 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
465 if (index
>= llen
|| list
[index
] == NULL
) {
471 static const char *trb_name(XHCITRB
*trb
)
473 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
474 ARRAY_SIZE(TRBType_names
));
477 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
480 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
482 if (sizeof(dma_addr_t
) == 4) {
485 return low
| (((dma_addr_t
)high
<< 16) << 16);
489 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
491 if (sizeof(dma_addr_t
) == 4) {
492 return addr
& 0xffffffff;
498 static void xhci_irq_update(XHCIState
*xhci
)
502 if (xhci
->iman
& IMAN_IP
&& xhci
->iman
& IMAN_IE
&&
503 xhci
->usbcmd
& USBCMD_INTE
) {
507 if (xhci
->msi
&& msi_enabled(&xhci
->pci_dev
)) {
509 trace_usb_xhci_irq_msi(0);
510 msi_notify(&xhci
->pci_dev
, 0);
513 trace_usb_xhci_irq_intx(level
);
514 qemu_set_irq(xhci
->irq
, level
);
518 static inline int xhci_running(XHCIState
*xhci
)
520 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->er_full
;
523 static void xhci_die(XHCIState
*xhci
)
525 xhci
->usbsts
|= USBSTS_HCE
;
526 fprintf(stderr
, "xhci: asserted controller error\n");
529 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
)
534 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
535 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
536 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
537 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
539 ev_trb
.control
|= TRB_C
;
541 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
543 trace_usb_xhci_queue_event(xhci
->er_ep_idx
, trb_name(&ev_trb
),
544 ev_trb
.parameter
, ev_trb
.status
, ev_trb
.control
);
546 addr
= xhci
->er_start
+ TRB_SIZE
*xhci
->er_ep_idx
;
547 pci_dma_write(&xhci
->pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
550 if (xhci
->er_ep_idx
>= xhci
->er_size
) {
552 xhci
->er_pcs
= !xhci
->er_pcs
;
556 static void xhci_events_update(XHCIState
*xhci
)
562 if (xhci
->usbsts
& USBSTS_HCH
) {
566 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
567 if (erdp
< xhci
->er_start
||
568 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
569 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
570 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
571 xhci
->er_start
, xhci
->er_size
);
575 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
576 assert(dp_idx
< xhci
->er_size
);
578 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
579 * deadlocks when the ER is full. Hack it by holding off events until
580 * the driver decides to free at least half of the ring */
582 int er_free
= dp_idx
- xhci
->er_ep_idx
;
584 er_free
+= xhci
->er_size
;
586 if (er_free
< (xhci
->er_size
/2)) {
587 DPRINTF("xhci_events_update(): event ring still "
588 "more than half full (hack)\n");
593 while (xhci
->ev_buffer_put
!= xhci
->ev_buffer_get
) {
594 assert(xhci
->er_full
);
595 if (((xhci
->er_ep_idx
+1) % xhci
->er_size
) == dp_idx
) {
596 DPRINTF("xhci_events_update(): event ring full again\n");
598 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
599 xhci_write_event(xhci
, &full
);
604 XHCIEvent
*event
= &xhci
->ev_buffer
[xhci
->ev_buffer_get
];
605 xhci_write_event(xhci
, event
);
606 xhci
->ev_buffer_get
++;
608 if (xhci
->ev_buffer_get
== EV_QUEUE
) {
609 xhci
->ev_buffer_get
= 0;
614 xhci
->erdp_low
|= ERDP_EHB
;
615 xhci
->iman
|= IMAN_IP
;
616 xhci
->usbsts
|= USBSTS_EINT
;
617 xhci_irq_update(xhci
);
620 if (xhci
->er_full
&& xhci
->ev_buffer_put
== xhci
->ev_buffer_get
) {
621 DPRINTF("xhci_events_update(): event ring no longer full\n");
627 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
)
633 DPRINTF("xhci_event(): ER full, queueing\n");
634 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
635 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
638 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
639 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
640 xhci
->ev_buffer_put
= 0;
645 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
646 if (erdp
< xhci
->er_start
||
647 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
648 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
649 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
650 xhci
->er_start
, xhci
->er_size
);
655 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
656 assert(dp_idx
< xhci
->er_size
);
658 if ((xhci
->er_ep_idx
+1) % xhci
->er_size
== dp_idx
) {
659 DPRINTF("xhci_event(): ER full, queueing\n");
661 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
662 xhci_write_event(xhci
, &full
);
665 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
666 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
669 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
670 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
671 xhci
->ev_buffer_put
= 0;
674 xhci_write_event(xhci
, event
);
677 xhci
->erdp_low
|= ERDP_EHB
;
678 xhci
->iman
|= IMAN_IP
;
679 xhci
->usbsts
|= USBSTS_EINT
;
681 xhci_irq_update(xhci
);
684 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
688 ring
->dequeue
= base
;
692 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
697 pci_dma_read(&xhci
->pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
698 trb
->addr
= ring
->dequeue
;
699 trb
->ccs
= ring
->ccs
;
700 le64_to_cpus(&trb
->parameter
);
701 le32_to_cpus(&trb
->status
);
702 le32_to_cpus(&trb
->control
);
704 DPRINTF("xhci: TRB fetched [" DMA_ADDR_FMT
"]: "
705 "%016" PRIx64
" %08x %08x %s\n",
706 ring
->dequeue
, trb
->parameter
, trb
->status
, trb
->control
,
709 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
713 type
= TRB_TYPE(*trb
);
715 if (type
!= TR_LINK
) {
717 *addr
= ring
->dequeue
;
719 ring
->dequeue
+= TRB_SIZE
;
722 ring
->dequeue
= xhci_mask64(trb
->parameter
);
723 if (trb
->control
& TRB_LK_TC
) {
724 ring
->ccs
= !ring
->ccs
;
730 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
734 dma_addr_t dequeue
= ring
->dequeue
;
735 bool ccs
= ring
->ccs
;
736 /* hack to bundle together the two/three TDs that make a setup transfer */
737 bool control_td_set
= 0;
741 pci_dma_read(&xhci
->pci_dev
, dequeue
, &trb
, TRB_SIZE
);
742 le64_to_cpus(&trb
.parameter
);
743 le32_to_cpus(&trb
.status
);
744 le32_to_cpus(&trb
.control
);
746 DPRINTF("xhci: TRB peeked [" DMA_ADDR_FMT
"]: "
747 "%016" PRIx64
" %08x %08x\n",
748 dequeue
, trb
.parameter
, trb
.status
, trb
.control
);
750 if ((trb
.control
& TRB_C
) != ccs
) {
754 type
= TRB_TYPE(trb
);
756 if (type
== TR_LINK
) {
757 dequeue
= xhci_mask64(trb
.parameter
);
758 if (trb
.control
& TRB_LK_TC
) {
767 if (type
== TR_SETUP
) {
769 } else if (type
== TR_STATUS
) {
773 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
779 static void xhci_er_reset(XHCIState
*xhci
)
783 /* cache the (sole) event ring segment location */
784 if (xhci
->erstsz
!= 1) {
785 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", xhci
->erstsz
);
789 dma_addr_t erstba
= xhci_addr64(xhci
->erstba_low
, xhci
->erstba_high
);
790 pci_dma_read(&xhci
->pci_dev
, erstba
, &seg
, sizeof(seg
));
791 le32_to_cpus(&seg
.addr_low
);
792 le32_to_cpus(&seg
.addr_high
);
793 le32_to_cpus(&seg
.size
);
794 if (seg
.size
< 16 || seg
.size
> 4096) {
795 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
799 xhci
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
800 xhci
->er_size
= seg
.size
;
806 DPRINTF("xhci: event ring:" DMA_ADDR_FMT
" [%d]\n",
807 xhci
->er_start
, xhci
->er_size
);
810 static void xhci_run(XHCIState
*xhci
)
812 trace_usb_xhci_run();
813 xhci
->usbsts
&= ~USBSTS_HCH
;
816 static void xhci_stop(XHCIState
*xhci
)
818 trace_usb_xhci_stop();
819 xhci
->usbsts
|= USBSTS_HCH
;
820 xhci
->crcr_low
&= ~CRCR_CRR
;
823 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
827 if (epctx
->state
== state
) {
831 pci_dma_read(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
832 ctx
[0] &= ~EP_STATE_MASK
;
834 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
835 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
836 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
837 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
838 pci_dma_write(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
839 epctx
->state
= state
;
842 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
843 unsigned int epid
, dma_addr_t pctx
,
847 XHCIEPContext
*epctx
;
851 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
852 assert(epid
>= 1 && epid
<= 31);
854 DPRINTF("xhci_enable_ep(%d, %d)\n", slotid
, epid
);
856 slot
= &xhci
->slots
[slotid
-1];
857 if (slot
->eps
[epid
-1]) {
858 fprintf(stderr
, "xhci: slot %d ep %d already enabled!\n", slotid
, epid
);
862 epctx
= g_malloc(sizeof(XHCIEPContext
));
863 memset(epctx
, 0, sizeof(XHCIEPContext
));
865 slot
->eps
[epid
-1] = epctx
;
867 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
868 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
);
869 epctx
->ring
.ccs
= ctx
[2] & 1;
871 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
872 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
874 epctx
->max_psize
= ctx
[1]>>16;
875 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
876 epctx
->has_bg
= false;
877 if (epctx
->type
== ET_ISO_IN
) {
878 epctx
->has_bg
= true;
880 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
881 epid
/2, epid
%2, epctx
->max_psize
);
882 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
883 usb_packet_init(&epctx
->transfers
[i
].packet
);
886 epctx
->state
= EP_RUNNING
;
887 ctx
[0] &= ~EP_STATE_MASK
;
888 ctx
[0] |= EP_RUNNING
;
893 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
897 XHCIEPContext
*epctx
;
898 int i
, xferi
, killed
= 0;
899 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
900 assert(epid
>= 1 && epid
<= 31);
902 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
904 slot
= &xhci
->slots
[slotid
-1];
906 if (!slot
->eps
[epid
-1]) {
910 epctx
= slot
->eps
[epid
-1];
912 xferi
= epctx
->next_xfer
;
913 for (i
= 0; i
< TD_QUEUE
; i
++) {
914 XHCITransfer
*t
= &epctx
->transfers
[xferi
];
915 if (t
->running_async
) {
916 usb_cancel_packet(&t
->packet
);
917 t
->running_async
= 0;
919 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i
);
922 if (t
->running_retry
) {
923 t
->running_retry
= 0;
926 if (t
->backgrounded
) {
938 t
->trb_count
= t
->trb_alloced
= 0;
939 t
->data_length
= t
->data_alloced
= 0;
940 xferi
= (xferi
+ 1) % TD_QUEUE
;
943 xferi
= epctx
->next_bg
;
944 for (i
= 0; i
< BG_XFERS
; i
++) {
945 XHCITransfer
*t
= &epctx
->bg_transfers
[xferi
];
946 if (t
->running_async
) {
947 usb_cancel_packet(&t
->packet
);
948 t
->running_async
= 0;
950 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i
);
958 xferi
= (xferi
+ 1) % BG_XFERS
;
964 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
968 XHCIEPContext
*epctx
;
970 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
971 assert(epid
>= 1 && epid
<= 31);
973 DPRINTF("xhci_disable_ep(%d, %d)\n", slotid
, epid
);
975 slot
= &xhci
->slots
[slotid
-1];
977 if (!slot
->eps
[epid
-1]) {
978 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
982 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
984 epctx
= slot
->eps
[epid
-1];
986 xhci_set_ep_state(xhci
, epctx
, EP_DISABLED
);
989 slot
->eps
[epid
-1] = NULL
;
994 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
998 XHCIEPContext
*epctx
;
1000 DPRINTF("xhci_stop_ep(%d, %d)\n", slotid
, epid
);
1002 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1004 if (epid
< 1 || epid
> 31) {
1005 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1006 return CC_TRB_ERROR
;
1009 slot
= &xhci
->slots
[slotid
-1];
1011 if (!slot
->eps
[epid
-1]) {
1012 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1013 return CC_EP_NOT_ENABLED_ERROR
;
1016 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1017 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1018 "data might be lost\n");
1021 epctx
= slot
->eps
[epid
-1];
1023 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1028 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1032 XHCIEPContext
*epctx
;
1035 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1037 DPRINTF("xhci_reset_ep(%d, %d)\n", slotid
, epid
);
1039 if (epid
< 1 || epid
> 31) {
1040 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1041 return CC_TRB_ERROR
;
1044 slot
= &xhci
->slots
[slotid
-1];
1046 if (!slot
->eps
[epid
-1]) {
1047 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1048 return CC_EP_NOT_ENABLED_ERROR
;
1051 epctx
= slot
->eps
[epid
-1];
1053 if (epctx
->state
!= EP_HALTED
) {
1054 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1055 epid
, epctx
->state
);
1056 return CC_CONTEXT_STATE_ERROR
;
1059 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1060 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1061 "data might be lost\n");
1064 uint8_t ep
= epid
>>1;
1070 dev
= xhci
->ports
[xhci
->slots
[slotid
-1].port
-1].port
.dev
;
1072 return CC_USB_TRANSACTION_ERROR
;
1075 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1080 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1081 unsigned int epid
, uint64_t pdequeue
)
1084 XHCIEPContext
*epctx
;
1087 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1089 if (epid
< 1 || epid
> 31) {
1090 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1091 return CC_TRB_ERROR
;
1094 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64
")\n", slotid
, epid
, pdequeue
);
1095 dequeue
= xhci_mask64(pdequeue
);
1097 slot
= &xhci
->slots
[slotid
-1];
1099 if (!slot
->eps
[epid
-1]) {
1100 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1101 return CC_EP_NOT_ENABLED_ERROR
;
1104 epctx
= slot
->eps
[epid
-1];
1107 if (epctx
->state
!= EP_STOPPED
) {
1108 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1109 return CC_CONTEXT_STATE_ERROR
;
1112 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1113 epctx
->ring
.ccs
= dequeue
& 1;
1115 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1120 static int xhci_xfer_data(XHCITransfer
*xfer
, uint8_t *data
,
1121 unsigned int length
, bool in_xfer
, bool out_xfer
,
1126 unsigned int transferred
= 0;
1127 unsigned int left
= length
;
1130 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1131 XHCIState
*xhci
= xfer
->xhci
;
1133 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
1134 length
, in_xfer
, out_xfer
, report
);
1136 assert(!(in_xfer
&& out_xfer
));
1138 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1139 XHCITRB
*trb
= &xfer
->trbs
[i
];
1141 unsigned int chunk
= 0;
1143 switch (TRB_TYPE(*trb
)) {
1145 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1146 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1153 addr
= xhci_mask64(trb
->parameter
);
1154 chunk
= trb
->status
& 0x1ffff;
1159 if (in_xfer
|| out_xfer
) {
1160 if (trb
->control
& TRB_TR_IDT
) {
1162 if (chunk
> 8 || in_xfer
) {
1163 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1167 idata
= le64_to_cpu(trb
->parameter
);
1168 memcpy(data
, &idata
, chunk
);
1170 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
1171 DMA_ADDR_FMT
"\n", in_xfer
, chunk
, addr
);
1173 pci_dma_write(&xhci
->pci_dev
, addr
, data
, chunk
);
1175 pci_dma_read(&xhci
->pci_dev
, addr
, data
, chunk
);
1178 unsigned int count
= chunk
;
1184 for (i
= 0; i
< count
; i
++) {
1185 DPRINTF(" %02x", data
[i
]);
1194 transferred
+= chunk
;
1202 if (report
&& !reported
&& (trb
->control
& TRB_TR_IOC
||
1203 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)))) {
1204 event
.slotid
= xfer
->slotid
;
1205 event
.epid
= xfer
->epid
;
1206 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1208 event
.ptr
= trb
->addr
;
1209 if (xfer
->status
== CC_SUCCESS
) {
1210 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1212 event
.ccode
= xfer
->status
;
1214 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1215 event
.ptr
= trb
->parameter
;
1216 event
.flags
|= TRB_EV_ED
;
1217 event
.length
= edtla
& 0xffffff;
1218 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1221 xhci_event(xhci
, &event
);
1228 static void xhci_stall_ep(XHCITransfer
*xfer
)
1230 XHCIState
*xhci
= xfer
->xhci
;
1231 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1232 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1234 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1235 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1236 xhci_set_ep_state(xhci
, epctx
, EP_HALTED
);
1237 DPRINTF("xhci: stalled slot %d ep %d\n", xfer
->slotid
, xfer
->epid
);
1238 DPRINTF("xhci: will continue at "DMA_ADDR_FMT
"\n", epctx
->ring
.dequeue
);
1241 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1242 XHCIEPContext
*epctx
);
1244 static void xhci_bg_update(XHCIState
*xhci
, XHCIEPContext
*epctx
)
1246 if (epctx
->bg_updating
) {
1249 DPRINTF("xhci_bg_update(%p, %p)\n", xhci
, epctx
);
1250 assert(epctx
->has_bg
);
1251 DPRINTF("xhci: fg=%d bg=%d\n", epctx
->comp_xfer
, epctx
->next_bg
);
1252 epctx
->bg_updating
= 1;
1253 while (epctx
->transfers
[epctx
->comp_xfer
].backgrounded
&&
1254 epctx
->bg_transfers
[epctx
->next_bg
].complete
) {
1255 XHCITransfer
*fg
= &epctx
->transfers
[epctx
->comp_xfer
];
1256 XHCITransfer
*bg
= &epctx
->bg_transfers
[epctx
->next_bg
];
1258 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
1259 epctx
->comp_xfer
, epctx
->next_bg
, bg
->cur_pkt
,
1260 bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].status
1263 assert(epctx
->type
== ET_ISO_IN
);
1264 assert(bg
->iso_xfer
);
1265 assert(bg
->in_xfer
);
1266 uint8_t *p
= bg
->data
+ bg
->cur_pkt
* bg
->pktsize
;
1268 int len
= bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].actual_length
;
1269 fg
->status
= libusb_to_ccode(bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].status
);
1275 fg
->backgrounded
= 0;
1277 if (fg
->status
== CC_STALL_ERROR
) {
1281 xhci_xfer_data(fg
, p
, len
, 1, 0, 1);
1284 if (epctx
->comp_xfer
== TD_QUEUE
) {
1285 epctx
->comp_xfer
= 0;
1287 DPRINTF("next fg xfer: %d\n", epctx
->comp_xfer
);
1289 if (bg
->cur_pkt
== bg
->pkts
) {
1291 if (xhci_submit(xhci
, bg
, epctx
) < 0) {
1292 fprintf(stderr
, "xhci: bg resubmit failed\n");
1295 if (epctx
->next_bg
== BG_XFERS
) {
1298 DPRINTF("next bg xfer: %d\n", epctx
->next_bg
);
1300 xhci_kick_ep(xhci
, fg
->slotid
, fg
->epid
);
1303 epctx
->bg_updating
= 0;
1307 static void xhci_xfer_cb(struct libusb_transfer
*transfer
)
1312 xfer
= (XHCITransfer
*)transfer
->user_data
;
1315 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer
->slotid
,
1316 xfer
->epid
, transfer
->status
);
1318 assert(xfer
->slotid
>= 1 && xfer
->slotid
<= MAXSLOTS
);
1319 assert(xfer
->epid
>= 1 && xfer
->epid
<= 31);
1321 if (xfer
->cancelled
) {
1322 DPRINTF("xhci: transfer cancelled, not reporting anything\n");
1327 XHCIEPContext
*epctx
;
1329 slot
= &xhci
->slots
[xfer
->slotid
-1];
1330 assert(slot
->eps
[xfer
->epid
-1]);
1331 epctx
= slot
->eps
[xfer
->epid
-1];
1333 if (xfer
->bg_xfer
) {
1334 DPRINTF("xhci: background transfer, updating\n");
1337 xhci_bg_update(xhci
, epctx
);
1341 if (xfer
->iso_xfer
) {
1342 transfer
->status
= transfer
->iso_packet_desc
[0].status
;
1343 transfer
->actual_length
= transfer
->iso_packet_desc
[0].actual_length
;
1346 xfer
->status
= libusb_to_ccode(transfer
->status
);
1351 if (transfer
->status
== LIBUSB_TRANSFER_STALL
)
1352 xhci_stall_ep(xhci
, epctx
, xfer
);
1354 DPRINTF("xhci: transfer actual length = %d\n", transfer
->actual_length
);
1356 if (xfer
->in_xfer
) {
1357 if (xfer
->epid
== 1) {
1358 xhci_xfer_data(xhci
, xfer
, xfer
->data
+ 8,
1359 transfer
->actual_length
, 1, 0, 1);
1361 xhci_xfer_data(xhci
, xfer
, xfer
->data
,
1362 transfer
->actual_length
, 1, 0, 1);
1365 xhci_xfer_data(xhci
, xfer
, NULL
, transfer
->actual_length
, 0, 0, 1);
1368 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1371 static int xhci_hle_control(XHCIState
*xhci
, XHCITransfer
*xfer
,
1372 uint8_t bmRequestType
, uint8_t bRequest
,
1373 uint16_t wValue
, uint16_t wIndex
, uint16_t wLength
)
1375 uint16_t type_req
= (bmRequestType
<< 8) | bRequest
;
1378 case 0x0000 | USB_REQ_SET_CONFIGURATION
:
1379 DPRINTF("xhci: HLE switch configuration\n");
1380 return xhci_switch_config(xhci
, xfer
->slotid
, wValue
) == 0;
1381 case 0x0100 | USB_REQ_SET_INTERFACE
:
1382 DPRINTF("xhci: HLE set interface altsetting\n");
1383 return xhci_set_iface_alt(xhci
, xfer
->slotid
, wIndex
, wValue
) == 0;
1384 case 0x0200 | USB_REQ_CLEAR_FEATURE
:
1385 if (wValue
== 0) { // endpoint halt
1386 DPRINTF("xhci: HLE clear halt\n");
1387 return xhci_clear_halt(xhci
, xfer
->slotid
, wIndex
);
1389 case 0x0000 | USB_REQ_SET_ADDRESS
:
1390 fprintf(stderr
, "xhci: warn: illegal SET_ADDRESS request\n");
1398 static int xhci_setup_packet(XHCITransfer
*xfer
, USBDevice
*dev
)
1403 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1404 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1405 usb_packet_setup(&xfer
->packet
, dir
, ep
);
1406 usb_packet_addbuf(&xfer
->packet
, xfer
->data
, xfer
->data_length
);
1407 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1408 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1412 static int xhci_complete_packet(XHCITransfer
*xfer
, int ret
)
1414 if (ret
== USB_RET_ASYNC
) {
1415 xfer
->running_async
= 1;
1416 xfer
->running_retry
= 0;
1418 xfer
->cancelled
= 0;
1420 } else if (ret
== USB_RET_NAK
) {
1421 xfer
->running_async
= 0;
1422 xfer
->running_retry
= 1;
1424 xfer
->cancelled
= 0;
1427 xfer
->running_async
= 0;
1428 xfer
->running_retry
= 0;
1433 xfer
->status
= CC_SUCCESS
;
1434 xhci_xfer_data(xfer
, xfer
->data
, ret
, xfer
->in_xfer
, 0, 1);
1441 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1442 xhci_xfer_data(xfer
, xfer
->data
, 0, xfer
->in_xfer
, 0, 1);
1443 xhci_stall_ep(xfer
);
1446 xfer
->status
= CC_STALL_ERROR
;
1447 xhci_xfer_data(xfer
, xfer
->data
, 0, xfer
->in_xfer
, 0, 1);
1448 xhci_stall_ep(xfer
);
1451 fprintf(stderr
, "%s: FIXME: ret = %d\n", __FUNCTION__
, ret
);
1457 static USBDevice
*xhci_find_device(XHCIPort
*port
, uint8_t addr
)
1459 if (!(port
->portsc
& PORTSC_PED
)) {
1462 return usb_find_device(&port
->port
, addr
);
1465 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1467 XHCITRB
*trb_setup
, *trb_status
;
1468 uint8_t bmRequestType
;
1474 DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer
->slotid
);
1476 trb_setup
= &xfer
->trbs
[0];
1477 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1479 /* at most one Event Data TRB allowed after STATUS */
1480 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1484 /* do some sanity checks */
1485 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1486 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1487 TRB_TYPE(*trb_setup
));
1490 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1491 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1492 TRB_TYPE(*trb_status
));
1495 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1496 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1499 if ((trb_setup
->status
& 0x1ffff) != 8) {
1500 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1501 (trb_setup
->status
& 0x1ffff));
1505 bmRequestType
= trb_setup
->parameter
;
1506 wLength
= trb_setup
->parameter
>> 48;
1508 if (xfer
->data
&& xfer
->data_alloced
< wLength
) {
1509 xfer
->data_alloced
= 0;
1514 DPRINTF("xhci: alloc %d bytes data\n", wLength
);
1515 xfer
->data
= g_malloc(wLength
+1);
1516 xfer
->data_alloced
= wLength
;
1518 xfer
->data_length
= wLength
;
1520 port
= &xhci
->ports
[xhci
->slots
[xfer
->slotid
-1].port
-1];
1521 dev
= xhci_find_device(port
, xhci
->slots
[xfer
->slotid
-1].devaddr
);
1523 fprintf(stderr
, "xhci: slot %d port %d has no device\n", xfer
->slotid
,
1524 xhci
->slots
[xfer
->slotid
-1].port
);
1528 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1529 xfer
->iso_xfer
= false;
1531 xhci_setup_packet(xfer
, dev
);
1532 xfer
->packet
.parameter
= trb_setup
->parameter
;
1533 if (!xfer
->in_xfer
) {
1534 xhci_xfer_data(xfer
, xfer
->data
, wLength
, 0, 1, 0);
1537 ret
= usb_handle_packet(dev
, &xfer
->packet
);
1539 xhci_complete_packet(xfer
, ret
);
1540 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1541 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1546 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1552 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1554 xfer
->in_xfer
= epctx
->type
>>2;
1556 if (xfer
->data
&& xfer
->data_alloced
< xfer
->data_length
) {
1557 xfer
->data_alloced
= 0;
1561 if (!xfer
->data
&& xfer
->data_length
) {
1562 DPRINTF("xhci: alloc %d bytes data\n", xfer
->data_length
);
1563 xfer
->data
= g_malloc(xfer
->data_length
);
1564 xfer
->data_alloced
= xfer
->data_length
;
1566 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1567 if (!xfer
->bg_xfer
) {
1574 port
= &xhci
->ports
[xhci
->slots
[xfer
->slotid
-1].port
-1];
1575 dev
= xhci_find_device(port
, xhci
->slots
[xfer
->slotid
-1].devaddr
);
1577 fprintf(stderr
, "xhci: slot %d port %d has no device\n", xfer
->slotid
,
1578 xhci
->slots
[xfer
->slotid
-1].port
);
1582 xhci_setup_packet(xfer
, dev
);
1584 switch(epctx
->type
) {
1595 fprintf(stderr
, "xhci: unknown or unhandled EP "
1596 "(type %d, in %d, ep %02x)\n",
1597 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1601 if (!xfer
->in_xfer
) {
1602 xhci_xfer_data(xfer
, xfer
->data
, xfer
->data_length
, 0, 1, 0);
1604 ret
= usb_handle_packet(dev
, &xfer
->packet
);
1606 xhci_complete_packet(xfer
, ret
);
1607 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1608 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1613 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1616 unsigned int length
= 0;
1619 DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1621 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1622 trb
= &xfer
->trbs
[i
];
1623 if (TRB_TYPE(*trb
) == TR_NORMAL
|| TRB_TYPE(*trb
) == TR_ISOCH
) {
1624 length
+= trb
->status
& 0x1ffff;
1627 DPRINTF("xhci: total TD length=%d\n", length
);
1629 if (!epctx
->has_bg
) {
1630 xfer
->data_length
= length
;
1631 xfer
->backgrounded
= 0;
1632 return xhci_submit(xhci
, xfer
, epctx
);
1634 if (!epctx
->bg_running
) {
1635 for (i
= 0; i
< BG_XFERS
; i
++) {
1636 XHCITransfer
*t
= &epctx
->bg_transfers
[i
];
1638 t
->epid
= xfer
->epid
;
1639 t
->slotid
= xfer
->slotid
;
1641 t
->pktsize
= epctx
->max_psize
;
1642 t
->data_length
= t
->pkts
* t
->pktsize
;
1644 if (xhci_submit(xhci
, t
, epctx
) < 0) {
1645 fprintf(stderr
, "xhci: bg submit failed\n");
1649 epctx
->bg_running
= 1;
1651 xfer
->backgrounded
= 1;
1652 xhci_bg_update(xhci
, epctx
);
1657 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
, unsigned int epid
)
1659 XHCIEPContext
*epctx
;
1663 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1664 assert(epid
>= 1 && epid
<= 31);
1665 DPRINTF("xhci_kick_ep(%d, %d)\n", slotid
, epid
);
1667 if (!xhci
->slots
[slotid
-1].enabled
) {
1668 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1671 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1673 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1679 /* retry nak'ed transfer */
1680 XHCITransfer
*xfer
= epctx
->retry
;
1683 DPRINTF("xhci: retry nack'ed transfer ...\n");
1684 assert(xfer
->running_retry
);
1685 xhci_setup_packet(xfer
, xfer
->packet
.ep
->dev
);
1686 result
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1687 if (result
== USB_RET_NAK
) {
1688 DPRINTF("xhci: ... xfer still nacked\n");
1691 DPRINTF("xhci: ... result %d\n", result
);
1692 xhci_complete_packet(xfer
, result
);
1693 assert(!xfer
->running_retry
);
1694 epctx
->retry
= NULL
;
1697 if (epctx
->state
== EP_HALTED
) {
1698 DPRINTF("xhci: ep halted, not running schedule\n");
1702 xhci_set_ep_state(xhci
, epctx
, EP_RUNNING
);
1705 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1706 if (xfer
->running_async
|| xfer
->running_retry
|| xfer
->backgrounded
) {
1707 DPRINTF("xhci: ep is busy (#%d,%d,%d,%d)\n",
1708 epctx
->next_xfer
, xfer
->running_async
,
1709 xfer
->running_retry
, xfer
->backgrounded
);
1712 DPRINTF("xhci: ep: using #%d\n", epctx
->next_xfer
);
1714 length
= xhci_ring_chain_length(xhci
, &epctx
->ring
);
1716 DPRINTF("xhci: incomplete TD (%d TRBs)\n", -length
);
1718 } else if (length
== 0) {
1721 DPRINTF("xhci: fetching %d-TRB TD\n", length
);
1722 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
1723 xfer
->trb_count
= 0;
1724 xfer
->trb_alloced
= 0;
1729 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
1730 xfer
->trb_alloced
= length
;
1732 xfer
->trb_count
= length
;
1734 for (i
= 0; i
< length
; i
++) {
1735 assert(xhci_ring_fetch(xhci
, &epctx
->ring
, &xfer
->trbs
[i
], NULL
));
1739 xfer
->slotid
= slotid
;
1742 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
1743 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1745 fprintf(stderr
, "xhci: error firing CTL transfer\n");
1748 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
1749 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1751 fprintf(stderr
, "xhci: error firing data transfer\n");
1755 if (epctx
->state
== EP_HALTED
) {
1756 DPRINTF("xhci: ep halted, stopping schedule\n");
1759 if (xfer
->running_retry
) {
1760 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1761 epctx
->retry
= xfer
;
1767 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1769 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1770 DPRINTF("xhci_enable_slot(%d)\n", slotid
);
1771 xhci
->slots
[slotid
-1].enabled
= 1;
1772 xhci
->slots
[slotid
-1].port
= 0;
1773 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1778 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1782 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1783 DPRINTF("xhci_disable_slot(%d)\n", slotid
);
1785 for (i
= 1; i
<= 31; i
++) {
1786 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1787 xhci_disable_ep(xhci
, slotid
, i
);
1791 xhci
->slots
[slotid
-1].enabled
= 0;
1795 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
1796 uint64_t pictx
, bool bsr
)
1800 dma_addr_t ictx
, octx
, dcbaap
;
1802 uint32_t ictl_ctx
[2];
1803 uint32_t slot_ctx
[4];
1804 uint32_t ep0_ctx
[5];
1809 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1810 DPRINTF("xhci_address_slot(%d)\n", slotid
);
1812 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
1813 pci_dma_read(&xhci
->pci_dev
, dcbaap
+ 8*slotid
, &poctx
, sizeof(poctx
));
1814 ictx
= xhci_mask64(pictx
);
1815 octx
= xhci_mask64(le64_to_cpu(poctx
));
1817 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1818 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1820 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1822 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
1823 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1824 ictl_ctx
[0], ictl_ctx
[1]);
1825 return CC_TRB_ERROR
;
1828 pci_dma_read(&xhci
->pci_dev
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
1829 pci_dma_read(&xhci
->pci_dev
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
1831 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1832 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1834 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1835 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1837 port
= (slot_ctx
[1]>>16) & 0xFF;
1838 dev
= xhci
->ports
[port
-1].port
.dev
;
1840 if (port
< 1 || port
> MAXPORTS
) {
1841 fprintf(stderr
, "xhci: bad port %d\n", port
);
1842 return CC_TRB_ERROR
;
1844 fprintf(stderr
, "xhci: port %d not connected\n", port
);
1845 return CC_USB_TRANSACTION_ERROR
;
1848 for (i
= 0; i
< MAXSLOTS
; i
++) {
1849 if (xhci
->slots
[i
].port
== port
) {
1850 fprintf(stderr
, "xhci: port %d already assigned to slot %d\n",
1852 return CC_TRB_ERROR
;
1856 slot
= &xhci
->slots
[slotid
-1];
1861 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1863 slot
->devaddr
= xhci
->devaddr
++;
1864 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slot
->devaddr
;
1865 DPRINTF("xhci: device address is %d\n", slot
->devaddr
);
1866 usb_device_handle_control(dev
, NULL
,
1867 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
1868 slot
->devaddr
, 0, 0, NULL
);
1871 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
1873 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1874 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1875 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1876 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1878 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1879 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1885 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
1886 uint64_t pictx
, bool dc
)
1888 dma_addr_t ictx
, octx
;
1889 uint32_t ictl_ctx
[2];
1890 uint32_t slot_ctx
[4];
1891 uint32_t islot_ctx
[4];
1896 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1897 DPRINTF("xhci_configure_slot(%d)\n", slotid
);
1899 ictx
= xhci_mask64(pictx
);
1900 octx
= xhci
->slots
[slotid
-1].ctx
;
1902 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1903 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1906 for (i
= 2; i
<= 31; i
++) {
1907 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1908 xhci_disable_ep(xhci
, slotid
, i
);
1912 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1913 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1914 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
1915 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1916 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1917 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1922 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1924 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
1925 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1926 ictl_ctx
[0], ictl_ctx
[1]);
1927 return CC_TRB_ERROR
;
1930 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
1931 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1933 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
1934 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
1935 return CC_CONTEXT_STATE_ERROR
;
1938 for (i
= 2; i
<= 31; i
++) {
1939 if (ictl_ctx
[0] & (1<<i
)) {
1940 xhci_disable_ep(xhci
, slotid
, i
);
1942 if (ictl_ctx
[1] & (1<<i
)) {
1943 pci_dma_read(&xhci
->pci_dev
, ictx
+32+(32*i
), ep_ctx
,
1945 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1946 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1947 ep_ctx
[3], ep_ctx
[4]);
1948 xhci_disable_ep(xhci
, slotid
, i
);
1949 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
1950 if (res
!= CC_SUCCESS
) {
1953 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1954 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1955 ep_ctx
[3], ep_ctx
[4]);
1956 pci_dma_write(&xhci
->pci_dev
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
1960 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1961 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
1962 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
1963 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
1964 SLOT_CONTEXT_ENTRIES_SHIFT
);
1965 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1966 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1968 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1974 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
1977 dma_addr_t ictx
, octx
;
1978 uint32_t ictl_ctx
[2];
1979 uint32_t iep0_ctx
[5];
1980 uint32_t ep0_ctx
[5];
1981 uint32_t islot_ctx
[4];
1982 uint32_t slot_ctx
[4];
1984 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1985 DPRINTF("xhci_evaluate_slot(%d)\n", slotid
);
1987 ictx
= xhci_mask64(pictx
);
1988 octx
= xhci
->slots
[slotid
-1].ctx
;
1990 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1991 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1993 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1995 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
1996 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1997 ictl_ctx
[0], ictl_ctx
[1]);
1998 return CC_TRB_ERROR
;
2001 if (ictl_ctx
[1] & 0x1) {
2002 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2004 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2005 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2007 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2009 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2010 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2011 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2012 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2014 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2015 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2017 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2020 if (ictl_ctx
[1] & 0x2) {
2021 pci_dma_read(&xhci
->pci_dev
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2023 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2024 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2025 iep0_ctx
[3], iep0_ctx
[4]);
2027 pci_dma_read(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2029 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2030 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2032 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2033 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2035 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2041 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2043 uint32_t slot_ctx
[4];
2047 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
2048 DPRINTF("xhci_reset_slot(%d)\n", slotid
);
2050 octx
= xhci
->slots
[slotid
-1].ctx
;
2052 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2054 for (i
= 2; i
<= 31; i
++) {
2055 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2056 xhci_disable_ep(xhci
, slotid
, i
);
2060 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2061 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2062 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2063 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2064 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2065 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2070 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2072 unsigned int slotid
;
2073 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2074 if (slotid
< 1 || slotid
> MAXSLOTS
) {
2075 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2076 event
->ccode
= CC_TRB_ERROR
;
2078 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2079 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2080 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2086 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2089 uint8_t bw_ctx
[MAXPORTS
+1];
2091 DPRINTF("xhci_get_port_bandwidth()\n");
2093 ctx
= xhci_mask64(pctx
);
2095 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2097 /* TODO: actually implement real values here */
2099 memset(&bw_ctx
[1], 80, MAXPORTS
); /* 80% */
2100 pci_dma_write(&xhci
->pci_dev
, ctx
, bw_ctx
, sizeof(bw_ctx
));
2105 static uint32_t rotl(uint32_t v
, unsigned count
)
2108 return (v
<< count
) | (v
>> (32 - count
));
2112 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2115 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2116 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2117 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2121 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2125 dma_addr_t paddr
= xhci_mask64(addr
);
2127 pci_dma_read(&xhci
->pci_dev
, paddr
, &buf
, 32);
2129 memcpy(obuf
, buf
, sizeof(obuf
));
2131 if ((buf
[0] & 0xff) == 2) {
2132 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2133 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2134 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2135 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2136 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2137 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2138 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2139 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2140 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2143 pci_dma_write(&xhci
->pci_dev
, paddr
, &obuf
, 32);
2146 static void xhci_process_commands(XHCIState
*xhci
)
2150 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2152 unsigned int i
, slotid
= 0;
2154 DPRINTF("xhci_process_commands()\n");
2155 if (!xhci_running(xhci
)) {
2156 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2160 xhci
->crcr_low
|= CRCR_CRR
;
2162 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2165 case CR_ENABLE_SLOT
:
2166 for (i
= 0; i
< MAXSLOTS
; i
++) {
2167 if (!xhci
->slots
[i
].enabled
) {
2171 if (i
>= MAXSLOTS
) {
2172 fprintf(stderr
, "xhci: no device slots available\n");
2173 event
.ccode
= CC_NO_SLOTS_ERROR
;
2176 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2179 case CR_DISABLE_SLOT
:
2180 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2182 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2185 case CR_ADDRESS_DEVICE
:
2186 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2188 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2189 trb
.control
& TRB_CR_BSR
);
2192 case CR_CONFIGURE_ENDPOINT
:
2193 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2195 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2196 trb
.control
& TRB_CR_DC
);
2199 case CR_EVALUATE_CONTEXT
:
2200 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2202 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2205 case CR_STOP_ENDPOINT
:
2206 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2208 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2210 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2213 case CR_RESET_ENDPOINT
:
2214 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2216 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2218 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2221 case CR_SET_TR_DEQUEUE
:
2222 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2224 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2226 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
, epid
,
2230 case CR_RESET_DEVICE
:
2231 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2233 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2236 case CR_GET_PORT_BANDWIDTH
:
2237 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2239 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2240 xhci_via_challenge(xhci
, trb
.parameter
);
2242 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2243 event
.type
= 48; /* NEC reply */
2244 event
.length
= 0x3025;
2246 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2248 uint32_t chi
= trb
.parameter
>> 32;
2249 uint32_t clo
= trb
.parameter
;
2250 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2251 event
.length
= val
& 0xFFFF;
2252 event
.epid
= val
>> 16;
2254 event
.type
= 48; /* NEC reply */
2258 fprintf(stderr
, "xhci: unimplemented command %d\n", type
);
2259 event
.ccode
= CC_TRB_ERROR
;
2262 event
.slotid
= slotid
;
2263 xhci_event(xhci
, &event
);
2267 static void xhci_update_port(XHCIState
*xhci
, XHCIPort
*port
, int is_detach
)
2269 int nr
= port
->port
.index
+ 1;
2271 port
->portsc
= PORTSC_PP
;
2272 if (port
->port
.dev
&& port
->port
.dev
->attached
&& !is_detach
) {
2273 port
->portsc
|= PORTSC_CCS
;
2274 switch (port
->port
.dev
->speed
) {
2276 port
->portsc
|= PORTSC_SPEED_LOW
;
2278 case USB_SPEED_FULL
:
2279 port
->portsc
|= PORTSC_SPEED_FULL
;
2281 case USB_SPEED_HIGH
:
2282 port
->portsc
|= PORTSC_SPEED_HIGH
;
2287 if (xhci_running(xhci
)) {
2288 port
->portsc
|= PORTSC_CSC
;
2289 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2290 xhci_event(xhci
, &ev
);
2291 DPRINTF("xhci: port change event for port %d\n", nr
);
2295 static void xhci_reset(DeviceState
*dev
)
2297 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
.qdev
, dev
);
2300 trace_usb_xhci_reset();
2301 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2302 fprintf(stderr
, "xhci: reset while running!\n");
2306 xhci
->usbsts
= USBSTS_HCH
;
2309 xhci
->crcr_high
= 0;
2310 xhci
->dcbaap_low
= 0;
2311 xhci
->dcbaap_high
= 0;
2315 for (i
= 0; i
< MAXSLOTS
; i
++) {
2316 xhci_disable_slot(xhci
, i
+1);
2319 for (i
= 0; i
< MAXPORTS
; i
++) {
2320 xhci_update_port(xhci
, xhci
->ports
+ i
, 0);
2327 xhci
->erstba_low
= 0;
2328 xhci
->erstba_high
= 0;
2330 xhci
->erdp_high
= 0;
2332 xhci
->er_ep_idx
= 0;
2335 xhci
->ev_buffer_put
= 0;
2336 xhci
->ev_buffer_get
= 0;
2339 static uint32_t xhci_cap_read(XHCIState
*xhci
, uint32_t reg
)
2344 case 0x00: /* HCIVERSION, CAPLENGTH */
2345 ret
= 0x01000000 | LEN_CAP
;
2347 case 0x04: /* HCSPARAMS 1 */
2348 ret
= (MAXPORTS
<<24) | (MAXINTRS
<<8) | MAXSLOTS
;
2350 case 0x08: /* HCSPARAMS 2 */
2353 case 0x0c: /* HCSPARAMS 3 */
2356 case 0x10: /* HCCPARAMS */
2357 if (sizeof(dma_addr_t
) == 4) {
2363 case 0x14: /* DBOFF */
2366 case 0x18: /* RTSOFF */
2370 /* extended capabilities */
2371 case 0x20: /* Supported Protocol:00 */
2372 ret
= 0x02000402; /* USB 2.0 */
2374 case 0x24: /* Supported Protocol:04 */
2375 ret
= 0x20425455; /* "USB " */
2377 case 0x28: /* Supported Protocol:08 */
2378 ret
= 0x00000001 | (USB2_PORTS
<<8);
2380 case 0x2c: /* Supported Protocol:0c */
2381 ret
= 0x00000000; /* reserved */
2383 case 0x30: /* Supported Protocol:00 */
2384 ret
= 0x03000002; /* USB 3.0 */
2386 case 0x34: /* Supported Protocol:04 */
2387 ret
= 0x20425455; /* "USB " */
2389 case 0x38: /* Supported Protocol:08 */
2390 ret
= 0x00000000 | (USB2_PORTS
+1) | (USB3_PORTS
<<8);
2392 case 0x3c: /* Supported Protocol:0c */
2393 ret
= 0x00000000; /* reserved */
2396 fprintf(stderr
, "xhci_cap_read: reg %d unimplemented\n", reg
);
2400 trace_usb_xhci_cap_read(reg
, ret
);
2404 static uint32_t xhci_port_read(XHCIState
*xhci
, uint32_t reg
)
2406 uint32_t port
= reg
>> 4;
2409 if (port
>= MAXPORTS
) {
2410 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2415 switch (reg
& 0xf) {
2416 case 0x00: /* PORTSC */
2417 ret
= xhci
->ports
[port
].portsc
;
2419 case 0x04: /* PORTPMSC */
2420 case 0x08: /* PORTLI */
2423 case 0x0c: /* reserved */
2425 fprintf(stderr
, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2431 trace_usb_xhci_port_read(port
, reg
& 0x0f, ret
);
2435 static void xhci_port_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2437 uint32_t port
= reg
>> 4;
2440 trace_usb_xhci_port_write(port
, reg
& 0x0f, val
);
2442 if (port
>= MAXPORTS
) {
2443 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2447 switch (reg
& 0xf) {
2448 case 0x00: /* PORTSC */
2449 portsc
= xhci
->ports
[port
].portsc
;
2450 /* write-1-to-clear bits*/
2451 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2452 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2453 if (val
& PORTSC_LWS
) {
2454 /* overwrite PLS only when LWS=1 */
2455 portsc
&= ~(PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2456 portsc
|= val
& (PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2458 /* read/write bits */
2459 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2460 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2461 /* write-1-to-start bits */
2462 if (val
& PORTSC_PR
) {
2463 DPRINTF("xhci: port %d reset\n", port
);
2464 usb_device_reset(xhci
->ports
[port
].port
.dev
);
2465 portsc
|= PORTSC_PRC
| PORTSC_PED
;
2467 xhci
->ports
[port
].portsc
= portsc
;
2469 case 0x04: /* PORTPMSC */
2470 case 0x08: /* PORTLI */
2472 fprintf(stderr
, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2477 static uint32_t xhci_oper_read(XHCIState
*xhci
, uint32_t reg
)
2482 return xhci_port_read(xhci
, reg
- 0x400);
2486 case 0x00: /* USBCMD */
2489 case 0x04: /* USBSTS */
2492 case 0x08: /* PAGESIZE */
2495 case 0x14: /* DNCTRL */
2498 case 0x18: /* CRCR low */
2499 ret
= xhci
->crcr_low
& ~0xe;
2501 case 0x1c: /* CRCR high */
2502 ret
= xhci
->crcr_high
;
2504 case 0x30: /* DCBAAP low */
2505 ret
= xhci
->dcbaap_low
;
2507 case 0x34: /* DCBAAP high */
2508 ret
= xhci
->dcbaap_high
;
2510 case 0x38: /* CONFIG */
2514 fprintf(stderr
, "xhci_oper_read: reg 0x%x unimplemented\n", reg
);
2518 trace_usb_xhci_oper_read(reg
, ret
);
2522 static void xhci_oper_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2525 xhci_port_write(xhci
, reg
- 0x400, val
);
2529 trace_usb_xhci_oper_write(reg
, val
);
2532 case 0x00: /* USBCMD */
2533 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2535 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2538 xhci
->usbcmd
= val
& 0xc0f;
2539 if (val
& USBCMD_HCRST
) {
2540 xhci_reset(&xhci
->pci_dev
.qdev
);
2542 xhci_irq_update(xhci
);
2545 case 0x04: /* USBSTS */
2546 /* these bits are write-1-to-clear */
2547 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2548 xhci_irq_update(xhci
);
2551 case 0x14: /* DNCTRL */
2552 xhci
->dnctrl
= val
& 0xffff;
2554 case 0x18: /* CRCR low */
2555 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2557 case 0x1c: /* CRCR high */
2558 xhci
->crcr_high
= val
;
2559 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2560 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2561 xhci
->crcr_low
&= ~CRCR_CRR
;
2562 xhci_event(xhci
, &event
);
2563 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2565 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2566 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2568 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2570 case 0x30: /* DCBAAP low */
2571 xhci
->dcbaap_low
= val
& 0xffffffc0;
2573 case 0x34: /* DCBAAP high */
2574 xhci
->dcbaap_high
= val
;
2576 case 0x38: /* CONFIG */
2577 xhci
->config
= val
& 0xff;
2580 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2584 static uint32_t xhci_runtime_read(XHCIState
*xhci
, uint32_t reg
)
2589 case 0x00: /* MFINDEX */
2590 fprintf(stderr
, "xhci_runtime_read: MFINDEX not yet implemented\n");
2591 ret
= xhci
->mfindex
;
2593 case 0x20: /* IMAN */
2596 case 0x24: /* IMOD */
2599 case 0x28: /* ERSTSZ */
2602 case 0x30: /* ERSTBA low */
2603 ret
= xhci
->erstba_low
;
2605 case 0x34: /* ERSTBA high */
2606 ret
= xhci
->erstba_high
;
2608 case 0x38: /* ERDP low */
2609 ret
= xhci
->erdp_low
;
2611 case 0x3c: /* ERDP high */
2612 ret
= xhci
->erdp_high
;
2615 fprintf(stderr
, "xhci_runtime_read: reg 0x%x unimplemented\n", reg
);
2619 trace_usb_xhci_runtime_read(reg
, ret
);
2623 static void xhci_runtime_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2625 trace_usb_xhci_runtime_read(reg
, val
);
2628 case 0x20: /* IMAN */
2629 if (val
& IMAN_IP
) {
2630 xhci
->iman
&= ~IMAN_IP
;
2632 xhci
->iman
&= ~IMAN_IE
;
2633 xhci
->iman
|= val
& IMAN_IE
;
2634 xhci_irq_update(xhci
);
2636 case 0x24: /* IMOD */
2639 case 0x28: /* ERSTSZ */
2640 xhci
->erstsz
= val
& 0xffff;
2642 case 0x30: /* ERSTBA low */
2643 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2644 xhci->erstba_low = val & 0xffffffc0; */
2645 xhci
->erstba_low
= val
& 0xfffffff0;
2647 case 0x34: /* ERSTBA high */
2648 xhci
->erstba_high
= val
;
2649 xhci_er_reset(xhci
);
2651 case 0x38: /* ERDP low */
2652 if (val
& ERDP_EHB
) {
2653 xhci
->erdp_low
&= ~ERDP_EHB
;
2655 xhci
->erdp_low
= (val
& ~ERDP_EHB
) | (xhci
->erdp_low
& ERDP_EHB
);
2657 case 0x3c: /* ERDP high */
2658 xhci
->erdp_high
= val
;
2659 xhci_events_update(xhci
);
2662 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2666 static uint32_t xhci_doorbell_read(XHCIState
*xhci
, uint32_t reg
)
2668 /* doorbells always read as 0 */
2669 trace_usb_xhci_doorbell_read(reg
, 0);
2673 static void xhci_doorbell_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2675 trace_usb_xhci_doorbell_write(reg
, val
);
2677 if (!xhci_running(xhci
)) {
2678 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
2686 xhci_process_commands(xhci
);
2688 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n", val
);
2691 if (reg
> MAXSLOTS
) {
2692 fprintf(stderr
, "xhci: bad doorbell %d\n", reg
);
2693 } else if (val
> 31) {
2694 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n", reg
, val
);
2696 xhci_kick_ep(xhci
, reg
, val
);
2701 static uint64_t xhci_mem_read(void *ptr
, target_phys_addr_t addr
,
2704 XHCIState
*xhci
= ptr
;
2706 /* Only aligned reads are allowed on xHCI */
2708 fprintf(stderr
, "xhci_mem_read: Mis-aligned read\n");
2712 if (addr
< LEN_CAP
) {
2713 return xhci_cap_read(xhci
, addr
);
2714 } else if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2715 return xhci_oper_read(xhci
, addr
- OFF_OPER
);
2716 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2717 return xhci_runtime_read(xhci
, addr
- OFF_RUNTIME
);
2718 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2719 return xhci_doorbell_read(xhci
, addr
- OFF_DOORBELL
);
2721 fprintf(stderr
, "xhci_mem_read: Bad offset %x\n", (int)addr
);
2726 static void xhci_mem_write(void *ptr
, target_phys_addr_t addr
,
2727 uint64_t val
, unsigned size
)
2729 XHCIState
*xhci
= ptr
;
2731 /* Only aligned writes are allowed on xHCI */
2733 fprintf(stderr
, "xhci_mem_write: Mis-aligned write\n");
2737 if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2738 xhci_oper_write(xhci
, addr
- OFF_OPER
, val
);
2739 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2740 xhci_runtime_write(xhci
, addr
- OFF_RUNTIME
, val
);
2741 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2742 xhci_doorbell_write(xhci
, addr
- OFF_DOORBELL
, val
);
2744 fprintf(stderr
, "xhci_mem_write: Bad offset %x\n", (int)addr
);
2748 static const MemoryRegionOps xhci_mem_ops
= {
2749 .read
= xhci_mem_read
,
2750 .write
= xhci_mem_write
,
2751 .valid
.min_access_size
= 4,
2752 .valid
.max_access_size
= 4,
2753 .endianness
= DEVICE_LITTLE_ENDIAN
,
2756 static void xhci_attach(USBPort
*usbport
)
2758 XHCIState
*xhci
= usbport
->opaque
;
2759 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2761 xhci_update_port(xhci
, port
, 0);
2764 static void xhci_detach(USBPort
*usbport
)
2766 XHCIState
*xhci
= usbport
->opaque
;
2767 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2769 xhci_update_port(xhci
, port
, 1);
2772 static void xhci_wakeup(USBPort
*usbport
)
2774 XHCIState
*xhci
= usbport
->opaque
;
2775 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2776 int nr
= port
->port
.index
+ 1;
2777 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2780 pls
= (port
->portsc
>> PORTSC_PLS_SHIFT
) & PORTSC_PLS_MASK
;
2784 port
->portsc
|= 0xf << PORTSC_PLS_SHIFT
;
2785 if (port
->portsc
& PORTSC_PLC
) {
2788 port
->portsc
|= PORTSC_PLC
;
2789 xhci_event(xhci
, &ev
);
2792 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
2794 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
2796 xhci_complete_packet(xfer
, packet
->result
);
2797 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
);
2800 static void xhci_child_detach(USBPort
*port
, USBDevice
*child
)
2805 static USBPortOps xhci_port_ops
= {
2806 .attach
= xhci_attach
,
2807 .detach
= xhci_detach
,
2808 .wakeup
= xhci_wakeup
,
2809 .complete
= xhci_complete
,
2810 .child_detach
= xhci_child_detach
,
2813 static int xhci_find_slotid(XHCIState
*xhci
, USBDevice
*dev
)
2818 for (slotid
= 1; slotid
<= MAXSLOTS
; slotid
++) {
2819 slot
= &xhci
->slots
[slotid
-1];
2820 if (slot
->devaddr
== dev
->addr
) {
2827 static int xhci_find_epid(USBEndpoint
*ep
)
2832 if (ep
->pid
== USB_TOKEN_IN
) {
2833 return ep
->nr
* 2 + 1;
2839 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
)
2841 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2844 DPRINTF("%s\n", __func__
);
2845 slotid
= xhci_find_slotid(xhci
, ep
->dev
);
2846 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
2847 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
2850 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
));
2853 static USBBusOps xhci_bus_ops
= {
2854 .wakeup_endpoint
= xhci_wakeup_endpoint
,
2857 static void usb_xhci_init(XHCIState
*xhci
, DeviceState
*dev
)
2861 xhci
->usbsts
= USBSTS_HCH
;
2863 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, &xhci
->pci_dev
.qdev
);
2865 for (i
= 0; i
< MAXPORTS
; i
++) {
2866 memset(&xhci
->ports
[i
], 0, sizeof(xhci
->ports
[i
]));
2867 usb_register_port(&xhci
->bus
, &xhci
->ports
[i
].port
, xhci
, i
,
2869 USB_SPEED_MASK_LOW
|
2870 USB_SPEED_MASK_FULL
|
2871 USB_SPEED_MASK_HIGH
);
2873 for (i
= 0; i
< MAXSLOTS
; i
++) {
2874 xhci
->slots
[i
].enabled
= 0;
2878 static int usb_xhci_initfn(struct PCIDevice
*dev
)
2882 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2884 xhci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
2885 xhci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
2886 xhci
->pci_dev
.config
[PCI_CACHE_LINE_SIZE
] = 0x10;
2887 xhci
->pci_dev
.config
[0x60] = 0x30; /* release number */
2889 usb_xhci_init(xhci
, &dev
->qdev
);
2891 xhci
->irq
= xhci
->pci_dev
.irq
[0];
2893 memory_region_init_io(&xhci
->mem
, &xhci_mem_ops
, xhci
,
2895 pci_register_bar(&xhci
->pci_dev
, 0,
2896 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
2899 ret
= pcie_cap_init(&xhci
->pci_dev
, 0xa0, PCI_EXP_TYPE_ENDPOINT
, 0);
2903 ret
= msi_init(&xhci
->pci_dev
, 0x70, 1, true, false);
2910 static void xhci_write_config(PCIDevice
*dev
, uint32_t addr
, uint32_t val
,
2913 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2915 pci_default_write_config(dev
, addr
, val
, len
);
2917 msi_write_config(dev
, addr
, val
, len
);
2921 static const VMStateDescription vmstate_xhci
= {
2926 static Property xhci_properties
[] = {
2927 DEFINE_PROP_UINT32("msi", XHCIState
, msi
, 0),
2928 DEFINE_PROP_END_OF_LIST(),
2931 static void xhci_class_init(ObjectClass
*klass
, void *data
)
2933 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2934 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2936 dc
->vmsd
= &vmstate_xhci
;
2937 dc
->props
= xhci_properties
;
2938 dc
->reset
= xhci_reset
;
2939 k
->init
= usb_xhci_initfn
;
2940 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
2941 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
2942 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2945 k
->config_write
= xhci_write_config
;
2948 static TypeInfo xhci_info
= {
2949 .name
= "nec-usb-xhci",
2950 .parent
= TYPE_PCI_DEVICE
,
2951 .instance_size
= sizeof(XHCIState
),
2952 .class_init
= xhci_class_init
,
2955 static void xhci_register_types(void)
2957 type_register_static(&xhci_info
);
2960 type_init(xhci_register_types
)