2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/bitops.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
32 #include "hw/southbridge/piix.h"
33 #include "hw/isa/superio.h"
34 #include "hw/char/serial.h"
36 #include "hw/boards.h"
37 #include "hw/i2c/smbus_eeprom.h"
38 #include "hw/block/flash.h"
39 #include "hw/mips/mips.h"
40 #include "hw/mips/cpudevs.h"
41 #include "hw/pci/pci.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/arch_init.h"
45 #include "hw/mips/bios.h"
48 #include "hw/loader.h"
50 #include "exec/address-spaces.h"
51 #include "qom/object.h"
52 #include "hw/sysbus.h" /* SysBusDevice */
53 #include "qemu/host-utils.h"
54 #include "sysemu/qtest.h"
55 #include "sysemu/reset.h"
56 #include "sysemu/runstate.h"
57 #include "qapi/error.h"
58 #include "qemu/error-report.h"
59 #include "hw/misc/empty_slot.h"
60 #include "sysemu/kvm.h"
61 #include "hw/semihosting/semihost.h"
62 #include "hw/mips/cps.h"
63 #include "hw/qdev-clock.h"
65 #define ENVP_PADDR 0x2000
66 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
67 #define ENVP_NB_ENTRIES 16
68 #define ENVP_ENTRY_SIZE 256
70 /* Hardware addresses */
71 #define FLASH_ADDRESS 0x1e000000ULL
72 #define FPGA_ADDRESS 0x1f000000ULL
73 #define RESET_ADDRESS 0x1fc00000ULL
75 #define FLASH_SIZE 0x400000
81 MemoryRegion iomem_lo
; /* 0 - 0x900 */
82 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
96 #define TYPE_MIPS_MALTA "mips-malta"
97 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState
, MIPS_MALTA
)
100 SysBusDevice parent_obj
;
104 qemu_irq i8259
[ISA_NUM_IRQS
];
107 static struct _loaderparams
{
108 int ram_size
, ram_low_size
;
109 const char *kernel_filename
;
110 const char *kernel_cmdline
;
111 const char *initrd_filename
;
115 static void malta_fpga_update_display(void *opaque
)
119 MaltaFPGAState
*s
= opaque
;
121 for (i
= 7 ; i
>= 0 ; i
--) {
122 if (s
->leds
& (1 << i
)) {
130 qemu_chr_fe_printf(&s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
132 qemu_chr_fe_printf(&s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
137 * EEPROM 24C01 / 24C02 emulation.
139 * Emulation for serial EEPROMs:
140 * 24C01 - 1024 bit (128 x 8)
141 * 24C02 - 2048 bit (256 x 8)
143 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
147 # define logout(fmt, ...) \
148 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
150 # define logout(fmt, ...) ((void)0)
153 struct _eeprom24c0x_t
{
162 uint8_t contents
[256];
165 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
167 static eeprom24c0x_t spd_eeprom
= {
170 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
172 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
174 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
176 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
178 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
204 static void generate_eeprom_spd(uint8_t *eeprom
, ram_addr_t ram_size
)
206 enum { SDR
= 0x4, DDR2
= 0x8 } type
;
207 uint8_t *spd
= spd_eeprom
.contents
;
209 uint16_t density
= 0;
212 /* work in terms of MB */
215 while ((ram_size
>= 4) && (nbanks
<= 2)) {
216 int sz_log2
= MIN(31 - clz32(ram_size
), 14);
218 density
|= 1 << (sz_log2
- 2);
219 ram_size
-= 1 << sz_log2
;
222 /* split to 2 banks if possible */
223 if ((nbanks
== 1) && (density
> 1)) {
228 if (density
& 0xff00) {
229 density
= (density
& 0xe0) | ((density
>> 8) & 0x1f);
231 } else if (!(density
& 0x1f)) {
238 warn_report("SPD cannot represent final " RAM_ADDR_FMT
"MB"
239 " of SDRAM", ram_size
);
242 /* fill in SPD memory information */
249 for (i
= 0; i
< 63; i
++) {
254 memcpy(eeprom
, spd
, sizeof(spd_eeprom
.contents
));
257 static void generate_eeprom_serial(uint8_t *eeprom
)
260 uint8_t mac
[6] = { 0x00 };
261 uint8_t sn
[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
264 eeprom
[pos
++] = 0x01;
267 eeprom
[pos
++] = 0x02;
270 eeprom
[pos
++] = 0x01; /* MAC */
271 eeprom
[pos
++] = 0x06; /* length */
272 memcpy(&eeprom
[pos
], mac
, sizeof(mac
));
276 eeprom
[pos
++] = 0x02; /* serial */
277 eeprom
[pos
++] = 0x05; /* length */
278 memcpy(&eeprom
[pos
], sn
, sizeof(sn
));
283 for (i
= 0; i
< pos
; i
++) {
284 eeprom
[pos
] += eeprom
[i
];
288 static uint8_t eeprom24c0x_read(eeprom24c0x_t
*eeprom
)
290 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
291 eeprom
->tick
, eeprom
->scl
, eeprom
->sda
, eeprom
->data
);
295 static void eeprom24c0x_write(eeprom24c0x_t
*eeprom
, int scl
, int sda
)
297 if (eeprom
->scl
&& scl
&& (eeprom
->sda
!= sda
)) {
298 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
299 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
,
300 sda
? "stop" : "start");
305 } else if (eeprom
->tick
== 0 && !eeprom
->ack
) {
306 /* Waiting for start. */
307 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
308 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
309 } else if (!eeprom
->scl
&& scl
) {
310 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
311 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
313 logout("\ti2c ack bit = 0\n");
316 } else if (eeprom
->sda
== sda
) {
317 uint8_t bit
= (sda
!= 0);
318 logout("\ti2c bit = %d\n", bit
);
319 if (eeprom
->tick
< 9) {
320 eeprom
->command
<<= 1;
321 eeprom
->command
+= bit
;
323 if (eeprom
->tick
== 9) {
324 logout("\tcommand 0x%04x, %s\n", eeprom
->command
,
325 bit
? "read" : "write");
328 } else if (eeprom
->tick
< 17) {
329 if (eeprom
->command
& 1) {
330 sda
= ((eeprom
->data
& 0x80) != 0);
332 eeprom
->address
<<= 1;
333 eeprom
->address
+= bit
;
336 if (eeprom
->tick
== 17) {
337 eeprom
->data
= eeprom
->contents
[eeprom
->address
];
338 logout("\taddress 0x%04x, data 0x%02x\n",
339 eeprom
->address
, eeprom
->data
);
343 } else if (eeprom
->tick
>= 17) {
347 logout("\tsda changed with raising scl\n");
350 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
->tick
, eeprom
->scl
,
351 scl
, eeprom
->sda
, sda
);
357 static uint64_t malta_fpga_read(void *opaque
, hwaddr addr
,
360 MaltaFPGAState
*s
= opaque
;
364 saddr
= (addr
& 0xfffff);
368 /* SWITCH Register */
373 /* STATUS Register */
375 #ifdef TARGET_WORDS_BIGENDIAN
387 /* LEDBAR Register */
392 /* BRKRES Register */
397 /* UART Registers are handled directly by the serial device */
404 /* XXX: implement a real I2C controller */
408 /* IN = OUT until a real I2C control is implemented */
416 /* I2CINP Register */
418 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read(&spd_eeprom
));
426 /* I2COUT Register */
431 /* I2CSEL Register */
437 qemu_log_mask(LOG_GUEST_ERROR
,
438 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX
"\n",
445 static void malta_fpga_write(void *opaque
, hwaddr addr
,
446 uint64_t val
, unsigned size
)
448 MaltaFPGAState
*s
= opaque
;
451 saddr
= (addr
& 0xfffff);
455 /* SWITCH Register */
463 /* LEDBAR Register */
465 s
->leds
= val
& 0xff;
466 malta_fpga_update_display(s
);
469 /* ASCIIWORD Register */
471 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
472 malta_fpga_update_display(s
);
475 /* ASCIIPOS0 to ASCIIPOS7 Registers */
484 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
485 malta_fpga_update_display(s
);
488 /* SOFTRES Register */
491 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
495 /* BRKRES Register */
500 /* UART Registers are handled directly by the serial device */
504 s
->gpout
= val
& 0xff;
509 s
->i2coe
= val
& 0x03;
512 /* I2COUT Register */
514 eeprom24c0x_write(&spd_eeprom
, val
& 0x02, val
& 0x01);
518 /* I2CSEL Register */
520 s
->i2csel
= val
& 0x01;
524 qemu_log_mask(LOG_GUEST_ERROR
,
525 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX
"\n",
531 static const MemoryRegionOps malta_fpga_ops
= {
532 .read
= malta_fpga_read
,
533 .write
= malta_fpga_write
,
534 .endianness
= DEVICE_NATIVE_ENDIAN
,
537 static void malta_fpga_reset(void *opaque
)
539 MaltaFPGAState
*s
= opaque
;
549 s
->display_text
[8] = '\0';
550 snprintf(s
->display_text
, 9, " ");
553 static void malta_fgpa_display_event(void *opaque
, QEMUChrEvent event
)
555 MaltaFPGAState
*s
= opaque
;
557 if (event
== CHR_EVENT_OPENED
&& !s
->display_inited
) {
558 qemu_chr_fe_printf(&s
->display
, "\e[HMalta LEDBAR\r\n");
559 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
560 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
561 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
562 qemu_chr_fe_printf(&s
->display
, "\n");
563 qemu_chr_fe_printf(&s
->display
, "Malta ASCII\r\n");
564 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
565 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
566 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
567 s
->display_inited
= true;
571 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
572 hwaddr base
, qemu_irq uart_irq
, Chardev
*uart_chr
)
577 s
= g_new0(MaltaFPGAState
, 1);
579 memory_region_init_io(&s
->iomem
, NULL
, &malta_fpga_ops
, s
,
580 "malta-fpga", 0x100000);
581 memory_region_init_alias(&s
->iomem_lo
, NULL
, "malta-fpga",
582 &s
->iomem
, 0, 0x900);
583 memory_region_init_alias(&s
->iomem_hi
, NULL
, "malta-fpga",
584 &s
->iomem
, 0xa00, 0x100000 - 0xa00);
586 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
587 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
589 chr
= qemu_chr_new("fpga", "vc:320x200", NULL
);
590 qemu_chr_fe_init(&s
->display
, chr
, NULL
);
591 qemu_chr_fe_set_handlers(&s
->display
, NULL
, NULL
,
592 malta_fgpa_display_event
, NULL
, s
, NULL
, true);
594 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
595 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
598 qemu_register_reset(malta_fpga_reset
, s
);
603 /* Network support */
604 static void network_init(PCIBus
*pci_bus
)
608 for (i
= 0; i
< nb_nics
; i
++) {
609 NICInfo
*nd
= &nd_table
[i
];
610 const char *default_devaddr
= NULL
;
612 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
613 /* The malta board has a PCNet card using PCI SLOT 11 */
614 default_devaddr
= "0b";
616 pci_nic_init_nofail(nd
, pci_bus
, "pcnet", default_devaddr
);
620 static void write_bootloader_nanomips(uint8_t *base
, uint64_t run_addr
,
621 uint64_t kernel_entry
)
625 /* Small bootloader */
626 p
= (uint16_t *)base
;
628 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
629 #define NM_HI2(VAL) \
630 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
631 #define NM_LO(VAL) ((VAL) & 0xfff)
633 stw_p(p
++, 0x2800); stw_p(p
++, 0x001c);
635 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
637 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
639 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
641 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
643 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
645 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
647 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
651 if (semihosting_get_argc()) {
652 /* Preserve a0 content as arguments have been passed */
653 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
656 stw_p(p
++, 0x0080); stw_p(p
++, 0x0002);
660 stw_p(p
++, 0xe3a0 | NM_HI1(ENVP_VADDR
- 64));
662 stw_p(p
++, NM_HI2(ENVP_VADDR
- 64));
663 /* lui sp,%hi(ENVP_VADDR - 64) */
665 stw_p(p
++, 0x83bd); stw_p(p
++, NM_LO(ENVP_VADDR
- 64));
666 /* ori sp,sp,%lo(ENVP_VADDR - 64) */
668 stw_p(p
++, 0xe0a0 | NM_HI1(ENVP_VADDR
));
670 stw_p(p
++, NM_HI2(ENVP_VADDR
));
671 /* lui a1,%hi(ENVP_VADDR) */
673 stw_p(p
++, 0x80a5); stw_p(p
++, NM_LO(ENVP_VADDR
));
674 /* ori a1,a1,%lo(ENVP_VADDR) */
676 stw_p(p
++, 0xe0c0 | NM_HI1(ENVP_VADDR
+ 8));
678 stw_p(p
++, NM_HI2(ENVP_VADDR
+ 8));
679 /* lui a2,%hi(ENVP_VADDR + 8) */
681 stw_p(p
++, 0x80c6); stw_p(p
++, NM_LO(ENVP_VADDR
+ 8));
682 /* ori a2,a2,%lo(ENVP_VADDR + 8) */
684 stw_p(p
++, 0xe0e0 | NM_HI1(loaderparams
.ram_low_size
));
686 stw_p(p
++, NM_HI2(loaderparams
.ram_low_size
));
687 /* lui a3,%hi(loaderparams.ram_low_size) */
689 stw_p(p
++, 0x80e7); stw_p(p
++, NM_LO(loaderparams
.ram_low_size
));
690 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
693 * Load BAR registers as done by YAMON:
695 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
696 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000
697 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
700 stw_p(p
++, 0xe040); stw_p(p
++, 0x0681);
701 /* lui t1, %hi(0xb4000000) */
703 #ifdef TARGET_WORDS_BIGENDIAN
705 stw_p(p
++, 0xe020); stw_p(p
++, 0x0be1);
706 /* lui t0, %hi(0xdf000000) */
708 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
709 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
710 /* sw t0, 0x68(t1) */
712 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
713 /* lui t1, %hi(0xbbe00000) */
715 stw_p(p
++, 0xe020); stw_p(p
++, 0x0801);
716 /* lui t0, %hi(0xc0000000) */
718 /* 0x48 corresponds to GT_PCI0IOLD */
719 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
720 /* sw t0, 0x48(t1) */
722 stw_p(p
++, 0xe020); stw_p(p
++, 0x0800);
723 /* lui t0, %hi(0x40000000) */
725 /* 0x50 corresponds to GT_PCI0IOHD */
726 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
727 /* sw t0, 0x50(t1) */
729 stw_p(p
++, 0xe020); stw_p(p
++, 0x0001);
730 /* lui t0, %hi(0x80000000) */
732 /* 0x58 corresponds to GT_PCI0M0LD */
733 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
734 /* sw t0, 0x58(t1) */
736 stw_p(p
++, 0xe020); stw_p(p
++, 0x07e0);
737 /* lui t0, %hi(0x3f000000) */
739 /* 0x60 corresponds to GT_PCI0M0HD */
740 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
741 /* sw t0, 0x60(t1) */
743 stw_p(p
++, 0xe020); stw_p(p
++, 0x0821);
744 /* lui t0, %hi(0xc1000000) */
746 /* 0x80 corresponds to GT_PCI0M1LD */
747 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
748 /* sw t0, 0x80(t1) */
750 stw_p(p
++, 0xe020); stw_p(p
++, 0x0bc0);
751 /* lui t0, %hi(0x5e000000) */
755 stw_p(p
++, 0x0020); stw_p(p
++, 0x00df);
756 /* addiu[32] t0, $0, 0xdf */
758 /* 0x68 corresponds to GT_ISD */
759 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
760 /* sw t0, 0x68(t1) */
762 /* Use kseg2 remapped address 0x1be00000 */
763 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
764 /* lui t1, %hi(0xbbe00000) */
766 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c0);
767 /* addiu[32] t0, $0, 0xc0 */
769 /* 0x48 corresponds to GT_PCI0IOLD */
770 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
771 /* sw t0, 0x48(t1) */
773 stw_p(p
++, 0x0020); stw_p(p
++, 0x0040);
774 /* addiu[32] t0, $0, 0x40 */
776 /* 0x50 corresponds to GT_PCI0IOHD */
777 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
778 /* sw t0, 0x50(t1) */
780 stw_p(p
++, 0x0020); stw_p(p
++, 0x0080);
781 /* addiu[32] t0, $0, 0x80 */
783 /* 0x58 corresponds to GT_PCI0M0LD */
784 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
785 /* sw t0, 0x58(t1) */
787 stw_p(p
++, 0x0020); stw_p(p
++, 0x003f);
788 /* addiu[32] t0, $0, 0x3f */
790 /* 0x60 corresponds to GT_PCI0M0HD */
791 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
792 /* sw t0, 0x60(t1) */
794 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c1);
795 /* addiu[32] t0, $0, 0xc1 */
797 /* 0x80 corresponds to GT_PCI0M1LD */
798 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
799 /* sw t0, 0x80(t1) */
801 stw_p(p
++, 0x0020); stw_p(p
++, 0x005e);
802 /* addiu[32] t0, $0, 0x5e */
806 /* 0x88 corresponds to GT_PCI0M1HD */
807 stw_p(p
++, 0x8422); stw_p(p
++, 0x9088);
808 /* sw t0, 0x88(t1) */
810 stw_p(p
++, 0xe320 | NM_HI1(kernel_entry
));
812 stw_p(p
++, NM_HI2(kernel_entry
));
813 /* lui t9,%hi(kernel_entry) */
815 stw_p(p
++, 0x8339); stw_p(p
++, NM_LO(kernel_entry
));
816 /* ori t9,t9,%lo(kernel_entry) */
818 stw_p(p
++, 0x4bf9); stw_p(p
++, 0x0000);
823 * ROM and pseudo bootloader
825 * The following code implements a very very simple bootloader. It first
826 * loads the registers a0 to a3 to the values expected by the OS, and
827 * then jump at the kernel address.
829 * The bootloader should pass the locations of the kernel arguments and
830 * environment variables tables. Those tables contain the 32-bit address
831 * of NULL terminated strings. The environment variables table should be
832 * terminated by a NULL address.
834 * For a simpler implementation, the number of kernel arguments is fixed
835 * to two (the name of the kernel and the command line), and the two
836 * tables are actually the same one.
838 * The registers a0 to a3 should contain the following values:
839 * a0 - number of kernel arguments
840 * a1 - 32-bit address of the kernel arguments table
841 * a2 - 32-bit address of the environment variables table
842 * a3 - RAM size in bytes
844 static void write_bootloader(uint8_t *base
, uint64_t run_addr
,
845 uint64_t kernel_entry
)
849 /* Small bootloader */
850 p
= (uint32_t *)base
;
852 stl_p(p
++, 0x08000000 | /* j 0x1fc00580 */
853 ((run_addr
+ 0x580) & 0x0fffffff) >> 2);
854 stl_p(p
++, 0x00000000); /* nop */
856 /* YAMON service vector */
857 stl_p(base
+ 0x500, run_addr
+ 0x0580); /* start: */
858 stl_p(base
+ 0x504, run_addr
+ 0x083c); /* print_count: */
859 stl_p(base
+ 0x520, run_addr
+ 0x0580); /* start: */
860 stl_p(base
+ 0x52c, run_addr
+ 0x0800); /* flush_cache: */
861 stl_p(base
+ 0x534, run_addr
+ 0x0808); /* print: */
862 stl_p(base
+ 0x538, run_addr
+ 0x0800); /* reg_cpu_isr: */
863 stl_p(base
+ 0x53c, run_addr
+ 0x0800); /* unred_cpu_isr: */
864 stl_p(base
+ 0x540, run_addr
+ 0x0800); /* reg_ic_isr: */
865 stl_p(base
+ 0x544, run_addr
+ 0x0800); /* unred_ic_isr: */
866 stl_p(base
+ 0x548, run_addr
+ 0x0800); /* reg_esr: */
867 stl_p(base
+ 0x54c, run_addr
+ 0x0800); /* unreg_esr: */
868 stl_p(base
+ 0x550, run_addr
+ 0x0800); /* getchar: */
869 stl_p(base
+ 0x554, run_addr
+ 0x0800); /* syscon_read: */
872 /* Second part of the bootloader */
873 p
= (uint32_t *) (base
+ 0x580);
875 if (semihosting_get_argc()) {
876 /* Preserve a0 content as arguments have been passed */
877 stl_p(p
++, 0x00000000); /* nop */
879 stl_p(p
++, 0x24040002); /* addiu a0, zero, 2 */
882 /* lui sp, high(ENVP_VADDR) */
883 stl_p(p
++, 0x3c1d0000 | (((ENVP_VADDR
- 64) >> 16) & 0xffff));
884 /* ori sp, sp, low(ENVP_VADDR) */
885 stl_p(p
++, 0x37bd0000 | ((ENVP_VADDR
- 64) & 0xffff));
886 /* lui a1, high(ENVP_VADDR) */
887 stl_p(p
++, 0x3c050000 | ((ENVP_VADDR
>> 16) & 0xffff));
888 /* ori a1, a1, low(ENVP_VADDR) */
889 stl_p(p
++, 0x34a50000 | (ENVP_VADDR
& 0xffff));
890 /* lui a2, high(ENVP_VADDR + 8) */
891 stl_p(p
++, 0x3c060000 | (((ENVP_VADDR
+ 8) >> 16) & 0xffff));
892 /* ori a2, a2, low(ENVP_VADDR + 8) */
893 stl_p(p
++, 0x34c60000 | ((ENVP_VADDR
+ 8) & 0xffff));
894 /* lui a3, high(ram_low_size) */
895 stl_p(p
++, 0x3c070000 | (loaderparams
.ram_low_size
>> 16));
896 /* ori a3, a3, low(ram_low_size) */
897 stl_p(p
++, 0x34e70000 | (loaderparams
.ram_low_size
& 0xffff));
899 /* Load BAR registers as done by YAMON */
900 stl_p(p
++, 0x3c09b400); /* lui t1, 0xb400 */
902 #ifdef TARGET_WORDS_BIGENDIAN
903 stl_p(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
905 stl_p(p
++, 0x340800df); /* ori t0, r0, 0x00df */
907 stl_p(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
909 stl_p(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
911 #ifdef TARGET_WORDS_BIGENDIAN
912 stl_p(p
++, 0x3c08c000); /* lui t0, 0xc000 */
914 stl_p(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
916 stl_p(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
917 #ifdef TARGET_WORDS_BIGENDIAN
918 stl_p(p
++, 0x3c084000); /* lui t0, 0x4000 */
920 stl_p(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
922 stl_p(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
924 #ifdef TARGET_WORDS_BIGENDIAN
925 stl_p(p
++, 0x3c088000); /* lui t0, 0x8000 */
927 stl_p(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
929 stl_p(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
930 #ifdef TARGET_WORDS_BIGENDIAN
931 stl_p(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
933 stl_p(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
935 stl_p(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
937 #ifdef TARGET_WORDS_BIGENDIAN
938 stl_p(p
++, 0x3c08c100); /* lui t0, 0xc100 */
940 stl_p(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
942 stl_p(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
943 #ifdef TARGET_WORDS_BIGENDIAN
944 stl_p(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
946 stl_p(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
948 stl_p(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
950 /* Jump to kernel code */
951 stl_p(p
++, 0x3c1f0000 |
952 ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
953 stl_p(p
++, 0x37ff0000 |
954 (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
955 stl_p(p
++, 0x03e00009); /* jalr ra */
956 stl_p(p
++, 0x00000000); /* nop */
958 /* YAMON subroutines */
959 p
= (uint32_t *) (base
+ 0x800);
960 stl_p(p
++, 0x03e00009); /* jalr ra */
961 stl_p(p
++, 0x24020000); /* li v0,0 */
962 /* 808 YAMON print */
963 stl_p(p
++, 0x03e06821); /* move t5,ra */
964 stl_p(p
++, 0x00805821); /* move t3,a0 */
965 stl_p(p
++, 0x00a05021); /* move t2,a1 */
966 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
967 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
968 stl_p(p
++, 0x10800005); /* beqz a0,834 */
969 stl_p(p
++, 0x00000000); /* nop */
970 stl_p(p
++, 0x0ff0021c); /* jal 870 */
971 stl_p(p
++, 0x00000000); /* nop */
972 stl_p(p
++, 0x1000fff9); /* b 814 */
973 stl_p(p
++, 0x00000000); /* nop */
974 stl_p(p
++, 0x01a00009); /* jalr t5 */
975 stl_p(p
++, 0x01602021); /* move a0,t3 */
976 /* 0x83c YAMON print_count */
977 stl_p(p
++, 0x03e06821); /* move t5,ra */
978 stl_p(p
++, 0x00805821); /* move t3,a0 */
979 stl_p(p
++, 0x00a05021); /* move t2,a1 */
980 stl_p(p
++, 0x00c06021); /* move t4,a2 */
981 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
982 stl_p(p
++, 0x0ff0021c); /* jal 870 */
983 stl_p(p
++, 0x00000000); /* nop */
984 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
985 stl_p(p
++, 0x258cffff); /* addiu t4,t4,-1 */
986 stl_p(p
++, 0x1580fffa); /* bnez t4,84c */
987 stl_p(p
++, 0x00000000); /* nop */
988 stl_p(p
++, 0x01a00009); /* jalr t5 */
989 stl_p(p
++, 0x01602021); /* move a0,t3 */
991 stl_p(p
++, 0x3c08b800); /* lui t0,0xb400 */
992 stl_p(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
993 stl_p(p
++, 0x91090005); /* lbu t1,5(t0) */
994 stl_p(p
++, 0x00000000); /* nop */
995 stl_p(p
++, 0x31290040); /* andi t1,t1,0x40 */
996 stl_p(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
997 stl_p(p
++, 0x00000000); /* nop */
998 stl_p(p
++, 0x03e00009); /* jalr ra */
999 stl_p(p
++, 0xa1040000); /* sb a0,0(t0) */
1003 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf
, int index
,
1004 const char *string
, ...)
1007 uint32_t table_addr
;
1009 if (index
>= ENVP_NB_ENTRIES
) {
1013 if (string
== NULL
) {
1014 prom_buf
[index
] = 0;
1018 table_addr
= sizeof(uint32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
1019 prom_buf
[index
] = tswap32(ENVP_VADDR
+ table_addr
);
1021 va_start(ap
, string
);
1022 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
1027 static uint64_t load_kernel(void)
1029 uint64_t kernel_entry
, kernel_high
, initrd_size
;
1031 ram_addr_t initrd_offset
;
1036 uint64_t (*xlate_to_kseg0
) (void *opaque
, uint64_t addr
);
1038 #ifdef TARGET_WORDS_BIGENDIAN
1044 kernel_size
= load_elf(loaderparams
.kernel_filename
, NULL
,
1045 cpu_mips_kseg0_to_phys
, NULL
,
1046 &kernel_entry
, NULL
,
1047 &kernel_high
, NULL
, big_endian
, EM_MIPS
,
1049 if (kernel_size
< 0) {
1050 error_report("could not load kernel '%s': %s",
1051 loaderparams
.kernel_filename
,
1052 load_elf_strerror(kernel_size
));
1056 /* Check where the kernel has been linked */
1057 if (kernel_entry
& 0x80000000ll
) {
1058 if (kvm_enabled()) {
1059 error_report("KVM guest kernels must be linked in useg. "
1060 "Did you forget to enable CONFIG_KVM_GUEST?");
1064 xlate_to_kseg0
= cpu_mips_phys_to_kseg0
;
1066 /* if kernel entry is in useg it is probably a KVM T&E kernel */
1067 mips_um_ksegs_enable();
1069 xlate_to_kseg0
= cpu_mips_kvm_um_phys_to_kseg0
;
1075 if (loaderparams
.initrd_filename
) {
1076 initrd_size
= get_image_size(loaderparams
.initrd_filename
);
1077 if (initrd_size
> 0) {
1079 * The kernel allocates the bootmap memory in the low memory after
1080 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
1083 initrd_offset
= ROUND_UP(loaderparams
.ram_low_size
1084 - (initrd_size
+ 128 * KiB
),
1086 if (kernel_high
>= initrd_offset
) {
1087 error_report("memory too small for initial ram disk '%s'",
1088 loaderparams
.initrd_filename
);
1091 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
1093 loaderparams
.ram_size
- initrd_offset
);
1095 if (initrd_size
== (target_ulong
) -1) {
1096 error_report("could not load initial ram disk '%s'",
1097 loaderparams
.initrd_filename
);
1102 /* Setup prom parameters. */
1103 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
1104 prom_buf
= g_malloc(prom_size
);
1106 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
1107 if (initrd_size
> 0) {
1108 prom_set(prom_buf
, prom_index
++,
1109 "rd_start=0x%" PRIx64
" rd_size=%" PRId64
" %s",
1110 xlate_to_kseg0(NULL
, initrd_offset
),
1111 initrd_size
, loaderparams
.kernel_cmdline
);
1113 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
1116 prom_set(prom_buf
, prom_index
++, "memsize");
1117 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_low_size
);
1119 prom_set(prom_buf
, prom_index
++, "ememsize");
1120 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_size
);
1122 prom_set(prom_buf
, prom_index
++, "modetty0");
1123 prom_set(prom_buf
, prom_index
++, "38400n8r");
1124 prom_set(prom_buf
, prom_index
++, NULL
);
1126 rom_add_blob_fixed("prom", prom_buf
, prom_size
, ENVP_PADDR
);
1129 return kernel_entry
;
1132 static void malta_mips_config(MIPSCPU
*cpu
)
1134 MachineState
*ms
= MACHINE(qdev_get_machine());
1135 unsigned int smp_cpus
= ms
->smp
.cpus
;
1136 CPUMIPSState
*env
= &cpu
->env
;
1137 CPUState
*cs
= CPU(cpu
);
1139 if (ase_mt_available(env
)) {
1140 env
->mvp
->CP0_MVPConf0
= deposit32(env
->mvp
->CP0_MVPConf0
,
1142 smp_cpus
* cs
->nr_threads
- 1);
1143 env
->mvp
->CP0_MVPConf0
= deposit32(env
->mvp
->CP0_MVPConf0
,
1144 CP0MVPC0_PVPE
, 4, smp_cpus
- 1);
1148 static void main_cpu_reset(void *opaque
)
1150 MIPSCPU
*cpu
= opaque
;
1151 CPUMIPSState
*env
= &cpu
->env
;
1153 cpu_reset(CPU(cpu
));
1156 * The bootloader does not need to be rewritten as it is located in a
1157 * read only location. The kernel location and the arguments table
1158 * location does not change.
1160 if (loaderparams
.kernel_filename
) {
1161 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1164 malta_mips_config(cpu
);
1166 if (kvm_enabled()) {
1167 /* Start running from the bootloader we wrote to end of RAM */
1168 env
->active_tc
.PC
= 0x40000000 + loaderparams
.ram_low_size
;
1172 static void create_cpu_without_cps(MachineState
*ms
, MaltaState
*s
,
1173 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1179 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
1180 cpu
= mips_cpu_create_with_clock(ms
->cpu_type
, s
->cpuclk
);
1182 /* Init internal devices */
1183 cpu_mips_irq_init_cpu(cpu
);
1184 cpu_mips_clock_init(cpu
);
1185 qemu_register_reset(main_cpu_reset
, cpu
);
1188 cpu
= MIPS_CPU(first_cpu
);
1190 *i8259_irq
= env
->irq
[2];
1191 *cbus_irq
= env
->irq
[4];
1194 static void create_cps(MachineState
*ms
, MaltaState
*s
,
1195 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1197 object_initialize_child(OBJECT(s
), "cps", &s
->cps
, TYPE_MIPS_CPS
);
1198 object_property_set_str(OBJECT(&s
->cps
), "cpu-type", ms
->cpu_type
,
1200 object_property_set_int(OBJECT(&s
->cps
), "num-vp", ms
->smp
.cpus
,
1202 qdev_connect_clock_in(DEVICE(&s
->cps
), "clk-in", s
->cpuclk
);
1203 sysbus_realize(SYS_BUS_DEVICE(&s
->cps
), &error_fatal
);
1205 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->cps
), 0, 0, 1);
1207 *i8259_irq
= get_cps_irq(&s
->cps
, 3);
1211 static void mips_create_cpu(MachineState
*ms
, MaltaState
*s
,
1212 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1214 if ((ms
->smp
.cpus
> 1) && cpu_type_supports_cps_smp(ms
->cpu_type
)) {
1215 create_cps(ms
, s
, cbus_irq
, i8259_irq
);
1217 create_cpu_without_cps(ms
, s
, cbus_irq
, i8259_irq
);
1222 void mips_malta_init(MachineState
*machine
)
1224 ram_addr_t ram_size
= machine
->ram_size
;
1225 ram_addr_t ram_low_size
;
1226 const char *kernel_filename
= machine
->kernel_filename
;
1227 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1228 const char *initrd_filename
= machine
->initrd_filename
;
1231 MemoryRegion
*system_memory
= get_system_memory();
1232 MemoryRegion
*ram_low_preio
= g_new(MemoryRegion
, 1);
1233 MemoryRegion
*ram_low_postio
;
1234 MemoryRegion
*bios
, *bios_copy
= g_new(MemoryRegion
, 1);
1235 const size_t smbus_eeprom_size
= 8 * 256;
1236 uint8_t *smbus_eeprom_buf
= g_malloc0(smbus_eeprom_size
);
1237 uint64_t kernel_entry
, bootloader_run_addr
;
1240 qemu_irq cbus_irq
, i8259_irq
;
1248 s
= MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA
));
1249 sysbus_realize_and_unref(SYS_BUS_DEVICE(s
), &error_fatal
);
1252 mips_create_cpu(machine
, s
, &cbus_irq
, &i8259_irq
);
1255 if (ram_size
> 2 * GiB
) {
1256 error_report("Too much memory for this machine: %" PRId64
"MB,"
1257 " maximum 2048MB", ram_size
/ MiB
);
1261 /* register RAM at high address where it is undisturbed by IO */
1262 memory_region_add_subregion(system_memory
, 0x80000000, machine
->ram
);
1264 /* alias for pre IO hole access */
1265 memory_region_init_alias(ram_low_preio
, NULL
, "mips_malta_low_preio.ram",
1266 machine
->ram
, 0, MIN(ram_size
, 256 * MiB
));
1267 memory_region_add_subregion(system_memory
, 0, ram_low_preio
);
1269 /* alias for post IO hole access, if there is enough RAM */
1270 if (ram_size
> 512 * MiB
) {
1271 ram_low_postio
= g_new(MemoryRegion
, 1);
1272 memory_region_init_alias(ram_low_postio
, NULL
,
1273 "mips_malta_low_postio.ram",
1274 machine
->ram
, 512 * MiB
,
1275 ram_size
- 512 * MiB
);
1276 memory_region_add_subregion(system_memory
, 512 * MiB
,
1280 #ifdef TARGET_WORDS_BIGENDIAN
1288 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1289 malta_fpga_init(system_memory
, FPGA_ADDRESS
, cbus_irq
, serial_hd(2));
1291 /* Load firmware in flash / BIOS. */
1292 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
1293 fl
= pflash_cfi01_register(FLASH_ADDRESS
, "mips_malta.bios",
1295 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
1297 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
1298 bios
= pflash_cfi01_get_memory(fl
);
1300 if (kernel_filename
) {
1301 ram_low_size
= MIN(ram_size
, 256 * MiB
);
1302 /* For KVM we reserve 1MB of RAM for running bootloader */
1303 if (kvm_enabled()) {
1304 ram_low_size
-= 0x100000;
1305 bootloader_run_addr
= cpu_mips_kvm_um_phys_to_kseg0(NULL
, ram_low_size
);
1307 bootloader_run_addr
= cpu_mips_phys_to_kseg0(NULL
, RESET_ADDRESS
);
1310 /* Write a small bootloader to the flash location. */
1311 loaderparams
.ram_size
= ram_size
;
1312 loaderparams
.ram_low_size
= ram_low_size
;
1313 loaderparams
.kernel_filename
= kernel_filename
;
1314 loaderparams
.kernel_cmdline
= kernel_cmdline
;
1315 loaderparams
.initrd_filename
= initrd_filename
;
1316 kernel_entry
= load_kernel();
1318 if (!cpu_type_supports_isa(machine
->cpu_type
, ISA_NANOMIPS32
)) {
1319 write_bootloader(memory_region_get_ram_ptr(bios
),
1320 bootloader_run_addr
, kernel_entry
);
1322 write_bootloader_nanomips(memory_region_get_ram_ptr(bios
),
1323 bootloader_run_addr
, kernel_entry
);
1325 if (kvm_enabled()) {
1326 /* Write the bootloader code @ the end of RAM, 1MB reserved */
1327 write_bootloader(memory_region_get_ram_ptr(ram_low_preio
) +
1329 bootloader_run_addr
, kernel_entry
);
1332 target_long bios_size
= FLASH_SIZE
;
1333 /* The flash region isn't executable from a KVM guest */
1334 if (kvm_enabled()) {
1335 error_report("KVM enabled but no -kernel argument was specified. "
1336 "Booting from flash is not supported with KVM.");
1339 /* Load firmware from flash. */
1341 /* Load a BIOS image. */
1342 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
,
1343 machine
->firmware
?: BIOS_FILENAME
);
1345 bios_size
= load_image_targphys(filename
, FLASH_ADDRESS
,
1351 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) &&
1352 machine
->firmware
&& !qtest_enabled()) {
1353 error_report("Could not load MIPS bios '%s'", machine
->firmware
);
1358 * In little endian mode the 32bit words in the bios are swapped,
1359 * a neat trick which allows bi-endian firmware.
1361 #ifndef TARGET_WORDS_BIGENDIAN
1363 uint32_t *end
, *addr
;
1364 const size_t swapsize
= MIN(bios_size
, 0x3e0000);
1365 addr
= rom_ptr(FLASH_ADDRESS
, swapsize
);
1367 addr
= memory_region_get_ram_ptr(bios
);
1369 end
= (void *)addr
+ swapsize
;
1370 while (addr
< end
) {
1379 * Map the BIOS at a 2nd physical location, as on the real board.
1380 * Copy it so that we can patch in the MIPS revision, which cannot be
1381 * handled by an overlapping region as the resulting ROM code subpage
1382 * regions are not executable.
1384 memory_region_init_ram(bios_copy
, NULL
, "bios.1fc", BIOS_SIZE
,
1386 if (!rom_copy(memory_region_get_ram_ptr(bios_copy
),
1387 FLASH_ADDRESS
, BIOS_SIZE
)) {
1388 memcpy(memory_region_get_ram_ptr(bios_copy
),
1389 memory_region_get_ram_ptr(bios
), BIOS_SIZE
);
1391 memory_region_set_readonly(bios_copy
, true);
1392 memory_region_add_subregion(system_memory
, RESET_ADDRESS
, bios_copy
);
1394 /* Board ID = 0x420 (Malta Board with CoreLV) */
1395 stl_p(memory_region_get_ram_ptr(bios_copy
) + 0x10, 0x00000420);
1398 pci_bus
= gt64120_register(s
->i8259
);
1400 * The whole address space decoded by the GT-64120A doesn't generate
1401 * exception when accessing invalid memory. Create an empty slot to
1402 * emulate this feature.
1404 empty_slot_init("GT64120", 0, 0x20000000);
1407 dev
= piix4_create(pci_bus
, &isa_bus
, &smbus
);
1409 /* Interrupt controller */
1410 qdev_connect_gpio_out_named(dev
, "intr", 0, i8259_irq
);
1411 for (int i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1412 s
->i8259
[i
] = qdev_get_gpio_in_named(dev
, "isa", i
);
1415 /* generate SPD EEPROM data */
1416 generate_eeprom_spd(&smbus_eeprom_buf
[0 * 256], ram_size
);
1417 generate_eeprom_serial(&smbus_eeprom_buf
[6 * 256]);
1418 smbus_eeprom_init(smbus
, 8, smbus_eeprom_buf
, smbus_eeprom_size
);
1419 g_free(smbus_eeprom_buf
);
1421 /* Super I/O: SMS FDC37M817 */
1422 isa_create_simple(isa_bus
, TYPE_FDC37M81X_SUPERIO
);
1425 network_init(pci_bus
);
1427 /* Optional PCI video card */
1428 pci_vga_init(pci_bus
);
1431 static void mips_malta_instance_init(Object
*obj
)
1433 MaltaState
*s
= MIPS_MALTA(obj
);
1435 s
->cpuclk
= qdev_init_clock_out(DEVICE(obj
), "cpu-refclk");
1436 clock_set_hz(s
->cpuclk
, 320000000); /* 320 MHz */
1439 static const TypeInfo mips_malta_device
= {
1440 .name
= TYPE_MIPS_MALTA
,
1441 .parent
= TYPE_SYS_BUS_DEVICE
,
1442 .instance_size
= sizeof(MaltaState
),
1443 .instance_init
= mips_malta_instance_init
,
1446 static void mips_malta_machine_init(MachineClass
*mc
)
1448 mc
->desc
= "MIPS Malta Core LV";
1449 mc
->init
= mips_malta_init
;
1450 mc
->block_default_type
= IF_IDE
;
1452 mc
->is_default
= true;
1453 #ifdef TARGET_MIPS64
1454 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("20Kc");
1456 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("24Kf");
1458 mc
->default_ram_id
= "mips_malta.ram";
1461 DEFINE_MACHINE("malta", mips_malta_machine_init
)
1463 static void mips_malta_register_types(void)
1465 type_register_static(&mips_malta_device
);
1468 type_init(mips_malta_register_types
)