ast2400: externalize revision numbers
[qemu/kevin.git] / hw / arm / ast2400.c
blob326fdb36eed55c4cc7f5a489ac6b094be8c493f1
1 /*
2 * AST2400 SoC
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
16 #include "cpu.h"
17 #include "exec/address-spaces.h"
18 #include "hw/arm/ast2400.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "hw/i2c/aspeed_i2c.h"
23 #define AST2400_UART_5_BASE 0x00184000
24 #define AST2400_IOMEM_SIZE 0x00200000
25 #define AST2400_IOMEM_BASE 0x1E600000
26 #define AST2400_SMC_BASE AST2400_IOMEM_BASE /* Legacy SMC */
27 #define AST2400_FMC_BASE 0X1E620000
28 #define AST2400_SPI_BASE 0X1E630000
29 #define AST2400_VIC_BASE 0x1E6C0000
30 #define AST2400_SCU_BASE 0x1E6E2000
31 #define AST2400_TIMER_BASE 0x1E782000
32 #define AST2400_I2C_BASE 0x1E78A000
34 #define AST2400_FMC_FLASH_BASE 0x20000000
35 #define AST2400_SPI_FLASH_BASE 0x30000000
37 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
38 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
41 * IO handlers: simply catch any reads/writes to IO addresses that aren't
42 * handled by a device mapping.
45 static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
48 __func__, offset, size);
49 return 0;
52 static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
53 unsigned size)
55 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
56 __func__, offset, value, size);
59 static const MemoryRegionOps ast2400_io_ops = {
60 .read = ast2400_io_read,
61 .write = ast2400_io_write,
62 .endianness = DEVICE_LITTLE_ENDIAN,
65 static void ast2400_init(Object *obj)
67 AST2400State *s = AST2400(obj);
69 s->cpu = cpu_arm_init("arm926");
71 object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
72 object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
73 qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
75 object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
76 object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
77 qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
79 object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
80 object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
81 qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
83 object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
84 object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
85 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
86 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
87 AST2400_A0_SILICON_REV);
88 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
89 "hw-strap1", &error_abort);
90 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
91 "hw-strap2", &error_abort);
93 object_initialize(&s->smc, sizeof(s->smc), "aspeed.smc.fmc");
94 object_property_add_child(obj, "smc", OBJECT(&s->smc), NULL);
95 qdev_set_parent_bus(DEVICE(&s->smc), sysbus_get_default());
97 object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi");
98 object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL);
99 qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default());
102 static void ast2400_realize(DeviceState *dev, Error **errp)
104 int i;
105 AST2400State *s = AST2400(dev);
106 Error *err = NULL, *local_err = NULL;
108 /* IO space */
109 memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
110 "ast2400.io", AST2400_IOMEM_SIZE);
111 memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
112 &s->iomem, -1);
114 /* VIC */
115 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
116 if (err) {
117 error_propagate(errp, err);
118 return;
120 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
121 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
122 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
123 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
124 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
126 /* Timer */
127 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
128 if (err) {
129 error_propagate(errp, err);
130 return;
132 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
133 for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
134 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
135 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
138 /* SCU */
139 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
140 if (err) {
141 error_propagate(errp, err);
142 return;
144 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
146 /* UART - attach an 8250 to the IO space as our UART5 */
147 if (serial_hds[0]) {
148 qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
149 serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
150 uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
153 /* I2C */
154 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
155 if (err) {
156 error_propagate(errp, err);
157 return;
159 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
160 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
161 qdev_get_gpio_in(DEVICE(&s->vic), 12));
163 /* SMC */
164 object_property_set_int(OBJECT(&s->smc), 1, "num-cs", &err);
165 object_property_set_bool(OBJECT(&s->smc), true, "realized", &local_err);
166 error_propagate(&err, local_err);
167 if (err) {
168 error_propagate(errp, err);
169 return;
171 sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, AST2400_FMC_BASE);
172 sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, AST2400_FMC_FLASH_BASE);
173 sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,
174 qdev_get_gpio_in(DEVICE(&s->vic), 19));
176 /* SPI */
177 object_property_set_int(OBJECT(&s->spi), 1, "num-cs", &err);
178 object_property_set_bool(OBJECT(&s->spi), true, "realized", &local_err);
179 error_propagate(&err, local_err);
180 if (err) {
181 error_propagate(errp, err);
182 return;
184 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);
185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);
188 static void ast2400_class_init(ObjectClass *oc, void *data)
190 DeviceClass *dc = DEVICE_CLASS(oc);
192 dc->realize = ast2400_realize;
195 * Reason: creates an ARM CPU, thus use after free(), see
196 * arm_cpu_class_init()
198 dc->cannot_destroy_with_object_finalize_yet = true;
201 static const TypeInfo ast2400_type_info = {
202 .name = TYPE_AST2400,
203 .parent = TYPE_SYS_BUS_DEVICE,
204 .instance_size = sizeof(AST2400State),
205 .instance_init = ast2400_init,
206 .class_init = ast2400_class_init,
209 static void ast2400_register_types(void)
211 type_register_static(&ast2400_type_info);
214 type_init(ast2400_register_types)