target/riscv/translate.c

   1 /*
   2  * RISC-V emulation for qemu: main translation routines.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "cpu.h"
  22 #include "tcg/tcg-op.h"
  23 #include "disas/disas.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/helper-proto.h"
  27 #include "exec/helper-gen.h"
  28
  29 #include "exec/translator.h"
  30 #include "exec/log.h"
  31
  32 #include "instmap.h"
  33
  34 /* global register indices */
  35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
  36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
  37 static TCGv load_res;
  38 static TCGv load_val;
  39
  40 #include "exec/gen-icount.h"
  41
  42 typedef struct DisasContext {
  43     DisasContextBase base;
  44     /* pc_succ_insn points to the instruction following base.pc_next */
  45     target_ulong pc_succ_insn;
  46     target_ulong priv_ver;
  47     bool virt_enabled;
  48     uint32_t opcode;
  49     uint32_t mstatus_fs;
  50     uint32_t misa;
  51     uint32_t mem_idx;
  52     /* Remember the rounding mode encoded in the previous fp instruction,
  53        which we have already installed into env->fp_status.  Or -1 for
  54        no previous fp instruction.  Note that we exit the TB when writing
  55        to any system register, which includes CSR_FRM, so we do not have
  56        to reset this known value.  */
  57     int frm;
  58     bool ext_ifencei;
  59     bool hlsx;
  60     /* vector extension */
  61     bool vill;
  62     uint8_t lmul;
  63     uint8_t sew;
  64     uint16_t vlen;
  65     uint16_t mlen;
  66     bool vl_eq_vlmax;
  67     CPUState *cs;
  68 } DisasContext;
  69
  70 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  71 {
  72     return ctx->misa & ext;
  73 }
  74
  75 #ifdef TARGET_RISCV32
  76 # define is_32bit(ctx)  true
  77 #elif defined(CONFIG_USER_ONLY)
  78 # define is_32bit(ctx)  false
  79 #else
  80 static inline bool is_32bit(DisasContext *ctx)
  81 {
  82     return (ctx->misa & RV32) == RV32;
  83 }
  84 #endif
  85
  86 /*
  87  * RISC-V requires NaN-boxing of narrower width floating point values.
  88  * This applies when a 32-bit value is assigned to a 64-bit FP register.
  89  * For consistency and simplicity, we nanbox results even when the RVD
  90  * extension is not present.
  91  */
  92 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
  93 {
  94     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
  95 }
  96
  97 /*
  98  * A narrow n-bit operation, where n < FLEN, checks that input operands
  99  * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
 100  * If so, the least-significant bits of the input are used, otherwise the
 101  * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
 102  *
 103  * Here, the result is always nan-boxed, even the canonical nan.
 104  */
 105 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 106 {
 107     TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
 108     TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull);
 109
 110     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 111     tcg_temp_free_i64(t_max);
 112     tcg_temp_free_i64(t_nan);
 113 }
 114
 115 static void generate_exception(DisasContext *ctx, int excp)
 116 {
 117     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 118     TCGv_i32 helper_tmp = tcg_const_i32(excp);
 119     gen_helper_raise_exception(cpu_env, helper_tmp);
 120     tcg_temp_free_i32(helper_tmp);
 121     ctx->base.is_jmp = DISAS_NORETURN;
 122 }
 123
 124 static void generate_exception_mtval(DisasContext *ctx, int excp)
 125 {
 126     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 127     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 128     TCGv_i32 helper_tmp = tcg_const_i32(excp);
 129     gen_helper_raise_exception(cpu_env, helper_tmp);
 130     tcg_temp_free_i32(helper_tmp);
 131     ctx->base.is_jmp = DISAS_NORETURN;
 132 }
 133
 134 static void gen_exception_debug(void)
 135 {
 136     TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
 137     gen_helper_raise_exception(cpu_env, helper_tmp);
 138     tcg_temp_free_i32(helper_tmp);
 139 }
 140
 141 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
 142 static void exit_tb(DisasContext *ctx)
 143 {
 144     if (ctx->base.singlestep_enabled) {
 145         gen_exception_debug();
 146     } else {
 147         tcg_gen_exit_tb(NULL, 0);
 148     }
 149 }
 150
 151 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
 152 static void lookup_and_goto_ptr(DisasContext *ctx)
 153 {
 154     if (ctx->base.singlestep_enabled) {
 155         gen_exception_debug();
 156     } else {
 157         tcg_gen_lookup_and_goto_ptr();
 158     }
 159 }
 160
 161 static void gen_exception_illegal(DisasContext *ctx)
 162 {
 163     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 164 }
 165
 166 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 167 {
 168     generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 169 }
 170
 171 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 172 {
 173     if (unlikely(ctx->base.singlestep_enabled)) {
 174         return false;
 175     }
 176
 177 #ifndef CONFIG_USER_ONLY
 178     return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 179 #else
 180     return true;
 181 #endif
 182 }
 183
 184 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 185 {
 186     if (use_goto_tb(ctx, dest)) {
 187         /* chaining is only allowed when the jump is to the same page */
 188         tcg_gen_goto_tb(n);
 189         tcg_gen_movi_tl(cpu_pc, dest);
 190
 191         /* No need to check for single stepping here as use_goto_tb() will
 192          * return false in case of single stepping.
 193          */
 194         tcg_gen_exit_tb(ctx->base.tb, n);
 195     } else {
 196         tcg_gen_movi_tl(cpu_pc, dest);
 197         lookup_and_goto_ptr(ctx);
 198     }
 199 }
 200
 201 /* Wrapper for getting reg values - need to check of reg is zero since
 202  * cpu_gpr[0] is not actually allocated
 203  */
 204 static inline void gen_get_gpr(TCGv t, int reg_num)
 205 {
 206     if (reg_num == 0) {
 207         tcg_gen_movi_tl(t, 0);
 208     } else {
 209         tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
 210     }
 211 }
 212
 213 /* Wrapper for setting reg values - need to check of reg is zero since
 214  * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
 215  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
 216  * $zero
 217  */
 218 static inline void gen_set_gpr(int reg_num_dst, TCGv t)
 219 {
 220     if (reg_num_dst != 0) {
 221         tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
 222     }
 223 }
 224
 225 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 226 {
 227     TCGv rl = tcg_temp_new();
 228     TCGv rh = tcg_temp_new();
 229
 230     tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
 231     /* fix up for one negative */
 232     tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
 233     tcg_gen_and_tl(rl, rl, arg2);
 234     tcg_gen_sub_tl(ret, rh, rl);
 235
 236     tcg_temp_free(rl);
 237     tcg_temp_free(rh);
 238 }
 239
 240 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 241 {
 242     TCGv cond1, cond2, zeroreg, resultopt1;
 243     /*
 244      * Handle by altering args to tcg_gen_div to produce req'd results:
 245      * For overflow: want source1 in source1 and 1 in source2
 246      * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
 247      */
 248     cond1 = tcg_temp_new();
 249     cond2 = tcg_temp_new();
 250     zeroreg = tcg_const_tl(0);
 251     resultopt1 = tcg_temp_new();
 252
 253     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 254     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
 255     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 256                         ((target_ulong)1) << (TARGET_LONG_BITS - 1));
 257     tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
 258     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
 259     /* if div by zero, set source1 to -1, otherwise don't change */
 260     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
 261             resultopt1);
 262     /* if overflow or div by zero, set source2 to 1, else don't change */
 263     tcg_gen_or_tl(cond1, cond1, cond2);
 264     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 265     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 266             resultopt1);
 267     tcg_gen_div_tl(ret, source1, source2);
 268
 269     tcg_temp_free(cond1);
 270     tcg_temp_free(cond2);
 271     tcg_temp_free(zeroreg);
 272     tcg_temp_free(resultopt1);
 273 }
 274
 275 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
 276 {
 277     TCGv cond1, zeroreg, resultopt1;
 278     cond1 = tcg_temp_new();
 279
 280     zeroreg = tcg_const_tl(0);
 281     resultopt1 = tcg_temp_new();
 282
 283     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 284     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 285     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
 286             resultopt1);
 287     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 288     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 289             resultopt1);
 290     tcg_gen_divu_tl(ret, source1, source2);
 291
 292     tcg_temp_free(cond1);
 293     tcg_temp_free(zeroreg);
 294     tcg_temp_free(resultopt1);
 295 }
 296
 297 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 298 {
 299     TCGv cond1, cond2, zeroreg, resultopt1;
 300
 301     cond1 = tcg_temp_new();
 302     cond2 = tcg_temp_new();
 303     zeroreg = tcg_const_tl(0);
 304     resultopt1 = tcg_temp_new();
 305
 306     tcg_gen_movi_tl(resultopt1, 1L);
 307     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
 308     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 309                         (target_ulong)1 << (TARGET_LONG_BITS - 1));
 310     tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
 311     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
 312     /* if overflow or div by zero, set source2 to 1, else don't change */
 313     tcg_gen_or_tl(cond2, cond1, cond2);
 314     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
 315             resultopt1);
 316     tcg_gen_rem_tl(resultopt1, source1, source2);
 317     /* if div by zero, just return the original dividend */
 318     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 319             source1);
 320
 321     tcg_temp_free(cond1);
 322     tcg_temp_free(cond2);
 323     tcg_temp_free(zeroreg);
 324     tcg_temp_free(resultopt1);
 325 }
 326
 327 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 328 {
 329     TCGv cond1, zeroreg, resultopt1;
 330     cond1 = tcg_temp_new();
 331     zeroreg = tcg_const_tl(0);
 332     resultopt1 = tcg_temp_new();
 333
 334     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 335     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 336     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 337             resultopt1);
 338     tcg_gen_remu_tl(resultopt1, source1, source2);
 339     /* if div by zero, just return the original dividend */
 340     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 341             source1);
 342
 343     tcg_temp_free(cond1);
 344     tcg_temp_free(zeroreg);
 345     tcg_temp_free(resultopt1);
 346 }
 347
 348 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 349 {
 350     target_ulong next_pc;
 351
 352     /* check misaligned: */
 353     next_pc = ctx->base.pc_next + imm;
 354     if (!has_ext(ctx, RVC)) {
 355         if ((next_pc & 0x3) != 0) {
 356             gen_exception_inst_addr_mis(ctx);
 357             return;
 358         }
 359     }
 360     if (rd != 0) {
 361         tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
 362     }
 363
 364     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
 365     ctx->base.is_jmp = DISAS_NORETURN;
 366 }
 367
 368 #ifndef CONFIG_USER_ONLY
 369 /* The states of mstatus_fs are:
 370  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
 371  * We will have already diagnosed disabled state,
 372  * and need to turn initial/clean into dirty.
 373  */
 374 static void mark_fs_dirty(DisasContext *ctx)
 375 {
 376     TCGv tmp;
 377     target_ulong sd;
 378
 379     if (ctx->mstatus_fs == MSTATUS_FS) {
 380         return;
 381     }
 382     /* Remember the state change for the rest of the TB.  */
 383     ctx->mstatus_fs = MSTATUS_FS;
 384
 385     tmp = tcg_temp_new();
 386     sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 387
 388     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 389     tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 390     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 391
 392     if (ctx->virt_enabled) {
 393         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 394         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 395         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 396     }
 397     tcg_temp_free(tmp);
 398 }
 399 #else
 400 static inline void mark_fs_dirty(DisasContext *ctx) { }
 401 #endif
 402
 403 static void gen_set_rm(DisasContext *ctx, int rm)
 404 {
 405     TCGv_i32 t0;
 406
 407     if (ctx->frm == rm) {
 408         return;
 409     }
 410     ctx->frm = rm;
 411     t0 = tcg_const_i32(rm);
 412     gen_helper_set_rounding_mode(cpu_env, t0);
 413     tcg_temp_free_i32(t0);
 414 }
 415
 416 static int ex_plus_1(DisasContext *ctx, int nf)
 417 {
 418     return nf + 1;
 419 }
 420
 421 #define EX_SH(amount) \
 422     static int ex_shift_##amount(DisasContext *ctx, int imm) \
 423     {                                         \
 424         return imm << amount;                 \
 425     }
 426 EX_SH(1)
 427 EX_SH(2)
 428 EX_SH(3)
 429 EX_SH(4)
 430 EX_SH(12)
 431
 432 #define REQUIRE_EXT(ctx, ext) do { \
 433     if (!has_ext(ctx, ext)) {      \
 434         return false;              \
 435     }                              \
 436 } while (0)
 437
 438 #define REQUIRE_64BIT(ctx) do { \
 439     if (is_32bit(ctx)) {        \
 440         return false;           \
 441     }                           \
 442 } while (0)
 443
 444 static int ex_rvc_register(DisasContext *ctx, int reg)
 445 {
 446     return 8 + reg;
 447 }
 448
 449 static int ex_rvc_shifti(DisasContext *ctx, int imm)
 450 {
 451     /* For RV128 a shamt of 0 means a shift by 64. */
 452     return imm ? imm : 64;
 453 }
 454
 455 /* Include the auto-generated decoder for 32 bit insn */
 456 #include "decode-insn32.c.inc"
 457
 458 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
 459                              void (*func)(TCGv, TCGv, target_long))
 460 {
 461     TCGv source1;
 462     source1 = tcg_temp_new();
 463
 464     gen_get_gpr(source1, a->rs1);
 465
 466     (*func)(source1, source1, a->imm);
 467
 468     gen_set_gpr(a->rd, source1);
 469     tcg_temp_free(source1);
 470     return true;
 471 }
 472
 473 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
 474                              void (*func)(TCGv, TCGv, TCGv))
 475 {
 476     TCGv source1, source2;
 477     source1 = tcg_temp_new();
 478     source2 = tcg_temp_new();
 479
 480     gen_get_gpr(source1, a->rs1);
 481     tcg_gen_movi_tl(source2, a->imm);
 482
 483     (*func)(source1, source1, source2);
 484
 485     gen_set_gpr(a->rd, source1);
 486     tcg_temp_free(source1);
 487     tcg_temp_free(source2);
 488     return true;
 489 }
 490
 491 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 492 {
 493     tcg_gen_add_tl(ret, arg1, arg2);
 494     tcg_gen_ext32s_tl(ret, ret);
 495 }
 496
 497 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
 498 {
 499     tcg_gen_sub_tl(ret, arg1, arg2);
 500     tcg_gen_ext32s_tl(ret, ret);
 501 }
 502
 503 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
 504 {
 505     tcg_gen_mul_tl(ret, arg1, arg2);
 506     tcg_gen_ext32s_tl(ret, ret);
 507 }
 508
 509 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
 510                             void(*func)(TCGv, TCGv, TCGv))
 511 {
 512     TCGv source1, source2;
 513     source1 = tcg_temp_new();
 514     source2 = tcg_temp_new();
 515
 516     gen_get_gpr(source1, a->rs1);
 517     gen_get_gpr(source2, a->rs2);
 518     tcg_gen_ext32s_tl(source1, source1);
 519     tcg_gen_ext32s_tl(source2, source2);
 520
 521     (*func)(source1, source1, source2);
 522
 523     tcg_gen_ext32s_tl(source1, source1);
 524     gen_set_gpr(a->rd, source1);
 525     tcg_temp_free(source1);
 526     tcg_temp_free(source2);
 527     return true;
 528 }
 529
 530 static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 531                             void(*func)(TCGv, TCGv, TCGv))
 532 {
 533     TCGv source1, source2;
 534     source1 = tcg_temp_new();
 535     source2 = tcg_temp_new();
 536
 537     gen_get_gpr(source1, a->rs1);
 538     gen_get_gpr(source2, a->rs2);
 539     tcg_gen_ext32u_tl(source1, source1);
 540     tcg_gen_ext32u_tl(source2, source2);
 541
 542     (*func)(source1, source1, source2);
 543
 544     tcg_gen_ext32s_tl(source1, source1);
 545     gen_set_gpr(a->rd, source1);
 546     tcg_temp_free(source1);
 547     tcg_temp_free(source2);
 548     return true;
 549 }
 550
 551 static bool gen_arith(DisasContext *ctx, arg_r *a,
 552                       void(*func)(TCGv, TCGv, TCGv))
 553 {
 554     TCGv source1, source2;
 555     source1 = tcg_temp_new();
 556     source2 = tcg_temp_new();
 557
 558     gen_get_gpr(source1, a->rs1);
 559     gen_get_gpr(source2, a->rs2);
 560
 561     (*func)(source1, source1, source2);
 562
 563     gen_set_gpr(a->rd, source1);
 564     tcg_temp_free(source1);
 565     tcg_temp_free(source2);
 566     return true;
 567 }
 568
 569 static bool gen_shift(DisasContext *ctx, arg_r *a,
 570                         void(*func)(TCGv, TCGv, TCGv))
 571 {
 572     TCGv source1 = tcg_temp_new();
 573     TCGv source2 = tcg_temp_new();
 574
 575     gen_get_gpr(source1, a->rs1);
 576     gen_get_gpr(source2, a->rs2);
 577
 578     tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
 579     (*func)(source1, source1, source2);
 580
 581     gen_set_gpr(a->rd, source1);
 582     tcg_temp_free(source1);
 583     tcg_temp_free(source2);
 584     return true;
 585 }
 586
 587 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 588 {
 589     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 590     CPUState *cpu = ctx->cs;
 591     CPURISCVState *env = cpu->env_ptr;
 592
 593     return cpu_ldl_code(env, pc);
 594 }
 595
 596 /* Include insn module translation function */
 597 #include "insn_trans/trans_rvi.c.inc"
 598 #include "insn_trans/trans_rvm.c.inc"
 599 #include "insn_trans/trans_rva.c.inc"
 600 #include "insn_trans/trans_rvf.c.inc"
 601 #include "insn_trans/trans_rvd.c.inc"
 602 #include "insn_trans/trans_rvh.c.inc"
 603 #include "insn_trans/trans_rvv.c.inc"
 604 #include "insn_trans/trans_privileged.c.inc"
 605
 606 /* Include the auto-generated decoder for 16 bit insn */
 607 #include "decode-insn16.c.inc"
 608
 609 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 610 {
 611     /* check for compressed insn */
 612     if (extract16(opcode, 0, 2) != 3) {
 613         if (!has_ext(ctx, RVC)) {
 614             gen_exception_illegal(ctx);
 615         } else {
 616             ctx->pc_succ_insn = ctx->base.pc_next + 2;
 617             if (!decode_insn16(ctx, opcode)) {
 618                 gen_exception_illegal(ctx);
 619             }
 620         }
 621     } else {
 622         uint32_t opcode32 = opcode;
 623         opcode32 = deposit32(opcode32, 16, 16,
 624                              translator_lduw(env, ctx->base.pc_next + 2));
 625         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 626         if (!decode_insn32(ctx, opcode32)) {
 627             gen_exception_illegal(ctx);
 628         }
 629     }
 630 }
 631
 632 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 633 {
 634     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 635     CPURISCVState *env = cs->env_ptr;
 636     RISCVCPU *cpu = RISCV_CPU(cs);
 637     uint32_t tb_flags = ctx->base.tb->flags;
 638
 639     ctx->pc_succ_insn = ctx->base.pc_first;
 640     ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
 641     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
 642     ctx->priv_ver = env->priv_ver;
 643 #if !defined(CONFIG_USER_ONLY)
 644     if (riscv_has_ext(env, RVH)) {
 645         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
 646     } else {
 647         ctx->virt_enabled = false;
 648     }
 649 #else
 650     ctx->virt_enabled = false;
 651 #endif
 652     ctx->misa = env->misa;
 653     ctx->frm = -1;  /* unknown rounding mode */
 654     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 655     ctx->vlen = cpu->cfg.vlen;
 656     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
 657     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
 658     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 659     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
 660     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
 661     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 662     ctx->cs = cs;
 663 }
 664
 665 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 666 {
 667 }
 668
 669 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 670 {
 671     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 672
 673     tcg_gen_insn_start(ctx->base.pc_next);
 674 }
 675
 676 static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
 677                                       const CPUBreakpoint *bp)
 678 {
 679     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 680
 681     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 682     ctx->base.is_jmp = DISAS_NORETURN;
 683     gen_exception_debug();
 684     /* The address covered by the breakpoint must be included in
 685        [tb->pc, tb->pc + tb->size) in order to for it to be
 686        properly cleared -- thus we increment the PC here so that
 687        the logic setting tb->size below does the right thing.  */
 688     ctx->base.pc_next += 4;
 689     return true;
 690 }
 691
 692 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 693 {
 694     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 695     CPURISCVState *env = cpu->env_ptr;
 696     uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
 697
 698     decode_opc(env, ctx, opcode16);
 699     ctx->base.pc_next = ctx->pc_succ_insn;
 700
 701     if (ctx->base.is_jmp == DISAS_NEXT) {
 702         target_ulong page_start;
 703
 704         page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
 705         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
 706             ctx->base.is_jmp = DISAS_TOO_MANY;
 707         }
 708     }
 709 }
 710
 711 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 712 {
 713     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 714
 715     switch (ctx->base.is_jmp) {
 716     case DISAS_TOO_MANY:
 717         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 718         break;
 719     case DISAS_NORETURN:
 720         break;
 721     default:
 722         g_assert_not_reached();
 723     }
 724 }
 725
 726 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 727 {
 728 #ifndef CONFIG_USER_ONLY
 729     RISCVCPU *rvcpu = RISCV_CPU(cpu);
 730     CPURISCVState *env = &rvcpu->env;
 731 #endif
 732
 733     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 734 #ifndef CONFIG_USER_ONLY
 735     qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
 736 #endif
 737     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 738 }
 739
 740 static const TranslatorOps riscv_tr_ops = {
 741     .init_disas_context = riscv_tr_init_disas_context,
 742     .tb_start           = riscv_tr_tb_start,
 743     .insn_start         = riscv_tr_insn_start,
 744     .breakpoint_check   = riscv_tr_breakpoint_check,
 745     .translate_insn     = riscv_tr_translate_insn,
 746     .tb_stop            = riscv_tr_tb_stop,
 747     .disas_log          = riscv_tr_disas_log,
 748 };
 749
 750 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 751 {
 752     DisasContext ctx;
 753
 754     translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
 755 }
 756
 757 void riscv_translate_init(void)
 758 {
 759     int i;
 760
 761     /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
 762     /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
 763     /* registers, unless you specifically block reads/writes to reg 0 */
 764     cpu_gpr[0] = NULL;
 765
 766     for (i = 1; i < 32; i++) {
 767         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 768             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
 769     }
 770
 771     for (i = 0; i < 32; i++) {
 772         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 773             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
 774     }
 775
 776     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
 777     cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
 778     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
 779                              "load_res");
 780     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
 781                              "load_val");
 782 }