hw/misc/aspeed_sdmc.c

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "hw/misc/aspeed_sdmc.h"
  14 #include "hw/misc/aspeed_scu.h"
  15 #include "hw/qdev-properties.h"
  16 #include "qapi/error.h"
  17 #include "trace.h"
  18
  19 /* Protection Key Register */
  20 #define R_PROT            (0x00 / 4)
  21 #define   PROT_KEY_UNLOCK     0xFC600309
  22
  23 /* Configuration Register */
  24 #define R_CONF            (0x04 / 4)
  25
  26 /* Control/Status Register #1 (ast2500) */
  27 #define R_STATUS1         (0x60 / 4)
  28 #define   PHY_BUSY_STATE      BIT(0)
  29
  30 #define R_ECC_TEST_CTRL   (0x70 / 4)
  31 #define   ECC_TEST_FINISHED   BIT(12)
  32 #define   ECC_TEST_FAIL       BIT(13)
  33
  34 /*
  35  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  36  *
  37  * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  38  * what we care about right now as it is checked by U-Boot to
  39  * determine the RAM size.
  40  */
  41
  42 #define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  43 #define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  44 #define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  45 #define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  46 #define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  47 #define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  48 #define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  49 #define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  50 #define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  51 #define     ASPEED_SDMC_VGA_8MB             0x0
  52 #define     ASPEED_SDMC_VGA_16MB            0x1
  53 #define     ASPEED_SDMC_VGA_32MB            0x2
  54 #define     ASPEED_SDMC_VGA_64MB            0x3
  55 #define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  56 #define     ASPEED_SDMC_DRAM_64MB           0x0
  57 #define     ASPEED_SDMC_DRAM_128MB          0x1
  58 #define     ASPEED_SDMC_DRAM_256MB          0x2
  59 #define     ASPEED_SDMC_DRAM_512MB          0x3
  60
  61 #define ASPEED_SDMC_READONLY_MASK                       \
  62     (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  63      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  64 /*
  65  * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  66  *
  67  * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  68  * should be set to 1 for the AST2500 SOC.
  69  */
  70 #define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  71 #define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  72 #define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  73 #define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  74 #define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  75 #define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  76 #define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  77 #define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  78 #define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  79
  80 /* DRAM size definitions differs */
  81 #define     ASPEED_SDMC_AST2500_128MB       0x0
  82 #define     ASPEED_SDMC_AST2500_256MB       0x1
  83 #define     ASPEED_SDMC_AST2500_512MB       0x2
  84 #define     ASPEED_SDMC_AST2500_1024MB      0x3
  85
  86 #define ASPEED_SDMC_AST2500_READONLY_MASK                               \
  87     (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
  88      ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
  89      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  90
  91 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
  92 {
  93     AspeedSDMCState *s = ASPEED_SDMC(opaque);
  94
  95     addr >>= 2;
  96
  97     if (addr >= ARRAY_SIZE(s->regs)) {
  98         qemu_log_mask(LOG_GUEST_ERROR,
  99                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 100                       __func__, addr);
 101         return 0;
 102     }
 103
 104     return s->regs[addr];
 105 }
 106
 107 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 108                              unsigned int size)
 109 {
 110     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 111
 112     addr >>= 2;
 113
 114     if (addr >= ARRAY_SIZE(s->regs)) {
 115         qemu_log_mask(LOG_GUEST_ERROR,
 116                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 117                       __func__, addr);
 118         return;
 119     }
 120
 121     if (addr == R_PROT) {
 122         s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
 123         return;
 124     }
 125
 126     if (!s->regs[R_PROT]) {
 127         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 128         return;
 129     }
 130
 131     if (addr == R_CONF) {
 132         /* Make sure readonly bits are kept */
 133         switch (s->silicon_rev) {
 134         case AST2400_A0_SILICON_REV:
 135         case AST2400_A1_SILICON_REV:
 136             data &= ~ASPEED_SDMC_READONLY_MASK;
 137             data |= s->fixed_conf;
 138             break;
 139         case AST2500_A0_SILICON_REV:
 140         case AST2500_A1_SILICON_REV:
 141             data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 142             data |= s->fixed_conf;
 143             break;
 144         default:
 145             g_assert_not_reached();
 146         }
 147     }
 148     if (s->silicon_rev == AST2500_A0_SILICON_REV ||
 149             s->silicon_rev == AST2500_A1_SILICON_REV) {
 150         switch (addr) {
 151         case R_STATUS1:
 152             /* Will never return 'busy' */
 153             data &= ~PHY_BUSY_STATE;
 154             break;
 155         case R_ECC_TEST_CTRL:
 156             /* Always done, always happy */
 157             data |= ECC_TEST_FINISHED;
 158             data &= ~ECC_TEST_FAIL;
 159             break;
 160         default:
 161             break;
 162         }
 163     }
 164
 165     s->regs[addr] = data;
 166 }
 167
 168 static const MemoryRegionOps aspeed_sdmc_ops = {
 169     .read = aspeed_sdmc_read,
 170     .write = aspeed_sdmc_write,
 171     .endianness = DEVICE_LITTLE_ENDIAN,
 172     .valid.min_access_size = 4,
 173     .valid.max_access_size = 4,
 174 };
 175
 176 static int ast2400_rambits(AspeedSDMCState *s)
 177 {
 178     switch (s->ram_size >> 20) {
 179     case 64:
 180         return ASPEED_SDMC_DRAM_64MB;
 181     case 128:
 182         return ASPEED_SDMC_DRAM_128MB;
 183     case 256:
 184         return ASPEED_SDMC_DRAM_256MB;
 185     case 512:
 186         return ASPEED_SDMC_DRAM_512MB;
 187     default:
 188         break;
 189     }
 190
 191     /* use a common default */
 192     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
 193                 s->ram_size);
 194     s->ram_size = 256 << 20;
 195     return ASPEED_SDMC_DRAM_256MB;
 196 }
 197
 198 static int ast2500_rambits(AspeedSDMCState *s)
 199 {
 200     switch (s->ram_size >> 20) {
 201     case 128:
 202         return ASPEED_SDMC_AST2500_128MB;
 203     case 256:
 204         return ASPEED_SDMC_AST2500_256MB;
 205     case 512:
 206         return ASPEED_SDMC_AST2500_512MB;
 207     case 1024:
 208         return ASPEED_SDMC_AST2500_1024MB;
 209     default:
 210         break;
 211     }
 212
 213     /* use a common default */
 214     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
 215                 s->ram_size);
 216     s->ram_size = 512 << 20;
 217     return ASPEED_SDMC_AST2500_512MB;
 218 }
 219
 220 static void aspeed_sdmc_reset(DeviceState *dev)
 221 {
 222     AspeedSDMCState *s = ASPEED_SDMC(dev);
 223
 224     memset(s->regs, 0, sizeof(s->regs));
 225
 226     /* Set ram size bit and defaults values */
 227     s->regs[R_CONF] = s->fixed_conf;
 228 }
 229
 230 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 231 {
 232     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 233     AspeedSDMCState *s = ASPEED_SDMC(dev);
 234
 235     if (!is_supported_silicon_rev(s->silicon_rev)) {
 236         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 237                 s->silicon_rev);
 238         return;
 239     }
 240
 241     switch (s->silicon_rev) {
 242     case AST2400_A0_SILICON_REV:
 243     case AST2400_A1_SILICON_REV:
 244         s->ram_bits = ast2400_rambits(s);
 245         s->max_ram_size = 512 << 20;
 246         s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 247             ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 248         break;
 249     case AST2500_A0_SILICON_REV:
 250     case AST2500_A1_SILICON_REV:
 251         s->ram_bits = ast2500_rambits(s);
 252         s->max_ram_size = 1024 << 20;
 253         s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 254             ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 255             ASPEED_SDMC_CACHE_INITIAL_DONE |
 256             ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 257         break;
 258     default:
 259         g_assert_not_reached();
 260     }
 261
 262     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 263                           TYPE_ASPEED_SDMC, 0x1000);
 264     sysbus_init_mmio(sbd, &s->iomem);
 265 }
 266
 267 static const VMStateDescription vmstate_aspeed_sdmc = {
 268     .name = "aspeed.sdmc",
 269     .version_id = 1,
 270     .minimum_version_id = 1,
 271     .fields = (VMStateField[]) {
 272         VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 273         VMSTATE_END_OF_LIST()
 274     }
 275 };
 276
 277 static Property aspeed_sdmc_properties[] = {
 278     DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
 279     DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
 280     DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
 281     DEFINE_PROP_END_OF_LIST(),
 282 };
 283
 284 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 285 {
 286     DeviceClass *dc = DEVICE_CLASS(klass);
 287     dc->realize = aspeed_sdmc_realize;
 288     dc->reset = aspeed_sdmc_reset;
 289     dc->desc = "ASPEED SDRAM Memory Controller";
 290     dc->vmsd = &vmstate_aspeed_sdmc;
 291     dc->props = aspeed_sdmc_properties;
 292 }
 293
 294 static const TypeInfo aspeed_sdmc_info = {
 295     .name = TYPE_ASPEED_SDMC,
 296     .parent = TYPE_SYS_BUS_DEVICE,
 297     .instance_size = sizeof(AspeedSDMCState),
 298     .class_init = aspeed_sdmc_class_init,
 299 };
 300
 301 static void aspeed_sdmc_register_types(void)
 302 {
 303     type_register_static(&aspeed_sdmc_info);
 304 }
 305
 306 type_init(aspeed_sdmc_register_types);