hw/intc/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu/thread.h"
  21 #include "qemu/error-report.h"
  22 #include "hw/i386/apic_internal.h"
  23 #include "hw/i386/apic.h"
  24 #include "hw/intc/ioapic.h"
  25 #include "hw/intc/i8259.h"
  26 #include "hw/intc/kvm_irqcount.h"
  27 #include "hw/pci/msi.h"
  28 #include "qemu/host-utils.h"
  29 #include "sysemu/kvm.h"
  30 #include "trace.h"
  31 #include "hw/i386/apic-msidef.h"
  32 #include "qapi/error.h"
  33 #include "qom/object.h"
  34
  35 #define MAX_APICS 255
  36 #define MAX_APIC_WORDS 8
  37
  38 #define SYNC_FROM_VAPIC                 0x1
  39 #define SYNC_TO_VAPIC                   0x2
  40 #define SYNC_ISR_IRR_TO_VAPIC           0x4
  41
  42 static APICCommonState *local_apics[MAX_APICS + 1];
  43
  44 #define TYPE_APIC "apic"
  45 /*This is reusing the APICCommonState typedef from APIC_COMMON */
  46 DECLARE_INSTANCE_CHECKER(APICCommonState, APIC,
  47                          TYPE_APIC)
  48
  49 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
  50 static void apic_update_irq(APICCommonState *s);
  51 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  52                                       uint8_t dest, uint8_t dest_mode);
  53
  54 /* Find first bit starting from msb */
  55 static int apic_fls_bit(uint32_t value)
  56 {
  57     return 31 - clz32(value);
  58 }
  59
  60 /* Find first bit starting from lsb */
  61 static int apic_ffs_bit(uint32_t value)
  62 {
  63     return ctz32(value);
  64 }
  65
  66 static inline void apic_reset_bit(uint32_t *tab, int index)
  67 {
  68     int i, mask;
  69     i = index >> 5;
  70     mask = 1 << (index & 0x1f);
  71     tab[i] &= ~mask;
  72 }
  73
  74 /* return -1 if no bit is set */
  75 static int get_highest_priority_int(uint32_t *tab)
  76 {
  77     int i;
  78     for (i = 7; i >= 0; i--) {
  79         if (tab[i] != 0) {
  80             return i * 32 + apic_fls_bit(tab[i]);
  81         }
  82     }
  83     return -1;
  84 }
  85
  86 static void apic_sync_vapic(APICCommonState *s, int sync_type)
  87 {
  88     VAPICState vapic_state;
  89     size_t length;
  90     off_t start;
  91     int vector;
  92
  93     if (!s->vapic_paddr) {
  94         return;
  95     }
  96     if (sync_type & SYNC_FROM_VAPIC) {
  97         cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
  98                                  sizeof(vapic_state));
  99         s->tpr = vapic_state.tpr;
 100     }
 101     if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
 102         start = offsetof(VAPICState, isr);
 103         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
 104
 105         if (sync_type & SYNC_TO_VAPIC) {
 106             assert(qemu_cpu_is_self(CPU(s->cpu)));
 107
 108             vapic_state.tpr = s->tpr;
 109             vapic_state.enabled = 1;
 110             start = 0;
 111             length = sizeof(VAPICState);
 112         }
 113
 114         vector = get_highest_priority_int(s->isr);
 115         if (vector < 0) {
 116             vector = 0;
 117         }
 118         vapic_state.isr = vector & 0xf0;
 119
 120         vapic_state.zero = 0;
 121
 122         vector = get_highest_priority_int(s->irr);
 123         if (vector < 0) {
 124             vector = 0;
 125         }
 126         vapic_state.irr = vector & 0xff;
 127
 128         address_space_write_rom(&address_space_memory,
 129                                 s->vapic_paddr + start,
 130                                 MEMTXATTRS_UNSPECIFIED,
 131                                 ((void *)&vapic_state) + start, length);
 132     }
 133 }
 134
 135 static void apic_vapic_base_update(APICCommonState *s)
 136 {
 137     apic_sync_vapic(s, SYNC_TO_VAPIC);
 138 }
 139
 140 static void apic_local_deliver(APICCommonState *s, int vector)
 141 {
 142     uint32_t lvt = s->lvt[vector];
 143     int trigger_mode;
 144
 145     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 146
 147     if (lvt & APIC_LVT_MASKED)
 148         return;
 149
 150     switch ((lvt >> 8) & 7) {
 151     case APIC_DM_SMI:
 152         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
 153         break;
 154
 155     case APIC_DM_NMI:
 156         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
 157         break;
 158
 159     case APIC_DM_EXTINT:
 160         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
 161         break;
 162
 163     case APIC_DM_FIXED:
 164         trigger_mode = APIC_TRIGGER_EDGE;
 165         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 166             (lvt & APIC_LVT_LEVEL_TRIGGER))
 167             trigger_mode = APIC_TRIGGER_LEVEL;
 168         apic_set_irq(s, lvt & 0xff, trigger_mode);
 169     }
 170 }
 171
 172 void apic_deliver_pic_intr(DeviceState *dev, int level)
 173 {
 174     APICCommonState *s = APIC(dev);
 175
 176     if (level) {
 177         apic_local_deliver(s, APIC_LVT_LINT0);
 178     } else {
 179         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 180
 181         switch ((lvt >> 8) & 7) {
 182         case APIC_DM_FIXED:
 183             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 184                 break;
 185             apic_reset_bit(s->irr, lvt & 0xff);
 186             /* fall through */
 187         case APIC_DM_EXTINT:
 188             apic_update_irq(s);
 189             break;
 190         }
 191     }
 192 }
 193
 194 static void apic_external_nmi(APICCommonState *s)
 195 {
 196     apic_local_deliver(s, APIC_LVT_LINT1);
 197 }
 198
 199 #define foreach_apic(apic, deliver_bitmask, code) \
 200 {\
 201     int __i, __j;\
 202     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 203         uint32_t __mask = deliver_bitmask[__i];\
 204         if (__mask) {\
 205             for(__j = 0; __j < 32; __j++) {\
 206                 if (__mask & (1U << __j)) {\
 207                     apic = local_apics[__i * 32 + __j];\
 208                     if (apic) {\
 209                         code;\
 210                     }\
 211                 }\
 212             }\
 213         }\
 214     }\
 215 }
 216
 217 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 218                              uint8_t delivery_mode, uint8_t vector_num,
 219                              uint8_t trigger_mode)
 220 {
 221     APICCommonState *apic_iter;
 222
 223     switch (delivery_mode) {
 224         case APIC_DM_LOWPRI:
 225             /* XXX: search for focus processor, arbitration */
 226             {
 227                 int i, d;
 228                 d = -1;
 229                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 230                     if (deliver_bitmask[i]) {
 231                         d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
 232                         break;
 233                     }
 234                 }
 235                 if (d >= 0) {
 236                     apic_iter = local_apics[d];
 237                     if (apic_iter) {
 238                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 239                     }
 240                 }
 241             }
 242             return;
 243
 244         case APIC_DM_FIXED:
 245             break;
 246
 247         case APIC_DM_SMI:
 248             foreach_apic(apic_iter, deliver_bitmask,
 249                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
 250             );
 251             return;
 252
 253         case APIC_DM_NMI:
 254             foreach_apic(apic_iter, deliver_bitmask,
 255                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
 256             );
 257             return;
 258
 259         case APIC_DM_INIT:
 260             /* normal INIT IPI sent to processors */
 261             foreach_apic(apic_iter, deliver_bitmask,
 262                          cpu_interrupt(CPU(apic_iter->cpu),
 263                                        CPU_INTERRUPT_INIT)
 264             );
 265             return;
 266
 267         case APIC_DM_EXTINT:
 268             /* handled in I/O APIC code */
 269             break;
 270
 271         default:
 272             return;
 273     }
 274
 275     foreach_apic(apic_iter, deliver_bitmask,
 276                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 277 }
 278
 279 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 280                       uint8_t vector_num, uint8_t trigger_mode)
 281 {
 282     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 283
 284     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 285                            trigger_mode);
 286
 287     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 288     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 289 }
 290
 291 static void apic_set_base(APICCommonState *s, uint64_t val)
 292 {
 293     s->apicbase = (val & 0xfffff000) |
 294         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 295     /* if disabled, cannot be enabled again */
 296     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 297         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 298         cpu_clear_apic_feature(&s->cpu->env);
 299         s->spurious_vec &= ~APIC_SV_ENABLE;
 300     }
 301 }
 302
 303 static void apic_set_tpr(APICCommonState *s, uint8_t val)
 304 {
 305     /* Updates from cr8 are ignored while the VAPIC is active */
 306     if (!s->vapic_paddr) {
 307         s->tpr = val << 4;
 308         apic_update_irq(s);
 309     }
 310 }
 311
 312 int apic_get_highest_priority_irr(DeviceState *dev)
 313 {
 314     APICCommonState *s;
 315
 316     if (!dev) {
 317         /* no interrupts */
 318         return -1;
 319     }
 320     s = APIC_COMMON(dev);
 321     return get_highest_priority_int(s->irr);
 322 }
 323
 324 static uint8_t apic_get_tpr(APICCommonState *s)
 325 {
 326     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 327     return s->tpr >> 4;
 328 }
 329
 330 int apic_get_ppr(APICCommonState *s)
 331 {
 332     int tpr, isrv, ppr;
 333
 334     tpr = (s->tpr >> 4);
 335     isrv = get_highest_priority_int(s->isr);
 336     if (isrv < 0)
 337         isrv = 0;
 338     isrv >>= 4;
 339     if (tpr >= isrv)
 340         ppr = s->tpr;
 341     else
 342         ppr = isrv << 4;
 343     return ppr;
 344 }
 345
 346 static int apic_get_arb_pri(APICCommonState *s)
 347 {
 348     /* XXX: arbitration */
 349     return 0;
 350 }
 351
 352
 353 /*
 354  * <0 - low prio interrupt,
 355  * 0  - no interrupt,
 356  * >0 - interrupt number
 357  */
 358 static int apic_irq_pending(APICCommonState *s)
 359 {
 360     int irrv, ppr;
 361
 362     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 363         return 0;
 364     }
 365
 366     irrv = get_highest_priority_int(s->irr);
 367     if (irrv < 0) {
 368         return 0;
 369     }
 370     ppr = apic_get_ppr(s);
 371     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 372         return -1;
 373     }
 374
 375     return irrv;
 376 }
 377
 378 /* signal the CPU if an irq is pending */
 379 static void apic_update_irq(APICCommonState *s)
 380 {
 381     CPUState *cpu;
 382     DeviceState *dev = (DeviceState *)s;
 383
 384     cpu = CPU(s->cpu);
 385     if (!qemu_cpu_is_self(cpu)) {
 386         cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
 387     } else if (apic_irq_pending(s) > 0) {
 388         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
 389     } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 390         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
 391     }
 392 }
 393
 394 void apic_poll_irq(DeviceState *dev)
 395 {
 396     APICCommonState *s = APIC(dev);
 397
 398     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 399     apic_update_irq(s);
 400 }
 401
 402 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
 403 {
 404     kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
 405
 406     apic_set_bit(s->irr, vector_num);
 407     if (trigger_mode)
 408         apic_set_bit(s->tmr, vector_num);
 409     else
 410         apic_reset_bit(s->tmr, vector_num);
 411     if (s->vapic_paddr) {
 412         apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
 413         /*
 414          * The vcpu thread needs to see the new IRR before we pull its current
 415          * TPR value. That way, if we miss a lowering of the TRP, the guest
 416          * has the chance to notice the new IRR and poll for IRQs on its own.
 417          */
 418         smp_wmb();
 419         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 420     }
 421     apic_update_irq(s);
 422 }
 423
 424 static void apic_eoi(APICCommonState *s)
 425 {
 426     int isrv;
 427     isrv = get_highest_priority_int(s->isr);
 428     if (isrv < 0)
 429         return;
 430     apic_reset_bit(s->isr, isrv);
 431     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
 432         ioapic_eoi_broadcast(isrv);
 433     }
 434     apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
 435     apic_update_irq(s);
 436 }
 437
 438 static int apic_find_dest(uint8_t dest)
 439 {
 440     APICCommonState *apic = local_apics[dest];
 441     int i;
 442
 443     if (apic && apic->id == dest)
 444         return dest;  /* shortcut in case apic->id == local_apics[dest]->id */
 445
 446     for (i = 0; i < MAX_APICS; i++) {
 447         apic = local_apics[i];
 448         if (apic && apic->id == dest)
 449             return i;
 450         if (!apic)
 451             break;
 452     }
 453
 454     return -1;
 455 }
 456
 457 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 458                                       uint8_t dest, uint8_t dest_mode)
 459 {
 460     APICCommonState *apic_iter;
 461     int i;
 462
 463     if (dest_mode == 0) {
 464         if (dest == 0xff) {
 465             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 466         } else {
 467             int idx = apic_find_dest(dest);
 468             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 469             if (idx >= 0)
 470                 apic_set_bit(deliver_bitmask, idx);
 471         }
 472     } else {
 473         /* XXX: cluster mode */
 474         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 475         for(i = 0; i < MAX_APICS; i++) {
 476             apic_iter = local_apics[i];
 477             if (apic_iter) {
 478                 if (apic_iter->dest_mode == 0xf) {
 479                     if (dest & apic_iter->log_dest)
 480                         apic_set_bit(deliver_bitmask, i);
 481                 } else if (apic_iter->dest_mode == 0x0) {
 482                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 483                         (dest & apic_iter->log_dest & 0x0f)) {
 484                         apic_set_bit(deliver_bitmask, i);
 485                     }
 486                 }
 487             } else {
 488                 break;
 489             }
 490         }
 491     }
 492 }
 493
 494 static void apic_startup(APICCommonState *s, int vector_num)
 495 {
 496     s->sipi_vector = vector_num;
 497     cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 498 }
 499
 500 void apic_sipi(DeviceState *dev)
 501 {
 502     APICCommonState *s = APIC(dev);
 503
 504     cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 505
 506     if (!s->wait_for_sipi)
 507         return;
 508     cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
 509     s->wait_for_sipi = 0;
 510 }
 511
 512 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
 513                          uint8_t delivery_mode, uint8_t vector_num,
 514                          uint8_t trigger_mode)
 515 {
 516     APICCommonState *s = APIC(dev);
 517     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 518     int dest_shorthand = (s->icr[0] >> 18) & 3;
 519     APICCommonState *apic_iter;
 520
 521     switch (dest_shorthand) {
 522     case 0:
 523         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 524         break;
 525     case 1:
 526         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 527         apic_set_bit(deliver_bitmask, s->id);
 528         break;
 529     case 2:
 530         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 531         break;
 532     case 3:
 533         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 534         apic_reset_bit(deliver_bitmask, s->id);
 535         break;
 536     }
 537
 538     switch (delivery_mode) {
 539         case APIC_DM_INIT:
 540             {
 541                 int trig_mode = (s->icr[0] >> 15) & 1;
 542                 int level = (s->icr[0] >> 14) & 1;
 543                 if (level == 0 && trig_mode == 1) {
 544                     foreach_apic(apic_iter, deliver_bitmask,
 545                                  apic_iter->arb_id = apic_iter->id );
 546                     return;
 547                 }
 548             }
 549             break;
 550
 551         case APIC_DM_SIPI:
 552             foreach_apic(apic_iter, deliver_bitmask,
 553                          apic_startup(apic_iter, vector_num) );
 554             return;
 555     }
 556
 557     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 558 }
 559
 560 static bool apic_check_pic(APICCommonState *s)
 561 {
 562     DeviceState *dev = (DeviceState *)s;
 563
 564     if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 565         return false;
 566     }
 567     apic_deliver_pic_intr(dev, 1);
 568     return true;
 569 }
 570
 571 int apic_get_interrupt(DeviceState *dev)
 572 {
 573     APICCommonState *s = APIC(dev);
 574     int intno;
 575
 576     /* if the APIC is installed or enabled, we let the 8259 handle the
 577        IRQs */
 578     if (!s)
 579         return -1;
 580     if (!(s->spurious_vec & APIC_SV_ENABLE))
 581         return -1;
 582
 583     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 584     intno = apic_irq_pending(s);
 585
 586     /* if there is an interrupt from the 8259, let the caller handle
 587      * that first since ExtINT interrupts ignore the priority.
 588      */
 589     if (intno == 0 || apic_check_pic(s)) {
 590         apic_sync_vapic(s, SYNC_TO_VAPIC);
 591         return -1;
 592     } else if (intno < 0) {
 593         apic_sync_vapic(s, SYNC_TO_VAPIC);
 594         return s->spurious_vec & 0xff;
 595     }
 596     apic_reset_bit(s->irr, intno);
 597     apic_set_bit(s->isr, intno);
 598     apic_sync_vapic(s, SYNC_TO_VAPIC);
 599
 600     apic_update_irq(s);
 601
 602     return intno;
 603 }
 604
 605 int apic_accept_pic_intr(DeviceState *dev)
 606 {
 607     APICCommonState *s = APIC(dev);
 608     uint32_t lvt0;
 609
 610     if (!s)
 611         return -1;
 612
 613     lvt0 = s->lvt[APIC_LVT_LINT0];
 614
 615     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 616         (lvt0 & APIC_LVT_MASKED) == 0)
 617         return isa_pic != NULL;
 618
 619     return 0;
 620 }
 621
 622 static void apic_timer_update(APICCommonState *s, int64_t current_time)
 623 {
 624     if (apic_next_timer(s, current_time)) {
 625         timer_mod(s->timer, s->next_time);
 626     } else {
 627         timer_del(s->timer);
 628     }
 629 }
 630
 631 static void apic_timer(void *opaque)
 632 {
 633     APICCommonState *s = opaque;
 634
 635     apic_local_deliver(s, APIC_LVT_TIMER);
 636     apic_timer_update(s, s->next_time);
 637 }
 638
 639 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
 640 {
 641     DeviceState *dev;
 642     APICCommonState *s;
 643     uint32_t val;
 644     int index;
 645
 646     if (size < 4) {
 647         return 0;
 648     }
 649
 650     dev = cpu_get_current_apic();
 651     if (!dev) {
 652         return 0;
 653     }
 654     s = APIC(dev);
 655
 656     index = (addr >> 4) & 0xff;
 657     switch(index) {
 658     case 0x02: /* id */
 659         val = s->id << 24;
 660         break;
 661     case 0x03: /* version */
 662         val = s->version | ((APIC_LVT_NB - 1) << 16);
 663         break;
 664     case 0x08:
 665         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 666         if (apic_report_tpr_access) {
 667             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
 668         }
 669         val = s->tpr;
 670         break;
 671     case 0x09:
 672         val = apic_get_arb_pri(s);
 673         break;
 674     case 0x0a:
 675         /* ppr */
 676         val = apic_get_ppr(s);
 677         break;
 678     case 0x0b:
 679         val = 0;
 680         break;
 681     case 0x0d:
 682         val = s->log_dest << 24;
 683         break;
 684     case 0x0e:
 685         val = (s->dest_mode << 28) | 0xfffffff;
 686         break;
 687     case 0x0f:
 688         val = s->spurious_vec;
 689         break;
 690     case 0x10 ... 0x17:
 691         val = s->isr[index & 7];
 692         break;
 693     case 0x18 ... 0x1f:
 694         val = s->tmr[index & 7];
 695         break;
 696     case 0x20 ... 0x27:
 697         val = s->irr[index & 7];
 698         break;
 699     case 0x28:
 700         val = s->esr;
 701         break;
 702     case 0x30:
 703     case 0x31:
 704         val = s->icr[index & 1];
 705         break;
 706     case 0x32 ... 0x37:
 707         val = s->lvt[index - 0x32];
 708         break;
 709     case 0x38:
 710         val = s->initial_count;
 711         break;
 712     case 0x39:
 713         val = apic_get_current_count(s);
 714         break;
 715     case 0x3e:
 716         val = s->divide_conf;
 717         break;
 718     default:
 719         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 720         val = 0;
 721         break;
 722     }
 723     trace_apic_mem_readl(addr, val);
 724     return val;
 725 }
 726
 727 static void apic_send_msi(MSIMessage *msi)
 728 {
 729     uint64_t addr = msi->address;
 730     uint32_t data = msi->data;
 731     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 732     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 733     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 734     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 735     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 736     /* XXX: Ignore redirection hint. */
 737     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 738 }
 739
 740 static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 741                            unsigned size)
 742 {
 743     DeviceState *dev;
 744     APICCommonState *s;
 745     int index = (addr >> 4) & 0xff;
 746
 747     if (size < 4) {
 748         return;
 749     }
 750
 751     if (addr > 0xfff || !index) {
 752         /* MSI and MMIO APIC are at the same memory location,
 753          * but actually not on the global bus: MSI is on PCI bus
 754          * APIC is connected directly to the CPU.
 755          * Mapping them on the global bus happens to work because
 756          * MSI registers are reserved in APIC MMIO and vice versa. */
 757         MSIMessage msi = { .address = addr, .data = val };
 758         apic_send_msi(&msi);
 759         return;
 760     }
 761
 762     dev = cpu_get_current_apic();
 763     if (!dev) {
 764         return;
 765     }
 766     s = APIC(dev);
 767
 768     trace_apic_mem_writel(addr, val);
 769
 770     switch(index) {
 771     case 0x02:
 772         s->id = (val >> 24);
 773         break;
 774     case 0x03:
 775         break;
 776     case 0x08:
 777         if (apic_report_tpr_access) {
 778             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
 779         }
 780         s->tpr = val;
 781         apic_sync_vapic(s, SYNC_TO_VAPIC);
 782         apic_update_irq(s);
 783         break;
 784     case 0x09:
 785     case 0x0a:
 786         break;
 787     case 0x0b: /* EOI */
 788         apic_eoi(s);
 789         break;
 790     case 0x0d:
 791         s->log_dest = val >> 24;
 792         break;
 793     case 0x0e:
 794         s->dest_mode = val >> 28;
 795         break;
 796     case 0x0f:
 797         s->spurious_vec = val & 0x1ff;
 798         apic_update_irq(s);
 799         break;
 800     case 0x10 ... 0x17:
 801     case 0x18 ... 0x1f:
 802     case 0x20 ... 0x27:
 803     case 0x28:
 804         break;
 805     case 0x30:
 806         s->icr[0] = val;
 807         apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 808                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 809                      (s->icr[0] >> 15) & 1);
 810         break;
 811     case 0x31:
 812         s->icr[1] = val;
 813         break;
 814     case 0x32 ... 0x37:
 815         {
 816             int n = index - 0x32;
 817             s->lvt[n] = val;
 818             if (n == APIC_LVT_TIMER) {
 819                 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 820             } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
 821                 apic_update_irq(s);
 822             }
 823         }
 824         break;
 825     case 0x38:
 826         s->initial_count = val;
 827         s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 828         apic_timer_update(s, s->initial_count_load_time);
 829         break;
 830     case 0x39:
 831         break;
 832     case 0x3e:
 833         {
 834             int v;
 835             s->divide_conf = val & 0xb;
 836             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 837             s->count_shift = (v + 1) & 7;
 838         }
 839         break;
 840     default:
 841         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 842         break;
 843     }
 844 }
 845
 846 static void apic_pre_save(APICCommonState *s)
 847 {
 848     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 849 }
 850
 851 static void apic_post_load(APICCommonState *s)
 852 {
 853     if (s->timer_expiry != -1) {
 854         timer_mod(s->timer, s->timer_expiry);
 855     } else {
 856         timer_del(s->timer);
 857     }
 858 }
 859
 860 static const MemoryRegionOps apic_io_ops = {
 861     .read = apic_mem_read,
 862     .write = apic_mem_write,
 863     .impl.min_access_size = 1,
 864     .impl.max_access_size = 4,
 865     .valid.min_access_size = 1,
 866     .valid.max_access_size = 4,
 867     .endianness = DEVICE_NATIVE_ENDIAN,
 868 };
 869
 870 static void apic_realize(DeviceState *dev, Error **errp)
 871 {
 872     APICCommonState *s = APIC(dev);
 873
 874     if (s->id >= MAX_APICS) {
 875         error_setg(errp, "%s initialization failed. APIC ID %d is invalid",
 876                    object_get_typename(OBJECT(dev)), s->id);
 877         return;
 878     }
 879
 880     if (kvm_enabled()) {
 881         warn_report("Userspace local APIC is deprecated for KVM.");
 882         warn_report("Do not use kernel-irqchip except for the -M isapc machine type.");
 883     }
 884
 885     memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
 886                           APIC_SPACE_SIZE);
 887
 888     /*
 889      * apic-msi's apic_mem_write can call into ioapic_eoi_broadcast, which can
 890      * write back to apic-msi. As such mark the apic-msi region re-entrancy
 891      * safe.
 892      */
 893     s->io_memory.disable_reentrancy_guard = true;
 894
 895     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
 896     local_apics[s->id] = s;
 897
 898     msi_nonbroken = true;
 899 }
 900
 901 static void apic_unrealize(DeviceState *dev)
 902 {
 903     APICCommonState *s = APIC(dev);
 904
 905     timer_free(s->timer);
 906     local_apics[s->id] = NULL;
 907 }
 908
 909 static void apic_class_init(ObjectClass *klass, void *data)
 910 {
 911     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 912
 913     k->realize = apic_realize;
 914     k->unrealize = apic_unrealize;
 915     k->set_base = apic_set_base;
 916     k->set_tpr = apic_set_tpr;
 917     k->get_tpr = apic_get_tpr;
 918     k->vapic_base_update = apic_vapic_base_update;
 919     k->external_nmi = apic_external_nmi;
 920     k->pre_save = apic_pre_save;
 921     k->post_load = apic_post_load;
 922     k->send_msi = apic_send_msi;
 923 }
 924
 925 static const TypeInfo apic_info = {
 926     .name          = TYPE_APIC,
 927     .instance_size = sizeof(APICCommonState),
 928     .parent        = TYPE_APIC_COMMON,
 929     .class_init    = apic_class_init,
 930 };
 931
 932 static void apic_register_types(void)
 933 {
 934     type_register_static(&apic_info);
 935 }
 936
 937 type_init(apic_register_types)