2 * QEMU RISC-V Host Target Interface (HTIF) Emulation
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This provides HTIF device emulation for QEMU. At the moment this allows
8 * for identical copies of bbl/linux to run on both spike and QEMU.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2 or later, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
26 #include "hw/char/riscv_htif.h"
27 #include "hw/char/serial.h"
28 #include "chardev/char.h"
29 #include "chardev/char-fe.h"
30 #include "qemu/timer.h"
31 #include "qemu/error-report.h"
32 #include "exec/address-spaces.h"
33 #include "sysemu/dma.h"
35 #define RISCV_DEBUG_HTIF 0
36 #define HTIF_DEBUG(fmt, ...) \
38 if (RISCV_DEBUG_HTIF) { \
39 qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
43 #define HTIF_DEV_SHIFT 56
44 #define HTIF_CMD_SHIFT 48
46 #define HTIF_DEV_SYSTEM 0
47 #define HTIF_DEV_CONSOLE 1
49 #define HTIF_SYSTEM_CMD_SYSCALL 0
50 #define HTIF_CONSOLE_CMD_GETC 0
51 #define HTIF_CONSOLE_CMD_PUTC 1
53 /* PK system call number */
54 #define PK_SYS_WRITE 64
57 uint8_t line_size
= 16;
59 static uint64_t fromhost_addr
, tohost_addr
, begin_sig_addr
, end_sig_addr
;
61 void htif_symbol_callback(const char *st_name
, int st_info
, uint64_t st_value
,
64 if (strcmp("fromhost", st_name
) == 0) {
65 fromhost_addr
= st_value
;
67 error_report("HTIF fromhost must be 8 bytes");
70 } else if (strcmp("tohost", st_name
) == 0) {
71 tohost_addr
= st_value
;
73 error_report("HTIF tohost must be 8 bytes");
76 } else if (strcmp("begin_signature", st_name
) == 0) {
77 begin_sig_addr
= st_value
;
78 } else if (strcmp("end_signature", st_name
) == 0) {
79 end_sig_addr
= st_value
;
84 * Called by the char dev to see if HTIF is ready to accept input.
86 static int htif_can_recv(void *opaque
)
92 * Called by the char dev to supply input to HTIF console.
93 * We assume that we will receive one character at a time.
95 static void htif_recv(void *opaque
, const uint8_t *buf
, int size
)
97 HTIFState
*s
= opaque
;
104 * TODO - we need to check whether mfromhost is zero which indicates
105 * the device is ready to receive. The current implementation
106 * will drop characters
109 uint64_t val_written
= s
->pending_read
;
110 uint64_t resp
= 0x100 | *buf
;
112 s
->fromhost
= (val_written
>> 48 << 48) | (resp
<< 16 >> 16);
116 * Called by the char dev to supply special events to the HTIF console.
119 static void htif_event(void *opaque
, QEMUChrEvent event
)
124 static int htif_be_change(void *opaque
)
126 HTIFState
*s
= opaque
;
128 qemu_chr_fe_set_handlers(&s
->chr
, htif_can_recv
, htif_recv
, htif_event
,
129 htif_be_change
, s
, NULL
, true);
135 * See below the tohost register format.
137 * Bits 63:56 indicate the "device".
138 * Bits 55:48 indicate the "command".
140 * Device 0 is the syscall device, which is used to emulate Unixy syscalls.
141 * It only implements command 0, which has two subfunctions:
142 * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
143 * describing the syscall.
144 * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
145 * value indicating success and other values indicating failure.
147 * Device 1 is the blocking character device.
148 * - Command 0 reads a character
149 * - Command 1 writes a character from the 8 LSBs of tohost
151 * For RV32, the tohost register is zero-extended, so only device=0 and
152 * command=0 (i.e. HTIF syscalls/exit codes) are supported.
154 static void htif_handle_tohost_write(HTIFState
*s
, uint64_t val_written
)
156 uint8_t device
= val_written
>> HTIF_DEV_SHIFT
;
157 uint8_t cmd
= val_written
>> HTIF_CMD_SHIFT
;
158 uint64_t payload
= val_written
& 0xFFFFFFFFFFFFULL
;
161 HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
162 " -payload: %016" PRIx64
"\n", device
, cmd
, payload
& 0xFF, payload
);
165 * Currently, there is a fixed mapping of devices:
166 * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
169 if (unlikely(device
== HTIF_DEV_SYSTEM
)) {
170 /* frontend syscall handler, shutdown and exit code support */
171 if (cmd
== HTIF_SYSTEM_CMD_SYSCALL
) {
174 int exit_code
= payload
>> 1;
177 * Dump signature data if sig_file is specified and
178 * begin/end_signature symbols exist.
180 if (sig_file
&& begin_sig_addr
&& end_sig_addr
) {
181 uint64_t sig_len
= end_sig_addr
- begin_sig_addr
;
182 char *sig_data
= g_malloc(sig_len
);
183 dma_memory_read(&address_space_memory
, begin_sig_addr
,
184 sig_data
, sig_len
, MEMTXATTRS_UNSPECIFIED
);
185 FILE *signature
= fopen(sig_file
, "w");
186 if (signature
== NULL
) {
187 error_report("Unable to open %s with error %s",
188 sig_file
, strerror(errno
));
192 for (int i
= 0; i
< sig_len
; i
+= line_size
) {
193 for (int j
= line_size
; j
> 0; j
--) {
194 if (i
+ j
<= sig_len
) {
195 fprintf(signature
, "%02x",
196 sig_data
[i
+ j
- 1] & 0xff);
198 fprintf(signature
, "%02x", 0);
201 fprintf(signature
, "\n");
211 cpu_physical_memory_read(payload
, syscall
, sizeof(syscall
));
212 if (syscall
[0] == PK_SYS_WRITE
&&
213 syscall
[1] == HTIF_DEV_CONSOLE
&&
214 syscall
[3] == HTIF_CONSOLE_CMD_PUTC
) {
216 cpu_physical_memory_read(syscall
[2], &ch
, 1);
217 qemu_chr_fe_write(&s
->chr
, &ch
, 1);
218 resp
= 0x100 | (uint8_t)payload
;
220 qemu_log_mask(LOG_UNIMP
,
221 "pk syscall proxy not supported\n");
225 qemu_log("HTIF device %d: unknown command\n", device
);
227 } else if (likely(device
== HTIF_DEV_CONSOLE
)) {
229 if (cmd
== HTIF_CONSOLE_CMD_GETC
) {
230 /* this should be a queue, but not yet implemented as such */
231 s
->pending_read
= val_written
;
232 s
->tohost
= 0; /* clear to indicate we read */
234 } else if (cmd
== HTIF_CONSOLE_CMD_PUTC
) {
235 qemu_chr_fe_write(&s
->chr
, (uint8_t *)&payload
, 1);
236 resp
= 0x100 | (uint8_t)payload
;
238 qemu_log("HTIF device %d: unknown command\n", device
);
241 qemu_log("HTIF unknown device or command\n");
242 HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
243 " payload: %016" PRIx64
, device
, cmd
, payload
& 0xFF, payload
);
246 * Latest bbl does not set fromhost to 0 if there is a value in tohost.
247 * With this code enabled, qemu hangs waiting for fromhost to go to 0.
248 * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
249 * HTIF needs protocol documentation and a more complete state machine.
251 * while (!s->fromhost_inprogress &&
252 * s->fromhost != 0x0) {
255 s
->fromhost
= (val_written
>> 48 << 48) | (resp
<< 16 >> 16);
256 s
->tohost
= 0; /* clear to indicate we read */
259 #define TOHOST_OFFSET1 (s->tohost_offset)
260 #define TOHOST_OFFSET2 (s->tohost_offset + 4)
261 #define FROMHOST_OFFSET1 (s->fromhost_offset)
262 #define FROMHOST_OFFSET2 (s->fromhost_offset + 4)
264 /* CPU wants to read an HTIF register */
265 static uint64_t htif_mm_read(void *opaque
, hwaddr addr
, unsigned size
)
267 HTIFState
*s
= opaque
;
268 if (addr
== TOHOST_OFFSET1
) {
269 return s
->tohost
& 0xFFFFFFFF;
270 } else if (addr
== TOHOST_OFFSET2
) {
271 return (s
->tohost
>> 32) & 0xFFFFFFFF;
272 } else if (addr
== FROMHOST_OFFSET1
) {
273 return s
->fromhost
& 0xFFFFFFFF;
274 } else if (addr
== FROMHOST_OFFSET2
) {
275 return (s
->fromhost
>> 32) & 0xFFFFFFFF;
277 qemu_log("Invalid htif read: address %016" PRIx64
"\n",
283 /* CPU wrote to an HTIF register */
284 static void htif_mm_write(void *opaque
, hwaddr addr
,
285 uint64_t value
, unsigned size
)
287 HTIFState
*s
= opaque
;
288 if (addr
== TOHOST_OFFSET1
) {
289 if (s
->tohost
== 0x0) {
291 s
->tohost
= value
& 0xFFFFFFFF;
295 } else if (addr
== TOHOST_OFFSET2
) {
296 if (s
->allow_tohost
) {
297 s
->tohost
|= value
<< 32;
298 htif_handle_tohost_write(s
, s
->tohost
);
300 } else if (addr
== FROMHOST_OFFSET1
) {
301 s
->fromhost_inprogress
= 1;
302 s
->fromhost
= value
& 0xFFFFFFFF;
303 } else if (addr
== FROMHOST_OFFSET2
) {
304 s
->fromhost
|= value
<< 32;
305 s
->fromhost_inprogress
= 0;
307 qemu_log("Invalid htif write: address %016" PRIx64
"\n",
312 static const MemoryRegionOps htif_mm_ops
= {
313 .read
= htif_mm_read
,
314 .write
= htif_mm_write
,
317 HTIFState
*htif_mm_init(MemoryRegion
*address_space
, Chardev
*chr
,
318 uint64_t nonelf_base
, bool custom_base
)
320 uint64_t base
, size
, tohost_offset
, fromhost_offset
;
323 fromhost_addr
= nonelf_base
;
324 tohost_addr
= nonelf_base
+ 8;
326 if (!fromhost_addr
|| !tohost_addr
) {
327 error_report("Invalid HTIF fromhost or tohost address");
332 base
= MIN(tohost_addr
, fromhost_addr
);
333 size
= MAX(tohost_addr
+ 8, fromhost_addr
+ 8) - base
;
334 tohost_offset
= tohost_addr
- base
;
335 fromhost_offset
= fromhost_addr
- base
;
337 HTIFState
*s
= g_new0(HTIFState
, 1);
338 s
->tohost_offset
= tohost_offset
;
339 s
->fromhost_offset
= fromhost_offset
;
342 s
->fromhost_inprogress
= 0;
343 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
344 qemu_chr_fe_set_handlers(&s
->chr
, htif_can_recv
, htif_recv
, htif_event
,
345 htif_be_change
, s
, NULL
, true);
347 memory_region_init_io(&s
->mmio
, NULL
, &htif_mm_ops
, s
,
348 TYPE_HTIF_UART
, size
);
349 memory_region_add_subregion_overlap(address_space
, base
,