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target/loongarch: Implement vmskltz/vmskgez/vmsknz
[qemu/kevin.git] / hw / arm / omap1.c
blobd5438156ee9ed86bbffb9f518ccd6abf78ca1fb2
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
24 #include "qapi/error.h"
25 #include "cpu.h"
26 #include "exec/address-spaces.h"
27 #include "hw/hw.h"
28 #include "hw/irq.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/omap.h"
32 #include "sysemu/blockdev.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/arm/soc_dma.h"
35 #include "sysemu/qtest.h"
36 #include "sysemu/reset.h"
37 #include "sysemu/runstate.h"
38 #include "sysemu/rtc.h"
39 #include "qemu/range.h"
40 #include "hw/sysbus.h"
41 #include "qemu/cutils.h"
42 #include "qemu/bcd.h"
43
44 static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz)
45 {
46 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n",
47 funcname, 8 * sz, addr);
48 }
49
50 /* Should signal the TCMI/GPMC */
51 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
52 {
53 uint8_t ret;
54
55 omap_log_badwidth(__func__, addr, 1);
56 cpu_physical_memory_read(addr, &ret, 1);
57 return ret;
58 }
59
60 void omap_badwidth_write8(void *opaque, hwaddr addr,
61 uint32_t value)
62 {
63 uint8_t val8 = value;
64
65 omap_log_badwidth(__func__, addr, 1);
66 cpu_physical_memory_write(addr, &val8, 1);
67 }
68
69 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
70 {
71 uint16_t ret;
72
73 omap_log_badwidth(__func__, addr, 2);
74 cpu_physical_memory_read(addr, &ret, 2);
75 return ret;
76 }
77
78 void omap_badwidth_write16(void *opaque, hwaddr addr,
79 uint32_t value)
80 {
81 uint16_t val16 = value;
82
83 omap_log_badwidth(__func__, addr, 2);
84 cpu_physical_memory_write(addr, &val16, 2);
85 }
86
87 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
88 {
89 uint32_t ret;
90
91 omap_log_badwidth(__func__, addr, 4);
92 cpu_physical_memory_read(addr, &ret, 4);
93 return ret;
94 }
95
96 void omap_badwidth_write32(void *opaque, hwaddr addr,
97 uint32_t value)
98 {
99 omap_log_badwidth(__func__, addr, 4);
100 cpu_physical_memory_write(addr, &value, 4);
101 }
102
103 /* MPU OS timers */
104 struct omap_mpu_timer_s {
105 MemoryRegion iomem;
106 qemu_irq irq;
107 omap_clk clk;
108 uint32_t val;
109 int64_t time;
110 QEMUTimer *timer;
111 QEMUBH *tick;
112 int64_t rate;
113 int it_ena;
114
115 int enable;
116 int ptv;
117 int ar;
118 int st;
119 uint32_t reset_val;
120 };
121
122 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
123 {
124 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
125
126 if (timer->st && timer->enable && timer->rate)
127 return timer->val - muldiv64(distance >> (timer->ptv + 1),
128 timer->rate, NANOSECONDS_PER_SECOND);
129 else
130 return timer->val;
131 }
132
133 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
134 {
135 timer->val = omap_timer_read(timer);
136 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
137 }
138
139 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
140 {
141 int64_t expires;
142
143 if (timer->enable && timer->st && timer->rate) {
144 timer->val = timer->reset_val; /* Should skip this on clk enable */
145 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
146 NANOSECONDS_PER_SECOND, timer->rate);
147
148 /* If timer expiry would be sooner than in about 1 ms and
149 * auto-reload isn't set, then fire immediately. This is a hack
150 * to make systems like PalmOS run in acceptable time. PalmOS
151 * sets the interval to a very low value and polls the status bit
152 * in a busy loop when it wants to sleep just a couple of CPU
153 * ticks. */
154 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) {
155 timer_mod(timer->timer, timer->time + expires);
156 } else {
157 qemu_bh_schedule(timer->tick);
158 }
159 } else
160 timer_del(timer->timer);
161 }
162
163 static void omap_timer_fire(void *opaque)
164 {
165 struct omap_mpu_timer_s *timer = opaque;
166
167 if (!timer->ar) {
168 timer->val = 0;
169 timer->st = 0;
170 }
171
172 if (timer->it_ena)
173 /* Edge-triggered irq */
174 qemu_irq_pulse(timer->irq);
175 }
176
177 static void omap_timer_tick(void *opaque)
178 {
179 struct omap_mpu_timer_s *timer = opaque;
180
181 omap_timer_sync(timer);
182 omap_timer_fire(timer);
183 omap_timer_update(timer);
184 }
185
186 static void omap_timer_clk_update(void *opaque, int line, int on)
187 {
188 struct omap_mpu_timer_s *timer = opaque;
189
190 omap_timer_sync(timer);
191 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
192 omap_timer_update(timer);
193 }
194
195 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
196 {
197 omap_clk_adduser(timer->clk,
198 qemu_allocate_irq(omap_timer_clk_update, timer, 0));
199 timer->rate = omap_clk_getrate(timer->clk);
200 }
201
202 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
203 unsigned size)
204 {
205 struct omap_mpu_timer_s *s = opaque;
206
207 if (size != 4) {
208 return omap_badwidth_read32(opaque, addr);
209 }
210
211 switch (addr) {
212 case 0x00: /* CNTL_TIMER */
213 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
214
215 case 0x04: /* LOAD_TIM */
216 break;
217
218 case 0x08: /* READ_TIM */
219 return omap_timer_read(s);
220 }
221
222 OMAP_BAD_REG(addr);
223 return 0;
224 }
225
226 static void omap_mpu_timer_write(void *opaque, hwaddr addr,
227 uint64_t value, unsigned size)
228 {
229 struct omap_mpu_timer_s *s = opaque;
230
231 if (size != 4) {
232 omap_badwidth_write32(opaque, addr, value);
233 return;
234 }
235
236 switch (addr) {
237 case 0x00: /* CNTL_TIMER */
238 omap_timer_sync(s);
239 s->enable = (value >> 5) & 1;
240 s->ptv = (value >> 2) & 7;
241 s->ar = (value >> 1) & 1;
242 s->st = value & 1;
243 omap_timer_update(s);
244 return;
245
246 case 0x04: /* LOAD_TIM */
247 s->reset_val = value;
248 return;
249
250 case 0x08: /* READ_TIM */
251 OMAP_RO_REG(addr);
252 break;
253
254 default:
255 OMAP_BAD_REG(addr);
256 }
257 }
258
259 static const MemoryRegionOps omap_mpu_timer_ops = {
260 .read = omap_mpu_timer_read,
261 .write = omap_mpu_timer_write,
262 .endianness = DEVICE_LITTLE_ENDIAN,
263 };
264
265 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
266 {
267 timer_del(s->timer);
268 s->enable = 0;
269 s->reset_val = 31337;
270 s->val = 0;
271 s->ptv = 0;
272 s->ar = 0;
273 s->st = 0;
274 s->it_ena = 1;
275 }
276
277 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
278 hwaddr base,
279 qemu_irq irq, omap_clk clk)
280 {
281 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
282
283 s->irq = irq;
284 s->clk = clk;
285 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
286 s->tick = qemu_bh_new(omap_timer_fire, s);
287 omap_mpu_timer_reset(s);
288 omap_timer_clk_setup(s);
289
290 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
291 "omap-mpu-timer", 0x100);
292
293 memory_region_add_subregion(system_memory, base, &s->iomem);
294
295 return s;
296 }
297
298 /* Watchdog timer */
299 struct omap_watchdog_timer_s {
300 struct omap_mpu_timer_s timer;
301 MemoryRegion iomem;
302 uint8_t last_wr;
303 int mode;
304 int free;
305 int reset;
306 };
307
308 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
309 unsigned size)
310 {
311 struct omap_watchdog_timer_s *s = opaque;
312
313 if (size != 2) {
314 return omap_badwidth_read16(opaque, addr);
315 }
316
317 switch (addr) {
318 case 0x00: /* CNTL_TIMER */
319 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
320 (s->timer.st << 7) | (s->free << 1);
321
322 case 0x04: /* READ_TIMER */
323 return omap_timer_read(&s->timer);
324
325 case 0x08: /* TIMER_MODE */
326 return s->mode << 15;
327 }
328
329 OMAP_BAD_REG(addr);
330 return 0;
331 }
332
333 static void omap_wd_timer_write(void *opaque, hwaddr addr,
334 uint64_t value, unsigned size)
335 {
336 struct omap_watchdog_timer_s *s = opaque;
337
338 if (size != 2) {
339 omap_badwidth_write16(opaque, addr, value);
340 return;
341 }
342
343 switch (addr) {
344 case 0x00: /* CNTL_TIMER */
345 omap_timer_sync(&s->timer);
346 s->timer.ptv = (value >> 9) & 7;
347 s->timer.ar = (value >> 8) & 1;
348 s->timer.st = (value >> 7) & 1;
349 s->free = (value >> 1) & 1;
350 omap_timer_update(&s->timer);
351 break;
352
353 case 0x04: /* LOAD_TIMER */
354 s->timer.reset_val = value & 0xffff;
355 break;
356
357 case 0x08: /* TIMER_MODE */
358 if (!s->mode && ((value >> 15) & 1))
359 omap_clk_get(s->timer.clk);
360 s->mode |= (value >> 15) & 1;
361 if (s->last_wr == 0xf5) {
362 if ((value & 0xff) == 0xa0) {
363 if (s->mode) {
364 s->mode = 0;
365 omap_clk_put(s->timer.clk);
366 }
367 } else {
368 /* XXX: on T|E hardware somehow this has no effect,
369 * on Zire 71 it works as specified. */
370 s->reset = 1;
371 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
372 }
373 }
374 s->last_wr = value & 0xff;
375 break;
376
377 default:
378 OMAP_BAD_REG(addr);
379 }
380 }
381
382 static const MemoryRegionOps omap_wd_timer_ops = {
383 .read = omap_wd_timer_read,
384 .write = omap_wd_timer_write,
385 .endianness = DEVICE_NATIVE_ENDIAN,
386 };
387
388 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
389 {
390 timer_del(s->timer.timer);
391 if (!s->mode)
392 omap_clk_get(s->timer.clk);
393 s->mode = 1;
394 s->free = 1;
395 s->reset = 0;
396 s->timer.enable = 1;
397 s->timer.it_ena = 1;
398 s->timer.reset_val = 0xffff;
399 s->timer.val = 0;
400 s->timer.st = 0;
401 s->timer.ptv = 0;
402 s->timer.ar = 0;
403 omap_timer_update(&s->timer);
404 }
405
406 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
407 hwaddr base,
408 qemu_irq irq, omap_clk clk)
409 {
410 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
411
412 s->timer.irq = irq;
413 s->timer.clk = clk;
414 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
415 omap_wd_timer_reset(s);
416 omap_timer_clk_setup(&s->timer);
417
418 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
419 "omap-wd-timer", 0x100);
420 memory_region_add_subregion(memory, base, &s->iomem);
421
422 return s;
423 }
424
425 /* 32-kHz timer */
426 struct omap_32khz_timer_s {
427 struct omap_mpu_timer_s timer;
428 MemoryRegion iomem;
429 };
430
431 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
432 unsigned size)
433 {
434 struct omap_32khz_timer_s *s = opaque;
435 int offset = addr & OMAP_MPUI_REG_MASK;
436
437 if (size != 4) {
438 return omap_badwidth_read32(opaque, addr);
439 }
440
441 switch (offset) {
442 case 0x00: /* TVR */
443 return s->timer.reset_val;
444
445 case 0x04: /* TCR */
446 return omap_timer_read(&s->timer);
447
448 case 0x08: /* CR */
449 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
450
451 default:
452 break;
453 }
454 OMAP_BAD_REG(addr);
455 return 0;
456 }
457
458 static void omap_os_timer_write(void *opaque, hwaddr addr,
459 uint64_t value, unsigned size)
460 {
461 struct omap_32khz_timer_s *s = opaque;
462 int offset = addr & OMAP_MPUI_REG_MASK;
463
464 if (size != 4) {
465 omap_badwidth_write32(opaque, addr, value);
466 return;
467 }
468
469 switch (offset) {
470 case 0x00: /* TVR */
471 s->timer.reset_val = value & 0x00ffffff;
472 break;
473
474 case 0x04: /* TCR */
475 OMAP_RO_REG(addr);
476 break;
477
478 case 0x08: /* CR */
479 s->timer.ar = (value >> 3) & 1;
480 s->timer.it_ena = (value >> 2) & 1;
481 if (s->timer.st != (value & 1) || (value & 2)) {
482 omap_timer_sync(&s->timer);
483 s->timer.enable = value & 1;
484 s->timer.st = value & 1;
485 omap_timer_update(&s->timer);
486 }
487 break;
488
489 default:
490 OMAP_BAD_REG(addr);
491 }
492 }
493
494 static const MemoryRegionOps omap_os_timer_ops = {
495 .read = omap_os_timer_read,
496 .write = omap_os_timer_write,
497 .endianness = DEVICE_NATIVE_ENDIAN,
498 };
499
500 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
501 {
502 timer_del(s->timer.timer);
503 s->timer.enable = 0;
504 s->timer.it_ena = 0;
505 s->timer.reset_val = 0x00ffffff;
506 s->timer.val = 0;
507 s->timer.st = 0;
508 s->timer.ptv = 0;
509 s->timer.ar = 1;
510 }
511
512 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
513 hwaddr base,
514 qemu_irq irq, omap_clk clk)
515 {
516 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
517
518 s->timer.irq = irq;
519 s->timer.clk = clk;
520 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
521 omap_os_timer_reset(s);
522 omap_timer_clk_setup(&s->timer);
523
524 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
525 "omap-os-timer", 0x800);
526 memory_region_add_subregion(memory, base, &s->iomem);
527
528 return s;
529 }
530
531 /* Ultra Low-Power Device Module */
532 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
533 unsigned size)
534 {
535 struct omap_mpu_state_s *s = opaque;
536 uint16_t ret;
537
538 if (size != 2) {
539 return omap_badwidth_read16(opaque, addr);
540 }
541
542 switch (addr) {
543 case 0x14: /* IT_STATUS */
544 ret = s->ulpd_pm_regs[addr >> 2];
545 s->ulpd_pm_regs[addr >> 2] = 0;
546 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
547 return ret;
548
549 case 0x18: /* Reserved */
550 case 0x1c: /* Reserved */
551 case 0x20: /* Reserved */
552 case 0x28: /* Reserved */
553 case 0x2c: /* Reserved */
554 OMAP_BAD_REG(addr);
555 /* fall through */
556 case 0x00: /* COUNTER_32_LSB */
557 case 0x04: /* COUNTER_32_MSB */
558 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
559 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
560 case 0x10: /* GAUGING_CTRL */
561 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
562 case 0x30: /* CLOCK_CTRL */
563 case 0x34: /* SOFT_REQ */
564 case 0x38: /* COUNTER_32_FIQ */
565 case 0x3c: /* DPLL_CTRL */
566 case 0x40: /* STATUS_REQ */
567 /* XXX: check clk::usecount state for every clock */
568 case 0x48: /* LOCL_TIME */
569 case 0x4c: /* APLL_CTRL */
570 case 0x50: /* POWER_CTRL */
571 return s->ulpd_pm_regs[addr >> 2];
572 }
573
574 OMAP_BAD_REG(addr);
575 return 0;
576 }
577
578 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
579 uint16_t diff, uint16_t value)
580 {
581 if (diff & (1 << 4)) /* USB_MCLK_EN */
582 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
583 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
584 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
585 }
586
587 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
588 uint16_t diff, uint16_t value)
589 {
590 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
591 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
592 if (diff & (1 << 1)) /* SOFT_COM_REQ */
593 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
594 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
595 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
596 if (diff & (1 << 3)) /* SOFT_USB_REQ */
597 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
598 }
599
600 static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
601 uint64_t value, unsigned size)
602 {
603 struct omap_mpu_state_s *s = opaque;
604 int64_t now, ticks;
605 int div, mult;
606 static const int bypass_div[4] = { 1, 2, 4, 4 };
607 uint16_t diff;
608
609 if (size != 2) {
610 omap_badwidth_write16(opaque, addr, value);
611 return;
612 }
613
614 switch (addr) {
615 case 0x00: /* COUNTER_32_LSB */
616 case 0x04: /* COUNTER_32_MSB */
617 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
618 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
619 case 0x14: /* IT_STATUS */
620 case 0x40: /* STATUS_REQ */
621 OMAP_RO_REG(addr);
622 break;
623
624 case 0x10: /* GAUGING_CTRL */
625 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
626 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
627 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
628
629 if (value & 1)
630 s->ulpd_gauge_start = now;
631 else {
632 now -= s->ulpd_gauge_start;
633
634 /* 32-kHz ticks */
635 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
636 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
637 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
638 if (ticks >> 32) /* OVERFLOW_32K */
639 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
640
641 /* High frequency ticks */
642 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
643 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
644 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
645 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
646 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
647
648 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
649 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
650 }
651 }
652 s->ulpd_pm_regs[addr >> 2] = value;
653 break;
654
655 case 0x18: /* Reserved */
656 case 0x1c: /* Reserved */
657 case 0x20: /* Reserved */
658 case 0x28: /* Reserved */
659 case 0x2c: /* Reserved */
660 OMAP_BAD_REG(addr);
661 /* fall through */
662 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
663 case 0x38: /* COUNTER_32_FIQ */
664 case 0x48: /* LOCL_TIME */
665 case 0x50: /* POWER_CTRL */
666 s->ulpd_pm_regs[addr >> 2] = value;
667 break;
668
669 case 0x30: /* CLOCK_CTRL */
670 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
671 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
672 omap_ulpd_clk_update(s, diff, value);
673 break;
674
675 case 0x34: /* SOFT_REQ */
676 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
677 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
678 omap_ulpd_req_update(s, diff, value);
679 break;
680
681 case 0x3c: /* DPLL_CTRL */
682 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
683 * omitted altogether, probably a typo. */
684 /* This register has identical semantics with DPLL(1:3) control
685 * registers, see omap_dpll_write() */
686 diff = s->ulpd_pm_regs[addr >> 2] & value;
687 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
688 if (diff & (0x3ff << 2)) {
689 if (value & (1 << 4)) { /* PLL_ENABLE */
690 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
691 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
692 } else {
693 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
694 mult = 1;
695 }
696 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
697 }
698
699 /* Enter the desired mode. */
700 s->ulpd_pm_regs[addr >> 2] =
701 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
702 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
703
704 /* Act as if the lock is restored. */
705 s->ulpd_pm_regs[addr >> 2] |= 2;
706 break;
707
708 case 0x4c: /* APLL_CTRL */
709 diff = s->ulpd_pm_regs[addr >> 2] & value;
710 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
711 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
712 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
713 (value & (1 << 0)) ? "apll" : "dpll4"));
714 break;
715
716 default:
717 OMAP_BAD_REG(addr);
718 }
719 }
720
721 static const MemoryRegionOps omap_ulpd_pm_ops = {
722 .read = omap_ulpd_pm_read,
723 .write = omap_ulpd_pm_write,
724 .endianness = DEVICE_NATIVE_ENDIAN,
725 };
726
727 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
728 {
729 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
730 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
731 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
732 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
733 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
734 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
735 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
736 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
737 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
738 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
739 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
740 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
741 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
742 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
743 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
744 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
745 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
746 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
747 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
748 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
749 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
750 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
751 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
752 }
753
754 static void omap_ulpd_pm_init(MemoryRegion *system_memory,
755 hwaddr base,
756 struct omap_mpu_state_s *mpu)
757 {
758 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
759 "omap-ulpd-pm", 0x800);
760 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
761 omap_ulpd_pm_reset(mpu);
762 }
763
764 /* OMAP Pin Configuration */
765 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
766 unsigned size)
767 {
768 struct omap_mpu_state_s *s = opaque;
769
770 if (size != 4) {
771 return omap_badwidth_read32(opaque, addr);
772 }
773
774 switch (addr) {
775 case 0x00: /* FUNC_MUX_CTRL_0 */
776 case 0x04: /* FUNC_MUX_CTRL_1 */
777 case 0x08: /* FUNC_MUX_CTRL_2 */
778 return s->func_mux_ctrl[addr >> 2];
779
780 case 0x0c: /* COMP_MODE_CTRL_0 */
781 return s->comp_mode_ctrl[0];
782
783 case 0x10: /* FUNC_MUX_CTRL_3 */
784 case 0x14: /* FUNC_MUX_CTRL_4 */
785 case 0x18: /* FUNC_MUX_CTRL_5 */
786 case 0x1c: /* FUNC_MUX_CTRL_6 */
787 case 0x20: /* FUNC_MUX_CTRL_7 */
788 case 0x24: /* FUNC_MUX_CTRL_8 */
789 case 0x28: /* FUNC_MUX_CTRL_9 */
790 case 0x2c: /* FUNC_MUX_CTRL_A */
791 case 0x30: /* FUNC_MUX_CTRL_B */
792 case 0x34: /* FUNC_MUX_CTRL_C */
793 case 0x38: /* FUNC_MUX_CTRL_D */
794 return s->func_mux_ctrl[(addr >> 2) - 1];
795
796 case 0x40: /* PULL_DWN_CTRL_0 */
797 case 0x44: /* PULL_DWN_CTRL_1 */
798 case 0x48: /* PULL_DWN_CTRL_2 */
799 case 0x4c: /* PULL_DWN_CTRL_3 */
800 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
801
802 case 0x50: /* GATE_INH_CTRL_0 */
803 return s->gate_inh_ctrl[0];
804
805 case 0x60: /* VOLTAGE_CTRL_0 */
806 return s->voltage_ctrl[0];
807
808 case 0x70: /* TEST_DBG_CTRL_0 */
809 return s->test_dbg_ctrl[0];
810
811 case 0x80: /* MOD_CONF_CTRL_0 */
812 return s->mod_conf_ctrl[0];
813 }
814
815 OMAP_BAD_REG(addr);
816 return 0;
817 }
818
819 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
820 uint32_t diff, uint32_t value)
821 {
822 if (s->compat1509) {
823 if (diff & (1 << 9)) /* BLUETOOTH */
824 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
825 (~value >> 9) & 1);
826 if (diff & (1 << 7)) /* USB.CLKO */
827 omap_clk_onoff(omap_findclk(s, "usb.clko"),
828 (value >> 7) & 1);
829 }
830 }
831
832 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
833 uint32_t diff, uint32_t value)
834 {
835 if (s->compat1509) {
836 if (diff & (1U << 31)) {
837 /* MCBSP3_CLK_HIZ_DI */
838 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
839 }
840 if (diff & (1 << 1)) {
841 /* CLK32K */
842 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
843 }
844 }
845 }
846
847 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
848 uint32_t diff, uint32_t value)
849 {
850 if (diff & (1U << 31)) {
851 /* CONF_MOD_UART3_CLK_MODE_R */
852 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
853 omap_findclk(s, ((value >> 31) & 1) ?
854 "ck_48m" : "armper_ck"));
855 }
856 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
857 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
858 omap_findclk(s, ((value >> 30) & 1) ?
859 "ck_48m" : "armper_ck"));
860 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
861 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
862 omap_findclk(s, ((value >> 29) & 1) ?
863 "ck_48m" : "armper_ck"));
864 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
865 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
866 omap_findclk(s, ((value >> 23) & 1) ?
867 "ck_48m" : "armper_ck"));
868 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
869 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
870 omap_findclk(s, ((value >> 12) & 1) ?
871 "ck_48m" : "armper_ck"));
872 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
873 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
874 }
875
876 static void omap_pin_cfg_write(void *opaque, hwaddr addr,
877 uint64_t value, unsigned size)
878 {
879 struct omap_mpu_state_s *s = opaque;
880 uint32_t diff;
881
882 if (size != 4) {
883 omap_badwidth_write32(opaque, addr, value);
884 return;
885 }
886
887 switch (addr) {
888 case 0x00: /* FUNC_MUX_CTRL_0 */
889 diff = s->func_mux_ctrl[addr >> 2] ^ value;
890 s->func_mux_ctrl[addr >> 2] = value;
891 omap_pin_funcmux0_update(s, diff, value);
892 return;
893
894 case 0x04: /* FUNC_MUX_CTRL_1 */
895 diff = s->func_mux_ctrl[addr >> 2] ^ value;
896 s->func_mux_ctrl[addr >> 2] = value;
897 omap_pin_funcmux1_update(s, diff, value);
898 return;
899
900 case 0x08: /* FUNC_MUX_CTRL_2 */
901 s->func_mux_ctrl[addr >> 2] = value;
902 return;
903
904 case 0x0c: /* COMP_MODE_CTRL_0 */
905 s->comp_mode_ctrl[0] = value;
906 s->compat1509 = (value != 0x0000eaef);
907 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
908 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
909 return;
910
911 case 0x10: /* FUNC_MUX_CTRL_3 */
912 case 0x14: /* FUNC_MUX_CTRL_4 */
913 case 0x18: /* FUNC_MUX_CTRL_5 */
914 case 0x1c: /* FUNC_MUX_CTRL_6 */
915 case 0x20: /* FUNC_MUX_CTRL_7 */
916 case 0x24: /* FUNC_MUX_CTRL_8 */
917 case 0x28: /* FUNC_MUX_CTRL_9 */
918 case 0x2c: /* FUNC_MUX_CTRL_A */
919 case 0x30: /* FUNC_MUX_CTRL_B */
920 case 0x34: /* FUNC_MUX_CTRL_C */
921 case 0x38: /* FUNC_MUX_CTRL_D */
922 s->func_mux_ctrl[(addr >> 2) - 1] = value;
923 return;
924
925 case 0x40: /* PULL_DWN_CTRL_0 */
926 case 0x44: /* PULL_DWN_CTRL_1 */
927 case 0x48: /* PULL_DWN_CTRL_2 */
928 case 0x4c: /* PULL_DWN_CTRL_3 */
929 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
930 return;
931
932 case 0x50: /* GATE_INH_CTRL_0 */
933 s->gate_inh_ctrl[0] = value;
934 return;
935
936 case 0x60: /* VOLTAGE_CTRL_0 */
937 s->voltage_ctrl[0] = value;
938 return;
939
940 case 0x70: /* TEST_DBG_CTRL_0 */
941 s->test_dbg_ctrl[0] = value;
942 return;
943
944 case 0x80: /* MOD_CONF_CTRL_0 */
945 diff = s->mod_conf_ctrl[0] ^ value;
946 s->mod_conf_ctrl[0] = value;
947 omap_pin_modconf1_update(s, diff, value);
948 return;
949
950 default:
951 OMAP_BAD_REG(addr);
952 }
953 }
954
955 static const MemoryRegionOps omap_pin_cfg_ops = {
956 .read = omap_pin_cfg_read,
957 .write = omap_pin_cfg_write,
958 .endianness = DEVICE_NATIVE_ENDIAN,
959 };
960
961 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
962 {
963 /* Start in Compatibility Mode. */
964 mpu->compat1509 = 1;
965 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
966 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
967 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
968 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
969 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
970 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
971 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
972 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
973 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
974 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
975 }
976
977 static void omap_pin_cfg_init(MemoryRegion *system_memory,
978 hwaddr base,
979 struct omap_mpu_state_s *mpu)
980 {
981 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
982 "omap-pin-cfg", 0x800);
983 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
984 omap_pin_cfg_reset(mpu);
985 }
986
987 /* Device Identification, Die Identification */
988 static uint64_t omap_id_read(void *opaque, hwaddr addr,
989 unsigned size)
990 {
991 struct omap_mpu_state_s *s = opaque;
992
993 if (size != 4) {
994 return omap_badwidth_read32(opaque, addr);
995 }
996
997 switch (addr) {
998 case 0xfffe1800: /* DIE_ID_LSB */
999 return 0xc9581f0e;
1000 case 0xfffe1804: /* DIE_ID_MSB */
1001 return 0xa8858bfa;
1002
1003 case 0xfffe2000: /* PRODUCT_ID_LSB */
1004 return 0x00aaaafc;
1005 case 0xfffe2004: /* PRODUCT_ID_MSB */
1006 return 0xcafeb574;
1007
1008 case 0xfffed400: /* JTAG_ID_LSB */
1009 switch (s->mpu_model) {
1010 case omap310:
1011 return 0x03310315;
1012 case omap1510:
1013 return 0x03310115;
1014 default:
1015 hw_error("%s: bad mpu model\n", __func__);
1016 }
1017 break;
1018
1019 case 0xfffed404: /* JTAG_ID_MSB */
1020 switch (s->mpu_model) {
1021 case omap310:
1022 return 0xfb57402f;
1023 case omap1510:
1024 return 0xfb47002f;
1025 default:
1026 hw_error("%s: bad mpu model\n", __func__);
1027 }
1028 break;
1029 }
1030
1031 OMAP_BAD_REG(addr);
1032 return 0;
1033 }
1034
1035 static void omap_id_write(void *opaque, hwaddr addr,
1036 uint64_t value, unsigned size)
1037 {
1038 if (size != 4) {
1039 omap_badwidth_write32(opaque, addr, value);
1040 return;
1041 }
1042
1043 OMAP_BAD_REG(addr);
1044 }
1045
1046 static const MemoryRegionOps omap_id_ops = {
1047 .read = omap_id_read,
1048 .write = omap_id_write,
1049 .endianness = DEVICE_NATIVE_ENDIAN,
1050 };
1051
1052 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
1053 {
1054 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
1055 "omap-id", 0x100000000ULL);
1056 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
1057 0xfffe1800, 0x800);
1058 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
1059 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
1060 0xfffed400, 0x100);
1061 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1062 if (!cpu_is_omap15xx(mpu)) {
1063 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
1064 &mpu->id_iomem, 0xfffe2000, 0x800);
1065 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
1066 }
1067 }
1068
1069 /* MPUI Control (Dummy) */
1070 static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
1071 unsigned size)
1072 {
1073 struct omap_mpu_state_s *s = opaque;
1074
1075 if (size != 4) {
1076 return omap_badwidth_read32(opaque, addr);
1077 }
1078
1079 switch (addr) {
1080 case 0x00: /* CTRL */
1081 return s->mpui_ctrl;
1082 case 0x04: /* DEBUG_ADDR */
1083 return 0x01ffffff;
1084 case 0x08: /* DEBUG_DATA */
1085 return 0xffffffff;
1086 case 0x0c: /* DEBUG_FLAG */
1087 return 0x00000800;
1088 case 0x10: /* STATUS */
1089 return 0x00000000;
1090
1091 /* Not in OMAP310 */
1092 case 0x14: /* DSP_STATUS */
1093 case 0x18: /* DSP_BOOT_CONFIG */
1094 return 0x00000000;
1095 case 0x1c: /* DSP_MPUI_CONFIG */
1096 return 0x0000ffff;
1097 }
1098
1099 OMAP_BAD_REG(addr);
1100 return 0;
1101 }
1102
1103 static void omap_mpui_write(void *opaque, hwaddr addr,
1104 uint64_t value, unsigned size)
1105 {
1106 struct omap_mpu_state_s *s = opaque;
1107
1108 if (size != 4) {
1109 omap_badwidth_write32(opaque, addr, value);
1110 return;
1111 }
1112
1113 switch (addr) {
1114 case 0x00: /* CTRL */
1115 s->mpui_ctrl = value & 0x007fffff;
1116 break;
1117
1118 case 0x04: /* DEBUG_ADDR */
1119 case 0x08: /* DEBUG_DATA */
1120 case 0x0c: /* DEBUG_FLAG */
1121 case 0x10: /* STATUS */
1122 /* Not in OMAP310 */
1123 case 0x14: /* DSP_STATUS */
1124 OMAP_RO_REG(addr);
1125 break;
1126 case 0x18: /* DSP_BOOT_CONFIG */
1127 case 0x1c: /* DSP_MPUI_CONFIG */
1128 break;
1129
1130 default:
1131 OMAP_BAD_REG(addr);
1132 }
1133 }
1134
1135 static const MemoryRegionOps omap_mpui_ops = {
1136 .read = omap_mpui_read,
1137 .write = omap_mpui_write,
1138 .endianness = DEVICE_NATIVE_ENDIAN,
1139 };
1140
1141 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1142 {
1143 s->mpui_ctrl = 0x0003ff1b;
1144 }
1145
1146 static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
1147 struct omap_mpu_state_s *mpu)
1148 {
1149 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
1150 "omap-mpui", 0x100);
1151 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
1152
1153 omap_mpui_reset(mpu);
1154 }
1155
1156 /* TIPB Bridges */
1157 struct omap_tipb_bridge_s {
1158 qemu_irq abort;
1159 MemoryRegion iomem;
1160
1161 int width_intr;
1162 uint16_t control;
1163 uint16_t alloc;
1164 uint16_t buffer;
1165 uint16_t enh_control;
1166 };
1167
1168 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
1169 unsigned size)
1170 {
1171 struct omap_tipb_bridge_s *s = opaque;
1172
1173 if (size < 2) {
1174 return omap_badwidth_read16(opaque, addr);
1175 }
1176
1177 switch (addr) {
1178 case 0x00: /* TIPB_CNTL */
1179 return s->control;
1180 case 0x04: /* TIPB_BUS_ALLOC */
1181 return s->alloc;
1182 case 0x08: /* MPU_TIPB_CNTL */
1183 return s->buffer;
1184 case 0x0c: /* ENHANCED_TIPB_CNTL */
1185 return s->enh_control;
1186 case 0x10: /* ADDRESS_DBG */
1187 case 0x14: /* DATA_DEBUG_LOW */
1188 case 0x18: /* DATA_DEBUG_HIGH */
1189 return 0xffff;
1190 case 0x1c: /* DEBUG_CNTR_SIG */
1191 return 0x00f8;
1192 }
1193
1194 OMAP_BAD_REG(addr);
1195 return 0;
1196 }
1197
1198 static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
1199 uint64_t value, unsigned size)
1200 {
1201 struct omap_tipb_bridge_s *s = opaque;
1202
1203 if (size < 2) {
1204 omap_badwidth_write16(opaque, addr, value);
1205 return;
1206 }
1207
1208 switch (addr) {
1209 case 0x00: /* TIPB_CNTL */
1210 s->control = value & 0xffff;
1211 break;
1212
1213 case 0x04: /* TIPB_BUS_ALLOC */
1214 s->alloc = value & 0x003f;
1215 break;
1216
1217 case 0x08: /* MPU_TIPB_CNTL */
1218 s->buffer = value & 0x0003;
1219 break;
1220
1221 case 0x0c: /* ENHANCED_TIPB_CNTL */
1222 s->width_intr = !(value & 2);
1223 s->enh_control = value & 0x000f;
1224 break;
1225
1226 case 0x10: /* ADDRESS_DBG */
1227 case 0x14: /* DATA_DEBUG_LOW */
1228 case 0x18: /* DATA_DEBUG_HIGH */
1229 case 0x1c: /* DEBUG_CNTR_SIG */
1230 OMAP_RO_REG(addr);
1231 break;
1232
1233 default:
1234 OMAP_BAD_REG(addr);
1235 }
1236 }
1237
1238 static const MemoryRegionOps omap_tipb_bridge_ops = {
1239 .read = omap_tipb_bridge_read,
1240 .write = omap_tipb_bridge_write,
1241 .endianness = DEVICE_NATIVE_ENDIAN,
1242 };
1243
1244 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1245 {
1246 s->control = 0xffff;
1247 s->alloc = 0x0009;
1248 s->buffer = 0x0000;
1249 s->enh_control = 0x000f;
1250 }
1251
1252 static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1253 MemoryRegion *memory, hwaddr base,
1254 qemu_irq abort_irq, omap_clk clk)
1255 {
1256 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
1257
1258 s->abort = abort_irq;
1259 omap_tipb_bridge_reset(s);
1260
1261 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
1262 "omap-tipb-bridge", 0x100);
1263 memory_region_add_subregion(memory, base, &s->iomem);
1264
1265 return s;
1266 }
1267
1268 /* Dummy Traffic Controller's Memory Interface */
1269 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
1270 unsigned size)
1271 {
1272 struct omap_mpu_state_s *s = opaque;
1273 uint32_t ret;
1274
1275 if (size != 4) {
1276 return omap_badwidth_read32(opaque, addr);
1277 }
1278
1279 switch (addr) {
1280 case 0x00: /* IMIF_PRIO */
1281 case 0x04: /* EMIFS_PRIO */
1282 case 0x08: /* EMIFF_PRIO */
1283 case 0x0c: /* EMIFS_CONFIG */
1284 case 0x10: /* EMIFS_CS0_CONFIG */
1285 case 0x14: /* EMIFS_CS1_CONFIG */
1286 case 0x18: /* EMIFS_CS2_CONFIG */
1287 case 0x1c: /* EMIFS_CS3_CONFIG */
1288 case 0x24: /* EMIFF_MRS */
1289 case 0x28: /* TIMEOUT1 */
1290 case 0x2c: /* TIMEOUT2 */
1291 case 0x30: /* TIMEOUT3 */
1292 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1293 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1294 return s->tcmi_regs[addr >> 2];
1295
1296 case 0x20: /* EMIFF_SDRAM_CONFIG */
1297 ret = s->tcmi_regs[addr >> 2];
1298 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1299 /* XXX: We can try using the VGA_DIRTY flag for this */
1300 return ret;
1301 }
1302
1303 OMAP_BAD_REG(addr);
1304 return 0;
1305 }
1306
1307 static void omap_tcmi_write(void *opaque, hwaddr addr,
1308 uint64_t value, unsigned size)
1309 {
1310 struct omap_mpu_state_s *s = opaque;
1311
1312 if (size != 4) {
1313 omap_badwidth_write32(opaque, addr, value);
1314 return;
1315 }
1316
1317 switch (addr) {
1318 case 0x00: /* IMIF_PRIO */
1319 case 0x04: /* EMIFS_PRIO */
1320 case 0x08: /* EMIFF_PRIO */
1321 case 0x10: /* EMIFS_CS0_CONFIG */
1322 case 0x14: /* EMIFS_CS1_CONFIG */
1323 case 0x18: /* EMIFS_CS2_CONFIG */
1324 case 0x1c: /* EMIFS_CS3_CONFIG */
1325 case 0x20: /* EMIFF_SDRAM_CONFIG */
1326 case 0x24: /* EMIFF_MRS */
1327 case 0x28: /* TIMEOUT1 */
1328 case 0x2c: /* TIMEOUT2 */
1329 case 0x30: /* TIMEOUT3 */
1330 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1331 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1332 s->tcmi_regs[addr >> 2] = value;
1333 break;
1334 case 0x0c: /* EMIFS_CONFIG */
1335 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
1336 break;
1337
1338 default:
1339 OMAP_BAD_REG(addr);
1340 }
1341 }
1342
1343 static const MemoryRegionOps omap_tcmi_ops = {
1344 .read = omap_tcmi_read,
1345 .write = omap_tcmi_write,
1346 .endianness = DEVICE_NATIVE_ENDIAN,
1347 };
1348
1349 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1350 {
1351 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1352 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1353 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1354 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1355 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1356 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1357 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1358 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1359 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1360 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1361 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1362 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1363 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1364 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1365 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1366 }
1367
1368 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
1369 struct omap_mpu_state_s *mpu)
1370 {
1371 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
1372 "omap-tcmi", 0x100);
1373 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
1374 omap_tcmi_reset(mpu);
1375 }
1376
1377 /* Digital phase-locked loops control */
1378 struct dpll_ctl_s {
1379 MemoryRegion iomem;
1380 uint16_t mode;
1381 omap_clk dpll;
1382 };
1383
1384 static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
1385 unsigned size)
1386 {
1387 struct dpll_ctl_s *s = opaque;
1388
1389 if (size != 2) {
1390 return omap_badwidth_read16(opaque, addr);
1391 }
1392
1393 if (addr == 0x00) /* CTL_REG */
1394 return s->mode;
1395
1396 OMAP_BAD_REG(addr);
1397 return 0;
1398 }
1399
1400 static void omap_dpll_write(void *opaque, hwaddr addr,
1401 uint64_t value, unsigned size)
1402 {
1403 struct dpll_ctl_s *s = opaque;
1404 uint16_t diff;
1405 static const int bypass_div[4] = { 1, 2, 4, 4 };
1406 int div, mult;
1407
1408 if (size != 2) {
1409 omap_badwidth_write16(opaque, addr, value);
1410 return;
1411 }
1412
1413 if (addr == 0x00) { /* CTL_REG */
1414 /* See omap_ulpd_pm_write() too */
1415 diff = s->mode & value;
1416 s->mode = value & 0x2fff;
1417 if (diff & (0x3ff << 2)) {
1418 if (value & (1 << 4)) { /* PLL_ENABLE */
1419 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1420 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1421 } else {
1422 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1423 mult = 1;
1424 }
1425 omap_clk_setrate(s->dpll, div, mult);
1426 }
1427
1428 /* Enter the desired mode. */
1429 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1430
1431 /* Act as if the lock is restored. */
1432 s->mode |= 2;
1433 } else {
1434 OMAP_BAD_REG(addr);
1435 }
1436 }
1437
1438 static const MemoryRegionOps omap_dpll_ops = {
1439 .read = omap_dpll_read,
1440 .write = omap_dpll_write,
1441 .endianness = DEVICE_NATIVE_ENDIAN,
1442 };
1443
1444 static void omap_dpll_reset(struct dpll_ctl_s *s)
1445 {
1446 s->mode = 0x2002;
1447 omap_clk_setrate(s->dpll, 1, 1);
1448 }
1449
1450 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
1451 hwaddr base, omap_clk clk)
1452 {
1453 struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
1454 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
1455
1456 s->dpll = clk;
1457 omap_dpll_reset(s);
1458
1459 memory_region_add_subregion(memory, base, &s->iomem);
1460 return s;
1461 }
1462
1463 /* MPU Clock/Reset/Power Mode Control */
1464 static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
1465 unsigned size)
1466 {
1467 struct omap_mpu_state_s *s = opaque;
1468
1469 if (size != 2) {
1470 return omap_badwidth_read16(opaque, addr);
1471 }
1472
1473 switch (addr) {
1474 case 0x00: /* ARM_CKCTL */
1475 return s->clkm.arm_ckctl;
1476
1477 case 0x04: /* ARM_IDLECT1 */
1478 return s->clkm.arm_idlect1;
1479
1480 case 0x08: /* ARM_IDLECT2 */
1481 return s->clkm.arm_idlect2;
1482
1483 case 0x0c: /* ARM_EWUPCT */
1484 return s->clkm.arm_ewupct;
1485
1486 case 0x10: /* ARM_RSTCT1 */
1487 return s->clkm.arm_rstct1;
1488
1489 case 0x14: /* ARM_RSTCT2 */
1490 return s->clkm.arm_rstct2;
1491
1492 case 0x18: /* ARM_SYSST */
1493 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
1494
1495 case 0x1c: /* ARM_CKOUT1 */
1496 return s->clkm.arm_ckout1;
1497
1498 case 0x20: /* ARM_CKOUT2 */
1499 break;
1500 }
1501
1502 OMAP_BAD_REG(addr);
1503 return 0;
1504 }
1505
1506 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1507 uint16_t diff, uint16_t value)
1508 {
1509 omap_clk clk;
1510
1511 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1512 if (value & (1 << 14))
1513 /* Reserved */;
1514 else {
1515 clk = omap_findclk(s, "arminth_ck");
1516 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1517 }
1518 }
1519 if (diff & (1 << 12)) { /* ARM_TIMXO */
1520 clk = omap_findclk(s, "armtim_ck");
1521 if (value & (1 << 12))
1522 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1523 else
1524 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1525 }
1526 /* XXX: en_dspck */
1527 if (diff & (3 << 10)) { /* DSPMMUDIV */
1528 clk = omap_findclk(s, "dspmmu_ck");
1529 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1530 }
1531 if (diff & (3 << 8)) { /* TCDIV */
1532 clk = omap_findclk(s, "tc_ck");
1533 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1534 }
1535 if (diff & (3 << 6)) { /* DSPDIV */
1536 clk = omap_findclk(s, "dsp_ck");
1537 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1538 }
1539 if (diff & (3 << 4)) { /* ARMDIV */
1540 clk = omap_findclk(s, "arm_ck");
1541 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1542 }
1543 if (diff & (3 << 2)) { /* LCDDIV */
1544 clk = omap_findclk(s, "lcd_ck");
1545 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1546 }
1547 if (diff & (3 << 0)) { /* PERDIV */
1548 clk = omap_findclk(s, "armper_ck");
1549 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1550 }
1551 }
1552
1553 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1554 uint16_t diff, uint16_t value)
1555 {
1556 omap_clk clk;
1557
1558 if (value & (1 << 11)) { /* SETARM_IDLE */
1559 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
1560 }
1561 if (!(value & (1 << 10))) { /* WKUP_MODE */
1562 /* XXX: disable wakeup from IRQ */
1563 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
1564 }
1565
1566 #define SET_CANIDLE(clock, bit) \
1567 if (diff & (1 << bit)) { \
1568 clk = omap_findclk(s, clock); \
1569 omap_clk_canidle(clk, (value >> bit) & 1); \
1570 }
1571 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1572 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1573 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1574 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1575 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1576 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1577 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1578 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1579 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1580 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1581 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1582 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1583 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1584 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1585 }
1586
1587 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1588 uint16_t diff, uint16_t value)
1589 {
1590 omap_clk clk;
1591
1592 #define SET_ONOFF(clock, bit) \
1593 if (diff & (1 << bit)) { \
1594 clk = omap_findclk(s, clock); \
1595 omap_clk_onoff(clk, (value >> bit) & 1); \
1596 }
1597 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1598 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1599 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1600 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1601 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1602 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1603 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1604 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1605 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1606 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1607 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1608 }
1609
1610 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1611 uint16_t diff, uint16_t value)
1612 {
1613 omap_clk clk;
1614
1615 if (diff & (3 << 4)) { /* TCLKOUT */
1616 clk = omap_findclk(s, "tclk_out");
1617 switch ((value >> 4) & 3) {
1618 case 1:
1619 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1620 omap_clk_onoff(clk, 1);
1621 break;
1622 case 2:
1623 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1624 omap_clk_onoff(clk, 1);
1625 break;
1626 default:
1627 omap_clk_onoff(clk, 0);
1628 }
1629 }
1630 if (diff & (3 << 2)) { /* DCLKOUT */
1631 clk = omap_findclk(s, "dclk_out");
1632 switch ((value >> 2) & 3) {
1633 case 0:
1634 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1635 break;
1636 case 1:
1637 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1638 break;
1639 case 2:
1640 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1641 break;
1642 case 3:
1643 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1644 break;
1645 }
1646 }
1647 if (diff & (3 << 0)) { /* ACLKOUT */
1648 clk = omap_findclk(s, "aclk_out");
1649 switch ((value >> 0) & 3) {
1650 case 1:
1651 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1652 omap_clk_onoff(clk, 1);
1653 break;
1654 case 2:
1655 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1656 omap_clk_onoff(clk, 1);
1657 break;
1658 case 3:
1659 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1660 omap_clk_onoff(clk, 1);
1661 break;
1662 default:
1663 omap_clk_onoff(clk, 0);
1664 }
1665 }
1666 }
1667
1668 static void omap_clkm_write(void *opaque, hwaddr addr,
1669 uint64_t value, unsigned size)
1670 {
1671 struct omap_mpu_state_s *s = opaque;
1672 uint16_t diff;
1673 omap_clk clk;
1674 static const char *clkschemename[8] = {
1675 "fully synchronous", "fully asynchronous", "synchronous scalable",
1676 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1677 };
1678
1679 if (size != 2) {
1680 omap_badwidth_write16(opaque, addr, value);
1681 return;
1682 }
1683
1684 switch (addr) {
1685 case 0x00: /* ARM_CKCTL */
1686 diff = s->clkm.arm_ckctl ^ value;
1687 s->clkm.arm_ckctl = value & 0x7fff;
1688 omap_clkm_ckctl_update(s, diff, value);
1689 return;
1690
1691 case 0x04: /* ARM_IDLECT1 */
1692 diff = s->clkm.arm_idlect1 ^ value;
1693 s->clkm.arm_idlect1 = value & 0x0fff;
1694 omap_clkm_idlect1_update(s, diff, value);
1695 return;
1696
1697 case 0x08: /* ARM_IDLECT2 */
1698 diff = s->clkm.arm_idlect2 ^ value;
1699 s->clkm.arm_idlect2 = value & 0x07ff;
1700 omap_clkm_idlect2_update(s, diff, value);
1701 return;
1702
1703 case 0x0c: /* ARM_EWUPCT */
1704 s->clkm.arm_ewupct = value & 0x003f;
1705 return;
1706
1707 case 0x10: /* ARM_RSTCT1 */
1708 diff = s->clkm.arm_rstct1 ^ value;
1709 s->clkm.arm_rstct1 = value & 0x0007;
1710 if (value & 9) {
1711 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1712 s->clkm.cold_start = 0xa;
1713 }
1714 if (diff & ~value & 4) { /* DSP_RST */
1715 omap_mpui_reset(s);
1716 omap_tipb_bridge_reset(s->private_tipb);
1717 omap_tipb_bridge_reset(s->public_tipb);
1718 }
1719 if (diff & 2) { /* DSP_EN */
1720 clk = omap_findclk(s, "dsp_ck");
1721 omap_clk_canidle(clk, (~value >> 1) & 1);
1722 }
1723 return;
1724
1725 case 0x14: /* ARM_RSTCT2 */
1726 s->clkm.arm_rstct2 = value & 0x0001;
1727 return;
1728
1729 case 0x18: /* ARM_SYSST */
1730 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1731 s->clkm.clocking_scheme = (value >> 11) & 7;
1732 printf("%s: clocking scheme set to %s\n", __func__,
1733 clkschemename[s->clkm.clocking_scheme]);
1734 }
1735 s->clkm.cold_start &= value & 0x3f;
1736 return;
1737
1738 case 0x1c: /* ARM_CKOUT1 */
1739 diff = s->clkm.arm_ckout1 ^ value;
1740 s->clkm.arm_ckout1 = value & 0x003f;
1741 omap_clkm_ckout1_update(s, diff, value);
1742 return;
1743
1744 case 0x20: /* ARM_CKOUT2 */
1745 default:
1746 OMAP_BAD_REG(addr);
1747 }
1748 }
1749
1750 static const MemoryRegionOps omap_clkm_ops = {
1751 .read = omap_clkm_read,
1752 .write = omap_clkm_write,
1753 .endianness = DEVICE_NATIVE_ENDIAN,
1754 };
1755
1756 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
1757 unsigned size)
1758 {
1759 struct omap_mpu_state_s *s = opaque;
1760 CPUState *cpu = CPU(s->cpu);
1761
1762 if (size != 2) {
1763 return omap_badwidth_read16(opaque, addr);
1764 }
1765
1766 switch (addr) {
1767 case 0x04: /* DSP_IDLECT1 */
1768 return s->clkm.dsp_idlect1;
1769
1770 case 0x08: /* DSP_IDLECT2 */
1771 return s->clkm.dsp_idlect2;
1772
1773 case 0x14: /* DSP_RSTCT2 */
1774 return s->clkm.dsp_rstct2;
1775
1776 case 0x18: /* DSP_SYSST */
1777 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
1778 (cpu->halted << 6); /* Quite useless... */
1779 }
1780
1781 OMAP_BAD_REG(addr);
1782 return 0;
1783 }
1784
1785 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1786 uint16_t diff, uint16_t value)
1787 {
1788 omap_clk clk;
1789
1790 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1791 }
1792
1793 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1794 uint16_t diff, uint16_t value)
1795 {
1796 omap_clk clk;
1797
1798 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1799 }
1800
1801 static void omap_clkdsp_write(void *opaque, hwaddr addr,
1802 uint64_t value, unsigned size)
1803 {
1804 struct omap_mpu_state_s *s = opaque;
1805 uint16_t diff;
1806
1807 if (size != 2) {
1808 omap_badwidth_write16(opaque, addr, value);
1809 return;
1810 }
1811
1812 switch (addr) {
1813 case 0x04: /* DSP_IDLECT1 */
1814 diff = s->clkm.dsp_idlect1 ^ value;
1815 s->clkm.dsp_idlect1 = value & 0x01f7;
1816 omap_clkdsp_idlect1_update(s, diff, value);
1817 break;
1818
1819 case 0x08: /* DSP_IDLECT2 */
1820 s->clkm.dsp_idlect2 = value & 0x0037;
1821 diff = s->clkm.dsp_idlect1 ^ value;
1822 omap_clkdsp_idlect2_update(s, diff, value);
1823 break;
1824
1825 case 0x14: /* DSP_RSTCT2 */
1826 s->clkm.dsp_rstct2 = value & 0x0001;
1827 break;
1828
1829 case 0x18: /* DSP_SYSST */
1830 s->clkm.cold_start &= value & 0x3f;
1831 break;
1832
1833 default:
1834 OMAP_BAD_REG(addr);
1835 }
1836 }
1837
1838 static const MemoryRegionOps omap_clkdsp_ops = {
1839 .read = omap_clkdsp_read,
1840 .write = omap_clkdsp_write,
1841 .endianness = DEVICE_NATIVE_ENDIAN,
1842 };
1843
1844 static void omap_clkm_reset(struct omap_mpu_state_s *s)
1845 {
1846 if (s->wdt && s->wdt->reset)
1847 s->clkm.cold_start = 0x6;
1848 s->clkm.clocking_scheme = 0;
1849 omap_clkm_ckctl_update(s, ~0, 0x3000);
1850 s->clkm.arm_ckctl = 0x3000;
1851 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
1852 s->clkm.arm_idlect1 = 0x0400;
1853 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
1854 s->clkm.arm_idlect2 = 0x0100;
1855 s->clkm.arm_ewupct = 0x003f;
1856 s->clkm.arm_rstct1 = 0x0000;
1857 s->clkm.arm_rstct2 = 0x0000;
1858 s->clkm.arm_ckout1 = 0x0015;
1859 s->clkm.dpll1_mode = 0x2002;
1860 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1861 s->clkm.dsp_idlect1 = 0x0040;
1862 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1863 s->clkm.dsp_idlect2 = 0x0000;
1864 s->clkm.dsp_rstct2 = 0x0000;
1865 }
1866
1867 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
1868 hwaddr dsp_base, struct omap_mpu_state_s *s)
1869 {
1870 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
1871 "omap-clkm", 0x100);
1872 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
1873 "omap-clkdsp", 0x1000);
1874
1875 s->clkm.arm_idlect1 = 0x03ff;
1876 s->clkm.arm_idlect2 = 0x0100;
1877 s->clkm.dsp_idlect1 = 0x0002;
1878 omap_clkm_reset(s);
1879 s->clkm.cold_start = 0x3a;
1880
1881 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
1882 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
1883 }
1884
1885 /* MPU I/O */
1886 struct omap_mpuio_s {
1887 qemu_irq irq;
1888 qemu_irq kbd_irq;
1889 qemu_irq *in;
1890 qemu_irq handler[16];
1891 qemu_irq wakeup;
1892 MemoryRegion iomem;
1893
1894 uint16_t inputs;
1895 uint16_t outputs;
1896 uint16_t dir;
1897 uint16_t edge;
1898 uint16_t mask;
1899 uint16_t ints;
1900
1901 uint16_t debounce;
1902 uint16_t latch;
1903 uint8_t event;
1904
1905 uint8_t buttons[5];
1906 uint8_t row_latch;
1907 uint8_t cols;
1908 int kbd_mask;
1909 int clk;
1910 };
1911
1912 static void omap_mpuio_set(void *opaque, int line, int level)
1913 {
1914 struct omap_mpuio_s *s = opaque;
1915 uint16_t prev = s->inputs;
1916
1917 if (level)
1918 s->inputs |= 1 << line;
1919 else
1920 s->inputs &= ~(1 << line);
1921
1922 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1923 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1924 s->ints |= 1 << line;
1925 qemu_irq_raise(s->irq);
1926 /* TODO: wakeup */
1927 }
1928 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1929 (s->event >> 1) == line) /* PIN_SELECT */
1930 s->latch = s->inputs;
1931 }
1932 }
1933
1934 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1935 {
1936 int i;
1937 uint8_t *row, rows = 0, cols = ~s->cols;
1938
1939 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
1940 if (*row & cols)
1941 rows |= i;
1942
1943 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1944 s->row_latch = ~rows;
1945 }
1946
1947 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
1948 unsigned size)
1949 {
1950 struct omap_mpuio_s *s = opaque;
1951 int offset = addr & OMAP_MPUI_REG_MASK;
1952 uint16_t ret;
1953
1954 if (size != 2) {
1955 return omap_badwidth_read16(opaque, addr);
1956 }
1957
1958 switch (offset) {
1959 case 0x00: /* INPUT_LATCH */
1960 return s->inputs;
1961
1962 case 0x04: /* OUTPUT_REG */
1963 return s->outputs;
1964
1965 case 0x08: /* IO_CNTL */
1966 return s->dir;
1967
1968 case 0x10: /* KBR_LATCH */
1969 return s->row_latch;
1970
1971 case 0x14: /* KBC_REG */
1972 return s->cols;
1973
1974 case 0x18: /* GPIO_EVENT_MODE_REG */
1975 return s->event;
1976
1977 case 0x1c: /* GPIO_INT_EDGE_REG */
1978 return s->edge;
1979
1980 case 0x20: /* KBD_INT */
1981 return (~s->row_latch & 0x1f) && !s->kbd_mask;
1982
1983 case 0x24: /* GPIO_INT */
1984 ret = s->ints;
1985 s->ints &= s->mask;
1986 if (ret)
1987 qemu_irq_lower(s->irq);
1988 return ret;
1989
1990 case 0x28: /* KBD_MASKIT */
1991 return s->kbd_mask;
1992
1993 case 0x2c: /* GPIO_MASKIT */
1994 return s->mask;
1995
1996 case 0x30: /* GPIO_DEBOUNCING_REG */
1997 return s->debounce;
1998
1999 case 0x34: /* GPIO_LATCH_REG */
2000 return s->latch;
2001 }
2002
2003 OMAP_BAD_REG(addr);
2004 return 0;
2005 }
2006
2007 static void omap_mpuio_write(void *opaque, hwaddr addr,
2008 uint64_t value, unsigned size)
2009 {
2010 struct omap_mpuio_s *s = opaque;
2011 int offset = addr & OMAP_MPUI_REG_MASK;
2012 uint16_t diff;
2013 int ln;
2014
2015 if (size != 2) {
2016 omap_badwidth_write16(opaque, addr, value);
2017 return;
2018 }
2019
2020 switch (offset) {
2021 case 0x04: /* OUTPUT_REG */
2022 diff = (s->outputs ^ value) & ~s->dir;
2023 s->outputs = value;
2024 while ((ln = ctz32(diff)) != 32) {
2025 if (s->handler[ln])
2026 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2027 diff &= ~(1 << ln);
2028 }
2029 break;
2030
2031 case 0x08: /* IO_CNTL */
2032 diff = s->outputs & (s->dir ^ value);
2033 s->dir = value;
2034
2035 value = s->outputs & ~s->dir;
2036 while ((ln = ctz32(diff)) != 32) {
2037 if (s->handler[ln])
2038 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2039 diff &= ~(1 << ln);
2040 }
2041 break;
2042
2043 case 0x14: /* KBC_REG */
2044 s->cols = value;
2045 omap_mpuio_kbd_update(s);
2046 break;
2047
2048 case 0x18: /* GPIO_EVENT_MODE_REG */
2049 s->event = value & 0x1f;
2050 break;
2051
2052 case 0x1c: /* GPIO_INT_EDGE_REG */
2053 s->edge = value;
2054 break;
2055
2056 case 0x28: /* KBD_MASKIT */
2057 s->kbd_mask = value & 1;
2058 omap_mpuio_kbd_update(s);
2059 break;
2060
2061 case 0x2c: /* GPIO_MASKIT */
2062 s->mask = value;
2063 break;
2064
2065 case 0x30: /* GPIO_DEBOUNCING_REG */
2066 s->debounce = value & 0x1ff;
2067 break;
2068
2069 case 0x00: /* INPUT_LATCH */
2070 case 0x10: /* KBR_LATCH */
2071 case 0x20: /* KBD_INT */
2072 case 0x24: /* GPIO_INT */
2073 case 0x34: /* GPIO_LATCH_REG */
2074 OMAP_RO_REG(addr);
2075 return;
2076
2077 default:
2078 OMAP_BAD_REG(addr);
2079 return;
2080 }
2081 }
2082
2083 static const MemoryRegionOps omap_mpuio_ops = {
2084 .read = omap_mpuio_read,
2085 .write = omap_mpuio_write,
2086 .endianness = DEVICE_NATIVE_ENDIAN,
2087 };
2088
2089 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2090 {
2091 s->inputs = 0;
2092 s->outputs = 0;
2093 s->dir = ~0;
2094 s->event = 0;
2095 s->edge = 0;
2096 s->kbd_mask = 0;
2097 s->mask = 0;
2098 s->debounce = 0;
2099 s->latch = 0;
2100 s->ints = 0;
2101 s->row_latch = 0x1f;
2102 s->clk = 1;
2103 }
2104
2105 static void omap_mpuio_onoff(void *opaque, int line, int on)
2106 {
2107 struct omap_mpuio_s *s = opaque;
2108
2109 s->clk = on;
2110 if (on)
2111 omap_mpuio_kbd_update(s);
2112 }
2113
2114 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
2115 hwaddr base,
2116 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2117 omap_clk clk)
2118 {
2119 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
2120
2121 s->irq = gpio_int;
2122 s->kbd_irq = kbd_int;
2123 s->wakeup = wakeup;
2124 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2125 omap_mpuio_reset(s);
2126
2127 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
2128 "omap-mpuio", 0x800);
2129 memory_region_add_subregion(memory, base, &s->iomem);
2130
2131 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0));
2132
2133 return s;
2134 }
2135
2136 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2137 {
2138 return s->in;
2139 }
2140
2141 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2142 {
2143 if (line >= 16 || line < 0)
2144 hw_error("%s: No GPIO line %i\n", __func__, line);
2145 s->handler[line] = handler;
2146 }
2147
2148 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2149 {
2150 if (row >= 5 || row < 0)
2151 hw_error("%s: No key %i-%i\n", __func__, col, row);
2152
2153 if (down)
2154 s->buttons[row] |= 1 << col;
2155 else
2156 s->buttons[row] &= ~(1 << col);
2157
2158 omap_mpuio_kbd_update(s);
2159 }
2160
2161 /* MicroWire Interface */
2162 struct omap_uwire_s {
2163 MemoryRegion iomem;
2164 qemu_irq txirq;
2165 qemu_irq rxirq;
2166 qemu_irq txdrq;
2167
2168 uint16_t txbuf;
2169 uint16_t rxbuf;
2170 uint16_t control;
2171 uint16_t setup[5];
2172
2173 uWireSlave *chip[4];
2174 };
2175
2176 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2177 {
2178 int chipselect = (s->control >> 10) & 3; /* INDEX */
2179 uWireSlave *slave = s->chip[chipselect];
2180
2181 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2182 if (s->control & (1 << 12)) /* CS_CMD */
2183 if (slave && slave->send)
2184 slave->send(slave->opaque,
2185 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2186 s->control &= ~(1 << 14); /* CSRB */
2187 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2188 * a DRQ. When is the level IRQ supposed to be reset? */
2189 }
2190
2191 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2192 if (s->control & (1 << 12)) /* CS_CMD */
2193 if (slave && slave->receive)
2194 s->rxbuf = slave->receive(slave->opaque);
2195 s->control |= 1 << 15; /* RDRB */
2196 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2197 * a DRQ. When is the level IRQ supposed to be reset? */
2198 }
2199 }
2200
2201 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
2202 {
2203 struct omap_uwire_s *s = opaque;
2204 int offset = addr & OMAP_MPUI_REG_MASK;
2205
2206 if (size != 2) {
2207 return omap_badwidth_read16(opaque, addr);
2208 }
2209
2210 switch (offset) {
2211 case 0x00: /* RDR */
2212 s->control &= ~(1 << 15); /* RDRB */
2213 return s->rxbuf;
2214
2215 case 0x04: /* CSR */
2216 return s->control;
2217
2218 case 0x08: /* SR1 */
2219 return s->setup[0];
2220 case 0x0c: /* SR2 */
2221 return s->setup[1];
2222 case 0x10: /* SR3 */
2223 return s->setup[2];
2224 case 0x14: /* SR4 */
2225 return s->setup[3];
2226 case 0x18: /* SR5 */
2227 return s->setup[4];
2228 }
2229
2230 OMAP_BAD_REG(addr);
2231 return 0;
2232 }
2233
2234 static void omap_uwire_write(void *opaque, hwaddr addr,
2235 uint64_t value, unsigned size)
2236 {
2237 struct omap_uwire_s *s = opaque;
2238 int offset = addr & OMAP_MPUI_REG_MASK;
2239
2240 if (size != 2) {
2241 omap_badwidth_write16(opaque, addr, value);
2242 return;
2243 }
2244
2245 switch (offset) {
2246 case 0x00: /* TDR */
2247 s->txbuf = value; /* TD */
2248 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2249 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2250 (s->control & (1 << 12)))) { /* CS_CMD */
2251 s->control |= 1 << 14; /* CSRB */
2252 omap_uwire_transfer_start(s);
2253 }
2254 break;
2255
2256 case 0x04: /* CSR */
2257 s->control = value & 0x1fff;
2258 if (value & (1 << 13)) /* START */
2259 omap_uwire_transfer_start(s);
2260 break;
2261
2262 case 0x08: /* SR1 */
2263 s->setup[0] = value & 0x003f;
2264 break;
2265
2266 case 0x0c: /* SR2 */
2267 s->setup[1] = value & 0x0fc0;
2268 break;
2269
2270 case 0x10: /* SR3 */
2271 s->setup[2] = value & 0x0003;
2272 break;
2273
2274 case 0x14: /* SR4 */
2275 s->setup[3] = value & 0x0001;
2276 break;
2277
2278 case 0x18: /* SR5 */
2279 s->setup[4] = value & 0x000f;
2280 break;
2281
2282 default:
2283 OMAP_BAD_REG(addr);
2284 return;
2285 }
2286 }
2287
2288 static const MemoryRegionOps omap_uwire_ops = {
2289 .read = omap_uwire_read,
2290 .write = omap_uwire_write,
2291 .endianness = DEVICE_NATIVE_ENDIAN,
2292 };
2293
2294 static void omap_uwire_reset(struct omap_uwire_s *s)
2295 {
2296 s->control = 0;
2297 s->setup[0] = 0;
2298 s->setup[1] = 0;
2299 s->setup[2] = 0;
2300 s->setup[3] = 0;
2301 s->setup[4] = 0;
2302 }
2303
2304 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
2305 hwaddr base,
2306 qemu_irq txirq, qemu_irq rxirq,
2307 qemu_irq dma,
2308 omap_clk clk)
2309 {
2310 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
2311
2312 s->txirq = txirq;
2313 s->rxirq = rxirq;
2314 s->txdrq = dma;
2315 omap_uwire_reset(s);
2316
2317 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
2318 memory_region_add_subregion(system_memory, base, &s->iomem);
2319
2320 return s;
2321 }
2322
2323 void omap_uwire_attach(struct omap_uwire_s *s,
2324 uWireSlave *slave, int chipselect)
2325 {
2326 if (chipselect < 0 || chipselect > 3) {
2327 error_report("%s: Bad chipselect %i", __func__, chipselect);
2328 exit(-1);
2329 }
2330
2331 s->chip[chipselect] = slave;
2332 }
2333
2334 /* Pseudonoise Pulse-Width Light Modulator */
2335 struct omap_pwl_s {
2336 MemoryRegion iomem;
2337 uint8_t output;
2338 uint8_t level;
2339 uint8_t enable;
2340 int clk;
2341 };
2342
2343 static void omap_pwl_update(struct omap_pwl_s *s)
2344 {
2345 int output = (s->clk && s->enable) ? s->level : 0;
2346
2347 if (output != s->output) {
2348 s->output = output;
2349 printf("%s: Backlight now at %i/256\n", __func__, output);
2350 }
2351 }
2352
2353 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
2354 {
2355 struct omap_pwl_s *s = opaque;
2356 int offset = addr & OMAP_MPUI_REG_MASK;
2357
2358 if (size != 1) {
2359 return omap_badwidth_read8(opaque, addr);
2360 }
2361
2362 switch (offset) {
2363 case 0x00: /* PWL_LEVEL */
2364 return s->level;
2365 case 0x04: /* PWL_CTRL */
2366 return s->enable;
2367 }
2368 OMAP_BAD_REG(addr);
2369 return 0;
2370 }
2371
2372 static void omap_pwl_write(void *opaque, hwaddr addr,
2373 uint64_t value, unsigned size)
2374 {
2375 struct omap_pwl_s *s = opaque;
2376 int offset = addr & OMAP_MPUI_REG_MASK;
2377
2378 if (size != 1) {
2379 omap_badwidth_write8(opaque, addr, value);
2380 return;
2381 }
2382
2383 switch (offset) {
2384 case 0x00: /* PWL_LEVEL */
2385 s->level = value;
2386 omap_pwl_update(s);
2387 break;
2388 case 0x04: /* PWL_CTRL */
2389 s->enable = value & 1;
2390 omap_pwl_update(s);
2391 break;
2392 default:
2393 OMAP_BAD_REG(addr);
2394 return;
2395 }
2396 }
2397
2398 static const MemoryRegionOps omap_pwl_ops = {
2399 .read = omap_pwl_read,
2400 .write = omap_pwl_write,
2401 .endianness = DEVICE_NATIVE_ENDIAN,
2402 };
2403
2404 static void omap_pwl_reset(struct omap_pwl_s *s)
2405 {
2406 s->output = 0;
2407 s->level = 0;
2408 s->enable = 0;
2409 s->clk = 1;
2410 omap_pwl_update(s);
2411 }
2412
2413 static void omap_pwl_clk_update(void *opaque, int line, int on)
2414 {
2415 struct omap_pwl_s *s = opaque;
2416
2417 s->clk = on;
2418 omap_pwl_update(s);
2419 }
2420
2421 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
2422 hwaddr base,
2423 omap_clk clk)
2424 {
2425 struct omap_pwl_s *s = g_malloc0(sizeof(*s));
2426
2427 omap_pwl_reset(s);
2428
2429 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
2430 "omap-pwl", 0x800);
2431 memory_region_add_subregion(system_memory, base, &s->iomem);
2432
2433 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0));
2434 return s;
2435 }
2436
2437 /* Pulse-Width Tone module */
2438 struct omap_pwt_s {
2439 MemoryRegion iomem;
2440 uint8_t frc;
2441 uint8_t vrc;
2442 uint8_t gcr;
2443 omap_clk clk;
2444 };
2445
2446 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
2447 {
2448 struct omap_pwt_s *s = opaque;
2449 int offset = addr & OMAP_MPUI_REG_MASK;
2450
2451 if (size != 1) {
2452 return omap_badwidth_read8(opaque, addr);
2453 }
2454
2455 switch (offset) {
2456 case 0x00: /* FRC */
2457 return s->frc;
2458 case 0x04: /* VCR */
2459 return s->vrc;
2460 case 0x08: /* GCR */
2461 return s->gcr;
2462 }
2463 OMAP_BAD_REG(addr);
2464 return 0;
2465 }
2466
2467 static void omap_pwt_write(void *opaque, hwaddr addr,
2468 uint64_t value, unsigned size)
2469 {
2470 struct omap_pwt_s *s = opaque;
2471 int offset = addr & OMAP_MPUI_REG_MASK;
2472
2473 if (size != 1) {
2474 omap_badwidth_write8(opaque, addr, value);
2475 return;
2476 }
2477
2478 switch (offset) {
2479 case 0x00: /* FRC */
2480 s->frc = value & 0x3f;
2481 break;
2482 case 0x04: /* VRC */
2483 if ((value ^ s->vrc) & 1) {
2484 if (value & 1)
2485 printf("%s: %iHz buzz on\n", __func__, (int)
2486 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2487 ((omap_clk_getrate(s->clk) >> 3) /
2488 /* Pre-multiplexer divider */
2489 ((s->gcr & 2) ? 1 : 154) /
2490 /* Octave multiplexer */
2491 (2 << (value & 3)) *
2492 /* 101/107 divider */
2493 ((value & (1 << 2)) ? 101 : 107) *
2494 /* 49/55 divider */
2495 ((value & (1 << 3)) ? 49 : 55) *
2496 /* 50/63 divider */
2497 ((value & (1 << 4)) ? 50 : 63) *
2498 /* 80/127 divider */
2499 ((value & (1 << 5)) ? 80 : 127) /
2500 (107 * 55 * 63 * 127)));
2501 else
2502 printf("%s: silence!\n", __func__);
2503 }
2504 s->vrc = value & 0x7f;
2505 break;
2506 case 0x08: /* GCR */
2507 s->gcr = value & 3;
2508 break;
2509 default:
2510 OMAP_BAD_REG(addr);
2511 return;
2512 }
2513 }
2514
2515 static const MemoryRegionOps omap_pwt_ops = {
2516 .read =omap_pwt_read,
2517 .write = omap_pwt_write,
2518 .endianness = DEVICE_NATIVE_ENDIAN,
2519 };
2520
2521 static void omap_pwt_reset(struct omap_pwt_s *s)
2522 {
2523 s->frc = 0;
2524 s->vrc = 0;
2525 s->gcr = 0;
2526 }
2527
2528 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
2529 hwaddr base,
2530 omap_clk clk)
2531 {
2532 struct omap_pwt_s *s = g_malloc0(sizeof(*s));
2533 s->clk = clk;
2534 omap_pwt_reset(s);
2535
2536 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
2537 "omap-pwt", 0x800);
2538 memory_region_add_subregion(system_memory, base, &s->iomem);
2539 return s;
2540 }
2541
2542 /* Real-time Clock module */
2543 struct omap_rtc_s {
2544 MemoryRegion iomem;
2545 qemu_irq irq;
2546 qemu_irq alarm;
2547 QEMUTimer *clk;
2548
2549 uint8_t interrupts;
2550 uint8_t status;
2551 int16_t comp_reg;
2552 int running;
2553 int pm_am;
2554 int auto_comp;
2555 int round;
2556 struct tm alarm_tm;
2557 time_t alarm_ti;
2558
2559 struct tm current_tm;
2560 time_t ti;
2561 uint64_t tick;
2562 };
2563
2564 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2565 {
2566 /* s->alarm is level-triggered */
2567 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2568 }
2569
2570 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2571 {
2572 s->alarm_ti = mktimegm(&s->alarm_tm);
2573 if (s->alarm_ti == -1)
2574 printf("%s: conversion failed\n", __func__);
2575 }
2576
2577 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
2578 {
2579 struct omap_rtc_s *s = opaque;
2580 int offset = addr & OMAP_MPUI_REG_MASK;
2581 uint8_t i;
2582
2583 if (size != 1) {
2584 return omap_badwidth_read8(opaque, addr);
2585 }
2586
2587 switch (offset) {
2588 case 0x00: /* SECONDS_REG */
2589 return to_bcd(s->current_tm.tm_sec);
2590
2591 case 0x04: /* MINUTES_REG */
2592 return to_bcd(s->current_tm.tm_min);
2593
2594 case 0x08: /* HOURS_REG */
2595 if (s->pm_am)
2596 return ((s->current_tm.tm_hour > 11) << 7) |
2597 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
2598 else
2599 return to_bcd(s->current_tm.tm_hour);
2600
2601 case 0x0c: /* DAYS_REG */
2602 return to_bcd(s->current_tm.tm_mday);
2603
2604 case 0x10: /* MONTHS_REG */
2605 return to_bcd(s->current_tm.tm_mon + 1);
2606
2607 case 0x14: /* YEARS_REG */
2608 return to_bcd(s->current_tm.tm_year % 100);
2609
2610 case 0x18: /* WEEK_REG */
2611 return s->current_tm.tm_wday;
2612
2613 case 0x20: /* ALARM_SECONDS_REG */
2614 return to_bcd(s->alarm_tm.tm_sec);
2615
2616 case 0x24: /* ALARM_MINUTES_REG */
2617 return to_bcd(s->alarm_tm.tm_min);
2618
2619 case 0x28: /* ALARM_HOURS_REG */
2620 if (s->pm_am)
2621 return ((s->alarm_tm.tm_hour > 11) << 7) |
2622 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
2623 else
2624 return to_bcd(s->alarm_tm.tm_hour);
2625
2626 case 0x2c: /* ALARM_DAYS_REG */
2627 return to_bcd(s->alarm_tm.tm_mday);
2628
2629 case 0x30: /* ALARM_MONTHS_REG */
2630 return to_bcd(s->alarm_tm.tm_mon + 1);
2631
2632 case 0x34: /* ALARM_YEARS_REG */
2633 return to_bcd(s->alarm_tm.tm_year % 100);
2634
2635 case 0x40: /* RTC_CTRL_REG */
2636 return (s->pm_am << 3) | (s->auto_comp << 2) |
2637 (s->round << 1) | s->running;
2638
2639 case 0x44: /* RTC_STATUS_REG */
2640 i = s->status;
2641 s->status &= ~0x3d;
2642 return i;
2643
2644 case 0x48: /* RTC_INTERRUPTS_REG */
2645 return s->interrupts;
2646
2647 case 0x4c: /* RTC_COMP_LSB_REG */
2648 return ((uint16_t) s->comp_reg) & 0xff;
2649
2650 case 0x50: /* RTC_COMP_MSB_REG */
2651 return ((uint16_t) s->comp_reg) >> 8;
2652 }
2653
2654 OMAP_BAD_REG(addr);
2655 return 0;
2656 }
2657
2658 static void omap_rtc_write(void *opaque, hwaddr addr,
2659 uint64_t value, unsigned size)
2660 {
2661 struct omap_rtc_s *s = opaque;
2662 int offset = addr & OMAP_MPUI_REG_MASK;
2663 struct tm new_tm;
2664 time_t ti[2];
2665
2666 if (size != 1) {
2667 omap_badwidth_write8(opaque, addr, value);
2668 return;
2669 }
2670
2671 switch (offset) {
2672 case 0x00: /* SECONDS_REG */
2673 #ifdef ALMDEBUG
2674 printf("RTC SEC_REG <-- %02x\n", value);
2675 #endif
2676 s->ti -= s->current_tm.tm_sec;
2677 s->ti += from_bcd(value);
2678 return;
2679
2680 case 0x04: /* MINUTES_REG */
2681 #ifdef ALMDEBUG
2682 printf("RTC MIN_REG <-- %02x\n", value);
2683 #endif
2684 s->ti -= s->current_tm.tm_min * 60;
2685 s->ti += from_bcd(value) * 60;
2686 return;
2687
2688 case 0x08: /* HOURS_REG */
2689 #ifdef ALMDEBUG
2690 printf("RTC HRS_REG <-- %02x\n", value);
2691 #endif
2692 s->ti -= s->current_tm.tm_hour * 3600;
2693 if (s->pm_am) {
2694 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
2695 s->ti += ((value >> 7) & 1) * 43200;
2696 } else
2697 s->ti += from_bcd(value & 0x3f) * 3600;
2698 return;
2699
2700 case 0x0c: /* DAYS_REG */
2701 #ifdef ALMDEBUG
2702 printf("RTC DAY_REG <-- %02x\n", value);
2703 #endif
2704 s->ti -= s->current_tm.tm_mday * 86400;
2705 s->ti += from_bcd(value) * 86400;
2706 return;
2707
2708 case 0x10: /* MONTHS_REG */
2709 #ifdef ALMDEBUG
2710 printf("RTC MTH_REG <-- %02x\n", value);
2711 #endif
2712 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2713 new_tm.tm_mon = from_bcd(value);
2714 ti[0] = mktimegm(&s->current_tm);
2715 ti[1] = mktimegm(&new_tm);
2716
2717 if (ti[0] != -1 && ti[1] != -1) {
2718 s->ti -= ti[0];
2719 s->ti += ti[1];
2720 } else {
2721 /* A less accurate version */
2722 s->ti -= s->current_tm.tm_mon * 2592000;
2723 s->ti += from_bcd(value) * 2592000;
2724 }
2725 return;
2726
2727 case 0x14: /* YEARS_REG */
2728 #ifdef ALMDEBUG
2729 printf("RTC YRS_REG <-- %02x\n", value);
2730 #endif
2731 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2732 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
2733 ti[0] = mktimegm(&s->current_tm);
2734 ti[1] = mktimegm(&new_tm);
2735
2736 if (ti[0] != -1 && ti[1] != -1) {
2737 s->ti -= ti[0];
2738 s->ti += ti[1];
2739 } else {
2740 /* A less accurate version */
2741 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
2742 s->ti += (time_t)from_bcd(value) * 31536000;
2743 }
2744 return;
2745
2746 case 0x18: /* WEEK_REG */
2747 return; /* Ignored */
2748
2749 case 0x20: /* ALARM_SECONDS_REG */
2750 #ifdef ALMDEBUG
2751 printf("ALM SEC_REG <-- %02x\n", value);
2752 #endif
2753 s->alarm_tm.tm_sec = from_bcd(value);
2754 omap_rtc_alarm_update(s);
2755 return;
2756
2757 case 0x24: /* ALARM_MINUTES_REG */
2758 #ifdef ALMDEBUG
2759 printf("ALM MIN_REG <-- %02x\n", value);
2760 #endif
2761 s->alarm_tm.tm_min = from_bcd(value);
2762 omap_rtc_alarm_update(s);
2763 return;
2764
2765 case 0x28: /* ALARM_HOURS_REG */
2766 #ifdef ALMDEBUG
2767 printf("ALM HRS_REG <-- %02x\n", value);
2768 #endif
2769 if (s->pm_am)
2770 s->alarm_tm.tm_hour =
2771 ((from_bcd(value & 0x3f)) % 12) +
2772 ((value >> 7) & 1) * 12;
2773 else
2774 s->alarm_tm.tm_hour = from_bcd(value);
2775 omap_rtc_alarm_update(s);
2776 return;
2777
2778 case 0x2c: /* ALARM_DAYS_REG */
2779 #ifdef ALMDEBUG
2780 printf("ALM DAY_REG <-- %02x\n", value);
2781 #endif
2782 s->alarm_tm.tm_mday = from_bcd(value);
2783 omap_rtc_alarm_update(s);
2784 return;
2785
2786 case 0x30: /* ALARM_MONTHS_REG */
2787 #ifdef ALMDEBUG
2788 printf("ALM MON_REG <-- %02x\n", value);
2789 #endif
2790 s->alarm_tm.tm_mon = from_bcd(value);
2791 omap_rtc_alarm_update(s);
2792 return;
2793
2794 case 0x34: /* ALARM_YEARS_REG */
2795 #ifdef ALMDEBUG
2796 printf("ALM YRS_REG <-- %02x\n", value);
2797 #endif
2798 s->alarm_tm.tm_year = from_bcd(value);
2799 omap_rtc_alarm_update(s);
2800 return;
2801
2802 case 0x40: /* RTC_CTRL_REG */
2803 #ifdef ALMDEBUG
2804 printf("RTC CONTROL <-- %02x\n", value);
2805 #endif
2806 s->pm_am = (value >> 3) & 1;
2807 s->auto_comp = (value >> 2) & 1;
2808 s->round = (value >> 1) & 1;
2809 s->running = value & 1;
2810 s->status &= 0xfd;
2811 s->status |= s->running << 1;
2812 return;
2813
2814 case 0x44: /* RTC_STATUS_REG */
2815 #ifdef ALMDEBUG
2816 printf("RTC STATUSL <-- %02x\n", value);
2817 #endif
2818 s->status &= ~((value & 0xc0) ^ 0x80);
2819 omap_rtc_interrupts_update(s);
2820 return;
2821
2822 case 0x48: /* RTC_INTERRUPTS_REG */
2823 #ifdef ALMDEBUG
2824 printf("RTC INTRS <-- %02x\n", value);
2825 #endif
2826 s->interrupts = value;
2827 return;
2828
2829 case 0x4c: /* RTC_COMP_LSB_REG */
2830 #ifdef ALMDEBUG
2831 printf("RTC COMPLSB <-- %02x\n", value);
2832 #endif
2833 s->comp_reg &= 0xff00;
2834 s->comp_reg |= 0x00ff & value;
2835 return;
2836
2837 case 0x50: /* RTC_COMP_MSB_REG */
2838 #ifdef ALMDEBUG
2839 printf("RTC COMPMSB <-- %02x\n", value);
2840 #endif
2841 s->comp_reg &= 0x00ff;
2842 s->comp_reg |= 0xff00 & (value << 8);
2843 return;
2844
2845 default:
2846 OMAP_BAD_REG(addr);
2847 return;
2848 }
2849 }
2850
2851 static const MemoryRegionOps omap_rtc_ops = {
2852 .read = omap_rtc_read,
2853 .write = omap_rtc_write,
2854 .endianness = DEVICE_NATIVE_ENDIAN,
2855 };
2856
2857 static void omap_rtc_tick(void *opaque)
2858 {
2859 struct omap_rtc_s *s = opaque;
2860
2861 if (s->round) {
2862 /* Round to nearest full minute. */
2863 if (s->current_tm.tm_sec < 30)
2864 s->ti -= s->current_tm.tm_sec;
2865 else
2866 s->ti += 60 - s->current_tm.tm_sec;
2867
2868 s->round = 0;
2869 }
2870
2871 localtime_r(&s->ti, &s->current_tm);
2872
2873 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2874 s->status |= 0x40;
2875 omap_rtc_interrupts_update(s);
2876 }
2877
2878 if (s->interrupts & 0x04)
2879 switch (s->interrupts & 3) {
2880 case 0:
2881 s->status |= 0x04;
2882 qemu_irq_pulse(s->irq);
2883 break;
2884 case 1:
2885 if (s->current_tm.tm_sec)
2886 break;
2887 s->status |= 0x08;
2888 qemu_irq_pulse(s->irq);
2889 break;
2890 case 2:
2891 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2892 break;
2893 s->status |= 0x10;
2894 qemu_irq_pulse(s->irq);
2895 break;
2896 case 3:
2897 if (s->current_tm.tm_sec ||
2898 s->current_tm.tm_min || s->current_tm.tm_hour)
2899 break;
2900 s->status |= 0x20;
2901 qemu_irq_pulse(s->irq);
2902 break;
2903 }
2904
2905 /* Move on */
2906 if (s->running)
2907 s->ti ++;
2908 s->tick += 1000;
2909
2910 /*
2911 * Every full hour add a rough approximation of the compensation
2912 * register to the 32kHz Timer (which drives the RTC) value.
2913 */
2914 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2915 s->tick += s->comp_reg * 1000 / 32768;
2916
2917 timer_mod(s->clk, s->tick);
2918 }
2919
2920 static void omap_rtc_reset(struct omap_rtc_s *s)
2921 {
2922 struct tm tm;
2923
2924 s->interrupts = 0;
2925 s->comp_reg = 0;
2926 s->running = 0;
2927 s->pm_am = 0;
2928 s->auto_comp = 0;
2929 s->round = 0;
2930 s->tick = qemu_clock_get_ms(rtc_clock);
2931 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2932 s->alarm_tm.tm_mday = 0x01;
2933 s->status = 1 << 7;
2934 qemu_get_timedate(&tm, 0);
2935 s->ti = mktimegm(&tm);
2936
2937 omap_rtc_alarm_update(s);
2938 omap_rtc_tick(s);
2939 }
2940
2941 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
2942 hwaddr base,
2943 qemu_irq timerirq, qemu_irq alarmirq,
2944 omap_clk clk)
2945 {
2946 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
2947
2948 s->irq = timerirq;
2949 s->alarm = alarmirq;
2950 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
2951
2952 omap_rtc_reset(s);
2953
2954 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
2955 "omap-rtc", 0x800);
2956 memory_region_add_subregion(system_memory, base, &s->iomem);
2957
2958 return s;
2959 }
2960
2961 /* Multi-channel Buffered Serial Port interfaces */
2962 struct omap_mcbsp_s {
2963 MemoryRegion iomem;
2964 qemu_irq txirq;
2965 qemu_irq rxirq;
2966 qemu_irq txdrq;
2967 qemu_irq rxdrq;
2968
2969 uint16_t spcr[2];
2970 uint16_t rcr[2];
2971 uint16_t xcr[2];
2972 uint16_t srgr[2];
2973 uint16_t mcr[2];
2974 uint16_t pcr;
2975 uint16_t rcer[8];
2976 uint16_t xcer[8];
2977 int tx_rate;
2978 int rx_rate;
2979 int tx_req;
2980 int rx_req;
2981
2982 I2SCodec *codec;
2983 QEMUTimer *source_timer;
2984 QEMUTimer *sink_timer;
2985 };
2986
2987 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2988 {
2989 int irq;
2990
2991 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2992 case 0:
2993 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2994 break;
2995 case 3:
2996 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2997 break;
2998 default:
2999 irq = 0;
3000 break;
3001 }
3002
3003 if (irq)
3004 qemu_irq_pulse(s->rxirq);
3005
3006 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3007 case 0:
3008 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3009 break;
3010 case 3:
3011 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3012 break;
3013 default:
3014 irq = 0;
3015 break;
3016 }
3017
3018 if (irq)
3019 qemu_irq_pulse(s->txirq);
3020 }
3021
3022 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
3023 {
3024 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3025 s->spcr[0] |= 1 << 2; /* RFULL */
3026 s->spcr[0] |= 1 << 1; /* RRDY */
3027 qemu_irq_raise(s->rxdrq);
3028 omap_mcbsp_intr_update(s);
3029 }
3030
3031 static void omap_mcbsp_source_tick(void *opaque)
3032 {
3033 struct omap_mcbsp_s *s = opaque;
3034 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3035
3036 if (!s->rx_rate)
3037 return;
3038 if (s->rx_req)
3039 printf("%s: Rx FIFO overrun\n", __func__);
3040
3041 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
3042
3043 omap_mcbsp_rx_newdata(s);
3044 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3045 NANOSECONDS_PER_SECOND);
3046 }
3047
3048 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3049 {
3050 if (!s->codec || !s->codec->rts)
3051 omap_mcbsp_source_tick(s);
3052 else if (s->codec->in.len) {
3053 s->rx_req = s->codec->in.len;
3054 omap_mcbsp_rx_newdata(s);
3055 }
3056 }
3057
3058 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
3059 {
3060 timer_del(s->source_timer);
3061 }
3062
3063 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
3064 {
3065 s->spcr[0] &= ~(1 << 1); /* RRDY */
3066 qemu_irq_lower(s->rxdrq);
3067 omap_mcbsp_intr_update(s);
3068 }
3069
3070 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3071 {
3072 s->spcr[1] |= 1 << 1; /* XRDY */
3073 qemu_irq_raise(s->txdrq);
3074 omap_mcbsp_intr_update(s);
3075 }
3076
3077 static void omap_mcbsp_sink_tick(void *opaque)
3078 {
3079 struct omap_mcbsp_s *s = opaque;
3080 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3081
3082 if (!s->tx_rate)
3083 return;
3084 if (s->tx_req)
3085 printf("%s: Tx FIFO underrun\n", __func__);
3086
3087 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3088
3089 omap_mcbsp_tx_newdata(s);
3090 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3091 NANOSECONDS_PER_SECOND);
3092 }
3093
3094 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3095 {
3096 if (!s->codec || !s->codec->cts)
3097 omap_mcbsp_sink_tick(s);
3098 else if (s->codec->out.size) {
3099 s->tx_req = s->codec->out.size;
3100 omap_mcbsp_tx_newdata(s);
3101 }
3102 }
3103
3104 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3105 {
3106 s->spcr[1] &= ~(1 << 1); /* XRDY */
3107 qemu_irq_lower(s->txdrq);
3108 omap_mcbsp_intr_update(s);
3109 if (s->codec && s->codec->cts)
3110 s->codec->tx_swallow(s->codec->opaque);
3111 }
3112
3113 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3114 {
3115 s->tx_req = 0;
3116 omap_mcbsp_tx_done(s);
3117 timer_del(s->sink_timer);
3118 }
3119
3120 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3121 {
3122 int prev_rx_rate, prev_tx_rate;
3123 int rx_rate = 0, tx_rate = 0;
3124 int cpu_rate = 1500000; /* XXX */
3125
3126 /* TODO: check CLKSTP bit */
3127 if (s->spcr[1] & (1 << 6)) { /* GRST */
3128 if (s->spcr[0] & (1 << 0)) { /* RRST */
3129 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3130 (s->pcr & (1 << 8))) { /* CLKRM */
3131 if (~s->pcr & (1 << 7)) /* SCLKME */
3132 rx_rate = cpu_rate /
3133 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3134 } else
3135 if (s->codec)
3136 rx_rate = s->codec->rx_rate;
3137 }
3138
3139 if (s->spcr[1] & (1 << 0)) { /* XRST */
3140 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3141 (s->pcr & (1 << 9))) { /* CLKXM */
3142 if (~s->pcr & (1 << 7)) /* SCLKME */
3143 tx_rate = cpu_rate /
3144 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3145 } else
3146 if (s->codec)
3147 tx_rate = s->codec->tx_rate;
3148 }
3149 }
3150 prev_tx_rate = s->tx_rate;
3151 prev_rx_rate = s->rx_rate;
3152 s->tx_rate = tx_rate;
3153 s->rx_rate = rx_rate;
3154
3155 if (s->codec)
3156 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3157
3158 if (!prev_tx_rate && tx_rate)
3159 omap_mcbsp_tx_start(s);
3160 else if (s->tx_rate && !tx_rate)
3161 omap_mcbsp_tx_stop(s);
3162
3163 if (!prev_rx_rate && rx_rate)
3164 omap_mcbsp_rx_start(s);
3165 else if (prev_tx_rate && !tx_rate)
3166 omap_mcbsp_rx_stop(s);
3167 }
3168
3169 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
3170 unsigned size)
3171 {
3172 struct omap_mcbsp_s *s = opaque;
3173 int offset = addr & OMAP_MPUI_REG_MASK;
3174 uint16_t ret;
3175
3176 if (size != 2) {
3177 return omap_badwidth_read16(opaque, addr);
3178 }
3179
3180 switch (offset) {
3181 case 0x00: /* DRR2 */
3182 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3183 return 0x0000;
3184 /* Fall through. */
3185 case 0x02: /* DRR1 */
3186 if (s->rx_req < 2) {
3187 printf("%s: Rx FIFO underrun\n", __func__);
3188 omap_mcbsp_rx_done(s);
3189 } else {
3190 s->tx_req -= 2;
3191 if (s->codec && s->codec->in.len >= 2) {
3192 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3193 ret |= s->codec->in.fifo[s->codec->in.start ++];
3194 s->codec->in.len -= 2;
3195 } else
3196 ret = 0x0000;
3197 if (!s->tx_req)
3198 omap_mcbsp_rx_done(s);
3199 return ret;
3200 }
3201 return 0x0000;
3202
3203 case 0x04: /* DXR2 */
3204 case 0x06: /* DXR1 */
3205 return 0x0000;
3206
3207 case 0x08: /* SPCR2 */
3208 return s->spcr[1];
3209 case 0x0a: /* SPCR1 */
3210 return s->spcr[0];
3211 case 0x0c: /* RCR2 */
3212 return s->rcr[1];
3213 case 0x0e: /* RCR1 */
3214 return s->rcr[0];
3215 case 0x10: /* XCR2 */
3216 return s->xcr[1];
3217 case 0x12: /* XCR1 */
3218 return s->xcr[0];
3219 case 0x14: /* SRGR2 */
3220 return s->srgr[1];
3221 case 0x16: /* SRGR1 */
3222 return s->srgr[0];
3223 case 0x18: /* MCR2 */
3224 return s->mcr[1];
3225 case 0x1a: /* MCR1 */
3226 return s->mcr[0];
3227 case 0x1c: /* RCERA */
3228 return s->rcer[0];
3229 case 0x1e: /* RCERB */
3230 return s->rcer[1];
3231 case 0x20: /* XCERA */
3232 return s->xcer[0];
3233 case 0x22: /* XCERB */
3234 return s->xcer[1];
3235 case 0x24: /* PCR0 */
3236 return s->pcr;
3237 case 0x26: /* RCERC */
3238 return s->rcer[2];
3239 case 0x28: /* RCERD */
3240 return s->rcer[3];
3241 case 0x2a: /* XCERC */
3242 return s->xcer[2];
3243 case 0x2c: /* XCERD */
3244 return s->xcer[3];
3245 case 0x2e: /* RCERE */
3246 return s->rcer[4];
3247 case 0x30: /* RCERF */
3248 return s->rcer[5];
3249 case 0x32: /* XCERE */
3250 return s->xcer[4];
3251 case 0x34: /* XCERF */
3252 return s->xcer[5];
3253 case 0x36: /* RCERG */
3254 return s->rcer[6];
3255 case 0x38: /* RCERH */
3256 return s->rcer[7];
3257 case 0x3a: /* XCERG */
3258 return s->xcer[6];
3259 case 0x3c: /* XCERH */
3260 return s->xcer[7];
3261 }
3262
3263 OMAP_BAD_REG(addr);
3264 return 0;
3265 }
3266
3267 static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
3268 uint32_t value)
3269 {
3270 struct omap_mcbsp_s *s = opaque;
3271 int offset = addr & OMAP_MPUI_REG_MASK;
3272
3273 switch (offset) {
3274 case 0x00: /* DRR2 */
3275 case 0x02: /* DRR1 */
3276 OMAP_RO_REG(addr);
3277 return;
3278
3279 case 0x04: /* DXR2 */
3280 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3281 return;
3282 /* Fall through. */
3283 case 0x06: /* DXR1 */
3284 if (s->tx_req > 1) {
3285 s->tx_req -= 2;
3286 if (s->codec && s->codec->cts) {
3287 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3288 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
3289 }
3290 if (s->tx_req < 2)
3291 omap_mcbsp_tx_done(s);
3292 } else
3293 printf("%s: Tx FIFO overrun\n", __func__);
3294 return;
3295
3296 case 0x08: /* SPCR2 */
3297 s->spcr[1] &= 0x0002;
3298 s->spcr[1] |= 0x03f9 & value;
3299 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
3300 if (~value & 1) /* XRST */
3301 s->spcr[1] &= ~6;
3302 omap_mcbsp_req_update(s);
3303 return;
3304 case 0x0a: /* SPCR1 */
3305 s->spcr[0] &= 0x0006;
3306 s->spcr[0] |= 0xf8f9 & value;
3307 if (value & (1 << 15)) /* DLB */
3308 printf("%s: Digital Loopback mode enable attempt\n", __func__);
3309 if (~value & 1) { /* RRST */
3310 s->spcr[0] &= ~6;
3311 s->rx_req = 0;
3312 omap_mcbsp_rx_done(s);
3313 }
3314 omap_mcbsp_req_update(s);
3315 return;
3316
3317 case 0x0c: /* RCR2 */
3318 s->rcr[1] = value & 0xffff;
3319 return;
3320 case 0x0e: /* RCR1 */
3321 s->rcr[0] = value & 0x7fe0;
3322 return;
3323 case 0x10: /* XCR2 */
3324 s->xcr[1] = value & 0xffff;
3325 return;
3326 case 0x12: /* XCR1 */
3327 s->xcr[0] = value & 0x7fe0;
3328 return;
3329 case 0x14: /* SRGR2 */
3330 s->srgr[1] = value & 0xffff;
3331 omap_mcbsp_req_update(s);
3332 return;
3333 case 0x16: /* SRGR1 */
3334 s->srgr[0] = value & 0xffff;
3335 omap_mcbsp_req_update(s);
3336 return;
3337 case 0x18: /* MCR2 */
3338 s->mcr[1] = value & 0x03e3;
3339 if (value & 3) /* XMCM */
3340 printf("%s: Tx channel selection mode enable attempt\n", __func__);
3341 return;
3342 case 0x1a: /* MCR1 */
3343 s->mcr[0] = value & 0x03e1;
3344 if (value & 1) /* RMCM */
3345 printf("%s: Rx channel selection mode enable attempt\n", __func__);
3346 return;
3347 case 0x1c: /* RCERA */
3348 s->rcer[0] = value & 0xffff;
3349 return;
3350 case 0x1e: /* RCERB */
3351 s->rcer[1] = value & 0xffff;
3352 return;
3353 case 0x20: /* XCERA */
3354 s->xcer[0] = value & 0xffff;
3355 return;
3356 case 0x22: /* XCERB */
3357 s->xcer[1] = value & 0xffff;
3358 return;
3359 case 0x24: /* PCR0 */
3360 s->pcr = value & 0x7faf;
3361 return;
3362 case 0x26: /* RCERC */
3363 s->rcer[2] = value & 0xffff;
3364 return;
3365 case 0x28: /* RCERD */
3366 s->rcer[3] = value & 0xffff;
3367 return;
3368 case 0x2a: /* XCERC */
3369 s->xcer[2] = value & 0xffff;
3370 return;
3371 case 0x2c: /* XCERD */
3372 s->xcer[3] = value & 0xffff;
3373 return;
3374 case 0x2e: /* RCERE */
3375 s->rcer[4] = value & 0xffff;
3376 return;
3377 case 0x30: /* RCERF */
3378 s->rcer[5] = value & 0xffff;
3379 return;
3380 case 0x32: /* XCERE */
3381 s->xcer[4] = value & 0xffff;
3382 return;
3383 case 0x34: /* XCERF */
3384 s->xcer[5] = value & 0xffff;
3385 return;
3386 case 0x36: /* RCERG */
3387 s->rcer[6] = value & 0xffff;
3388 return;
3389 case 0x38: /* RCERH */
3390 s->rcer[7] = value & 0xffff;
3391 return;
3392 case 0x3a: /* XCERG */
3393 s->xcer[6] = value & 0xffff;
3394 return;
3395 case 0x3c: /* XCERH */
3396 s->xcer[7] = value & 0xffff;
3397 return;
3398 }
3399
3400 OMAP_BAD_REG(addr);
3401 }
3402
3403 static void omap_mcbsp_writew(void *opaque, hwaddr addr,
3404 uint32_t value)
3405 {
3406 struct omap_mcbsp_s *s = opaque;
3407 int offset = addr & OMAP_MPUI_REG_MASK;
3408
3409 if (offset == 0x04) { /* DXR */
3410 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3411 return;
3412 if (s->tx_req > 3) {
3413 s->tx_req -= 4;
3414 if (s->codec && s->codec->cts) {
3415 s->codec->out.fifo[s->codec->out.len ++] =
3416 (value >> 24) & 0xff;
3417 s->codec->out.fifo[s->codec->out.len ++] =
3418 (value >> 16) & 0xff;
3419 s->codec->out.fifo[s->codec->out.len ++] =
3420 (value >> 8) & 0xff;
3421 s->codec->out.fifo[s->codec->out.len ++] =
3422 (value >> 0) & 0xff;
3423 }
3424 if (s->tx_req < 4)
3425 omap_mcbsp_tx_done(s);
3426 } else
3427 printf("%s: Tx FIFO overrun\n", __func__);
3428 return;
3429 }
3430
3431 omap_badwidth_write16(opaque, addr, value);
3432 }
3433
3434 static void omap_mcbsp_write(void *opaque, hwaddr addr,
3435 uint64_t value, unsigned size)
3436 {
3437 switch (size) {
3438 case 2:
3439 omap_mcbsp_writeh(opaque, addr, value);
3440 break;
3441 case 4:
3442 omap_mcbsp_writew(opaque, addr, value);
3443 break;
3444 default:
3445 omap_badwidth_write16(opaque, addr, value);
3446 }
3447 }
3448
3449 static const MemoryRegionOps omap_mcbsp_ops = {
3450 .read = omap_mcbsp_read,
3451 .write = omap_mcbsp_write,
3452 .endianness = DEVICE_NATIVE_ENDIAN,
3453 };
3454
3455 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3456 {
3457 memset(&s->spcr, 0, sizeof(s->spcr));
3458 memset(&s->rcr, 0, sizeof(s->rcr));
3459 memset(&s->xcr, 0, sizeof(s->xcr));
3460 s->srgr[0] = 0x0001;
3461 s->srgr[1] = 0x2000;
3462 memset(&s->mcr, 0, sizeof(s->mcr));
3463 memset(&s->pcr, 0, sizeof(s->pcr));
3464 memset(&s->rcer, 0, sizeof(s->rcer));
3465 memset(&s->xcer, 0, sizeof(s->xcer));
3466 s->tx_req = 0;
3467 s->rx_req = 0;
3468 s->tx_rate = 0;
3469 s->rx_rate = 0;
3470 timer_del(s->source_timer);
3471 timer_del(s->sink_timer);
3472 }
3473
3474 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
3475 hwaddr base,
3476 qemu_irq txirq, qemu_irq rxirq,
3477 qemu_irq *dma, omap_clk clk)
3478 {
3479 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
3480
3481 s->txirq = txirq;
3482 s->rxirq = rxirq;
3483 s->txdrq = dma[0];
3484 s->rxdrq = dma[1];
3485 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
3486 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
3487 omap_mcbsp_reset(s);
3488
3489 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
3490 memory_region_add_subregion(system_memory, base, &s->iomem);
3491
3492 return s;
3493 }
3494
3495 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
3496 {
3497 struct omap_mcbsp_s *s = opaque;
3498
3499 if (s->rx_rate) {
3500 s->rx_req = s->codec->in.len;
3501 omap_mcbsp_rx_newdata(s);
3502 }
3503 }
3504
3505 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
3506 {
3507 struct omap_mcbsp_s *s = opaque;
3508
3509 if (s->tx_rate) {
3510 s->tx_req = s->codec->out.size;
3511 omap_mcbsp_tx_newdata(s);
3512 }
3513 }
3514
3515 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
3516 {
3517 s->codec = slave;
3518 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0);
3519 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0);
3520 }
3521
3522 /* LED Pulse Generators */
3523 struct omap_lpg_s {
3524 MemoryRegion iomem;
3525 QEMUTimer *tm;
3526
3527 uint8_t control;
3528 uint8_t power;
3529 int64_t on;
3530 int64_t period;
3531 int clk;
3532 int cycle;
3533 };
3534
3535 static void omap_lpg_tick(void *opaque)
3536 {
3537 struct omap_lpg_s *s = opaque;
3538
3539 if (s->cycle)
3540 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
3541 else
3542 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
3543
3544 s->cycle = !s->cycle;
3545 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off");
3546 }
3547
3548 static void omap_lpg_update(struct omap_lpg_s *s)
3549 {
3550 int64_t on, period = 1, ticks = 1000;
3551 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3552
3553 if (~s->control & (1 << 6)) /* LPGRES */
3554 on = 0;
3555 else if (s->control & (1 << 7)) /* PERM_ON */
3556 on = period;
3557 else {
3558 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3559 256 / 32);
3560 on = (s->clk && s->power) ? muldiv64(ticks,
3561 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3562 }
3563
3564 timer_del(s->tm);
3565 if (on == period && s->on < s->period)
3566 printf("%s: LED is on\n", __func__);
3567 else if (on == 0 && s->on)
3568 printf("%s: LED is off\n", __func__);
3569 else if (on && (on != s->on || period != s->period)) {
3570 s->cycle = 0;
3571 s->on = on;
3572 s->period = period;
3573 omap_lpg_tick(s);
3574 return;
3575 }
3576
3577 s->on = on;
3578 s->period = period;
3579 }
3580
3581 static void omap_lpg_reset(struct omap_lpg_s *s)
3582 {
3583 s->control = 0x00;
3584 s->power = 0x00;
3585 s->clk = 1;
3586 omap_lpg_update(s);
3587 }
3588
3589 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
3590 {
3591 struct omap_lpg_s *s = opaque;
3592 int offset = addr & OMAP_MPUI_REG_MASK;
3593
3594 if (size != 1) {
3595 return omap_badwidth_read8(opaque, addr);
3596 }
3597
3598 switch (offset) {
3599 case 0x00: /* LCR */
3600 return s->control;
3601
3602 case 0x04: /* PMR */
3603 return s->power;
3604 }
3605
3606 OMAP_BAD_REG(addr);
3607 return 0;
3608 }
3609
3610 static void omap_lpg_write(void *opaque, hwaddr addr,
3611 uint64_t value, unsigned size)
3612 {
3613 struct omap_lpg_s *s = opaque;
3614 int offset = addr & OMAP_MPUI_REG_MASK;
3615
3616 if (size != 1) {
3617 omap_badwidth_write8(opaque, addr, value);
3618 return;
3619 }
3620
3621 switch (offset) {
3622 case 0x00: /* LCR */
3623 if (~value & (1 << 6)) /* LPGRES */
3624 omap_lpg_reset(s);
3625 s->control = value & 0xff;
3626 omap_lpg_update(s);
3627 return;
3628
3629 case 0x04: /* PMR */
3630 s->power = value & 0x01;
3631 omap_lpg_update(s);
3632 return;
3633
3634 default:
3635 OMAP_BAD_REG(addr);
3636 return;
3637 }
3638 }
3639
3640 static const MemoryRegionOps omap_lpg_ops = {
3641 .read = omap_lpg_read,
3642 .write = omap_lpg_write,
3643 .endianness = DEVICE_NATIVE_ENDIAN,
3644 };
3645
3646 static void omap_lpg_clk_update(void *opaque, int line, int on)
3647 {
3648 struct omap_lpg_s *s = opaque;
3649
3650 s->clk = on;
3651 omap_lpg_update(s);
3652 }
3653
3654 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
3655 hwaddr base, omap_clk clk)
3656 {
3657 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
3658
3659 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
3660
3661 omap_lpg_reset(s);
3662
3663 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
3664 memory_region_add_subregion(system_memory, base, &s->iomem);
3665
3666 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0));
3667
3668 return s;
3669 }
3670
3671 /* MPUI Peripheral Bridge configuration */
3672 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
3673 unsigned size)
3674 {
3675 if (size != 2) {
3676 return omap_badwidth_read16(opaque, addr);
3677 }
3678
3679 if (addr == OMAP_MPUI_BASE) /* CMR */
3680 return 0xfe4d;
3681
3682 OMAP_BAD_REG(addr);
3683 return 0;
3684 }
3685
3686 static void omap_mpui_io_write(void *opaque, hwaddr addr,
3687 uint64_t value, unsigned size)
3688 {
3689 /* FIXME: infinite loop */
3690 omap_badwidth_write16(opaque, addr, value);
3691 }
3692
3693 static const MemoryRegionOps omap_mpui_io_ops = {
3694 .read = omap_mpui_io_read,
3695 .write = omap_mpui_io_write,
3696 .endianness = DEVICE_NATIVE_ENDIAN,
3697 };
3698
3699 static void omap_setup_mpui_io(MemoryRegion *system_memory,
3700 struct omap_mpu_state_s *mpu)
3701 {
3702 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
3703 "omap-mpui-io", 0x7fff);
3704 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
3705 &mpu->mpui_io_iomem);
3706 }
3707
3708 /* General chip reset */
3709 static void omap1_mpu_reset(void *opaque)
3710 {
3711 struct omap_mpu_state_s *mpu = opaque;
3712
3713 omap_dma_reset(mpu->dma);
3714 omap_mpu_timer_reset(mpu->timer[0]);
3715 omap_mpu_timer_reset(mpu->timer[1]);
3716 omap_mpu_timer_reset(mpu->timer[2]);
3717 omap_wd_timer_reset(mpu->wdt);
3718 omap_os_timer_reset(mpu->os_timer);
3719 omap_lcdc_reset(mpu->lcd);
3720 omap_ulpd_pm_reset(mpu);
3721 omap_pin_cfg_reset(mpu);
3722 omap_mpui_reset(mpu);
3723 omap_tipb_bridge_reset(mpu->private_tipb);
3724 omap_tipb_bridge_reset(mpu->public_tipb);
3725 omap_dpll_reset(mpu->dpll[0]);
3726 omap_dpll_reset(mpu->dpll[1]);
3727 omap_dpll_reset(mpu->dpll[2]);
3728 omap_uart_reset(mpu->uart[0]);
3729 omap_uart_reset(mpu->uart[1]);
3730 omap_uart_reset(mpu->uart[2]);
3731 omap_mmc_reset(mpu->mmc);
3732 omap_mpuio_reset(mpu->mpuio);
3733 omap_uwire_reset(mpu->microwire);
3734 omap_pwl_reset(mpu->pwl);
3735 omap_pwt_reset(mpu->pwt);
3736 omap_rtc_reset(mpu->rtc);
3737 omap_mcbsp_reset(mpu->mcbsp1);
3738 omap_mcbsp_reset(mpu->mcbsp2);
3739 omap_mcbsp_reset(mpu->mcbsp3);
3740 omap_lpg_reset(mpu->led[0]);
3741 omap_lpg_reset(mpu->led[1]);
3742 omap_clkm_reset(mpu);
3743 cpu_reset(CPU(mpu->cpu));
3744 }
3745
3746 static const struct omap_map_s {
3747 hwaddr phys_dsp;
3748 hwaddr phys_mpu;
3749 uint32_t size;
3750 const char *name;
3751 } omap15xx_dsp_mm[] = {
3752 /* Strobe 0 */
3753 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3754 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3755 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3756 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3757 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3758 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3759 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3760 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3761 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3762 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3763 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3764 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3765 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3766 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3767 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3768 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3769 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3770 /* Strobe 1 */
3771 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3772
3773 { 0 }
3774 };
3775
3776 static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
3777 const struct omap_map_s *map)
3778 {
3779 MemoryRegion *io;
3780
3781 for (; map->phys_dsp; map ++) {
3782 io = g_new(MemoryRegion, 1);
3783 memory_region_init_alias(io, NULL, map->name,
3784 system_memory, map->phys_mpu, map->size);
3785 memory_region_add_subregion(system_memory, map->phys_dsp, io);
3786 }
3787 }
3788
3789 void omap_mpu_wakeup(void *opaque, int irq, int req)
3790 {
3791 struct omap_mpu_state_s *mpu = opaque;
3792 CPUState *cpu = CPU(mpu->cpu);
3793
3794 if (cpu->halted) {
3795 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
3796 }
3797 }
3798
3799 static const struct dma_irq_map omap1_dma_irq_map[] = {
3800 { 0, OMAP_INT_DMA_CH0_6 },
3801 { 0, OMAP_INT_DMA_CH1_7 },
3802 { 0, OMAP_INT_DMA_CH2_8 },
3803 { 0, OMAP_INT_DMA_CH3 },
3804 { 0, OMAP_INT_DMA_CH4 },
3805 { 0, OMAP_INT_DMA_CH5 },
3806 { 1, OMAP_INT_1610_DMA_CH6 },
3807 { 1, OMAP_INT_1610_DMA_CH7 },
3808 { 1, OMAP_INT_1610_DMA_CH8 },
3809 { 1, OMAP_INT_1610_DMA_CH9 },
3810 { 1, OMAP_INT_1610_DMA_CH10 },
3811 { 1, OMAP_INT_1610_DMA_CH11 },
3812 { 1, OMAP_INT_1610_DMA_CH12 },
3813 { 1, OMAP_INT_1610_DMA_CH13 },
3814 { 1, OMAP_INT_1610_DMA_CH14 },
3815 { 1, OMAP_INT_1610_DMA_CH15 }
3816 };
3817
3818 /* DMA ports for OMAP1 */
3819 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
3820 hwaddr addr)
3821 {
3822 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
3823 }
3824
3825 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
3826 hwaddr addr)
3827 {
3828 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3829 addr);
3830 }
3831
3832 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
3833 hwaddr addr)
3834 {
3835 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
3836 }
3837
3838 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
3839 hwaddr addr)
3840 {
3841 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
3842 }
3843
3844 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
3845 hwaddr addr)
3846 {
3847 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
3848 }
3849
3850 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
3851 hwaddr addr)
3852 {
3853 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
3854 }
3855
3856 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
3857 const char *cpu_type)
3858 {
3859 int i;
3860 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
3861 qemu_irq dma_irqs[6];
3862 DriveInfo *dinfo;
3863 SysBusDevice *busdev;
3864 MemoryRegion *system_memory = get_system_memory();
3865
3866 /* Core */
3867 s->mpu_model = omap310;
3868 s->cpu = ARM_CPU(cpu_create(cpu_type));
3869 s->sdram_size = memory_region_size(dram);
3870 s->sram_size = OMAP15XX_SRAM_SIZE;
3871
3872 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
3873
3874 /* Clocks */
3875 omap_clk_init(s);
3876
3877 /* Memory-mapped stuff */
3878 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
3879 &error_fatal);
3880 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
3881
3882 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
3883
3884 s->ih[0] = qdev_new("omap-intc");
3885 qdev_prop_set_uint32(s->ih[0], "size", 0x100);
3886 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
3887 busdev = SYS_BUS_DEVICE(s->ih[0]);
3888 sysbus_realize_and_unref(busdev, &error_fatal);
3889 sysbus_connect_irq(busdev, 0,
3890 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
3891 sysbus_connect_irq(busdev, 1,
3892 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
3893 sysbus_mmio_map(busdev, 0, 0xfffecb00);
3894 s->ih[1] = qdev_new("omap-intc");
3895 qdev_prop_set_uint32(s->ih[1], "size", 0x800);
3896 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
3897 busdev = SYS_BUS_DEVICE(s->ih[1]);
3898 sysbus_realize_and_unref(busdev, &error_fatal);
3899 sysbus_connect_irq(busdev, 0,
3900 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
3901 /* The second interrupt controller's FIQ output is not wired up */
3902 sysbus_mmio_map(busdev, 0, 0xfffe0000);
3903
3904 for (i = 0; i < 6; i++) {
3905 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
3906 omap1_dma_irq_map[i].intr);
3907 }
3908 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
3909 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
3910 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3911
3912 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3913 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3914 s->port[imif ].addr_valid = omap_validate_imif_addr;
3915 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3916 s->port[local ].addr_valid = omap_validate_local_addr;
3917 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3918
3919 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3920 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram),
3921 OMAP_EMIFF_BASE, s->sdram_size);
3922 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
3923 OMAP_IMIF_BASE, s->sram_size);
3924
3925 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
3926 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
3927 omap_findclk(s, "mputim_ck"));
3928 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
3929 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
3930 omap_findclk(s, "mputim_ck"));
3931 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
3932 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
3933 omap_findclk(s, "mputim_ck"));
3934
3935 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
3936 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
3937 omap_findclk(s, "armwdt_ck"));
3938
3939 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
3940 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
3941 omap_findclk(s, "clk32-kHz"));
3942
3943 s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
3944 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
3945 omap_dma_get_lcdch(s->dma),
3946 omap_findclk(s, "lcd_ck"));
3947
3948 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3949 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3950 omap_id_init(system_memory, s);
3951
3952 omap_mpui_init(system_memory, 0xfffec900, s);
3953
3954 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
3955 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
3956 omap_findclk(s, "tipb_ck"));
3957 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
3958 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
3959 omap_findclk(s, "tipb_ck"));
3960
3961 omap_tcmi_init(system_memory, 0xfffecc00, s);
3962
3963 s->uart[0] = omap_uart_init(0xfffb0000,
3964 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
3965 omap_findclk(s, "uart1_ck"),
3966 omap_findclk(s, "uart1_ck"),
3967 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
3968 "uart1",
3969 serial_hd(0));
3970 s->uart[1] = omap_uart_init(0xfffb0800,
3971 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
3972 omap_findclk(s, "uart2_ck"),
3973 omap_findclk(s, "uart2_ck"),
3974 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
3975 "uart2",
3976 serial_hd(0) ? serial_hd(1) : NULL);
3977 s->uart[2] = omap_uart_init(0xfffb9800,
3978 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
3979 omap_findclk(s, "uart3_ck"),
3980 omap_findclk(s, "uart3_ck"),
3981 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
3982 "uart3",
3983 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
3984
3985 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
3986 omap_findclk(s, "dpll1"));
3987 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
3988 omap_findclk(s, "dpll2"));
3989 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
3990 omap_findclk(s, "dpll3"));
3991
3992 dinfo = drive_get(IF_SD, 0, 0);
3993 if (!dinfo && !qtest_enabled()) {
3994 warn_report("missing SecureDigital device");
3995 }
3996 s->mmc = omap_mmc_init(0xfffb7800, system_memory,
3997 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
3998 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
3999 &s->drq[OMAP_DMA_MMC_TX],
4000 omap_findclk(s, "mmc_ck"));
4001
4002 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
4004 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
4005 s->wakeup, omap_findclk(s, "clk32-kHz"));
4006
4007 s->gpio = qdev_new("omap-gpio");
4008 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
4009 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
4010 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
4011 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
4012 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
4013 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
4014
4015 s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
4016 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
4017 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
4018 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4019
4020 s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
4021 omap_findclk(s, "armxor_ck"));
4022 s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
4023 omap_findclk(s, "armxor_ck"));
4024
4025 s->i2c[0] = qdev_new("omap_i2c");
4026 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
4027 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
4028 busdev = SYS_BUS_DEVICE(s->i2c[0]);
4029 sysbus_realize_and_unref(busdev, &error_fatal);
4030 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
4031 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
4032 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
4033 sysbus_mmio_map(busdev, 0, 0xfffb3800);
4034
4035 s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
4036 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
4037 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
4038 omap_findclk(s, "clk32-kHz"));
4039
4040 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
4042 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
4043 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4044 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
4045 qdev_get_gpio_in(s->ih[0],
4046 OMAP_INT_310_McBSP2_TX),
4047 qdev_get_gpio_in(s->ih[0],
4048 OMAP_INT_310_McBSP2_RX),
4049 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4050 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
4051 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
4052 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
4053 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4054
4055 s->led[0] = omap_lpg_init(system_memory,
4056 0xfffbd000, omap_findclk(s, "clk32-kHz"));
4057 s->led[1] = omap_lpg_init(system_memory,
4058 0xfffbd800, omap_findclk(s, "clk32-kHz"));
4059
4060 /* Register mappings not currently implemented:
4061 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4062 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4063 * USB W2FC fffb4000 - fffb47ff
4064 * Camera Interface fffb6800 - fffb6fff
4065 * USB Host fffba000 - fffba7ff
4066 * FAC fffba800 - fffbafff
4067 * HDQ/1-Wire fffbc000 - fffbc7ff
4068 * TIPB switches fffbc800 - fffbcfff
4069 * Mailbox fffcf000 - fffcf7ff
4070 * Local bus IF fffec100 - fffec1ff
4071 * Local bus MMU fffec200 - fffec2ff
4072 * DSP MMU fffed200 - fffed2ff
4073 */
4074
4075 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
4076 omap_setup_mpui_io(system_memory, s);
4077
4078 qemu_register_reset(omap1_mpu_reset, s);
4079
4080 return s;
4081 }
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