4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-objects.h"
35 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
37 # define PCI_DPRINTF(format, ...) do { } while (0)
43 pci_set_irq_fn set_irq
;
44 pci_map_irq_fn map_irq
;
45 pci_hotplug_fn hotplug
;
46 DeviceState
*hotplug_qdev
;
48 PCIDevice
*devices
[256];
49 PCIDevice
*parent_dev
;
50 target_phys_addr_t mem_base
;
52 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
53 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
55 /* The bus IRQ state is the logical OR of the connected devices.
56 Keep a count of the number of devices with raised IRQs. */
61 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
62 static char *pcibus_get_dev_path(DeviceState
*dev
);
64 static struct BusInfo pci_bus_info
= {
66 .size
= sizeof(PCIBus
),
67 .print_dev
= pcibus_dev_print
,
68 .get_dev_path
= pcibus_get_dev_path
,
69 .props
= (Property
[]) {
70 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
71 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
72 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
73 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
74 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
75 DEFINE_PROP_END_OF_LIST()
79 static void pci_update_mappings(PCIDevice
*d
);
80 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
81 static int pci_add_option_rom(PCIDevice
*pdev
);
82 static void pci_del_option_rom(PCIDevice
*pdev
);
84 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
85 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
90 QLIST_ENTRY(PCIHostBus
) next
;
92 static QLIST_HEAD(, PCIHostBus
) host_buses
;
94 static const VMStateDescription vmstate_pcibus
= {
97 .minimum_version_id
= 1,
98 .minimum_version_id_old
= 1,
99 .fields
= (VMStateField
[]) {
100 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
101 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
102 VMSTATE_END_OF_LIST()
106 static int pci_bar(PCIDevice
*d
, int reg
)
110 if (reg
!= PCI_ROM_SLOT
)
111 return PCI_BASE_ADDRESS_0
+ reg
* 4;
113 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
114 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
117 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
119 return (d
->irq_state
>> irq_num
) & 0x1;
122 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
124 d
->irq_state
&= ~(0x1 << irq_num
);
125 d
->irq_state
|= level
<< irq_num
;
128 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
133 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
136 pci_dev
= bus
->parent_dev
;
138 bus
->irq_count
[irq_num
] += change
;
139 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
142 /* Update interrupt status bit in config space on interrupt
144 static void pci_update_irq_status(PCIDevice
*dev
)
146 if (dev
->irq_state
) {
147 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
149 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
153 static void pci_device_reset(PCIDevice
*dev
)
158 pci_update_irq_status(dev
);
159 /* Clear all writeable bits */
160 pci_set_word(dev
->config
+ PCI_COMMAND
,
161 pci_get_word(dev
->config
+ PCI_COMMAND
) &
162 ~pci_get_word(dev
->wmask
+ PCI_COMMAND
));
163 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
164 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
165 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
166 PCIIORegion
*region
= &dev
->io_regions
[r
];
171 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
172 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
173 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
175 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
178 pci_update_mappings(dev
);
181 static void pci_bus_reset(void *opaque
)
183 PCIBus
*bus
= opaque
;
186 for (i
= 0; i
< bus
->nirq
; i
++) {
187 bus
->irq_count
[i
] = 0;
189 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
190 if (bus
->devices
[i
]) {
191 pci_device_reset(bus
->devices
[i
]);
196 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
198 struct PCIHostBus
*host
;
199 host
= qemu_mallocz(sizeof(*host
));
200 host
->domain
= domain
;
202 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
205 PCIBus
*pci_find_root_bus(int domain
)
207 struct PCIHostBus
*host
;
209 QLIST_FOREACH(host
, &host_buses
, next
) {
210 if (host
->domain
== domain
) {
218 int pci_find_domain(const PCIBus
*bus
)
221 struct PCIHostBus
*host
;
223 /* obtain root bus */
224 while ((d
= bus
->parent_dev
) != NULL
) {
228 QLIST_FOREACH(host
, &host_buses
, next
) {
229 if (host
->bus
== bus
) {
234 abort(); /* should not be reached */
238 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
239 const char *name
, int devfn_min
)
241 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
242 assert(PCI_FUNC(devfn_min
) == 0);
243 bus
->devfn_min
= devfn_min
;
246 QLIST_INIT(&bus
->child
);
247 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
249 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
250 qemu_register_reset(pci_bus_reset
, bus
);
253 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
257 bus
= qemu_mallocz(sizeof(*bus
));
258 bus
->qbus
.qdev_allocated
= 1;
259 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
263 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
264 void *irq_opaque
, int nirq
)
266 bus
->set_irq
= set_irq
;
267 bus
->map_irq
= map_irq
;
268 bus
->irq_opaque
= irq_opaque
;
270 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
273 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
275 bus
->qbus
.allow_hotplug
= 1;
276 bus
->hotplug
= hotplug
;
277 bus
->hotplug_qdev
= qdev
;
280 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
)
282 bus
->mem_base
= base
;
285 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
286 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
287 void *irq_opaque
, int devfn_min
, int nirq
)
291 bus
= pci_bus_new(parent
, name
, devfn_min
);
292 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
296 static void pci_register_secondary_bus(PCIBus
*parent
,
299 pci_map_irq_fn map_irq
,
302 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
303 bus
->map_irq
= map_irq
;
304 bus
->parent_dev
= dev
;
306 QLIST_INIT(&bus
->child
);
307 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
310 static void pci_unregister_secondary_bus(PCIBus
*bus
)
312 assert(QLIST_EMPTY(&bus
->child
));
313 QLIST_REMOVE(bus
, sibling
);
316 int pci_bus_num(PCIBus
*s
)
319 return 0; /* pci host bridge */
320 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
323 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
325 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
329 assert(size
== pci_config_size(s
));
330 config
= qemu_malloc(size
);
332 qemu_get_buffer(f
, config
, size
);
333 for (i
= 0; i
< size
; ++i
) {
334 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
339 memcpy(s
->config
, config
, size
);
341 pci_update_mappings(s
);
347 /* just put buffer */
348 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
350 const uint8_t **v
= pv
;
351 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
352 qemu_put_buffer(f
, *v
, size
);
355 static VMStateInfo vmstate_info_pci_config
= {
356 .name
= "pci config",
357 .get
= get_pci_config_device
,
358 .put
= put_pci_config_device
,
361 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
363 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
364 uint32_t irq_state
[PCI_NUM_PINS
];
366 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
367 irq_state
[i
] = qemu_get_be32(f
);
368 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
369 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
375 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
376 pci_set_irq_state(s
, i
, irq_state
[i
]);
382 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
385 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
387 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
388 qemu_put_be32(f
, pci_irq_state(s
, i
));
392 static VMStateInfo vmstate_info_pci_irq_state
= {
393 .name
= "pci irq state",
394 .get
= get_pci_irq_state
,
395 .put
= put_pci_irq_state
,
398 const VMStateDescription vmstate_pci_device
= {
401 .minimum_version_id
= 1,
402 .minimum_version_id_old
= 1,
403 .fields
= (VMStateField
[]) {
404 VMSTATE_INT32_LE(version_id
, PCIDevice
),
405 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
406 vmstate_info_pci_config
,
407 PCI_CONFIG_SPACE_SIZE
),
408 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
409 vmstate_info_pci_irq_state
,
410 PCI_NUM_PINS
* sizeof(int32_t)),
411 VMSTATE_END_OF_LIST()
415 const VMStateDescription vmstate_pcie_device
= {
418 .minimum_version_id
= 1,
419 .minimum_version_id_old
= 1,
420 .fields
= (VMStateField
[]) {
421 VMSTATE_INT32_LE(version_id
, PCIDevice
),
422 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
423 vmstate_info_pci_config
,
424 PCIE_CONFIG_SPACE_SIZE
),
425 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
426 vmstate_info_pci_irq_state
,
427 PCI_NUM_PINS
* sizeof(int32_t)),
428 VMSTATE_END_OF_LIST()
432 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
434 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
437 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
439 /* Clear interrupt status bit: it is implicit
440 * in irq_state which we are saving.
441 * This makes us compatible with old devices
442 * which never set or clear this bit. */
443 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
444 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
445 /* Restore the interrupt status bit. */
446 pci_update_irq_status(s
);
449 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
452 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
453 /* Restore the interrupt status bit. */
454 pci_update_irq_status(s
);
458 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
460 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
461 pci_default_sub_vendor_id
);
462 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
463 pci_default_sub_device_id
);
467 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
469 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
474 unsigned long dom
= 0, bus
= 0;
478 val
= strtoul(p
, &e
, 16);
484 val
= strtoul(p
, &e
, 16);
491 val
= strtoul(p
, &e
, 16);
497 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
505 /* Note: QEMU doesn't implement domains other than 0 */
506 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
515 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
518 /* strip legacy tag */
519 if (!strncmp(addr
, "pci_addr=", 9)) {
522 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
523 monitor_printf(mon
, "Invalid pci address\n");
529 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
536 return pci_find_bus(pci_find_root_bus(0), 0);
539 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
544 return pci_find_bus(pci_find_root_bus(dom
), bus
);
547 static void pci_init_cmask(PCIDevice
*dev
)
549 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
550 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
551 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
552 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
553 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
554 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
555 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
556 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
559 static void pci_init_wmask(PCIDevice
*dev
)
561 int config_size
= pci_config_size(dev
);
563 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
564 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
565 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
566 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
567 PCI_COMMAND_INTX_DISABLE
);
569 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
570 config_size
- PCI_CONFIG_HEADER_SIZE
);
573 static void pci_init_wmask_bridge(PCIDevice
*d
)
575 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
576 PCI_SEC_LETENCY_TIMER */
577 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
580 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
581 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
582 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
583 PCI_MEMORY_RANGE_MASK
& 0xffff);
584 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
585 PCI_MEMORY_RANGE_MASK
& 0xffff);
586 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
587 PCI_PREF_RANGE_MASK
& 0xffff);
588 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
589 PCI_PREF_RANGE_MASK
& 0xffff);
591 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
592 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
594 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
597 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
599 uint8_t slot
= PCI_SLOT(dev
->devfn
);
602 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
603 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
607 * multifuction bit is interpreted in two ways as follows.
608 * - all functions must set the bit to 1.
610 * - function 0 must set the bit, but the rest function (> 0)
611 * is allowed to leave the bit to 0.
612 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
614 * So OS (at least Linux) checks the bit of only function 0,
615 * and doesn't see the bit of function > 0.
617 * The below check allows both interpretation.
619 if (PCI_FUNC(dev
->devfn
)) {
620 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
621 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
622 /* function 0 should set multifunction bit */
623 error_report("PCI: single function device can't be populated "
624 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
630 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
633 /* function 0 indicates single function, so function > 0 must be NULL */
634 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
635 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
636 error_report("PCI: %x.0 indicates single function, "
637 "but %x.%x is already populated.",
645 static void pci_config_alloc(PCIDevice
*pci_dev
)
647 int config_size
= pci_config_size(pci_dev
);
649 pci_dev
->config
= qemu_mallocz(config_size
);
650 pci_dev
->cmask
= qemu_mallocz(config_size
);
651 pci_dev
->wmask
= qemu_mallocz(config_size
);
652 pci_dev
->used
= qemu_mallocz(config_size
);
655 static void pci_config_free(PCIDevice
*pci_dev
)
657 qemu_free(pci_dev
->config
);
658 qemu_free(pci_dev
->cmask
);
659 qemu_free(pci_dev
->wmask
);
660 qemu_free(pci_dev
->used
);
663 /* -1 for devfn means auto assign */
664 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
665 const char *name
, int devfn
,
666 PCIConfigReadFunc
*config_read
,
667 PCIConfigWriteFunc
*config_write
,
671 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
672 devfn
+= PCI_FUNC_MAX
) {
673 if (!bus
->devices
[devfn
])
676 error_report("PCI: no slot/function available for %s, all in use", name
);
679 } else if (bus
->devices
[devfn
]) {
680 error_report("PCI: slot %d function %d not available for %s, in use by %s",
681 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
685 pci_dev
->devfn
= devfn
;
686 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
687 pci_dev
->irq_state
= 0;
688 pci_config_alloc(pci_dev
);
691 pci_set_default_subsystem_id(pci_dev
);
693 pci_init_cmask(pci_dev
);
694 pci_init_wmask(pci_dev
);
696 pci_init_wmask_bridge(pci_dev
);
698 if (pci_init_multifunction(bus
, pci_dev
)) {
699 pci_config_free(pci_dev
);
704 config_read
= pci_default_read_config
;
706 config_write
= pci_default_write_config
;
707 pci_dev
->config_read
= config_read
;
708 pci_dev
->config_write
= config_write
;
709 bus
->devices
[devfn
] = pci_dev
;
710 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
711 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
715 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
717 qemu_free_irqs(pci_dev
->irq
);
718 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
719 pci_config_free(pci_dev
);
722 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
723 int instance_size
, int devfn
,
724 PCIConfigReadFunc
*config_read
,
725 PCIConfigWriteFunc
*config_write
)
729 pci_dev
= qemu_mallocz(instance_size
);
730 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
731 config_read
, config_write
,
732 PCI_HEADER_TYPE_NORMAL
);
733 if (pci_dev
== NULL
) {
734 hw_error("PCI: can't register device\n");
739 static target_phys_addr_t
pci_to_cpu_addr(PCIBus
*bus
,
740 target_phys_addr_t addr
)
742 return addr
+ bus
->mem_base
;
745 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
750 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
751 r
= &pci_dev
->io_regions
[i
];
752 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
754 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
755 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
757 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev
->bus
,
765 static int pci_unregister_device(DeviceState
*dev
)
767 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
768 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
772 ret
= info
->exit(pci_dev
);
776 pci_unregister_io_regions(pci_dev
);
777 pci_del_option_rom(pci_dev
);
778 do_pci_unregister_device(pci_dev
);
782 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
783 pcibus_t size
, int type
,
784 PCIMapIORegionFunc
*map_func
)
790 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
793 if (size
& (size
-1)) {
794 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
795 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
799 r
= &pci_dev
->io_regions
[region_num
];
800 r
->addr
= PCI_BAR_UNMAPPED
;
802 r
->filtered_size
= size
;
804 r
->map_func
= map_func
;
807 addr
= pci_bar(pci_dev
, region_num
);
808 if (region_num
== PCI_ROM_SLOT
) {
809 /* ROM enable bit is writeable */
810 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
812 pci_set_long(pci_dev
->config
+ addr
, type
);
813 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
814 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
815 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
816 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
818 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
819 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
823 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
824 uint32_t base
, uint32_t base_upper16
)
828 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
829 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
830 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
835 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
837 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
841 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
842 uint32_t base
, uint32_t upper
)
847 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
848 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
849 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
850 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
855 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
858 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
859 base
= pci_config_get_io_base(bridge
,
860 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
862 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
863 base
= pci_config_get_pref_base(
864 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
866 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
873 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
876 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
877 limit
= pci_config_get_io_base(bridge
,
878 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
879 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
881 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
882 limit
= pci_config_get_pref_base(
883 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
885 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
887 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
892 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
895 pcibus_t base
= *addr
;
896 pcibus_t limit
= *addr
+ *size
- 1;
899 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
900 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
902 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
903 if (!(cmd
& PCI_COMMAND_IO
)) {
907 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
912 base
= MAX(base
, pci_bridge_get_base(br
, type
));
913 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
920 *size
= limit
- base
+ 1;
923 *addr
= PCI_BAR_UNMAPPED
;
927 static pcibus_t
pci_bar_address(PCIDevice
*d
,
928 int reg
, uint8_t type
, pcibus_t size
)
930 pcibus_t new_addr
, last_addr
;
931 int bar
= pci_bar(d
, reg
);
932 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
934 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
935 if (!(cmd
& PCI_COMMAND_IO
)) {
936 return PCI_BAR_UNMAPPED
;
938 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
939 last_addr
= new_addr
+ size
- 1;
940 /* NOTE: we have only 64K ioports on PC */
941 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
942 return PCI_BAR_UNMAPPED
;
947 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
948 return PCI_BAR_UNMAPPED
;
950 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
951 new_addr
= pci_get_quad(d
->config
+ bar
);
953 new_addr
= pci_get_long(d
->config
+ bar
);
955 /* the ROM slot has a specific enable bit */
956 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
957 return PCI_BAR_UNMAPPED
;
959 new_addr
&= ~(size
- 1);
960 last_addr
= new_addr
+ size
- 1;
961 /* NOTE: we do not support wrapping */
962 /* XXX: as we cannot support really dynamic
963 mappings, we handle specific values as invalid
965 if (last_addr
<= new_addr
|| new_addr
== 0 ||
966 last_addr
== PCI_BAR_UNMAPPED
) {
967 return PCI_BAR_UNMAPPED
;
970 /* Now pcibus_t is 64bit.
971 * Check if 32 bit BAR wraps around explicitly.
972 * Without this, PC ide doesn't work well.
973 * TODO: remove this work around.
975 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
976 return PCI_BAR_UNMAPPED
;
980 * OS is allowed to set BAR beyond its addressable
981 * bits. For example, 32 bit OS can set 64bit bar
982 * to >4G. Check it. TODO: we might need to support
983 * it in the future for e.g. PAE.
985 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
986 return PCI_BAR_UNMAPPED
;
992 static void pci_update_mappings(PCIDevice
*d
)
996 pcibus_t new_addr
, filtered_size
;
998 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
999 r
= &d
->io_regions
[i
];
1001 /* this region isn't registered */
1005 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1007 /* bridge filtering */
1008 filtered_size
= r
->size
;
1009 if (new_addr
!= PCI_BAR_UNMAPPED
) {
1010 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
1013 /* This bar isn't changed */
1014 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
1017 /* now do the real mapping */
1018 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1019 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1021 /* NOTE: specific hack for IDE in PC case:
1022 only one byte must be mapped. */
1023 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1024 if (class == 0x0101 && r
->size
== 4) {
1025 isa_unassign_ioport(r
->addr
+ 2, 1);
1027 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
1030 cpu_register_physical_memory(pci_to_cpu_addr(d
->bus
, r
->addr
),
1033 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
1037 r
->filtered_size
= filtered_size
;
1038 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1040 * TODO: currently almost all the map funcions assumes
1041 * filtered_size == size and addr & ~(size - 1) == addr.
1042 * However with bridge filtering, they aren't always true.
1043 * Teach them such cases, such that filtered_size < size and
1044 * addr & (size - 1) != 0.
1046 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1047 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
1049 r
->map_func(d
, i
, pci_to_cpu_addr(d
->bus
, r
->addr
),
1050 r
->filtered_size
, r
->type
);
1056 static inline int pci_irq_disabled(PCIDevice
*d
)
1058 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1061 /* Called after interrupt disabled field update in config space,
1062 * assert/deassert interrupts if necessary.
1063 * Gets original interrupt disable bit value (before update). */
1064 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1066 int i
, disabled
= pci_irq_disabled(d
);
1067 if (disabled
== was_irq_disabled
)
1069 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1070 int state
= pci_irq_state(d
, i
);
1071 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1075 uint32_t pci_default_read_config(PCIDevice
*d
,
1076 uint32_t address
, int len
)
1079 assert(len
== 1 || len
== 2 || len
== 4);
1080 len
= MIN(len
, pci_config_size(d
) - address
);
1081 memcpy(&val
, d
->config
+ address
, len
);
1082 return le32_to_cpu(val
);
1085 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1087 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1088 uint32_t config_size
= pci_config_size(d
);
1090 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
1091 uint8_t wmask
= d
->wmask
[addr
+ i
];
1092 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1094 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1095 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1096 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1097 range_covers_byte(addr
, l
, PCI_COMMAND
))
1098 pci_update_mappings(d
);
1100 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1101 pci_update_irq_disabled(d
, was_irq_disabled
);
1104 /***********************************************************/
1105 /* generic PCI irq support */
1107 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1108 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1110 PCIDevice
*pci_dev
= opaque
;
1113 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1117 pci_set_irq_state(pci_dev
, irq_num
, level
);
1118 pci_update_irq_status(pci_dev
);
1119 if (pci_irq_disabled(pci_dev
))
1121 pci_change_irq_level(pci_dev
, irq_num
, change
);
1124 /***********************************************************/
1125 /* monitor info on PCI */
1132 static const pci_class_desc pci_class_descriptions
[] =
1134 { 0x0100, "SCSI controller"},
1135 { 0x0101, "IDE controller"},
1136 { 0x0102, "Floppy controller"},
1137 { 0x0103, "IPI controller"},
1138 { 0x0104, "RAID controller"},
1139 { 0x0106, "SATA controller"},
1140 { 0x0107, "SAS controller"},
1141 { 0x0180, "Storage controller"},
1142 { 0x0200, "Ethernet controller"},
1143 { 0x0201, "Token Ring controller"},
1144 { 0x0202, "FDDI controller"},
1145 { 0x0203, "ATM controller"},
1146 { 0x0280, "Network controller"},
1147 { 0x0300, "VGA controller"},
1148 { 0x0301, "XGA controller"},
1149 { 0x0302, "3D controller"},
1150 { 0x0380, "Display controller"},
1151 { 0x0400, "Video controller"},
1152 { 0x0401, "Audio controller"},
1154 { 0x0480, "Multimedia controller"},
1155 { 0x0500, "RAM controller"},
1156 { 0x0501, "Flash controller"},
1157 { 0x0580, "Memory controller"},
1158 { 0x0600, "Host bridge"},
1159 { 0x0601, "ISA bridge"},
1160 { 0x0602, "EISA bridge"},
1161 { 0x0603, "MC bridge"},
1162 { 0x0604, "PCI bridge"},
1163 { 0x0605, "PCMCIA bridge"},
1164 { 0x0606, "NUBUS bridge"},
1165 { 0x0607, "CARDBUS bridge"},
1166 { 0x0608, "RACEWAY bridge"},
1167 { 0x0680, "Bridge"},
1168 { 0x0c03, "USB controller"},
1172 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1173 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1178 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1179 d
= bus
->devices
[devfn
];
1186 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1187 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1189 bus
= pci_find_bus(bus
, bus_num
);
1192 pci_for_each_device_under_bus(bus
, fn
);
1196 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1200 uint64_t addr
, size
;
1202 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1203 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1204 qdict_get_int(device
, "slot"),
1205 qdict_get_int(device
, "function"));
1206 monitor_printf(mon
, " ");
1208 qdict
= qdict_get_qdict(device
, "class_info");
1209 if (qdict_haskey(qdict
, "desc")) {
1210 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1212 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1215 qdict
= qdict_get_qdict(device
, "id");
1216 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1217 qdict_get_int(qdict
, "device"),
1218 qdict_get_int(qdict
, "vendor"));
1220 if (qdict_haskey(device
, "irq")) {
1221 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1222 qdict_get_int(device
, "irq"));
1225 if (qdict_haskey(device
, "pci_bridge")) {
1228 qdict
= qdict_get_qdict(device
, "pci_bridge");
1230 info
= qdict_get_qdict(qdict
, "bus");
1231 monitor_printf(mon
, " BUS %" PRId64
".\n",
1232 qdict_get_int(info
, "number"));
1233 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1234 qdict_get_int(info
, "secondary"));
1235 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1236 qdict_get_int(info
, "subordinate"));
1238 info
= qdict_get_qdict(qdict
, "io_range");
1239 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1240 qdict_get_int(info
, "base"),
1241 qdict_get_int(info
, "limit"));
1243 info
= qdict_get_qdict(qdict
, "memory_range");
1245 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1246 qdict_get_int(info
, "base"),
1247 qdict_get_int(info
, "limit"));
1249 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1250 monitor_printf(mon
, " prefetchable memory range "
1251 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1252 qdict_get_int(info
, "base"),
1253 qdict_get_int(info
, "limit"));
1256 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1257 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1258 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1260 addr
= qdict_get_int(qdict
, "address");
1261 size
= qdict_get_int(qdict
, "size");
1263 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1264 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1265 " [0x%04"FMT_PCIBUS
"].\n",
1266 addr
, addr
+ size
- 1);
1268 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1269 " [0x%08"FMT_PCIBUS
"].\n",
1270 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1271 qdict_get_bool(qdict
, "prefetch") ?
1272 " prefetchable" : "", addr
, addr
+ size
- 1);
1276 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1278 if (qdict_haskey(device
, "pci_bridge")) {
1279 qdict
= qdict_get_qdict(device
, "pci_bridge");
1280 if (qdict_haskey(qdict
, "devices")) {
1282 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1283 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1289 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1291 QListEntry
*bus
, *dev
;
1293 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1294 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1295 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1296 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1301 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1304 const pci_class_desc
*desc
;
1306 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1307 desc
= pci_class_descriptions
;
1308 while (desc
->desc
&& class != desc
->class)
1312 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1315 return qobject_from_jsonf("{ 'class': %d }", class);
1319 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1321 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1322 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1323 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1326 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1329 QList
*regions_list
;
1331 regions_list
= qlist_new();
1333 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1335 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1341 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1342 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1343 "'address': %" PRId64
", "
1344 "'size': %" PRId64
" }",
1345 i
, r
->addr
, r
->size
);
1347 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1349 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1350 "'mem_type_64': %i, 'prefetch': %i, "
1351 "'address': %" PRId64
", "
1352 "'size': %" PRId64
" }",
1354 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1358 qlist_append_obj(regions_list
, obj
);
1361 return QOBJECT(regions_list
);
1364 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1366 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1371 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1374 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1375 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1376 pci_get_regions_list(dev
),
1377 dev
->qdev
.id
? dev
->qdev
.id
: "");
1379 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1380 QDict
*qdict
= qobject_to_qdict(obj
);
1381 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1384 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1385 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1387 QObject
*pci_bridge
;
1389 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1390 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1391 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1392 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1393 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1394 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1395 dev
->config
[PCI_SUBORDINATE_BUS
],
1396 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1397 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1398 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1399 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1400 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1401 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1402 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1403 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1405 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1406 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1409 qdict
= qobject_to_qdict(pci_bridge
);
1410 qdict_put_obj(qdict
, "devices",
1411 pci_get_devices_list(child_bus
,
1412 dev
->config
[PCI_SECONDARY_BUS
]));
1415 qdict
= qobject_to_qdict(obj
);
1416 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1422 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1428 dev_list
= qlist_new();
1430 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1431 dev
= bus
->devices
[devfn
];
1433 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1437 return QOBJECT(dev_list
);
1440 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1442 bus
= pci_find_bus(bus
, bus_num
);
1444 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1445 bus_num
, pci_get_devices_list(bus
, bus_num
));
1451 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1454 struct PCIHostBus
*host
;
1456 bus_list
= qlist_new();
1458 QLIST_FOREACH(host
, &host_buses
, next
) {
1459 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1461 qlist_append_obj(bus_list
, obj
);
1465 *ret_data
= QOBJECT(bus_list
);
1468 static const char * const pci_nic_models
[] = {
1480 static const char * const pci_nic_names
[] = {
1492 /* Initialize a PCI NIC. */
1493 /* FIXME callers should check for failure, but don't */
1494 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1495 const char *default_devaddr
)
1497 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1504 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1508 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1510 error_report("Invalid PCI device address %s for device %s",
1511 devaddr
, pci_nic_names
[i
]);
1515 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1516 dev
= &pci_dev
->qdev
;
1517 qdev_set_nic_properties(dev
, nd
);
1518 if (qdev_init(dev
) < 0)
1523 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1524 const char *default_devaddr
)
1528 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1531 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1545 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1547 pci_update_mappings(d
);
1550 static void pci_bridge_update_mappings(PCIBus
*b
)
1554 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1556 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1557 pci_bridge_update_mappings(child
);
1561 static void pci_bridge_write_config(PCIDevice
*d
,
1562 uint32_t address
, uint32_t val
, int len
)
1564 pci_default_write_config(d
, address
, val
, len
);
1566 if (/* io base/limit */
1567 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1569 /* memory base/limit, prefetchable base/limit and
1570 io base/limit upper 16 */
1571 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1572 PCIBridge
*s
= container_of(d
, PCIBridge
, dev
);
1573 PCIBus
*secondary_bus
= &s
->bus
;
1574 pci_bridge_update_mappings(secondary_bus
);
1578 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1586 if (pci_bus_num(bus
) == bus_num
) {
1591 if (!bus
->parent_dev
/* host pci bridge */ ||
1592 (bus
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1593 bus_num
<= bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1594 for (; bus
; bus
= sec
) {
1595 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1596 assert(sec
->parent_dev
);
1597 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1600 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1601 bus_num
<= sec
->parent_dev
->config
[PCI_SUBORDINATE_BUS
]) {
1611 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1613 bus
= pci_find_bus(bus
, bus_num
);
1618 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1621 static int pci_bridge_initfn(PCIDevice
*dev
)
1623 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1625 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1626 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1628 pci_set_word(dev
->config
+ PCI_STATUS
,
1629 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1630 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1631 dev
->config
[PCI_HEADER_TYPE
] =
1632 (dev
->config
[PCI_HEADER_TYPE
] & PCI_HEADER_TYPE_MULTI_FUNCTION
) |
1633 PCI_HEADER_TYPE_BRIDGE
;
1634 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1635 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1639 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1641 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1642 PCIBus
*bus
= &s
->bus
;
1643 pci_unregister_secondary_bus(bus
);
1647 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, bool multifunction
,
1648 uint16_t vid
, uint16_t did
,
1649 pci_map_irq_fn map_irq
, const char *name
)
1654 dev
= pci_create_multifunction(bus
, devfn
, multifunction
, "pci-bridge");
1655 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1656 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1657 qdev_init_nofail(&dev
->qdev
);
1659 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1660 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1664 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1666 return bus
->parent_dev
;
1669 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1671 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1672 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1676 /* initialize cap_present for pci_is_express() and pci_config_size() */
1677 if (info
->is_express
) {
1678 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1681 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1682 devfn
= pci_dev
->devfn
;
1683 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1684 info
->config_read
, info
->config_write
,
1686 if (pci_dev
== NULL
)
1688 rc
= info
->init(pci_dev
);
1690 do_pci_unregister_device(pci_dev
);
1695 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
)
1696 pci_dev
->romfile
= qemu_strdup(info
->romfile
);
1697 pci_add_option_rom(pci_dev
);
1699 if (qdev
->hotplugged
) {
1700 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
, 1);
1702 int r
= pci_unregister_device(&pci_dev
->qdev
);
1710 static int pci_unplug_device(DeviceState
*qdev
)
1712 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1714 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
, 0);
1717 void pci_qdev_register(PCIDeviceInfo
*info
)
1719 info
->qdev
.init
= pci_qdev_init
;
1720 info
->qdev
.unplug
= pci_unplug_device
;
1721 info
->qdev
.exit
= pci_unregister_device
;
1722 info
->qdev
.bus_info
= &pci_bus_info
;
1723 qdev_register(&info
->qdev
);
1726 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1728 while (info
->qdev
.name
) {
1729 pci_qdev_register(info
);
1734 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1739 dev
= qdev_create(&bus
->qbus
, name
);
1740 qdev_prop_set_uint32(dev
, "addr", devfn
);
1741 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1742 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1745 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1749 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1750 qdev_init_nofail(&dev
->qdev
);
1754 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1756 return pci_create_multifunction(bus
, devfn
, false, name
);
1759 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1761 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1764 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1766 int config_size
= pci_config_size(pdev
);
1767 int offset
= PCI_CONFIG_HEADER_SIZE
;
1769 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1772 else if (i
- offset
+ 1 == size
)
1777 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1782 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1785 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1786 prev
= next
+ PCI_CAP_LIST_NEXT
)
1787 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1795 static void pci_map_option_rom(PCIDevice
*pdev
, int region_num
, pcibus_t addr
, pcibus_t size
, int type
)
1797 cpu_register_physical_memory(addr
, size
, pdev
->rom_offset
);
1800 /* Add an option rom for the device */
1801 static int pci_add_option_rom(PCIDevice
*pdev
)
1810 if (strlen(pdev
->romfile
) == 0)
1813 if (!pdev
->rom_bar
) {
1815 * Load rom via fw_cfg instead of creating a rom bar,
1816 * for 0.11 compatibility.
1818 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1819 if (class == 0x0300) {
1820 rom_add_vga(pdev
->romfile
);
1822 rom_add_option(pdev
->romfile
);
1827 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1829 path
= qemu_strdup(pdev
->romfile
);
1832 size
= get_image_size(path
);
1834 error_report("%s: failed to find romfile \"%s\"",
1835 __FUNCTION__
, pdev
->romfile
);
1838 if (size
& (size
- 1)) {
1839 size
= 1 << qemu_fls(size
);
1842 if (pdev
->qdev
.info
->vmsd
)
1843 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->vmsd
->name
);
1845 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->name
);
1846 pdev
->rom_offset
= qemu_ram_alloc(&pdev
->qdev
, name
, size
);
1848 ptr
= qemu_get_ram_ptr(pdev
->rom_offset
);
1849 load_image(path
, ptr
);
1852 pci_register_bar(pdev
, PCI_ROM_SLOT
, size
,
1853 0, pci_map_option_rom
);
1858 static void pci_del_option_rom(PCIDevice
*pdev
)
1860 if (!pdev
->rom_offset
)
1863 qemu_ram_free(pdev
->rom_offset
);
1864 pdev
->rom_offset
= 0;
1867 /* Reserve space and add capability to the linked list in pci config space */
1868 int pci_add_capability_at_offset(PCIDevice
*pdev
, uint8_t cap_id
,
1869 uint8_t offset
, uint8_t size
)
1871 uint8_t *config
= pdev
->config
+ offset
;
1872 config
[PCI_CAP_LIST_ID
] = cap_id
;
1873 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1874 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1875 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1876 memset(pdev
->used
+ offset
, 0xFF, size
);
1877 /* Make capability read-only by default */
1878 memset(pdev
->wmask
+ offset
, 0, size
);
1879 /* Check capability by default */
1880 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1884 /* Find and reserve space and add capability to the linked list
1885 * in pci config space */
1886 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1888 uint8_t offset
= pci_find_space(pdev
, size
);
1892 return pci_add_capability_at_offset(pdev
, cap_id
, offset
, size
);
1895 /* Unlink capability from the pci config space. */
1896 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1898 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1901 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1902 /* Make capability writeable again */
1903 memset(pdev
->wmask
+ offset
, 0xff, size
);
1904 /* Clear cmask as device-specific registers can't be checked */
1905 memset(pdev
->cmask
+ offset
, 0, size
);
1906 memset(pdev
->used
+ offset
, 0, size
);
1908 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1909 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1912 /* Reserve space for capability at a known offset (to call after load). */
1913 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1915 memset(pdev
->used
+ offset
, 0xff, size
);
1918 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1920 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1923 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1925 PCIDevice
*d
= (PCIDevice
*)dev
;
1926 const pci_class_desc
*desc
;
1931 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1932 desc
= pci_class_descriptions
;
1933 while (desc
->desc
&& class != desc
->class)
1936 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1938 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1941 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1942 "pci id %04x:%04x (sub %04x:%04x)\n",
1944 d
->config
[PCI_SECONDARY_BUS
],
1945 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1946 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1947 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1948 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1949 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1950 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1951 r
= &d
->io_regions
[i
];
1954 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1955 " [0x%"FMT_PCIBUS
"]\n",
1957 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1958 r
->addr
, r
->addr
+ r
->size
- 1);
1962 static char *pcibus_get_dev_path(DeviceState
*dev
)
1964 PCIDevice
*d
= (PCIDevice
*)dev
;
1967 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%x",
1968 pci_find_domain(d
->bus
), d
->config
[PCI_SECONDARY_BUS
],
1969 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
1971 return strdup(path
);
1974 static PCIDeviceInfo bridge_info
= {
1975 .qdev
.name
= "pci-bridge",
1976 .qdev
.size
= sizeof(PCIBridge
),
1977 .init
= pci_bridge_initfn
,
1978 .exit
= pci_bridge_exitfn
,
1979 .config_write
= pci_bridge_write_config
,
1981 .qdev
.props
= (Property
[]) {
1982 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1983 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1984 DEFINE_PROP_END_OF_LIST(),
1988 static void pci_register_devices(void)
1990 pci_qdev_register(&bridge_info
);
1993 device_init(pci_register_devices
)