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arm: replace cpu_arm_init() with cpu_generic_init()
[qemu/kevin.git] / hw / arm / pxa2xx.c
blobb0ac3cfd649a794869f236c9872795f53af556ea
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "qemu-common.h"
13 #include "cpu.h"
14 #include "hw/sysbus.h"
15 #include "hw/arm/pxa.h"
16 #include "sysemu/sysemu.h"
17 #include "hw/char/serial.h"
18 #include "hw/i2c/i2c.h"
19 #include "hw/ssi/ssi.h"
20 #include "chardev/char-fe.h"
21 #include "sysemu/block-backend.h"
22 #include "sysemu/blockdev.h"
23 #include "qemu/cutils.h"
24
25 static struct {
26 hwaddr io_base;
27 int irqn;
28 } pxa255_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0x41600000, PXA25X_PIC_HWUART },
33 { 0, 0 }
34 }, pxa270_serial[] = {
35 { 0x40100000, PXA2XX_PIC_FFUART },
36 { 0x40200000, PXA2XX_PIC_BTUART },
37 { 0x40700000, PXA2XX_PIC_STUART },
38 { 0, 0 }
39 };
40
41 typedef struct PXASSPDef {
42 hwaddr io_base;
43 int irqn;
44 } PXASSPDef;
45
46 #if 0
47 static PXASSPDef pxa250_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0, 0 }
50 };
51 #endif
52
53 static PXASSPDef pxa255_ssp[] = {
54 { 0x41000000, PXA2XX_PIC_SSP },
55 { 0x41400000, PXA25X_PIC_NSSP },
56 { 0, 0 }
57 };
58
59 #if 0
60 static PXASSPDef pxa26x_ssp[] = {
61 { 0x41000000, PXA2XX_PIC_SSP },
62 { 0x41400000, PXA25X_PIC_NSSP },
63 { 0x41500000, PXA26X_PIC_ASSP },
64 { 0, 0 }
65 };
66 #endif
67
68 static PXASSPDef pxa27x_ssp[] = {
69 { 0x41000000, PXA2XX_PIC_SSP },
70 { 0x41700000, PXA27X_PIC_SSP2 },
71 { 0x41900000, PXA2XX_PIC_SSP3 },
72 { 0, 0 }
73 };
74
75 #define PMCR 0x00 /* Power Manager Control register */
76 #define PSSR 0x04 /* Power Manager Sleep Status register */
77 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
78 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
79 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
80 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
81 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
82 #define PCFR 0x1c /* Power Manager General Configuration register */
83 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
84 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
85 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
86 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
87 #define RCSR 0x30 /* Reset Controller Status register */
88 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
89 #define PTSR 0x38 /* Power Manager Standby Configuration register */
90 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
91 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
92 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
93 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
94 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
95 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
96
97 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
98 unsigned size)
99 {
100 PXA2xxState *s = (PXA2xxState *) opaque;
101
102 switch (addr) {
103 case PMCR ... PCMD31:
104 if (addr & 3)
105 goto fail;
106
107 return s->pm_regs[addr >> 2];
108 default:
109 fail:
110 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
111 break;
112 }
113 return 0;
114 }
115
116 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
117 uint64_t value, unsigned size)
118 {
119 PXA2xxState *s = (PXA2xxState *) opaque;
120
121 switch (addr) {
122 case PMCR:
123 /* Clear the write-one-to-clear bits... */
124 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
125 /* ...and set the plain r/w bits */
126 s->pm_regs[addr >> 2] &= ~0x15;
127 s->pm_regs[addr >> 2] |= value & 0x15;
128 break;
129
130 case PSSR: /* Read-clean registers */
131 case RCSR:
132 case PKSR:
133 s->pm_regs[addr >> 2] &= ~value;
134 break;
135
136 default: /* Read-write registers */
137 if (!(addr & 3)) {
138 s->pm_regs[addr >> 2] = value;
139 break;
140 }
141
142 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
143 break;
144 }
145 }
146
147 static const MemoryRegionOps pxa2xx_pm_ops = {
148 .read = pxa2xx_pm_read,
149 .write = pxa2xx_pm_write,
150 .endianness = DEVICE_NATIVE_ENDIAN,
151 };
152
153 static const VMStateDescription vmstate_pxa2xx_pm = {
154 .name = "pxa2xx_pm",
155 .version_id = 0,
156 .minimum_version_id = 0,
157 .fields = (VMStateField[]) {
158 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
159 VMSTATE_END_OF_LIST()
160 }
161 };
162
163 #define CCCR 0x00 /* Core Clock Configuration register */
164 #define CKEN 0x04 /* Clock Enable register */
165 #define OSCC 0x08 /* Oscillator Configuration register */
166 #define CCSR 0x0c /* Core Clock Status register */
167
168 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
169 unsigned size)
170 {
171 PXA2xxState *s = (PXA2xxState *) opaque;
172
173 switch (addr) {
174 case CCCR:
175 case CKEN:
176 case OSCC:
177 return s->cm_regs[addr >> 2];
178
179 case CCSR:
180 return s->cm_regs[CCCR >> 2] | (3 << 28);
181
182 default:
183 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
184 break;
185 }
186 return 0;
187 }
188
189 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
190 uint64_t value, unsigned size)
191 {
192 PXA2xxState *s = (PXA2xxState *) opaque;
193
194 switch (addr) {
195 case CCCR:
196 case CKEN:
197 s->cm_regs[addr >> 2] = value;
198 break;
199
200 case OSCC:
201 s->cm_regs[addr >> 2] &= ~0x6c;
202 s->cm_regs[addr >> 2] |= value & 0x6e;
203 if ((value >> 1) & 1) /* OON */
204 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
205 break;
206
207 default:
208 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
209 break;
210 }
211 }
212
213 static const MemoryRegionOps pxa2xx_cm_ops = {
214 .read = pxa2xx_cm_read,
215 .write = pxa2xx_cm_write,
216 .endianness = DEVICE_NATIVE_ENDIAN,
217 };
218
219 static const VMStateDescription vmstate_pxa2xx_cm = {
220 .name = "pxa2xx_cm",
221 .version_id = 0,
222 .minimum_version_id = 0,
223 .fields = (VMStateField[]) {
224 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
225 VMSTATE_UINT32(clkcfg, PXA2xxState),
226 VMSTATE_UINT32(pmnc, PXA2xxState),
227 VMSTATE_END_OF_LIST()
228 }
229 };
230
231 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
232 {
233 PXA2xxState *s = (PXA2xxState *)ri->opaque;
234 return s->clkcfg;
235 }
236
237 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
238 uint64_t value)
239 {
240 PXA2xxState *s = (PXA2xxState *)ri->opaque;
241 s->clkcfg = value & 0xf;
242 if (value & 2) {
243 printf("%s: CPU frequency change attempt\n", __func__);
244 }
245 }
246
247 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
248 uint64_t value)
249 {
250 PXA2xxState *s = (PXA2xxState *)ri->opaque;
251 static const char *pwrmode[8] = {
252 "Normal", "Idle", "Deep-idle", "Standby",
253 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
254 };
255
256 if (value & 8) {
257 printf("%s: CPU voltage change attempt\n", __func__);
258 }
259 switch (value & 7) {
260 case 0:
261 /* Do nothing */
262 break;
263
264 case 1:
265 /* Idle */
266 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
267 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
268 break;
269 }
270 /* Fall through. */
271
272 case 2:
273 /* Deep-Idle */
274 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
275 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
276 goto message;
277
278 case 3:
279 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
280 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
281 s->cpu->env.cp15.sctlr_ns = 0;
282 s->cpu->env.cp15.cpacr_el1 = 0;
283 s->cpu->env.cp15.ttbr0_el[1] = 0;
284 s->cpu->env.cp15.dacr_ns = 0;
285 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
286 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
287
288 /*
289 * The scratch-pad register is almost universally used
290 * for storing the return address on suspend. For the
291 * lack of a resuming bootloader, perform a jump
292 * directly to that address.
293 */
294 memset(s->cpu->env.regs, 0, 4 * 15);
295 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
296
297 #if 0
298 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
299 cpu_physical_memory_write(0, &buffer, 4);
300 buffer = s->pm_regs[PSPR >> 2];
301 cpu_physical_memory_write(8, &buffer, 4);
302 #endif
303
304 /* Suspend */
305 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
306
307 goto message;
308
309 default:
310 message:
311 printf("%s: machine entered %s mode\n", __func__,
312 pwrmode[value & 7]);
313 }
314 }
315
316 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
317 {
318 PXA2xxState *s = (PXA2xxState *)ri->opaque;
319 return s->pmnc;
320 }
321
322 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
323 uint64_t value)
324 {
325 PXA2xxState *s = (PXA2xxState *)ri->opaque;
326 s->pmnc = value;
327 }
328
329 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
330 {
331 PXA2xxState *s = (PXA2xxState *)ri->opaque;
332 if (s->pmnc & 1) {
333 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
334 } else {
335 return 0;
336 }
337 }
338
339 static const ARMCPRegInfo pxa_cp_reginfo[] = {
340 /* cp14 crm==1: perf registers */
341 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
342 .access = PL1_RW, .type = ARM_CP_IO,
343 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
344 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
345 .access = PL1_RW, .type = ARM_CP_IO,
346 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
347 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
348 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
349 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
350 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
351 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
352 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
353 /* cp14 crm==2: performance count registers */
354 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
356 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
358 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
359 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
360 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
362 /* cp14 crn==6: CLKCFG */
363 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
364 .access = PL1_RW, .type = ARM_CP_IO,
365 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
366 /* cp14 crn==7: PWRMODE */
367 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
368 .access = PL1_RW, .type = ARM_CP_IO,
369 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
370 REGINFO_SENTINEL
371 };
372
373 static void pxa2xx_setup_cp14(PXA2xxState *s)
374 {
375 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
376 }
377
378 #define MDCNFG 0x00 /* SDRAM Configuration register */
379 #define MDREFR 0x04 /* SDRAM Refresh Control register */
380 #define MSC0 0x08 /* Static Memory Control register 0 */
381 #define MSC1 0x0c /* Static Memory Control register 1 */
382 #define MSC2 0x10 /* Static Memory Control register 2 */
383 #define MECR 0x14 /* Expansion Memory Bus Config register */
384 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
385 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
386 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
387 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
388 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
389 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
390 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
391 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
392 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
393 #define ARB_CNTL 0x48 /* Arbiter Control register */
394 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
395 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
396 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
397 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
398 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
399 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
400 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
401
402 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
403 unsigned size)
404 {
405 PXA2xxState *s = (PXA2xxState *) opaque;
406
407 switch (addr) {
408 case MDCNFG ... SA1110:
409 if ((addr & 3) == 0)
410 return s->mm_regs[addr >> 2];
411
412 default:
413 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
414 break;
415 }
416 return 0;
417 }
418
419 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
420 uint64_t value, unsigned size)
421 {
422 PXA2xxState *s = (PXA2xxState *) opaque;
423
424 switch (addr) {
425 case MDCNFG ... SA1110:
426 if ((addr & 3) == 0) {
427 s->mm_regs[addr >> 2] = value;
428 break;
429 }
430
431 default:
432 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
433 break;
434 }
435 }
436
437 static const MemoryRegionOps pxa2xx_mm_ops = {
438 .read = pxa2xx_mm_read,
439 .write = pxa2xx_mm_write,
440 .endianness = DEVICE_NATIVE_ENDIAN,
441 };
442
443 static const VMStateDescription vmstate_pxa2xx_mm = {
444 .name = "pxa2xx_mm",
445 .version_id = 0,
446 .minimum_version_id = 0,
447 .fields = (VMStateField[]) {
448 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
449 VMSTATE_END_OF_LIST()
450 }
451 };
452
453 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
454 #define PXA2XX_SSP(obj) \
455 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
456
457 /* Synchronous Serial Ports */
458 typedef struct {
459 /*< private >*/
460 SysBusDevice parent_obj;
461 /*< public >*/
462
463 MemoryRegion iomem;
464 qemu_irq irq;
465 uint32_t enable;
466 SSIBus *bus;
467
468 uint32_t sscr[2];
469 uint32_t sspsp;
470 uint32_t ssto;
471 uint32_t ssitr;
472 uint32_t sssr;
473 uint8_t sstsa;
474 uint8_t ssrsa;
475 uint8_t ssacd;
476
477 uint32_t rx_fifo[16];
478 uint32_t rx_level;
479 uint32_t rx_start;
480 } PXA2xxSSPState;
481
482 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
483 {
484 PXA2xxSSPState *s = opaque;
485
486 return s->rx_start < sizeof(s->rx_fifo);
487 }
488
489 static const VMStateDescription vmstate_pxa2xx_ssp = {
490 .name = "pxa2xx-ssp",
491 .version_id = 1,
492 .minimum_version_id = 1,
493 .fields = (VMStateField[]) {
494 VMSTATE_UINT32(enable, PXA2xxSSPState),
495 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
496 VMSTATE_UINT32(sspsp, PXA2xxSSPState),
497 VMSTATE_UINT32(ssto, PXA2xxSSPState),
498 VMSTATE_UINT32(ssitr, PXA2xxSSPState),
499 VMSTATE_UINT32(sssr, PXA2xxSSPState),
500 VMSTATE_UINT8(sstsa, PXA2xxSSPState),
501 VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
502 VMSTATE_UINT8(ssacd, PXA2xxSSPState),
503 VMSTATE_UINT32(rx_level, PXA2xxSSPState),
504 VMSTATE_UINT32(rx_start, PXA2xxSSPState),
505 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
506 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
507 VMSTATE_END_OF_LIST()
508 }
509 };
510
511 #define SSCR0 0x00 /* SSP Control register 0 */
512 #define SSCR1 0x04 /* SSP Control register 1 */
513 #define SSSR 0x08 /* SSP Status register */
514 #define SSITR 0x0c /* SSP Interrupt Test register */
515 #define SSDR 0x10 /* SSP Data register */
516 #define SSTO 0x28 /* SSP Time-Out register */
517 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
518 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
519 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
520 #define SSTSS 0x38 /* SSP Time Slot Status register */
521 #define SSACD 0x3c /* SSP Audio Clock Divider register */
522
523 /* Bitfields for above registers */
524 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
525 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
526 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
527 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
528 #define SSCR0_SSE (1 << 7)
529 #define SSCR0_RIM (1 << 22)
530 #define SSCR0_TIM (1 << 23)
531 #define SSCR0_MOD (1U << 31)
532 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
533 #define SSCR1_RIE (1 << 0)
534 #define SSCR1_TIE (1 << 1)
535 #define SSCR1_LBM (1 << 2)
536 #define SSCR1_MWDS (1 << 5)
537 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
538 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
539 #define SSCR1_EFWR (1 << 14)
540 #define SSCR1_PINTE (1 << 18)
541 #define SSCR1_TINTE (1 << 19)
542 #define SSCR1_RSRE (1 << 20)
543 #define SSCR1_TSRE (1 << 21)
544 #define SSCR1_EBCEI (1 << 29)
545 #define SSITR_INT (7 << 5)
546 #define SSSR_TNF (1 << 2)
547 #define SSSR_RNE (1 << 3)
548 #define SSSR_TFS (1 << 5)
549 #define SSSR_RFS (1 << 6)
550 #define SSSR_ROR (1 << 7)
551 #define SSSR_PINT (1 << 18)
552 #define SSSR_TINT (1 << 19)
553 #define SSSR_EOC (1 << 20)
554 #define SSSR_TUR (1 << 21)
555 #define SSSR_BCE (1 << 23)
556 #define SSSR_RW 0x00bc0080
557
558 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
559 {
560 int level = 0;
561
562 level |= s->ssitr & SSITR_INT;
563 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
564 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
565 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
566 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
567 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
568 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
569 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
570 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
571 qemu_set_irq(s->irq, !!level);
572 }
573
574 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
575 {
576 s->sssr &= ~(0xf << 12); /* Clear RFL */
577 s->sssr &= ~(0xf << 8); /* Clear TFL */
578 s->sssr &= ~SSSR_TFS;
579 s->sssr &= ~SSSR_TNF;
580 if (s->enable) {
581 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
582 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
583 s->sssr |= SSSR_RFS;
584 else
585 s->sssr &= ~SSSR_RFS;
586 if (s->rx_level)
587 s->sssr |= SSSR_RNE;
588 else
589 s->sssr &= ~SSSR_RNE;
590 /* TX FIFO is never filled, so it is always in underrun
591 condition if SSP is enabled */
592 s->sssr |= SSSR_TFS;
593 s->sssr |= SSSR_TNF;
594 }
595
596 pxa2xx_ssp_int_update(s);
597 }
598
599 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
600 unsigned size)
601 {
602 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
603 uint32_t retval;
604
605 switch (addr) {
606 case SSCR0:
607 return s->sscr[0];
608 case SSCR1:
609 return s->sscr[1];
610 case SSPSP:
611 return s->sspsp;
612 case SSTO:
613 return s->ssto;
614 case SSITR:
615 return s->ssitr;
616 case SSSR:
617 return s->sssr | s->ssitr;
618 case SSDR:
619 if (!s->enable)
620 return 0xffffffff;
621 if (s->rx_level < 1) {
622 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
623 return 0xffffffff;
624 }
625 s->rx_level --;
626 retval = s->rx_fifo[s->rx_start ++];
627 s->rx_start &= 0xf;
628 pxa2xx_ssp_fifo_update(s);
629 return retval;
630 case SSTSA:
631 return s->sstsa;
632 case SSRSA:
633 return s->ssrsa;
634 case SSTSS:
635 return 0;
636 case SSACD:
637 return s->ssacd;
638 default:
639 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
640 break;
641 }
642 return 0;
643 }
644
645 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
646 uint64_t value64, unsigned size)
647 {
648 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
649 uint32_t value = value64;
650
651 switch (addr) {
652 case SSCR0:
653 s->sscr[0] = value & 0xc7ffffff;
654 s->enable = value & SSCR0_SSE;
655 if (value & SSCR0_MOD)
656 printf("%s: Attempt to use network mode\n", __FUNCTION__);
657 if (s->enable && SSCR0_DSS(value) < 4)
658 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
659 SSCR0_DSS(value));
660 if (!(value & SSCR0_SSE)) {
661 s->sssr = 0;
662 s->ssitr = 0;
663 s->rx_level = 0;
664 }
665 pxa2xx_ssp_fifo_update(s);
666 break;
667
668 case SSCR1:
669 s->sscr[1] = value;
670 if (value & (SSCR1_LBM | SSCR1_EFWR))
671 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
672 pxa2xx_ssp_fifo_update(s);
673 break;
674
675 case SSPSP:
676 s->sspsp = value;
677 break;
678
679 case SSTO:
680 s->ssto = value;
681 break;
682
683 case SSITR:
684 s->ssitr = value & SSITR_INT;
685 pxa2xx_ssp_int_update(s);
686 break;
687
688 case SSSR:
689 s->sssr &= ~(value & SSSR_RW);
690 pxa2xx_ssp_int_update(s);
691 break;
692
693 case SSDR:
694 if (SSCR0_UWIRE(s->sscr[0])) {
695 if (s->sscr[1] & SSCR1_MWDS)
696 value &= 0xffff;
697 else
698 value &= 0xff;
699 } else
700 /* Note how 32bits overflow does no harm here */
701 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
702
703 /* Data goes from here to the Tx FIFO and is shifted out from
704 * there directly to the slave, no need to buffer it.
705 */
706 if (s->enable) {
707 uint32_t readval;
708 readval = ssi_transfer(s->bus, value);
709 if (s->rx_level < 0x10) {
710 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
711 } else {
712 s->sssr |= SSSR_ROR;
713 }
714 }
715 pxa2xx_ssp_fifo_update(s);
716 break;
717
718 case SSTSA:
719 s->sstsa = value;
720 break;
721
722 case SSRSA:
723 s->ssrsa = value;
724 break;
725
726 case SSACD:
727 s->ssacd = value;
728 break;
729
730 default:
731 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
732 break;
733 }
734 }
735
736 static const MemoryRegionOps pxa2xx_ssp_ops = {
737 .read = pxa2xx_ssp_read,
738 .write = pxa2xx_ssp_write,
739 .endianness = DEVICE_NATIVE_ENDIAN,
740 };
741
742 static void pxa2xx_ssp_reset(DeviceState *d)
743 {
744 PXA2xxSSPState *s = PXA2XX_SSP(d);
745
746 s->enable = 0;
747 s->sscr[0] = s->sscr[1] = 0;
748 s->sspsp = 0;
749 s->ssto = 0;
750 s->ssitr = 0;
751 s->sssr = 0;
752 s->sstsa = 0;
753 s->ssrsa = 0;
754 s->ssacd = 0;
755 s->rx_start = s->rx_level = 0;
756 }
757
758 static void pxa2xx_ssp_init(Object *obj)
759 {
760 DeviceState *dev = DEVICE(obj);
761 PXA2xxSSPState *s = PXA2XX_SSP(obj);
762 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
763 sysbus_init_irq(sbd, &s->irq);
764
765 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
766 "pxa2xx-ssp", 0x1000);
767 sysbus_init_mmio(sbd, &s->iomem);
768
769 s->bus = ssi_create_bus(dev, "ssi");
770 }
771
772 /* Real-Time Clock */
773 #define RCNR 0x00 /* RTC Counter register */
774 #define RTAR 0x04 /* RTC Alarm register */
775 #define RTSR 0x08 /* RTC Status register */
776 #define RTTR 0x0c /* RTC Timer Trim register */
777 #define RDCR 0x10 /* RTC Day Counter register */
778 #define RYCR 0x14 /* RTC Year Counter register */
779 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
780 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
781 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
782 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
783 #define SWCR 0x28 /* RTC Stopwatch Counter register */
784 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
785 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
786 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
787 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
788
789 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
790 #define PXA2XX_RTC(obj) \
791 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
792
793 typedef struct {
794 /*< private >*/
795 SysBusDevice parent_obj;
796 /*< public >*/
797
798 MemoryRegion iomem;
799 uint32_t rttr;
800 uint32_t rtsr;
801 uint32_t rtar;
802 uint32_t rdar1;
803 uint32_t rdar2;
804 uint32_t ryar1;
805 uint32_t ryar2;
806 uint32_t swar1;
807 uint32_t swar2;
808 uint32_t piar;
809 uint32_t last_rcnr;
810 uint32_t last_rdcr;
811 uint32_t last_rycr;
812 uint32_t last_swcr;
813 uint32_t last_rtcpicr;
814 int64_t last_hz;
815 int64_t last_sw;
816 int64_t last_pi;
817 QEMUTimer *rtc_hz;
818 QEMUTimer *rtc_rdal1;
819 QEMUTimer *rtc_rdal2;
820 QEMUTimer *rtc_swal1;
821 QEMUTimer *rtc_swal2;
822 QEMUTimer *rtc_pi;
823 qemu_irq rtc_irq;
824 } PXA2xxRTCState;
825
826 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
827 {
828 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
829 }
830
831 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
832 {
833 int64_t rt = qemu_clock_get_ms(rtc_clock);
834 s->last_rcnr += ((rt - s->last_hz) << 15) /
835 (1000 * ((s->rttr & 0xffff) + 1));
836 s->last_rdcr += ((rt - s->last_hz) << 15) /
837 (1000 * ((s->rttr & 0xffff) + 1));
838 s->last_hz = rt;
839 }
840
841 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
842 {
843 int64_t rt = qemu_clock_get_ms(rtc_clock);
844 if (s->rtsr & (1 << 12))
845 s->last_swcr += (rt - s->last_sw) / 10;
846 s->last_sw = rt;
847 }
848
849 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
850 {
851 int64_t rt = qemu_clock_get_ms(rtc_clock);
852 if (s->rtsr & (1 << 15))
853 s->last_swcr += rt - s->last_pi;
854 s->last_pi = rt;
855 }
856
857 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
858 uint32_t rtsr)
859 {
860 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
861 timer_mod(s->rtc_hz, s->last_hz +
862 (((s->rtar - s->last_rcnr) * 1000 *
863 ((s->rttr & 0xffff) + 1)) >> 15));
864 else
865 timer_del(s->rtc_hz);
866
867 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
868 timer_mod(s->rtc_rdal1, s->last_hz +
869 (((s->rdar1 - s->last_rdcr) * 1000 *
870 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
871 else
872 timer_del(s->rtc_rdal1);
873
874 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
875 timer_mod(s->rtc_rdal2, s->last_hz +
876 (((s->rdar2 - s->last_rdcr) * 1000 *
877 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
878 else
879 timer_del(s->rtc_rdal2);
880
881 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
882 timer_mod(s->rtc_swal1, s->last_sw +
883 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
884 else
885 timer_del(s->rtc_swal1);
886
887 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
888 timer_mod(s->rtc_swal2, s->last_sw +
889 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
890 else
891 timer_del(s->rtc_swal2);
892
893 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
894 timer_mod(s->rtc_pi, s->last_pi +
895 (s->piar & 0xffff) - s->last_rtcpicr);
896 else
897 timer_del(s->rtc_pi);
898 }
899
900 static inline void pxa2xx_rtc_hz_tick(void *opaque)
901 {
902 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
903 s->rtsr |= (1 << 0);
904 pxa2xx_rtc_alarm_update(s, s->rtsr);
905 pxa2xx_rtc_int_update(s);
906 }
907
908 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
909 {
910 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
911 s->rtsr |= (1 << 4);
912 pxa2xx_rtc_alarm_update(s, s->rtsr);
913 pxa2xx_rtc_int_update(s);
914 }
915
916 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
917 {
918 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
919 s->rtsr |= (1 << 6);
920 pxa2xx_rtc_alarm_update(s, s->rtsr);
921 pxa2xx_rtc_int_update(s);
922 }
923
924 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
925 {
926 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
927 s->rtsr |= (1 << 8);
928 pxa2xx_rtc_alarm_update(s, s->rtsr);
929 pxa2xx_rtc_int_update(s);
930 }
931
932 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
933 {
934 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
935 s->rtsr |= (1 << 10);
936 pxa2xx_rtc_alarm_update(s, s->rtsr);
937 pxa2xx_rtc_int_update(s);
938 }
939
940 static inline void pxa2xx_rtc_pi_tick(void *opaque)
941 {
942 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
943 s->rtsr |= (1 << 13);
944 pxa2xx_rtc_piupdate(s);
945 s->last_rtcpicr = 0;
946 pxa2xx_rtc_alarm_update(s, s->rtsr);
947 pxa2xx_rtc_int_update(s);
948 }
949
950 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
951 unsigned size)
952 {
953 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
954
955 switch (addr) {
956 case RTTR:
957 return s->rttr;
958 case RTSR:
959 return s->rtsr;
960 case RTAR:
961 return s->rtar;
962 case RDAR1:
963 return s->rdar1;
964 case RDAR2:
965 return s->rdar2;
966 case RYAR1:
967 return s->ryar1;
968 case RYAR2:
969 return s->ryar2;
970 case SWAR1:
971 return s->swar1;
972 case SWAR2:
973 return s->swar2;
974 case PIAR:
975 return s->piar;
976 case RCNR:
977 return s->last_rcnr +
978 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
979 (1000 * ((s->rttr & 0xffff) + 1));
980 case RDCR:
981 return s->last_rdcr +
982 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
983 (1000 * ((s->rttr & 0xffff) + 1));
984 case RYCR:
985 return s->last_rycr;
986 case SWCR:
987 if (s->rtsr & (1 << 12))
988 return s->last_swcr +
989 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
990 else
991 return s->last_swcr;
992 default:
993 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
994 break;
995 }
996 return 0;
997 }
998
999 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1000 uint64_t value64, unsigned size)
1001 {
1002 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1003 uint32_t value = value64;
1004
1005 switch (addr) {
1006 case RTTR:
1007 if (!(s->rttr & (1U << 31))) {
1008 pxa2xx_rtc_hzupdate(s);
1009 s->rttr = value;
1010 pxa2xx_rtc_alarm_update(s, s->rtsr);
1011 }
1012 break;
1013
1014 case RTSR:
1015 if ((s->rtsr ^ value) & (1 << 15))
1016 pxa2xx_rtc_piupdate(s);
1017
1018 if ((s->rtsr ^ value) & (1 << 12))
1019 pxa2xx_rtc_swupdate(s);
1020
1021 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1022 pxa2xx_rtc_alarm_update(s, value);
1023
1024 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1025 pxa2xx_rtc_int_update(s);
1026 break;
1027
1028 case RTAR:
1029 s->rtar = value;
1030 pxa2xx_rtc_alarm_update(s, s->rtsr);
1031 break;
1032
1033 case RDAR1:
1034 s->rdar1 = value;
1035 pxa2xx_rtc_alarm_update(s, s->rtsr);
1036 break;
1037
1038 case RDAR2:
1039 s->rdar2 = value;
1040 pxa2xx_rtc_alarm_update(s, s->rtsr);
1041 break;
1042
1043 case RYAR1:
1044 s->ryar1 = value;
1045 pxa2xx_rtc_alarm_update(s, s->rtsr);
1046 break;
1047
1048 case RYAR2:
1049 s->ryar2 = value;
1050 pxa2xx_rtc_alarm_update(s, s->rtsr);
1051 break;
1052
1053 case SWAR1:
1054 pxa2xx_rtc_swupdate(s);
1055 s->swar1 = value;
1056 s->last_swcr = 0;
1057 pxa2xx_rtc_alarm_update(s, s->rtsr);
1058 break;
1059
1060 case SWAR2:
1061 s->swar2 = value;
1062 pxa2xx_rtc_alarm_update(s, s->rtsr);
1063 break;
1064
1065 case PIAR:
1066 s->piar = value;
1067 pxa2xx_rtc_alarm_update(s, s->rtsr);
1068 break;
1069
1070 case RCNR:
1071 pxa2xx_rtc_hzupdate(s);
1072 s->last_rcnr = value;
1073 pxa2xx_rtc_alarm_update(s, s->rtsr);
1074 break;
1075
1076 case RDCR:
1077 pxa2xx_rtc_hzupdate(s);
1078 s->last_rdcr = value;
1079 pxa2xx_rtc_alarm_update(s, s->rtsr);
1080 break;
1081
1082 case RYCR:
1083 s->last_rycr = value;
1084 break;
1085
1086 case SWCR:
1087 pxa2xx_rtc_swupdate(s);
1088 s->last_swcr = value;
1089 pxa2xx_rtc_alarm_update(s, s->rtsr);
1090 break;
1091
1092 case RTCPICR:
1093 pxa2xx_rtc_piupdate(s);
1094 s->last_rtcpicr = value & 0xffff;
1095 pxa2xx_rtc_alarm_update(s, s->rtsr);
1096 break;
1097
1098 default:
1099 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1100 }
1101 }
1102
1103 static const MemoryRegionOps pxa2xx_rtc_ops = {
1104 .read = pxa2xx_rtc_read,
1105 .write = pxa2xx_rtc_write,
1106 .endianness = DEVICE_NATIVE_ENDIAN,
1107 };
1108
1109 static void pxa2xx_rtc_init(Object *obj)
1110 {
1111 PXA2xxRTCState *s = PXA2XX_RTC(obj);
1112 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1113 struct tm tm;
1114 int wom;
1115
1116 s->rttr = 0x7fff;
1117 s->rtsr = 0;
1118
1119 qemu_get_timedate(&tm, 0);
1120 wom = ((tm.tm_mday - 1) / 7) + 1;
1121
1122 s->last_rcnr = (uint32_t) mktimegm(&tm);
1123 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1124 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1125 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1126 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1127 s->last_swcr = (tm.tm_hour << 19) |
1128 (tm.tm_min << 13) | (tm.tm_sec << 7);
1129 s->last_rtcpicr = 0;
1130 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1131
1132 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1133 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1134 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1135 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1136 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1137 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1138
1139 sysbus_init_irq(dev, &s->rtc_irq);
1140
1141 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
1142 "pxa2xx-rtc", 0x10000);
1143 sysbus_init_mmio(dev, &s->iomem);
1144 }
1145
1146 static void pxa2xx_rtc_pre_save(void *opaque)
1147 {
1148 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1149
1150 pxa2xx_rtc_hzupdate(s);
1151 pxa2xx_rtc_piupdate(s);
1152 pxa2xx_rtc_swupdate(s);
1153 }
1154
1155 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1156 {
1157 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1158
1159 pxa2xx_rtc_alarm_update(s, s->rtsr);
1160
1161 return 0;
1162 }
1163
1164 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1165 .name = "pxa2xx_rtc",
1166 .version_id = 0,
1167 .minimum_version_id = 0,
1168 .pre_save = pxa2xx_rtc_pre_save,
1169 .post_load = pxa2xx_rtc_post_load,
1170 .fields = (VMStateField[]) {
1171 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1172 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1173 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1174 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1175 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1176 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1177 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1178 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1179 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1180 VMSTATE_UINT32(piar, PXA2xxRTCState),
1181 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1182 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1183 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1184 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1185 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1186 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1187 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1188 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1189 VMSTATE_END_OF_LIST(),
1190 },
1191 };
1192
1193 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1194 {
1195 DeviceClass *dc = DEVICE_CLASS(klass);
1196
1197 dc->desc = "PXA2xx RTC Controller";
1198 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1199 }
1200
1201 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1202 .name = TYPE_PXA2XX_RTC,
1203 .parent = TYPE_SYS_BUS_DEVICE,
1204 .instance_size = sizeof(PXA2xxRTCState),
1205 .instance_init = pxa2xx_rtc_init,
1206 .class_init = pxa2xx_rtc_sysbus_class_init,
1207 };
1208
1209 /* I2C Interface */
1210
1211 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1212 #define PXA2XX_I2C_SLAVE(obj) \
1213 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1214
1215 typedef struct PXA2xxI2CSlaveState {
1216 I2CSlave parent_obj;
1217
1218 PXA2xxI2CState *host;
1219 } PXA2xxI2CSlaveState;
1220
1221 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1222 #define PXA2XX_I2C(obj) \
1223 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1224
1225 struct PXA2xxI2CState {
1226 /*< private >*/
1227 SysBusDevice parent_obj;
1228 /*< public >*/
1229
1230 MemoryRegion iomem;
1231 PXA2xxI2CSlaveState *slave;
1232 I2CBus *bus;
1233 qemu_irq irq;
1234 uint32_t offset;
1235 uint32_t region_size;
1236
1237 uint16_t control;
1238 uint16_t status;
1239 uint8_t ibmr;
1240 uint8_t data;
1241 };
1242
1243 #define IBMR 0x80 /* I2C Bus Monitor register */
1244 #define IDBR 0x88 /* I2C Data Buffer register */
1245 #define ICR 0x90 /* I2C Control register */
1246 #define ISR 0x98 /* I2C Status register */
1247 #define ISAR 0xa0 /* I2C Slave Address register */
1248
1249 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1250 {
1251 uint16_t level = 0;
1252 level |= s->status & s->control & (1 << 10); /* BED */
1253 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1254 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1255 level |= s->status & (1 << 9); /* SAD */
1256 qemu_set_irq(s->irq, !!level);
1257 }
1258
1259 /* These are only stubs now. */
1260 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1261 {
1262 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1263 PXA2xxI2CState *s = slave->host;
1264
1265 switch (event) {
1266 case I2C_START_SEND:
1267 s->status |= (1 << 9); /* set SAD */
1268 s->status &= ~(1 << 0); /* clear RWM */
1269 break;
1270 case I2C_START_RECV:
1271 s->status |= (1 << 9); /* set SAD */
1272 s->status |= 1 << 0; /* set RWM */
1273 break;
1274 case I2C_FINISH:
1275 s->status |= (1 << 4); /* set SSD */
1276 break;
1277 case I2C_NACK:
1278 s->status |= 1 << 1; /* set ACKNAK */
1279 break;
1280 }
1281 pxa2xx_i2c_update(s);
1282
1283 return 0;
1284 }
1285
1286 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1287 {
1288 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1289 PXA2xxI2CState *s = slave->host;
1290
1291 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1292 return 0;
1293 }
1294
1295 if (s->status & (1 << 0)) { /* RWM */
1296 s->status |= 1 << 6; /* set ITE */
1297 }
1298 pxa2xx_i2c_update(s);
1299
1300 return s->data;
1301 }
1302
1303 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1304 {
1305 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1306 PXA2xxI2CState *s = slave->host;
1307
1308 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1309 return 1;
1310 }
1311
1312 if (!(s->status & (1 << 0))) { /* RWM */
1313 s->status |= 1 << 7; /* set IRF */
1314 s->data = data;
1315 }
1316 pxa2xx_i2c_update(s);
1317
1318 return 1;
1319 }
1320
1321 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1322 unsigned size)
1323 {
1324 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1325 I2CSlave *slave;
1326
1327 addr -= s->offset;
1328 switch (addr) {
1329 case ICR:
1330 return s->control;
1331 case ISR:
1332 return s->status | (i2c_bus_busy(s->bus) << 2);
1333 case ISAR:
1334 slave = I2C_SLAVE(s->slave);
1335 return slave->address;
1336 case IDBR:
1337 return s->data;
1338 case IBMR:
1339 if (s->status & (1 << 2))
1340 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1341 else
1342 s->ibmr = 0;
1343 return s->ibmr;
1344 default:
1345 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1346 break;
1347 }
1348 return 0;
1349 }
1350
1351 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1352 uint64_t value64, unsigned size)
1353 {
1354 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1355 uint32_t value = value64;
1356 int ack;
1357
1358 addr -= s->offset;
1359 switch (addr) {
1360 case ICR:
1361 s->control = value & 0xfff7;
1362 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1363 /* TODO: slave mode */
1364 if (value & (1 << 0)) { /* START condition */
1365 if (s->data & 1)
1366 s->status |= 1 << 0; /* set RWM */
1367 else
1368 s->status &= ~(1 << 0); /* clear RWM */
1369 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1370 } else {
1371 if (s->status & (1 << 0)) { /* RWM */
1372 s->data = i2c_recv(s->bus);
1373 if (value & (1 << 2)) /* ACKNAK */
1374 i2c_nack(s->bus);
1375 ack = 1;
1376 } else
1377 ack = !i2c_send(s->bus, s->data);
1378 }
1379
1380 if (value & (1 << 1)) /* STOP condition */
1381 i2c_end_transfer(s->bus);
1382
1383 if (ack) {
1384 if (value & (1 << 0)) /* START condition */
1385 s->status |= 1 << 6; /* set ITE */
1386 else
1387 if (s->status & (1 << 0)) /* RWM */
1388 s->status |= 1 << 7; /* set IRF */
1389 else
1390 s->status |= 1 << 6; /* set ITE */
1391 s->status &= ~(1 << 1); /* clear ACKNAK */
1392 } else {
1393 s->status |= 1 << 6; /* set ITE */
1394 s->status |= 1 << 10; /* set BED */
1395 s->status |= 1 << 1; /* set ACKNAK */
1396 }
1397 }
1398 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1399 if (value & (1 << 4)) /* MA */
1400 i2c_end_transfer(s->bus);
1401 pxa2xx_i2c_update(s);
1402 break;
1403
1404 case ISR:
1405 s->status &= ~(value & 0x07f0);
1406 pxa2xx_i2c_update(s);
1407 break;
1408
1409 case ISAR:
1410 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1411 break;
1412
1413 case IDBR:
1414 s->data = value & 0xff;
1415 break;
1416
1417 default:
1418 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1419 }
1420 }
1421
1422 static const MemoryRegionOps pxa2xx_i2c_ops = {
1423 .read = pxa2xx_i2c_read,
1424 .write = pxa2xx_i2c_write,
1425 .endianness = DEVICE_NATIVE_ENDIAN,
1426 };
1427
1428 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1429 .name = "pxa2xx_i2c_slave",
1430 .version_id = 1,
1431 .minimum_version_id = 1,
1432 .fields = (VMStateField[]) {
1433 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1434 VMSTATE_END_OF_LIST()
1435 }
1436 };
1437
1438 static const VMStateDescription vmstate_pxa2xx_i2c = {
1439 .name = "pxa2xx_i2c",
1440 .version_id = 1,
1441 .minimum_version_id = 1,
1442 .fields = (VMStateField[]) {
1443 VMSTATE_UINT16(control, PXA2xxI2CState),
1444 VMSTATE_UINT16(status, PXA2xxI2CState),
1445 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1446 VMSTATE_UINT8(data, PXA2xxI2CState),
1447 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1448 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1449 VMSTATE_END_OF_LIST()
1450 }
1451 };
1452
1453 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1454 {
1455 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1456
1457 k->event = pxa2xx_i2c_event;
1458 k->recv = pxa2xx_i2c_rx;
1459 k->send = pxa2xx_i2c_tx;
1460 }
1461
1462 static const TypeInfo pxa2xx_i2c_slave_info = {
1463 .name = TYPE_PXA2XX_I2C_SLAVE,
1464 .parent = TYPE_I2C_SLAVE,
1465 .instance_size = sizeof(PXA2xxI2CSlaveState),
1466 .class_init = pxa2xx_i2c_slave_class_init,
1467 };
1468
1469 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1470 qemu_irq irq, uint32_t region_size)
1471 {
1472 DeviceState *dev;
1473 SysBusDevice *i2c_dev;
1474 PXA2xxI2CState *s;
1475 I2CBus *i2cbus;
1476
1477 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1478 qdev_prop_set_uint32(dev, "size", region_size + 1);
1479 qdev_prop_set_uint32(dev, "offset", base & region_size);
1480 qdev_init_nofail(dev);
1481
1482 i2c_dev = SYS_BUS_DEVICE(dev);
1483 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1484 sysbus_connect_irq(i2c_dev, 0, irq);
1485
1486 s = PXA2XX_I2C(i2c_dev);
1487 /* FIXME: Should the slave device really be on a separate bus? */
1488 i2cbus = i2c_init_bus(dev, "dummy");
1489 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1490 s->slave = PXA2XX_I2C_SLAVE(dev);
1491 s->slave->host = s;
1492
1493 return s;
1494 }
1495
1496 static void pxa2xx_i2c_initfn(Object *obj)
1497 {
1498 DeviceState *dev = DEVICE(obj);
1499 PXA2xxI2CState *s = PXA2XX_I2C(obj);
1500 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1501
1502 s->bus = i2c_init_bus(dev, NULL);
1503
1504 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
1505 "pxa2xx-i2c", s->region_size);
1506 sysbus_init_mmio(sbd, &s->iomem);
1507 sysbus_init_irq(sbd, &s->irq);
1508 }
1509
1510 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1511 {
1512 return s->bus;
1513 }
1514
1515 static Property pxa2xx_i2c_properties[] = {
1516 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1517 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1518 DEFINE_PROP_END_OF_LIST(),
1519 };
1520
1521 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1522 {
1523 DeviceClass *dc = DEVICE_CLASS(klass);
1524
1525 dc->desc = "PXA2xx I2C Bus Controller";
1526 dc->vmsd = &vmstate_pxa2xx_i2c;
1527 dc->props = pxa2xx_i2c_properties;
1528 }
1529
1530 static const TypeInfo pxa2xx_i2c_info = {
1531 .name = TYPE_PXA2XX_I2C,
1532 .parent = TYPE_SYS_BUS_DEVICE,
1533 .instance_size = sizeof(PXA2xxI2CState),
1534 .instance_init = pxa2xx_i2c_initfn,
1535 .class_init = pxa2xx_i2c_class_init,
1536 };
1537
1538 /* PXA Inter-IC Sound Controller */
1539 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1540 {
1541 i2s->rx_len = 0;
1542 i2s->tx_len = 0;
1543 i2s->fifo_len = 0;
1544 i2s->clk = 0x1a;
1545 i2s->control[0] = 0x00;
1546 i2s->control[1] = 0x00;
1547 i2s->status = 0x00;
1548 i2s->mask = 0x00;
1549 }
1550
1551 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1552 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1553 #define SACR_DREC(val) (val & (1 << 3))
1554 #define SACR_DPRL(val) (val & (1 << 4))
1555
1556 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1557 {
1558 int rfs, tfs;
1559 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1560 !SACR_DREC(i2s->control[1]);
1561 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1562 i2s->enable && !SACR_DPRL(i2s->control[1]);
1563
1564 qemu_set_irq(i2s->rx_dma, rfs);
1565 qemu_set_irq(i2s->tx_dma, tfs);
1566
1567 i2s->status &= 0xe0;
1568 if (i2s->fifo_len < 16 || !i2s->enable)
1569 i2s->status |= 1 << 0; /* TNF */
1570 if (i2s->rx_len)
1571 i2s->status |= 1 << 1; /* RNE */
1572 if (i2s->enable)
1573 i2s->status |= 1 << 2; /* BSY */
1574 if (tfs)
1575 i2s->status |= 1 << 3; /* TFS */
1576 if (rfs)
1577 i2s->status |= 1 << 4; /* RFS */
1578 if (!(i2s->tx_len && i2s->enable))
1579 i2s->status |= i2s->fifo_len << 8; /* TFL */
1580 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1581
1582 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1583 }
1584
1585 #define SACR0 0x00 /* Serial Audio Global Control register */
1586 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1587 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1588 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1589 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1590 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1591 #define SADR 0x80 /* Serial Audio Data register */
1592
1593 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1594 unsigned size)
1595 {
1596 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1597
1598 switch (addr) {
1599 case SACR0:
1600 return s->control[0];
1601 case SACR1:
1602 return s->control[1];
1603 case SASR0:
1604 return s->status;
1605 case SAIMR:
1606 return s->mask;
1607 case SAICR:
1608 return 0;
1609 case SADIV:
1610 return s->clk;
1611 case SADR:
1612 if (s->rx_len > 0) {
1613 s->rx_len --;
1614 pxa2xx_i2s_update(s);
1615 return s->codec_in(s->opaque);
1616 }
1617 return 0;
1618 default:
1619 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1620 break;
1621 }
1622 return 0;
1623 }
1624
1625 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1626 uint64_t value, unsigned size)
1627 {
1628 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1629 uint32_t *sample;
1630
1631 switch (addr) {
1632 case SACR0:
1633 if (value & (1 << 3)) /* RST */
1634 pxa2xx_i2s_reset(s);
1635 s->control[0] = value & 0xff3d;
1636 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1637 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1638 s->codec_out(s->opaque, *sample);
1639 s->status &= ~(1 << 7); /* I2SOFF */
1640 }
1641 if (value & (1 << 4)) /* EFWR */
1642 printf("%s: Attempt to use special function\n", __FUNCTION__);
1643 s->enable = (value & 9) == 1; /* ENB && !RST*/
1644 pxa2xx_i2s_update(s);
1645 break;
1646 case SACR1:
1647 s->control[1] = value & 0x0039;
1648 if (value & (1 << 5)) /* ENLBF */
1649 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1650 if (value & (1 << 4)) /* DPRL */
1651 s->fifo_len = 0;
1652 pxa2xx_i2s_update(s);
1653 break;
1654 case SAIMR:
1655 s->mask = value & 0x0078;
1656 pxa2xx_i2s_update(s);
1657 break;
1658 case SAICR:
1659 s->status &= ~(value & (3 << 5));
1660 pxa2xx_i2s_update(s);
1661 break;
1662 case SADIV:
1663 s->clk = value & 0x007f;
1664 break;
1665 case SADR:
1666 if (s->tx_len && s->enable) {
1667 s->tx_len --;
1668 pxa2xx_i2s_update(s);
1669 s->codec_out(s->opaque, value);
1670 } else if (s->fifo_len < 16) {
1671 s->fifo[s->fifo_len ++] = value;
1672 pxa2xx_i2s_update(s);
1673 }
1674 break;
1675 default:
1676 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1677 }
1678 }
1679
1680 static const MemoryRegionOps pxa2xx_i2s_ops = {
1681 .read = pxa2xx_i2s_read,
1682 .write = pxa2xx_i2s_write,
1683 .endianness = DEVICE_NATIVE_ENDIAN,
1684 };
1685
1686 static const VMStateDescription vmstate_pxa2xx_i2s = {
1687 .name = "pxa2xx_i2s",
1688 .version_id = 0,
1689 .minimum_version_id = 0,
1690 .fields = (VMStateField[]) {
1691 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1692 VMSTATE_UINT32(status, PXA2xxI2SState),
1693 VMSTATE_UINT32(mask, PXA2xxI2SState),
1694 VMSTATE_UINT32(clk, PXA2xxI2SState),
1695 VMSTATE_INT32(enable, PXA2xxI2SState),
1696 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1697 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1698 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1699 VMSTATE_END_OF_LIST()
1700 }
1701 };
1702
1703 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1704 {
1705 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1706 uint32_t *sample;
1707
1708 /* Signal FIFO errors */
1709 if (s->enable && s->tx_len)
1710 s->status |= 1 << 5; /* TUR */
1711 if (s->enable && s->rx_len)
1712 s->status |= 1 << 6; /* ROR */
1713
1714 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1715 * handle the cases where it makes a difference. */
1716 s->tx_len = tx - s->fifo_len;
1717 s->rx_len = rx;
1718 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1719 if (s->enable)
1720 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1721 s->codec_out(s->opaque, *sample);
1722 pxa2xx_i2s_update(s);
1723 }
1724
1725 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1726 hwaddr base,
1727 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1728 {
1729 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1730
1731 s->irq = irq;
1732 s->rx_dma = rx_dma;
1733 s->tx_dma = tx_dma;
1734 s->data_req = pxa2xx_i2s_data_req;
1735
1736 pxa2xx_i2s_reset(s);
1737
1738 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1739 "pxa2xx-i2s", 0x100000);
1740 memory_region_add_subregion(sysmem, base, &s->iomem);
1741
1742 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1743
1744 return s;
1745 }
1746
1747 /* PXA Fast Infra-red Communications Port */
1748 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
1749 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1750
1751 struct PXA2xxFIrState {
1752 /*< private >*/
1753 SysBusDevice parent_obj;
1754 /*< public >*/
1755
1756 MemoryRegion iomem;
1757 qemu_irq irq;
1758 qemu_irq rx_dma;
1759 qemu_irq tx_dma;
1760 uint32_t enable;
1761 CharBackend chr;
1762
1763 uint8_t control[3];
1764 uint8_t status[2];
1765
1766 uint32_t rx_len;
1767 uint32_t rx_start;
1768 uint8_t rx_fifo[64];
1769 };
1770
1771 static void pxa2xx_fir_reset(DeviceState *d)
1772 {
1773 PXA2xxFIrState *s = PXA2XX_FIR(d);
1774
1775 s->control[0] = 0x00;
1776 s->control[1] = 0x00;
1777 s->control[2] = 0x00;
1778 s->status[0] = 0x00;
1779 s->status[1] = 0x00;
1780 s->enable = 0;
1781 }
1782
1783 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1784 {
1785 static const int tresh[4] = { 8, 16, 32, 0 };
1786 int intr = 0;
1787 if ((s->control[0] & (1 << 4)) && /* RXE */
1788 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1789 s->status[0] |= 1 << 4; /* RFS */
1790 else
1791 s->status[0] &= ~(1 << 4); /* RFS */
1792 if (s->control[0] & (1 << 3)) /* TXE */
1793 s->status[0] |= 1 << 3; /* TFS */
1794 else
1795 s->status[0] &= ~(1 << 3); /* TFS */
1796 if (s->rx_len)
1797 s->status[1] |= 1 << 2; /* RNE */
1798 else
1799 s->status[1] &= ~(1 << 2); /* RNE */
1800 if (s->control[0] & (1 << 4)) /* RXE */
1801 s->status[1] |= 1 << 0; /* RSY */
1802 else
1803 s->status[1] &= ~(1 << 0); /* RSY */
1804
1805 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1806 (s->status[0] & (1 << 4)); /* RFS */
1807 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1808 (s->status[0] & (1 << 3)); /* TFS */
1809 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1810 (s->status[0] & (1 << 6)); /* EOC */
1811 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1812 (s->status[0] & (1 << 1)); /* TUR */
1813 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1814
1815 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1816 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1817
1818 qemu_set_irq(s->irq, intr && s->enable);
1819 }
1820
1821 #define ICCR0 0x00 /* FICP Control register 0 */
1822 #define ICCR1 0x04 /* FICP Control register 1 */
1823 #define ICCR2 0x08 /* FICP Control register 2 */
1824 #define ICDR 0x0c /* FICP Data register */
1825 #define ICSR0 0x14 /* FICP Status register 0 */
1826 #define ICSR1 0x18 /* FICP Status register 1 */
1827 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1828
1829 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1830 unsigned size)
1831 {
1832 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1833 uint8_t ret;
1834
1835 switch (addr) {
1836 case ICCR0:
1837 return s->control[0];
1838 case ICCR1:
1839 return s->control[1];
1840 case ICCR2:
1841 return s->control[2];
1842 case ICDR:
1843 s->status[0] &= ~0x01;
1844 s->status[1] &= ~0x72;
1845 if (s->rx_len) {
1846 s->rx_len --;
1847 ret = s->rx_fifo[s->rx_start ++];
1848 s->rx_start &= 63;
1849 pxa2xx_fir_update(s);
1850 return ret;
1851 }
1852 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1853 break;
1854 case ICSR0:
1855 return s->status[0];
1856 case ICSR1:
1857 return s->status[1] | (1 << 3); /* TNF */
1858 case ICFOR:
1859 return s->rx_len;
1860 default:
1861 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1862 break;
1863 }
1864 return 0;
1865 }
1866
1867 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1868 uint64_t value64, unsigned size)
1869 {
1870 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1871 uint32_t value = value64;
1872 uint8_t ch;
1873
1874 switch (addr) {
1875 case ICCR0:
1876 s->control[0] = value;
1877 if (!(value & (1 << 4))) /* RXE */
1878 s->rx_len = s->rx_start = 0;
1879 if (!(value & (1 << 3))) { /* TXE */
1880 /* Nop */
1881 }
1882 s->enable = value & 1; /* ITR */
1883 if (!s->enable)
1884 s->status[0] = 0;
1885 pxa2xx_fir_update(s);
1886 break;
1887 case ICCR1:
1888 s->control[1] = value;
1889 break;
1890 case ICCR2:
1891 s->control[2] = value & 0x3f;
1892 pxa2xx_fir_update(s);
1893 break;
1894 case ICDR:
1895 if (s->control[2] & (1 << 2)) { /* TXP */
1896 ch = value;
1897 } else {
1898 ch = ~value;
1899 }
1900 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
1901 /* XXX this blocks entire thread. Rewrite to use
1902 * qemu_chr_fe_write and background I/O callbacks */
1903 qemu_chr_fe_write_all(&s->chr, &ch, 1);
1904 }
1905 break;
1906 case ICSR0:
1907 s->status[0] &= ~(value & 0x66);
1908 pxa2xx_fir_update(s);
1909 break;
1910 case ICFOR:
1911 break;
1912 default:
1913 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1914 }
1915 }
1916
1917 static const MemoryRegionOps pxa2xx_fir_ops = {
1918 .read = pxa2xx_fir_read,
1919 .write = pxa2xx_fir_write,
1920 .endianness = DEVICE_NATIVE_ENDIAN,
1921 };
1922
1923 static int pxa2xx_fir_is_empty(void *opaque)
1924 {
1925 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1926 return (s->rx_len < 64);
1927 }
1928
1929 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1930 {
1931 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1932 if (!(s->control[0] & (1 << 4))) /* RXE */
1933 return;
1934
1935 while (size --) {
1936 s->status[1] |= 1 << 4; /* EOF */
1937 if (s->rx_len >= 64) {
1938 s->status[1] |= 1 << 6; /* ROR */
1939 break;
1940 }
1941
1942 if (s->control[2] & (1 << 3)) /* RXP */
1943 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1944 else
1945 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1946 }
1947
1948 pxa2xx_fir_update(s);
1949 }
1950
1951 static void pxa2xx_fir_event(void *opaque, int event)
1952 {
1953 }
1954
1955 static void pxa2xx_fir_instance_init(Object *obj)
1956 {
1957 PXA2xxFIrState *s = PXA2XX_FIR(obj);
1958 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1959
1960 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
1961 "pxa2xx-fir", 0x1000);
1962 sysbus_init_mmio(sbd, &s->iomem);
1963 sysbus_init_irq(sbd, &s->irq);
1964 sysbus_init_irq(sbd, &s->rx_dma);
1965 sysbus_init_irq(sbd, &s->tx_dma);
1966 }
1967
1968 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
1969 {
1970 PXA2xxFIrState *s = PXA2XX_FIR(dev);
1971
1972 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
1973 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL,
1974 true);
1975 }
1976
1977 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
1978 {
1979 PXA2xxFIrState *s = opaque;
1980
1981 return s->rx_start < ARRAY_SIZE(s->rx_fifo);
1982 }
1983
1984 static const VMStateDescription pxa2xx_fir_vmsd = {
1985 .name = "pxa2xx-fir",
1986 .version_id = 1,
1987 .minimum_version_id = 1,
1988 .fields = (VMStateField[]) {
1989 VMSTATE_UINT32(enable, PXA2xxFIrState),
1990 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
1991 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
1992 VMSTATE_UINT32(rx_len, PXA2xxFIrState),
1993 VMSTATE_UINT32(rx_start, PXA2xxFIrState),
1994 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
1995 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
1996 VMSTATE_END_OF_LIST()
1997 }
1998 };
1999
2000 static Property pxa2xx_fir_properties[] = {
2001 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2002 DEFINE_PROP_END_OF_LIST(),
2003 };
2004
2005 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2006 {
2007 DeviceClass *dc = DEVICE_CLASS(klass);
2008
2009 dc->realize = pxa2xx_fir_realize;
2010 dc->vmsd = &pxa2xx_fir_vmsd;
2011 dc->props = pxa2xx_fir_properties;
2012 dc->reset = pxa2xx_fir_reset;
2013 }
2014
2015 static const TypeInfo pxa2xx_fir_info = {
2016 .name = TYPE_PXA2XX_FIR,
2017 .parent = TYPE_SYS_BUS_DEVICE,
2018 .instance_size = sizeof(PXA2xxFIrState),
2019 .class_init = pxa2xx_fir_class_init,
2020 .instance_init = pxa2xx_fir_instance_init,
2021 };
2022
2023 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2024 hwaddr base,
2025 qemu_irq irq, qemu_irq rx_dma,
2026 qemu_irq tx_dma,
2027 Chardev *chr)
2028 {
2029 DeviceState *dev;
2030 SysBusDevice *sbd;
2031
2032 dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
2033 qdev_prop_set_chr(dev, "chardev", chr);
2034 qdev_init_nofail(dev);
2035 sbd = SYS_BUS_DEVICE(dev);
2036 sysbus_mmio_map(sbd, 0, base);
2037 sysbus_connect_irq(sbd, 0, irq);
2038 sysbus_connect_irq(sbd, 1, rx_dma);
2039 sysbus_connect_irq(sbd, 2, tx_dma);
2040 return PXA2XX_FIR(dev);
2041 }
2042
2043 static void pxa2xx_reset(void *opaque, int line, int level)
2044 {
2045 PXA2xxState *s = (PXA2xxState *) opaque;
2046
2047 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2048 cpu_reset(CPU(s->cpu));
2049 /* TODO: reset peripherals */
2050 }
2051 }
2052
2053 /* Initialise a PXA270 integrated chip (ARM based core). */
2054 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2055 unsigned int sdram_size, const char *revision)
2056 {
2057 PXA2xxState *s;
2058 int i;
2059 DriveInfo *dinfo;
2060 s = g_new0(PXA2xxState, 1);
2061
2062 if (revision && strncmp(revision, "pxa27", 5)) {
2063 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2064 exit(1);
2065 }
2066 if (!revision)
2067 revision = "pxa270";
2068
2069 s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
2070 if (s->cpu == NULL) {
2071 fprintf(stderr, "Unable to find CPU definition\n");
2072 exit(1);
2073 }
2074 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2075
2076 /* SDRAM & Internal Memory Storage */
2077 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2078 &error_fatal);
2079 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2080 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2081 &error_fatal);
2082 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2083 &s->internal);
2084
2085 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2086
2087 s->dma = pxa27x_dma_init(0x40000000,
2088 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2089
2090 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2091 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2092 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2093 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2094 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2095 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2096 NULL);
2097
2098 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2099
2100 dinfo = drive_get(IF_SD, 0, 0);
2101 if (!dinfo) {
2102 fprintf(stderr, "qemu: missing SecureDigital device\n");
2103 exit(1);
2104 }
2105 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2106 blk_by_legacy_dinfo(dinfo),
2107 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2108 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2109 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2110
2111 for (i = 0; pxa270_serial[i].io_base; i++) {
2112 if (serial_hds[i]) {
2113 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2114 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2115 14857000 / 16, serial_hds[i],
2116 DEVICE_NATIVE_ENDIAN);
2117 } else {
2118 break;
2119 }
2120 }
2121 if (serial_hds[i])
2122 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2123 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2124 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2125 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2126 serial_hds[i]);
2127
2128 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2129 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2130
2131 s->cm_base = 0x41300000;
2132 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2133 s->clkcfg = 0x00000009; /* Turbo mode active */
2134 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2135 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2136 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2137
2138 pxa2xx_setup_cp14(s);
2139
2140 s->mm_base = 0x48000000;
2141 s->mm_regs[MDMRS >> 2] = 0x00020002;
2142 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2143 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2144 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2145 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2146 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2147
2148 s->pm_base = 0x40f00000;
2149 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2150 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2151 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2152
2153 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2154 s->ssp = g_new0(SSIBus *, i);
2155 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2156 DeviceState *dev;
2157 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2158 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2159 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2160 }
2161
2162 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2163 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2164
2165 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2166 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2167
2168 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2169 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2170
2171 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2172 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2173 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2175
2176 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2178 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2179 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2180
2181 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2182 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2183
2184 /* GPIO1 resets the processor */
2185 /* The handler can be overridden by board-specific code */
2186 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2187 return s;
2188 }
2189
2190 /* Initialise a PXA255 integrated chip (ARM based core). */
2191 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2192 {
2193 PXA2xxState *s;
2194 int i;
2195 DriveInfo *dinfo;
2196
2197 s = g_new0(PXA2xxState, 1);
2198
2199 s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
2200 if (s->cpu == NULL) {
2201 fprintf(stderr, "Unable to find CPU definition\n");
2202 exit(1);
2203 }
2204 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2205
2206 /* SDRAM & Internal Memory Storage */
2207 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2208 &error_fatal);
2209 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2210 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2211 PXA2XX_INTERNAL_SIZE, &error_fatal);
2212 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2213 &s->internal);
2214
2215 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2216
2217 s->dma = pxa255_dma_init(0x40000000,
2218 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2219
2220 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2221 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2222 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2223 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2224 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2225 NULL);
2226
2227 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2228
2229 dinfo = drive_get(IF_SD, 0, 0);
2230 if (!dinfo) {
2231 fprintf(stderr, "qemu: missing SecureDigital device\n");
2232 exit(1);
2233 }
2234 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2235 blk_by_legacy_dinfo(dinfo),
2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2237 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2238 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2239
2240 for (i = 0; pxa255_serial[i].io_base; i++) {
2241 if (serial_hds[i]) {
2242 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2243 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2244 14745600 / 16, serial_hds[i],
2245 DEVICE_NATIVE_ENDIAN);
2246 } else {
2247 break;
2248 }
2249 }
2250 if (serial_hds[i])
2251 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2252 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2253 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2254 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2255 serial_hds[i]);
2256
2257 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2259
2260 s->cm_base = 0x41300000;
2261 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */
2262 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */
2263
2264 s->clkcfg = 0x00000009; /* Turbo mode active */
2265 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2266 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2267 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2268
2269 pxa2xx_setup_cp14(s);
2270
2271 s->mm_base = 0x48000000;
2272 s->mm_regs[MDMRS >> 2] = 0x00020002;
2273 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2274 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2275 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2276 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2277 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2278
2279 s->pm_base = 0x40f00000;
2280 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2281 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2282 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2283
2284 for (i = 0; pxa255_ssp[i].io_base; i ++);
2285 s->ssp = g_new0(SSIBus *, i);
2286 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2287 DeviceState *dev;
2288 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2289 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2290 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2291 }
2292
2293 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2294 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2295
2296 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2297 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2298
2299 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2300 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2301
2302 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2303 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2304 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2305 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2306
2307 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2308 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2309 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2310 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2311
2312 /* GPIO1 resets the processor */
2313 /* The handler can be overridden by board-specific code */
2314 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2315 return s;
2316 }
2317
2318 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2319 {
2320 DeviceClass *dc = DEVICE_CLASS(klass);
2321
2322 dc->reset = pxa2xx_ssp_reset;
2323 dc->vmsd = &vmstate_pxa2xx_ssp;
2324 }
2325
2326 static const TypeInfo pxa2xx_ssp_info = {
2327 .name = TYPE_PXA2XX_SSP,
2328 .parent = TYPE_SYS_BUS_DEVICE,
2329 .instance_size = sizeof(PXA2xxSSPState),
2330 .instance_init = pxa2xx_ssp_init,
2331 .class_init = pxa2xx_ssp_class_init,
2332 };
2333
2334 static void pxa2xx_register_types(void)
2335 {
2336 type_register_static(&pxa2xx_i2c_slave_info);
2337 type_register_static(&pxa2xx_ssp_info);
2338 type_register_static(&pxa2xx_i2c_info);
2339 type_register_static(&pxa2xx_rtc_sysbus_info);
2340 type_register_static(&pxa2xx_fir_info);
2341 }
2342
2343 type_init(pxa2xx_register_types)
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