target/mips/internal.h

   1 /*
   2  * MIPS internal definitions and helpers
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #ifndef MIPS_INTERNAL_H
   9 #define MIPS_INTERNAL_H
  10
  11 #include "exec/memattrs.h"
  12 #ifdef CONFIG_TCG
  13 #include "tcg/tcg-internal.h"
  14 #endif
  15
  16 /*
  17  * MMU types, the first four entries have the same layout as the
  18  * CP0C0_MT field.
  19  */
  20 enum mips_mmu_types {
  21     MMU_TYPE_NONE       = 0,
  22     MMU_TYPE_R4000      = 1,    /* Standard TLB */
  23     MMU_TYPE_BAT        = 2,    /* Block Address Translation */
  24     MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
  25     MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
  26     MMU_TYPE_R3000,
  27     MMU_TYPE_R6000,
  28     MMU_TYPE_R8000
  29 };
  30
  31 struct mips_def_t {
  32     const char *name;
  33     int32_t CP0_PRid;
  34     int32_t CP0_Config0;
  35     int32_t CP0_Config1;
  36     int32_t CP0_Config2;
  37     int32_t CP0_Config3;
  38     int32_t CP0_Config4;
  39     int32_t CP0_Config4_rw_bitmask;
  40     int32_t CP0_Config5;
  41     int32_t CP0_Config5_rw_bitmask;
  42     int32_t CP0_Config6;
  43     int32_t CP0_Config6_rw_bitmask;
  44     int32_t CP0_Config7;
  45     int32_t CP0_Config7_rw_bitmask;
  46     target_ulong CP0_LLAddr_rw_bitmask;
  47     int CP0_LLAddr_shift;
  48     int32_t SYNCI_Step;
  49     int32_t CCRes;
  50     int32_t CP0_Status_rw_bitmask;
  51     int32_t CP0_TCStatus_rw_bitmask;
  52     int32_t CP0_SRSCtl;
  53     int32_t CP1_fcr0;
  54     int32_t CP1_fcr31_rw_bitmask;
  55     int32_t CP1_fcr31;
  56     int32_t MSAIR;
  57     int32_t SEGBITS;
  58     int32_t PABITS;
  59     int32_t CP0_SRSConf0_rw_bitmask;
  60     int32_t CP0_SRSConf0;
  61     int32_t CP0_SRSConf1_rw_bitmask;
  62     int32_t CP0_SRSConf1;
  63     int32_t CP0_SRSConf2_rw_bitmask;
  64     int32_t CP0_SRSConf2;
  65     int32_t CP0_SRSConf3_rw_bitmask;
  66     int32_t CP0_SRSConf3;
  67     int32_t CP0_SRSConf4_rw_bitmask;
  68     int32_t CP0_SRSConf4;
  69     int32_t CP0_PageGrain_rw_bitmask;
  70     int32_t CP0_PageGrain;
  71     target_ulong CP0_EBaseWG_rw_bitmask;
  72     uint64_t insn_flags;
  73     enum mips_mmu_types mmu_type;
  74     int32_t SAARP;
  75 };
  76
  77 extern const char regnames[32][4];
  78 extern const char fregnames[32][4];
  79
  80 extern const struct mips_def_t mips_defs[];
  81 extern const int mips_defs_number;
  82
  83 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  84 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  85 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  86 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  87 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  88                                   MMUAccessType access_type,
  89                                   int mmu_idx, uintptr_t retaddr);
  90
  91 #if !defined(CONFIG_USER_ONLY)
  92
  93 typedef struct r4k_tlb_t r4k_tlb_t;
  94 struct r4k_tlb_t {
  95     target_ulong VPN;
  96     uint32_t PageMask;
  97     uint16_t ASID;
  98     uint32_t MMID;
  99     unsigned int G:1;
 100     unsigned int C0:3;
 101     unsigned int C1:3;
 102     unsigned int V0:1;
 103     unsigned int V1:1;
 104     unsigned int D0:1;
 105     unsigned int D1:1;
 106     unsigned int XI0:1;
 107     unsigned int XI1:1;
 108     unsigned int RI0:1;
 109     unsigned int RI1:1;
 110     unsigned int EHINV:1;
 111     uint64_t PFN[2];
 112 };
 113
 114 struct CPUMIPSTLBContext {
 115     uint32_t nb_tlb;
 116     uint32_t tlb_in_use;
 117     int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 118                        target_ulong address, MMUAccessType access_type);
 119     void (*helper_tlbwi)(struct CPUMIPSState *env);
 120     void (*helper_tlbwr)(struct CPUMIPSState *env);
 121     void (*helper_tlbp)(struct CPUMIPSState *env);
 122     void (*helper_tlbr)(struct CPUMIPSState *env);
 123     void (*helper_tlbinv)(struct CPUMIPSState *env);
 124     void (*helper_tlbinvf)(struct CPUMIPSState *env);
 125     union {
 126         struct {
 127             r4k_tlb_t tlb[MIPS_TLB_MAX];
 128         } r4k;
 129     } mmu;
 130 };
 131
 132 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 133                        target_ulong address, MMUAccessType access_type);
 134 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 135                           target_ulong address, MMUAccessType access_type);
 136 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 137                     target_ulong address, MMUAccessType access_type);
 138 void r4k_helper_tlbwi(CPUMIPSState *env);
 139 void r4k_helper_tlbwr(CPUMIPSState *env);
 140 void r4k_helper_tlbp(CPUMIPSState *env);
 141 void r4k_helper_tlbr(CPUMIPSState *env);
 142 void r4k_helper_tlbinv(CPUMIPSState *env);
 143 void r4k_helper_tlbinvf(CPUMIPSState *env);
 144 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 145 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 146
 147 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 148                                     vaddr addr, unsigned size,
 149                                     MMUAccessType access_type,
 150                                     int mmu_idx, MemTxAttrs attrs,
 151                                     MemTxResult response, uintptr_t retaddr);
 152 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
 153                                   MMUAccessType access_type, uintptr_t retaddr);
 154 #endif
 155
 156 #define cpu_signal_handler cpu_mips_signal_handler
 157
 158 #ifndef CONFIG_USER_ONLY
 159 extern const VMStateDescription vmstate_mips_cpu;
 160 #endif
 161
 162 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 163 {
 164     return (env->CP0_Status & (1 << CP0St_IE)) &&
 165         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 166         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 167         !(env->hflags & MIPS_HFLAG_DM) &&
 168         /*
 169          * Note that the TCStatus IXMT field is initialized to zero,
 170          * and only MT capable cores can set it to one. So we don't
 171          * need to check for MT capabilities here.
 172          */
 173         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 174 }
 175
 176 /* Check if there is pending and not masked out interrupt */
 177 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 178 {
 179     int32_t pending;
 180     int32_t status;
 181     bool r;
 182
 183     pending = env->CP0_Cause & CP0Ca_IP_mask;
 184     status = env->CP0_Status & CP0Ca_IP_mask;
 185
 186     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 187         /*
 188          * A MIPS configured with a vectorizing external interrupt controller
 189          * will feed a vector into the Cause pending lines. The core treats
 190          * the status lines as a vector level, not as individual masks.
 191          */
 192         r = pending > status;
 193     } else {
 194         /*
 195          * A MIPS configured with compatibility or VInt (Vectored Interrupts)
 196          * treats the pending lines as individual interrupt lines, the status
 197          * lines are individual masks.
 198          */
 199         r = (pending & status) != 0;
 200     }
 201     return r;
 202 }
 203
 204 void mips_tcg_init(void);
 205
 206 void msa_reset(CPUMIPSState *env);
 207
 208 /* cp0_timer.c */
 209 uint32_t cpu_mips_get_count(CPUMIPSState *env);
 210 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 211 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 212 void cpu_mips_start_count(CPUMIPSState *env);
 213 void cpu_mips_stop_count(CPUMIPSState *env);
 214
 215 /* helper.c */
 216 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 217
 218 /* op_helper.c */
 219 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 220
 221 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
 222 {
 223     env->active_tc.PC = value & ~(target_ulong)1;
 224     if (value & 1) {
 225         env->hflags |= MIPS_HFLAG_M16;
 226     } else {
 227         env->hflags &= ~(MIPS_HFLAG_M16);
 228     }
 229 }
 230
 231 static inline void restore_pamask(CPUMIPSState *env)
 232 {
 233     if (env->hflags & MIPS_HFLAG_ELPA) {
 234         env->PAMask = (1ULL << env->PABITS) - 1;
 235     } else {
 236         env->PAMask = PAMASK_BASE;
 237     }
 238 }
 239
 240 static inline int mips_vpe_active(CPUMIPSState *env)
 241 {
 242     int active = 1;
 243
 244     /* Check that the VPE is enabled.  */
 245     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 246         active = 0;
 247     }
 248     /* Check that the VPE is activated.  */
 249     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 250         active = 0;
 251     }
 252
 253     /*
 254      * Now verify that there are active thread contexts in the VPE.
 255      *
 256      * This assumes the CPU model will internally reschedule threads
 257      * if the active one goes to sleep. If there are no threads available
 258      * the active one will be in a sleeping state, and we can turn off
 259      * the entire VPE.
 260      */
 261     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 262         /* TC is not activated.  */
 263         active = 0;
 264     }
 265     if (env->active_tc.CP0_TCHalt & 1) {
 266         /* TC is in halt state.  */
 267         active = 0;
 268     }
 269
 270     return active;
 271 }
 272
 273 static inline int mips_vp_active(CPUMIPSState *env)
 274 {
 275     CPUState *other_cs = first_cpu;
 276
 277     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 278     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 279         return 1;
 280     }
 281
 282     /* Check if the virtual processor is disabled due to a DVP */
 283     CPU_FOREACH(other_cs) {
 284         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 285         if ((&other_cpu->env != env) &&
 286             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 287             return 0;
 288         }
 289     }
 290     return 1;
 291 }
 292
 293 static inline void compute_hflags(CPUMIPSState *env)
 294 {
 295     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 296                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 297                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 298                      MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
 299                      MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 300     if (env->CP0_Status & (1 << CP0St_ERL)) {
 301         env->hflags |= MIPS_HFLAG_ERL;
 302     }
 303     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 304         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 305         !(env->hflags & MIPS_HFLAG_DM)) {
 306         env->hflags |= (env->CP0_Status >> CP0St_KSU) &
 307                        MIPS_HFLAG_KSU;
 308     }
 309 #if defined(TARGET_MIPS64)
 310     if ((env->insn_flags & ISA_MIPS3) &&
 311         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 312          (env->CP0_Status & (1 << CP0St_PX)) ||
 313          (env->CP0_Status & (1 << CP0St_UX)))) {
 314         env->hflags |= MIPS_HFLAG_64;
 315     }
 316
 317     if (!(env->insn_flags & ISA_MIPS3)) {
 318         env->hflags |= MIPS_HFLAG_AWRAP;
 319     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 320                !(env->CP0_Status & (1 << CP0St_UX))) {
 321         env->hflags |= MIPS_HFLAG_AWRAP;
 322     } else if (env->insn_flags & ISA_MIPS_R6) {
 323         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 324         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 325              !(env->CP0_Status & (1 << CP0St_SX))) ||
 326             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 327              !(env->CP0_Status & (1 << CP0St_KX)))) {
 328             env->hflags |= MIPS_HFLAG_AWRAP;
 329         }
 330     }
 331 #endif
 332     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 333          !(env->insn_flags & ISA_MIPS_R6)) ||
 334         !(env->hflags & MIPS_HFLAG_KSU)) {
 335         env->hflags |= MIPS_HFLAG_CP0;
 336     }
 337     if (env->CP0_Status & (1 << CP0St_CU1)) {
 338         env->hflags |= MIPS_HFLAG_FPU;
 339     }
 340     if (env->CP0_Status & (1 << CP0St_FR)) {
 341         env->hflags |= MIPS_HFLAG_F64;
 342     }
 343     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 344         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 345         env->hflags |= MIPS_HFLAG_SBRI;
 346     }
 347     if (env->insn_flags & ASE_DSP_R3) {
 348         /*
 349          * Our cpu supports DSP R3 ASE, so enable
 350          * access to DSP R3 resources.
 351          */
 352         if (env->CP0_Status & (1 << CP0St_MX)) {
 353             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 354                            MIPS_HFLAG_DSP_R3;
 355         }
 356     } else if (env->insn_flags & ASE_DSP_R2) {
 357         /*
 358          * Our cpu supports DSP R2 ASE, so enable
 359          * access to DSP R2 resources.
 360          */
 361         if (env->CP0_Status & (1 << CP0St_MX)) {
 362             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
 363         }
 364
 365     } else if (env->insn_flags & ASE_DSP) {
 366         /*
 367          * Our cpu supports DSP ASE, so enable
 368          * access to DSP resources.
 369          */
 370         if (env->CP0_Status & (1 << CP0St_MX)) {
 371             env->hflags |= MIPS_HFLAG_DSP;
 372         }
 373
 374     }
 375     if (env->insn_flags & ISA_MIPS_R2) {
 376         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 377             env->hflags |= MIPS_HFLAG_COP1X;
 378         }
 379     } else if (env->insn_flags & ISA_MIPS_R1) {
 380         if (env->hflags & MIPS_HFLAG_64) {
 381             env->hflags |= MIPS_HFLAG_COP1X;
 382         }
 383     } else if (env->insn_flags & ISA_MIPS4) {
 384         /*
 385          * All supported MIPS IV CPUs use the XX (CU3) to enable
 386          * and disable the MIPS IV extensions to the MIPS III ISA.
 387          * Some other MIPS IV CPUs ignore the bit, so the check here
 388          * would be too restrictive for them.
 389          */
 390         if (env->CP0_Status & (1U << CP0St_CU3)) {
 391             env->hflags |= MIPS_HFLAG_COP1X;
 392         }
 393     }
 394     if (ase_msa_available(env)) {
 395         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 396             env->hflags |= MIPS_HFLAG_MSA;
 397         }
 398     }
 399     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 400         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 401             env->hflags |= MIPS_HFLAG_FRE;
 402         }
 403     }
 404     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 405         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 406             env->hflags |= MIPS_HFLAG_ELPA;
 407         }
 408     }
 409 }
 410
 411 void cpu_mips_tlb_flush(CPUMIPSState *env);
 412 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 413 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 414 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 415
 416 const char *mips_exception_name(int32_t exception);
 417
 418 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 419                                           int error_code, uintptr_t pc);
 420
 421 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 422                                                     uint32_t exception,
 423                                                     uintptr_t pc)
 424 {
 425     do_raise_exception_err(env, exception, 0, pc);
 426 }
 427
 428 #endif