2 * QEMU MIPS Jazz support
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/mips/mips.h"
27 #include "hw/mips/cpudevs.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/isa/isa.h"
31 #include "hw/block/fdc.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/arch_init.h"
34 #include "hw/boards.h"
36 #include "hw/scsi/esp.h"
37 #include "hw/mips/bios.h"
38 #include "hw/loader.h"
39 #include "hw/timer/mc146818rtc.h"
40 #include "hw/timer/i8254.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/block-backend.h"
43 #include "hw/sysbus.h"
44 #include "exec/address-spaces.h"
45 #include "sysemu/qtest.h"
46 #include "qemu/error-report.h"
54 static void main_cpu_reset(void *opaque
)
56 MIPSCPU
*cpu
= opaque
;
61 static uint64_t rtc_read(void *opaque
, hwaddr addr
, unsigned size
)
64 address_space_read(&address_space_memory
, 0x90000071, &val
, 1);
68 static void rtc_write(void *opaque
, hwaddr addr
,
69 uint64_t val
, unsigned size
)
71 uint8_t buf
= val
& 0xff;
72 address_space_write(&address_space_memory
, 0x90000071, &buf
, 1);
75 static const MemoryRegionOps rtc_ops
= {
78 .endianness
= DEVICE_NATIVE_ENDIAN
,
81 static uint64_t dma_dummy_read(void *opaque
, hwaddr addr
,
84 /* Nothing to do. That is only to ensure that
85 * the current DMA acknowledge cycle is completed. */
89 static void dma_dummy_write(void *opaque
, hwaddr addr
,
90 uint64_t val
, unsigned size
)
92 /* Nothing to do. That is only to ensure that
93 * the current DMA acknowledge cycle is completed. */
96 static const MemoryRegionOps dma_dummy_ops
= {
97 .read
= dma_dummy_read
,
98 .write
= dma_dummy_write
,
99 .endianness
= DEVICE_NATIVE_ENDIAN
,
102 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
103 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
105 static void cpu_request_exit(void *opaque
, int irq
, int level
)
107 CPUState
*cpu
= current_cpu
;
114 static CPUUnassignedAccess real_do_unassigned_access
;
115 static void mips_jazz_do_unassigned_access(CPUState
*cpu
, hwaddr addr
,
116 bool is_write
, bool is_exec
,
117 int opaque
, unsigned size
)
120 /* ignore invalid access (ie do not raise exception) */
123 (*real_do_unassigned_access
)(cpu
, addr
, is_write
, is_exec
, opaque
, size
);
126 static void mips_jazz_init(MachineState
*machine
,
127 enum jazz_model_e jazz_model
)
129 MemoryRegion
*address_space
= get_system_memory();
130 const char *cpu_model
= machine
->cpu_model
;
136 qemu_irq
*rc4030
, *i8259
;
139 MemoryRegion
*isa_mem
= g_new(MemoryRegion
, 1);
140 MemoryRegion
*isa_io
= g_new(MemoryRegion
, 1);
141 MemoryRegion
*rtc
= g_new(MemoryRegion
, 1);
142 MemoryRegion
*i8042
= g_new(MemoryRegion
, 1);
143 MemoryRegion
*dma_dummy
= g_new(MemoryRegion
, 1);
146 SysBusDevice
*sysbus
;
149 DriveInfo
*fds
[MAX_FD
];
150 qemu_irq esp_reset
, dma_enable
;
151 qemu_irq
*cpu_exit_irq
;
152 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
153 MemoryRegion
*bios
= g_new(MemoryRegion
, 1);
154 MemoryRegion
*bios2
= g_new(MemoryRegion
, 1);
157 if (cpu_model
== NULL
) {
161 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
165 cpu
= cpu_mips_init(cpu_model
);
167 fprintf(stderr
, "Unable to find CPU definition\n");
171 qemu_register_reset(main_cpu_reset
, cpu
);
173 /* Chipset returns 0 in invalid reads and do not raise data exceptions.
174 * However, we can't simply add a global memory region to catch
175 * everything, as memory core directly call unassigned_mem_read/write
176 * on some invalid accesses, which call do_unassigned_access on the
177 * CPU, which raise an exception.
178 * Handle that case by hijacking the do_unassigned_access method on
179 * the CPU, and do not raise exceptions for data access. */
180 cc
= CPU_GET_CLASS(cpu
);
181 real_do_unassigned_access
= cc
->do_unassigned_access
;
182 cc
->do_unassigned_access
= mips_jazz_do_unassigned_access
;
185 memory_region_init_ram(ram
, NULL
, "mips_jazz.ram", machine
->ram_size
,
187 vmstate_register_ram_global(ram
);
188 memory_region_add_subregion(address_space
, 0, ram
);
190 memory_region_init_ram(bios
, NULL
, "mips_jazz.bios", MAGNUM_BIOS_SIZE
,
192 vmstate_register_ram_global(bios
);
193 memory_region_set_readonly(bios
, true);
194 memory_region_init_alias(bios2
, NULL
, "mips_jazz.bios", bios
,
195 0, MAGNUM_BIOS_SIZE
);
196 memory_region_add_subregion(address_space
, 0x1fc00000LL
, bios
);
197 memory_region_add_subregion(address_space
, 0xfff00000LL
, bios2
);
199 /* load the BIOS image. */
200 if (bios_name
== NULL
)
201 bios_name
= BIOS_FILENAME
;
202 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
204 bios_size
= load_image_targphys(filename
, 0xfff00000LL
,
210 if ((bios_size
< 0 || bios_size
> MAGNUM_BIOS_SIZE
) && !qtest_enabled()) {
211 error_report("Could not load MIPS bios '%s'", bios_name
);
215 /* Init CPU internal devices */
216 cpu_mips_irq_init_cpu(env
);
217 cpu_mips_clock_init(env
);
220 rc4030_opaque
= rc4030_init(env
->irq
[6], env
->irq
[3], &rc4030
, &dmas
,
222 memory_region_init_io(dma_dummy
, NULL
, &dma_dummy_ops
, NULL
, "dummy_dma", 0x1000);
223 memory_region_add_subregion(address_space
, 0x8000d000, dma_dummy
);
225 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
226 memory_region_init(isa_io
, NULL
, "isa-io", 0x00010000);
227 memory_region_init(isa_mem
, NULL
, "isa-mem", 0x01000000);
228 memory_region_add_subregion(address_space
, 0x90000000, isa_io
);
229 memory_region_add_subregion(address_space
, 0x91000000, isa_mem
);
230 isa_bus
= isa_bus_new(NULL
, isa_mem
, isa_io
);
233 i8259
= i8259_init(isa_bus
, env
->irq
[4]);
234 isa_bus_irqs(isa_bus
, i8259
);
235 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
236 DMA_init(0, cpu_exit_irq
);
237 pit
= pit_init(isa_bus
, 0x40, 0, NULL
);
238 pcspk_init(isa_bus
, pit
);
241 switch (jazz_model
) {
243 dev
= qdev_create(NULL
, "sysbus-g364");
244 qdev_init_nofail(dev
);
245 sysbus
= SYS_BUS_DEVICE(dev
);
246 sysbus_mmio_map(sysbus
, 0, 0x60080000);
247 sysbus_mmio_map(sysbus
, 1, 0x40000000);
248 sysbus_connect_irq(sysbus
, 0, rc4030
[3]);
250 /* Simple ROM, so user doesn't have to provide one */
251 MemoryRegion
*rom_mr
= g_new(MemoryRegion
, 1);
252 memory_region_init_ram(rom_mr
, NULL
, "g364fb.rom", 0x80000,
254 vmstate_register_ram_global(rom_mr
);
255 memory_region_set_readonly(rom_mr
, true);
256 uint8_t *rom
= memory_region_get_ram_ptr(rom_mr
);
257 memory_region_add_subregion(address_space
, 0x60000000, rom_mr
);
258 rom
[0] = 0x10; /* Mips G364 */
262 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
268 /* Network controller */
269 for (n
= 0; n
< nb_nics
; n
++) {
272 nd
->model
= g_strdup("dp83932");
273 if (strcmp(nd
->model
, "dp83932") == 0) {
274 dp83932_init(nd
, 0x80001000, 2, get_system_memory(), rc4030
[4],
275 rc4030_opaque
, rc4030_dma_memory_rw
);
277 } else if (is_help_option(nd
->model
)) {
278 fprintf(stderr
, "qemu: Supported NICs: dp83932\n");
281 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd
->model
);
287 esp_init(0x80002000, 0,
288 rc4030_dma_read
, rc4030_dma_write
, dmas
[0],
289 rc4030
[5], &esp_reset
, &dma_enable
);
292 if (drive_get_max_bus(IF_FLOPPY
) >= MAX_FD
) {
293 fprintf(stderr
, "qemu: too many floppy drives\n");
296 for (n
= 0; n
< MAX_FD
; n
++) {
297 fds
[n
] = drive_get(IF_FLOPPY
, 0, n
);
299 fdctrl_init_sysbus(rc4030
[1], 0, 0x80003000, fds
);
301 /* Real time clock */
302 rtc_init(isa_bus
, 1980, NULL
);
303 memory_region_init_io(rtc
, NULL
, &rtc_ops
, NULL
, "rtc", 0x1000);
304 memory_region_add_subregion(address_space
, 0x80004000, rtc
);
306 /* Keyboard (i8042) */
307 i8042_mm_init(rc4030
[6], rc4030
[7], i8042
, 0x1000, 0x1);
308 memory_region_add_subregion(address_space
, 0x80005000, i8042
);
312 serial_mm_init(address_space
, 0x80006000, 0, rc4030
[8], 8000000/16,
313 serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
316 serial_mm_init(address_space
, 0x80007000, 0, rc4030
[9], 8000000/16,
317 serial_hds
[1], DEVICE_NATIVE_ENDIAN
);
322 parallel_mm_init(address_space
, 0x80008000, 0, rc4030
[0],
325 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
328 dev
= qdev_create(NULL
, "ds1225y");
329 qdev_init_nofail(dev
);
330 sysbus
= SYS_BUS_DEVICE(dev
);
331 sysbus_mmio_map(sysbus
, 0, 0x80009000);
334 sysbus_create_simple("jazz-led", 0x8000f000, NULL
);
338 void mips_magnum_init(MachineState
*machine
)
340 mips_jazz_init(machine
, JAZZ_MAGNUM
);
344 void mips_pica61_init(MachineState
*machine
)
346 mips_jazz_init(machine
, JAZZ_PICA61
);
349 static QEMUMachine mips_magnum_machine
= {
351 .desc
= "MIPS Magnum",
352 .init
= mips_magnum_init
,
353 .block_default_type
= IF_SCSI
,
356 static QEMUMachine mips_pica61_machine
= {
358 .desc
= "Acer Pica 61",
359 .init
= mips_pica61_init
,
360 .block_default_type
= IF_SCSI
,
363 static void mips_jazz_machine_init(void)
365 qemu_register_machine(&mips_magnum_machine
);
366 qemu_register_machine(&mips_pica61_machine
);
369 machine_init(mips_jazz_machine_init
);