target-ppc/excp_helper.c

   1 /*
   2  *  PowerPC exception emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #include "helper_regs.h"
  26
  27 //#define DEBUG_OP
  28 //#define DEBUG_SOFTWARE_TLB
  29 //#define DEBUG_EXCEPTIONS
  30
  31 #ifdef DEBUG_EXCEPTIONS
  32 #  define LOG_EXCP(...) qemu_log(__VA_ARGS__)
  33 #else
  34 #  define LOG_EXCP(...) do { } while (0)
  35 #endif
  36
  37 /*****************************************************************************/
  38 /* PowerPC Hypercall emulation */
  39
  40 void (*cpu_ppc_hypercall)(PowerPCCPU *);
  41
  42 /*****************************************************************************/
  43 /* Exception processing */
  44 #if defined(CONFIG_USER_ONLY)
  45 void ppc_cpu_do_interrupt(CPUState *cs)
  46 {
  47     PowerPCCPU *cpu = POWERPC_CPU(cs);
  48     CPUPPCState *env = &cpu->env;
  49
  50     cs->exception_index = POWERPC_EXCP_NONE;
  51     env->error_code = 0;
  52 }
  53
  54 static void ppc_hw_interrupt(CPUPPCState *env)
  55 {
  56     CPUState *cs = CPU(ppc_env_get_cpu(env));
  57
  58     cs->exception_index = POWERPC_EXCP_NONE;
  59     env->error_code = 0;
  60 }
  61 #else /* defined(CONFIG_USER_ONLY) */
  62 static inline void dump_syscall(CPUPPCState *env)
  63 {
  64     qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
  65                   " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
  66                   " nip=" TARGET_FMT_lx "\n",
  67                   ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
  68                   ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
  69                   ppc_dump_gpr(env, 6), env->nip);
  70 }
  71
  72 /* Note that this function should be greatly optimized
  73  * when called with a constant excp, from ppc_hw_interrupt
  74  */
  75 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
  76 {
  77     CPUState *cs = CPU(cpu);
  78     CPUPPCState *env = &cpu->env;
  79     target_ulong msr, new_msr, vector;
  80     int srr0, srr1, asrr0, asrr1, lev, ail;
  81     bool lpes0;
  82
  83     qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
  84                   " => %08x (%02x)\n", env->nip, excp, env->error_code);
  85
  86     /* new srr1 value excluding must-be-zero bits */
  87     if (excp_model == POWERPC_EXCP_BOOKE) {
  88         msr = env->msr;
  89     } else {
  90         msr = env->msr & ~0x783f0000ULL;
  91     }
  92
  93     /* new interrupt handler msr preserves existing HV and ME unless
  94      * explicitly overriden
  95      */
  96     new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
  97
  98     /* target registers */
  99     srr0 = SPR_SRR0;
 100     srr1 = SPR_SRR1;
 101     asrr0 = -1;
 102     asrr1 = -1;
 103
 104     /* Exception targetting modifiers
 105      *
 106      * LPES0 is supported on POWER7/8
 107      * LPES1 is not supported (old iSeries mode)
 108      *
 109      * On anything else, we behave as if LPES0 is 1
 110      * (externals don't alter MSR:HV)
 111      *
 112      * AIL is initialized here but can be cleared by
 113      * selected exceptions
 114      */
 115 #if defined(TARGET_PPC64)
 116     if (excp_model == POWERPC_EXCP_POWER7 ||
 117         excp_model == POWERPC_EXCP_POWER8) {
 118         lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 119         if (excp_model == POWERPC_EXCP_POWER8) {
 120             ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
 121         } else {
 122             ail = 0;
 123         }
 124     } else
 125 #endif /* defined(TARGET_PPC64) */
 126     {
 127         lpes0 = true;
 128         ail = 0;
 129     }
 130
 131     switch (excp) {
 132     case POWERPC_EXCP_NONE:
 133         /* Should never happen */
 134         return;
 135     case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
 136         switch (excp_model) {
 137         case POWERPC_EXCP_40x:
 138             srr0 = SPR_40x_SRR2;
 139             srr1 = SPR_40x_SRR3;
 140             break;
 141         case POWERPC_EXCP_BOOKE:
 142             srr0 = SPR_BOOKE_CSRR0;
 143             srr1 = SPR_BOOKE_CSRR1;
 144             break;
 145         case POWERPC_EXCP_G2:
 146             break;
 147         default:
 148             goto excp_invalid;
 149         }
 150         goto store_next;
 151     case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
 152         if (msr_me == 0) {
 153             /* Machine check exception is not enabled.
 154              * Enter checkstop state.
 155              */
 156             fprintf(stderr, "Machine check while not allowed. "
 157                     "Entering checkstop state\n");
 158             if (qemu_log_separate()) {
 159                 qemu_log("Machine check while not allowed. "
 160                         "Entering checkstop state\n");
 161             }
 162             cs->halted = 1;
 163             cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 164         }
 165         new_msr |= (target_ulong)MSR_HVB;
 166         ail = 0;
 167
 168         /* machine check exceptions don't have ME set */
 169         new_msr &= ~((target_ulong)1 << MSR_ME);
 170
 171         /* XXX: should also have something loaded in DAR / DSISR */
 172         switch (excp_model) {
 173         case POWERPC_EXCP_40x:
 174             srr0 = SPR_40x_SRR2;
 175             srr1 = SPR_40x_SRR3;
 176             break;
 177         case POWERPC_EXCP_BOOKE:
 178             /* FIXME: choose one or the other based on CPU type */
 179             srr0 = SPR_BOOKE_MCSRR0;
 180             srr1 = SPR_BOOKE_MCSRR1;
 181             asrr0 = SPR_BOOKE_CSRR0;
 182             asrr1 = SPR_BOOKE_CSRR1;
 183             break;
 184         default:
 185             break;
 186         }
 187         goto store_next;
 188     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
 189         LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
 190                  "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
 191         goto store_next;
 192     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
 193         LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
 194                  "\n", msr, env->nip);
 195         msr |= env->error_code;
 196         goto store_next;
 197     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
 198         cs = CPU(cpu);
 199
 200         if (!lpes0) {
 201             new_msr |= (target_ulong)MSR_HVB;
 202             new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 203             srr0 = SPR_HSRR0;
 204             srr1 = SPR_HSRR1;
 205         }
 206         if (env->mpic_proxy) {
 207             /* IACK the IRQ on delivery */
 208             env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
 209         }
 210         goto store_next;
 211     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
 212         /* XXX: this is false */
 213         /* Get rS/rD and rA from faulting opcode */
 214         env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4))
 215                                 & 0x03FF0000) >> 16;
 216         goto store_next;
 217     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
 218         switch (env->error_code & ~0xF) {
 219         case POWERPC_EXCP_FP:
 220             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
 221                 LOG_EXCP("Ignore floating point exception\n");
 222                 cs->exception_index = POWERPC_EXCP_NONE;
 223                 env->error_code = 0;
 224                 return;
 225             }
 226             msr |= 0x00100000;
 227             if (msr_fe0 == msr_fe1) {
 228                 goto store_next;
 229             }
 230             msr |= 0x00010000;
 231             break;
 232         case POWERPC_EXCP_INVAL:
 233             LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
 234             msr |= 0x00080000;
 235             env->spr[SPR_BOOKE_ESR] = ESR_PIL;
 236             break;
 237         case POWERPC_EXCP_PRIV:
 238             msr |= 0x00040000;
 239             env->spr[SPR_BOOKE_ESR] = ESR_PPR;
 240             break;
 241         case POWERPC_EXCP_TRAP:
 242             msr |= 0x00020000;
 243             env->spr[SPR_BOOKE_ESR] = ESR_PTR;
 244             break;
 245         default:
 246             /* Should never occur */
 247             cpu_abort(cs, "Invalid program exception %d. Aborting\n",
 248                       env->error_code);
 249             break;
 250         }
 251         goto store_current;
 252     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
 253         goto store_current;
 254     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
 255         dump_syscall(env);
 256         lev = env->error_code;
 257
 258         /* "PAPR mode" built-in hypercall emulation */
 259         if ((lev == 1) && cpu_ppc_hypercall) {
 260             cpu_ppc_hypercall(cpu);
 261             return;
 262         }
 263         if (lev == 1) {
 264             new_msr |= (target_ulong)MSR_HVB;
 265         }
 266         goto store_next;
 267     case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
 268         goto store_current;
 269     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
 270         goto store_next;
 271     case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
 272         /* FIT on 4xx */
 273         LOG_EXCP("FIT exception\n");
 274         goto store_next;
 275     case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
 276         LOG_EXCP("WDT exception\n");
 277         switch (excp_model) {
 278         case POWERPC_EXCP_BOOKE:
 279             srr0 = SPR_BOOKE_CSRR0;
 280             srr1 = SPR_BOOKE_CSRR1;
 281             break;
 282         default:
 283             break;
 284         }
 285         goto store_next;
 286     case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
 287         goto store_next;
 288     case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
 289         goto store_next;
 290     case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
 291         switch (excp_model) {
 292         case POWERPC_EXCP_BOOKE:
 293             /* FIXME: choose one or the other based on CPU type */
 294             srr0 = SPR_BOOKE_DSRR0;
 295             srr1 = SPR_BOOKE_DSRR1;
 296             asrr0 = SPR_BOOKE_CSRR0;
 297             asrr1 = SPR_BOOKE_CSRR1;
 298             break;
 299         default:
 300             break;
 301         }
 302         /* XXX: TODO */
 303         cpu_abort(cs, "Debug exception is not implemented yet !\n");
 304         goto store_next;
 305     case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
 306         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 307         goto store_current;
 308     case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
 309         /* XXX: TODO */
 310         cpu_abort(cs, "Embedded floating point data exception "
 311                   "is not implemented yet !\n");
 312         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 313         goto store_next;
 314     case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
 315         /* XXX: TODO */
 316         cpu_abort(cs, "Embedded floating point round exception "
 317                   "is not implemented yet !\n");
 318         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 319         goto store_next;
 320     case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
 321         /* XXX: TODO */
 322         cpu_abort(cs,
 323                   "Performance counter exception is not implemented yet !\n");
 324         goto store_next;
 325     case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
 326         goto store_next;
 327     case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
 328         srr0 = SPR_BOOKE_CSRR0;
 329         srr1 = SPR_BOOKE_CSRR1;
 330         goto store_next;
 331     case POWERPC_EXCP_RESET:     /* System reset exception                   */
 332         if (msr_pow) {
 333             /* indicate that we resumed from power save mode */
 334             msr |= 0x10000;
 335         } else {
 336             new_msr &= ~((target_ulong)1 << MSR_ME);
 337         }
 338
 339         new_msr |= (target_ulong)MSR_HVB;
 340         ail = 0;
 341         goto store_next;
 342     case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
 343         goto store_next;
 344     case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
 345         goto store_next;
 346     case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
 347         srr0 = SPR_HSRR0;
 348         srr1 = SPR_HSRR1;
 349         new_msr |= (target_ulong)MSR_HVB;
 350         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 351         goto store_next;
 352     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
 353         goto store_next;
 354     case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
 355         srr0 = SPR_HSRR0;
 356         srr1 = SPR_HSRR1;
 357         new_msr |= (target_ulong)MSR_HVB;
 358         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 359         goto store_next;
 360     case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
 361         srr0 = SPR_HSRR0;
 362         srr1 = SPR_HSRR1;
 363         new_msr |= (target_ulong)MSR_HVB;
 364         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 365         goto store_next;
 366     case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
 367         srr0 = SPR_HSRR0;
 368         srr1 = SPR_HSRR1;
 369         new_msr |= (target_ulong)MSR_HVB;
 370         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 371         goto store_next;
 372     case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
 373         srr0 = SPR_HSRR0;
 374         srr1 = SPR_HSRR1;
 375         new_msr |= (target_ulong)MSR_HVB;
 376         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 377         goto store_next;
 378     case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
 379         goto store_current;
 380     case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
 381         goto store_current;
 382     case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
 383         goto store_current;
 384     case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
 385         LOG_EXCP("PIT exception\n");
 386         goto store_next;
 387     case POWERPC_EXCP_IO:        /* IO error exception                       */
 388         /* XXX: TODO */
 389         cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
 390         goto store_next;
 391     case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
 392         /* XXX: TODO */
 393         cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
 394         goto store_next;
 395     case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
 396         /* XXX: TODO */
 397         cpu_abort(cs, "602 emulation trap exception "
 398                   "is not implemented yet !\n");
 399         goto store_next;
 400     case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
 401         switch (excp_model) {
 402         case POWERPC_EXCP_602:
 403         case POWERPC_EXCP_603:
 404         case POWERPC_EXCP_603E:
 405         case POWERPC_EXCP_G2:
 406             goto tlb_miss_tgpr;
 407         case POWERPC_EXCP_7x5:
 408             goto tlb_miss;
 409         case POWERPC_EXCP_74xx:
 410             goto tlb_miss_74xx;
 411         default:
 412             cpu_abort(cs, "Invalid instruction TLB miss exception\n");
 413             break;
 414         }
 415         break;
 416     case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
 417         switch (excp_model) {
 418         case POWERPC_EXCP_602:
 419         case POWERPC_EXCP_603:
 420         case POWERPC_EXCP_603E:
 421         case POWERPC_EXCP_G2:
 422             goto tlb_miss_tgpr;
 423         case POWERPC_EXCP_7x5:
 424             goto tlb_miss;
 425         case POWERPC_EXCP_74xx:
 426             goto tlb_miss_74xx;
 427         default:
 428             cpu_abort(cs, "Invalid data load TLB miss exception\n");
 429             break;
 430         }
 431         break;
 432     case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
 433         switch (excp_model) {
 434         case POWERPC_EXCP_602:
 435         case POWERPC_EXCP_603:
 436         case POWERPC_EXCP_603E:
 437         case POWERPC_EXCP_G2:
 438         tlb_miss_tgpr:
 439             /* Swap temporary saved registers with GPRs */
 440             if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
 441                 new_msr |= (target_ulong)1 << MSR_TGPR;
 442                 hreg_swap_gpr_tgpr(env);
 443             }
 444             goto tlb_miss;
 445         case POWERPC_EXCP_7x5:
 446         tlb_miss:
 447 #if defined(DEBUG_SOFTWARE_TLB)
 448             if (qemu_log_enabled()) {
 449                 const char *es;
 450                 target_ulong *miss, *cmp;
 451                 int en;
 452
 453                 if (excp == POWERPC_EXCP_IFTLB) {
 454                     es = "I";
 455                     en = 'I';
 456                     miss = &env->spr[SPR_IMISS];
 457                     cmp = &env->spr[SPR_ICMP];
 458                 } else {
 459                     if (excp == POWERPC_EXCP_DLTLB) {
 460                         es = "DL";
 461                     } else {
 462                         es = "DS";
 463                     }
 464                     en = 'D';
 465                     miss = &env->spr[SPR_DMISS];
 466                     cmp = &env->spr[SPR_DCMP];
 467                 }
 468                 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 469                          TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
 470                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 471                          env->spr[SPR_HASH1], env->spr[SPR_HASH2],
 472                          env->error_code);
 473             }
 474 #endif
 475             msr |= env->crf[0] << 28;
 476             msr |= env->error_code; /* key, D/I, S/L bits */
 477             /* Set way using a LRU mechanism */
 478             msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
 479             break;
 480         case POWERPC_EXCP_74xx:
 481         tlb_miss_74xx:
 482 #if defined(DEBUG_SOFTWARE_TLB)
 483             if (qemu_log_enabled()) {
 484                 const char *es;
 485                 target_ulong *miss, *cmp;
 486                 int en;
 487
 488                 if (excp == POWERPC_EXCP_IFTLB) {
 489                     es = "I";
 490                     en = 'I';
 491                     miss = &env->spr[SPR_TLBMISS];
 492                     cmp = &env->spr[SPR_PTEHI];
 493                 } else {
 494                     if (excp == POWERPC_EXCP_DLTLB) {
 495                         es = "DL";
 496                     } else {
 497                         es = "DS";
 498                     }
 499                     en = 'D';
 500                     miss = &env->spr[SPR_TLBMISS];
 501                     cmp = &env->spr[SPR_PTEHI];
 502                 }
 503                 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 504                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 505                          env->error_code);
 506             }
 507 #endif
 508             msr |= env->error_code; /* key bit */
 509             break;
 510         default:
 511             cpu_abort(cs, "Invalid data store TLB miss exception\n");
 512             break;
 513         }
 514         goto store_next;
 515     case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
 516         /* XXX: TODO */
 517         cpu_abort(cs, "Floating point assist exception "
 518                   "is not implemented yet !\n");
 519         goto store_next;
 520     case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
 521         /* XXX: TODO */
 522         cpu_abort(cs, "DABR exception is not implemented yet !\n");
 523         goto store_next;
 524     case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
 525         /* XXX: TODO */
 526         cpu_abort(cs, "IABR exception is not implemented yet !\n");
 527         goto store_next;
 528     case POWERPC_EXCP_SMI:       /* System management interrupt              */
 529         /* XXX: TODO */
 530         cpu_abort(cs, "SMI exception is not implemented yet !\n");
 531         goto store_next;
 532     case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
 533         /* XXX: TODO */
 534         cpu_abort(cs, "Thermal management exception "
 535                   "is not implemented yet !\n");
 536         goto store_next;
 537     case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
 538         /* XXX: TODO */
 539         cpu_abort(cs,
 540                   "Performance counter exception is not implemented yet !\n");
 541         goto store_next;
 542     case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
 543         /* XXX: TODO */
 544         cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
 545         goto store_next;
 546     case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
 547         /* XXX: TODO */
 548         cpu_abort(cs,
 549                   "970 soft-patch exception is not implemented yet !\n");
 550         goto store_next;
 551     case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
 552         /* XXX: TODO */
 553         cpu_abort(cs,
 554                   "970 maintenance exception is not implemented yet !\n");
 555         goto store_next;
 556     case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
 557         /* XXX: TODO */
 558         cpu_abort(cs, "Maskable external exception "
 559                   "is not implemented yet !\n");
 560         goto store_next;
 561     case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
 562         /* XXX: TODO */
 563         cpu_abort(cs, "Non maskable external exception "
 564                   "is not implemented yet !\n");
 565         goto store_next;
 566     default:
 567     excp_invalid:
 568         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
 569         break;
 570     store_current:
 571         /* save current instruction location */
 572         env->spr[srr0] = env->nip - 4;
 573         break;
 574     store_next:
 575         /* save next instruction location */
 576         env->spr[srr0] = env->nip;
 577         break;
 578     }
 579     /* Save MSR */
 580     env->spr[srr1] = msr;
 581
 582     /* Sanity check */
 583     if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) {
 584         cpu_abort(cs, "Trying to deliver HV exception %d with "
 585                   "no HV support\n", excp);
 586     }
 587
 588     /* If any alternate SRR register are defined, duplicate saved values */
 589     if (asrr0 != -1) {
 590         env->spr[asrr0] = env->spr[srr0];
 591     }
 592     if (asrr1 != -1) {
 593         env->spr[asrr1] = env->spr[srr1];
 594     }
 595
 596     /* Sort out endianness of interrupt, this differs depending on the
 597      * CPU, the HV mode, etc...
 598      */
 599 #ifdef TARGET_PPC64
 600     if (excp_model == POWERPC_EXCP_POWER7) {
 601         if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
 602             new_msr |= (target_ulong)1 << MSR_LE;
 603         }
 604     } else if (excp_model == POWERPC_EXCP_POWER8) {
 605         if (new_msr & MSR_HVB) {
 606             if (env->spr[SPR_HID0] & HID0_HILE) {
 607                 new_msr |= (target_ulong)1 << MSR_LE;
 608             }
 609         } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
 610             new_msr |= (target_ulong)1 << MSR_LE;
 611         }
 612     } else if (msr_ile) {
 613         new_msr |= (target_ulong)1 << MSR_LE;
 614     }
 615 #else
 616     if (msr_ile) {
 617         new_msr |= (target_ulong)1 << MSR_LE;
 618     }
 619 #endif
 620
 621     /* Jump to handler */
 622     vector = env->excp_vectors[excp];
 623     if (vector == (target_ulong)-1ULL) {
 624         cpu_abort(cs, "Raised an exception without defined vector %d\n",
 625                   excp);
 626     }
 627     vector |= env->excp_prefix;
 628
 629     /* AIL only works if there is no HV transition and we are running with
 630      * translations enabled
 631      */
 632     if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
 633         ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
 634         ail = 0;
 635     }
 636     /* Handle AIL */
 637     if (ail) {
 638         new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
 639         switch(ail) {
 640         case AIL_0001_8000:
 641             vector |= 0x18000;
 642             break;
 643         case AIL_C000_0000_0000_4000:
 644             vector |= 0xc000000000004000ull;
 645             break;
 646         default:
 647             cpu_abort(cs, "Invalid AIL combination %d\n", ail);
 648             break;
 649         }
 650     }
 651
 652 #if defined(TARGET_PPC64)
 653     if (excp_model == POWERPC_EXCP_BOOKE) {
 654         if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
 655             /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
 656             new_msr |= (target_ulong)1 << MSR_CM;
 657         } else {
 658             vector = (uint32_t)vector;
 659         }
 660     } else {
 661         if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
 662             vector = (uint32_t)vector;
 663         } else {
 664             new_msr |= (target_ulong)1 << MSR_SF;
 665         }
 666     }
 667 #endif
 668     /* We don't use hreg_store_msr here as already have treated
 669      * any special case that could occur. Just store MSR and update hflags
 670      *
 671      * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
 672      * will prevent setting of the HV bit which some exceptions might need
 673      * to do.
 674      */
 675     env->msr = new_msr & env->msr_mask;
 676     hreg_compute_hflags(env);
 677     env->nip = vector;
 678     /* Reset exception state */
 679     cs->exception_index = POWERPC_EXCP_NONE;
 680     env->error_code = 0;
 681
 682     /* Any interrupt is context synchronizing, check if TCG TLB
 683      * needs a delayed flush on ppc64
 684      */
 685     check_tlb_flush(env);
 686 }
 687
 688 void ppc_cpu_do_interrupt(CPUState *cs)
 689 {
 690     PowerPCCPU *cpu = POWERPC_CPU(cs);
 691     CPUPPCState *env = &cpu->env;
 692
 693     powerpc_excp(cpu, env->excp_model, cs->exception_index);
 694 }
 695
 696 static void ppc_hw_interrupt(CPUPPCState *env)
 697 {
 698     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 699     int hdice;
 700 #if 0
 701     CPUState *cs = CPU(cpu);
 702
 703     qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
 704                   __func__, env, env->pending_interrupts,
 705                   cs->interrupt_request, (int)msr_me, (int)msr_ee);
 706 #endif
 707     /* External reset */
 708     if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
 709         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
 710         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 711         return;
 712     }
 713     /* Machine check exception */
 714     if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
 715         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
 716         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
 717         return;
 718     }
 719 #if 0 /* TODO */
 720     /* External debug exception */
 721     if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
 722         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
 723         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
 724         return;
 725     }
 726 #endif
 727     if (0) {
 728         /* XXX: find a suitable condition to enable the hypervisor mode */
 729         hdice = env->spr[SPR_LPCR] & 1;
 730     } else {
 731         hdice = 0;
 732     }
 733     if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
 734         /* Hypervisor decrementer exception */
 735         if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
 736             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
 737             return;
 738         }
 739     }
 740     if (msr_ce != 0) {
 741         /* External critical interrupt */
 742         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
 743             /* Taking a critical external interrupt does not clear the external
 744              * critical interrupt status
 745              */
 746 #if 0
 747             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
 748 #endif
 749             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
 750             return;
 751         }
 752     }
 753     if (msr_ee != 0) {
 754         /* Watchdog timer on embedded PowerPC */
 755         if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
 756             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
 757             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
 758             return;
 759         }
 760         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
 761             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
 762             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
 763             return;
 764         }
 765         /* Fixed interval timer on embedded PowerPC */
 766         if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
 767             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
 768             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
 769             return;
 770         }
 771         /* Programmable interval timer on embedded PowerPC */
 772         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
 773             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
 774             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
 775             return;
 776         }
 777         /* Decrementer exception */
 778         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
 779             if (ppc_decr_clear_on_delivery(env)) {
 780                 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
 781             }
 782             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
 783             return;
 784         }
 785         /* External interrupt */
 786         if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
 787             /* Taking an external interrupt does not clear the external
 788              * interrupt status
 789              */
 790 #if 0
 791             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
 792 #endif
 793             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
 794             return;
 795         }
 796         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
 797             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
 798             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
 799             return;
 800         }
 801         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
 802             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
 803             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
 804             return;
 805         }
 806         /* Thermal interrupt */
 807         if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
 808             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
 809             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
 810             return;
 811         }
 812     }
 813 }
 814
 815 void ppc_cpu_do_system_reset(CPUState *cs)
 816 {
 817     PowerPCCPU *cpu = POWERPC_CPU(cs);
 818     CPUPPCState *env = &cpu->env;
 819
 820     powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 821 }
 822 #endif /* !CONFIG_USER_ONLY */
 823
 824 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 825 {
 826     PowerPCCPU *cpu = POWERPC_CPU(cs);
 827     CPUPPCState *env = &cpu->env;
 828
 829     if (interrupt_request & CPU_INTERRUPT_HARD) {
 830         ppc_hw_interrupt(env);
 831         if (env->pending_interrupts == 0) {
 832             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
 833         }
 834         return true;
 835     }
 836     return false;
 837 }
 838
 839 #if defined(DEBUG_OP)
 840 static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
 841 {
 842     qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
 843              TARGET_FMT_lx "\n", RA, msr);
 844 }
 845 #endif
 846
 847 /*****************************************************************************/
 848 /* Exceptions processing helpers */
 849
 850 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
 851                                 uint32_t error_code)
 852 {
 853     CPUState *cs = CPU(ppc_env_get_cpu(env));
 854
 855 #if 0
 856     printf("Raise exception %3x code : %d\n", exception, error_code);
 857 #endif
 858     cs->exception_index = exception;
 859     env->error_code = error_code;
 860     cpu_loop_exit(cs);
 861 }
 862
 863 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
 864 {
 865     helper_raise_exception_err(env, exception, 0);
 866 }
 867
 868 #if !defined(CONFIG_USER_ONLY)
 869 void helper_store_msr(CPUPPCState *env, target_ulong val)
 870 {
 871     CPUState *cs;
 872
 873     val = hreg_store_msr(env, val, 0);
 874     if (val != 0) {
 875         cs = CPU(ppc_env_get_cpu(env));
 876         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 877         helper_raise_exception(env, val);
 878     }
 879 }
 880
 881 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
 882 {
 883     CPUState *cs = CPU(ppc_env_get_cpu(env));
 884
 885     /* MSR:POW cannot be set by any form of rfi */
 886     msr &= ~(1ULL << MSR_POW);
 887
 888 #if defined(TARGET_PPC64)
 889     /* Switching to 32-bit ? Crop the nip */
 890     if (!msr_is_64bit(env, msr)) {
 891         nip = (uint32_t)nip;
 892     }
 893 #else
 894     nip = (uint32_t)nip;
 895 #endif
 896     /* XXX: beware: this is false if VLE is supported */
 897     env->nip = nip & ~((target_ulong)0x00000003);
 898     hreg_store_msr(env, msr, 1);
 899 #if defined(DEBUG_OP)
 900     cpu_dump_rfi(env->nip, env->msr);
 901 #endif
 902     /* No need to raise an exception here,
 903      * as rfi is always the last insn of a TB
 904      */
 905     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 906
 907     /* Context synchronizing: check if TCG TLB needs flush */
 908     check_tlb_flush(env);
 909 }
 910
 911 void helper_rfi(CPUPPCState *env)
 912 {
 913     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
 914 }
 915
 916 #define MSR_BOOK3S_MASK
 917 #if defined(TARGET_PPC64)
 918 void helper_rfid(CPUPPCState *env)
 919 {
 920     /* The architeture defines a number of rules for which bits
 921      * can change but in practice, we handle this in hreg_store_msr()
 922      * which will be called by do_rfi(), so there is no need to filter
 923      * here
 924      */
 925     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
 926 }
 927
 928 void helper_hrfid(CPUPPCState *env)
 929 {
 930     do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
 931 }
 932 #endif
 933
 934 /*****************************************************************************/
 935 /* Embedded PowerPC specific helpers */
 936 void helper_40x_rfci(CPUPPCState *env)
 937 {
 938     do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
 939 }
 940
 941 void helper_rfci(CPUPPCState *env)
 942 {
 943     do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
 944 }
 945
 946 void helper_rfdi(CPUPPCState *env)
 947 {
 948     /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
 949     do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
 950 }
 951
 952 void helper_rfmci(CPUPPCState *env)
 953 {
 954     /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
 955     do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
 956 }
 957 #endif
 958
 959 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
 960                uint32_t flags)
 961 {
 962     if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
 963                   ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
 964                   ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
 965                   ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
 966                   ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
 967         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 968                                    POWERPC_EXCP_TRAP);
 969     }
 970 }
 971
 972 #if defined(TARGET_PPC64)
 973 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
 974                uint32_t flags)
 975 {
 976     if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
 977                   ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
 978                   ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
 979                   ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
 980                   ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
 981         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 982                                    POWERPC_EXCP_TRAP);
 983     }
 984 }
 985 #endif
 986
 987 #if !defined(CONFIG_USER_ONLY)
 988 /*****************************************************************************/
 989 /* PowerPC 601 specific instructions (POWER bridge) */
 990
 991 void helper_rfsvc(CPUPPCState *env)
 992 {
 993     do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
 994 }
 995
 996 /* Embedded.Processor Control */
 997 static int dbell2irq(target_ulong rb)
 998 {
 999     int msg = rb & DBELL_TYPE_MASK;
1000     int irq = -1;
1001
1002     switch (msg) {
1003     case DBELL_TYPE_DBELL:
1004         irq = PPC_INTERRUPT_DOORBELL;
1005         break;
1006     case DBELL_TYPE_DBELL_CRIT:
1007         irq = PPC_INTERRUPT_CDOORBELL;
1008         break;
1009     case DBELL_TYPE_G_DBELL:
1010     case DBELL_TYPE_G_DBELL_CRIT:
1011     case DBELL_TYPE_G_DBELL_MC:
1012         /* XXX implement */
1013     default:
1014         break;
1015     }
1016
1017     return irq;
1018 }
1019
1020 void helper_msgclr(CPUPPCState *env, target_ulong rb)
1021 {
1022     int irq = dbell2irq(rb);
1023
1024     if (irq < 0) {
1025         return;
1026     }
1027
1028     env->pending_interrupts &= ~(1 << irq);
1029 }
1030
1031 void helper_msgsnd(target_ulong rb)
1032 {
1033     int irq = dbell2irq(rb);
1034     int pir = rb & DBELL_PIRTAG_MASK;
1035     CPUState *cs;
1036
1037     if (irq < 0) {
1038         return;
1039     }
1040
1041     CPU_FOREACH(cs) {
1042         PowerPCCPU *cpu = POWERPC_CPU(cs);
1043         CPUPPCState *cenv = &cpu->env;
1044
1045         if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1046             cenv->pending_interrupts |= 1 << irq;
1047             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1048         }
1049     }
1050 }
1051 #endif