target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  45 }
  46
  47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  48 {
  49     /* Reset a single ARMCPRegInfo register */
  50     ARMCPRegInfo *ri = value;
  51     ARMCPU *cpu = opaque;
  52
  53     if (ri->type & ARM_CP_SPECIAL) {
  54         return;
  55     }
  56
  57     if (ri->resetfn) {
  58         ri->resetfn(&cpu->env, ri);
  59         return;
  60     }
  61
  62     /* A zero offset is never possible as it would be regs[0]
  63      * so we use it to indicate that reset is being handled elsewhere.
  64      * This is basically only used for fields in non-core coprocessors
  65      * (like the pxa2xx ones).
  66      */
  67     if (!ri->fieldoffset) {
  68         return;
  69     }
  70
  71     if (cpreg_field_is_64bit(ri)) {
  72         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  73     } else {
  74         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  75     }
  76 }
  77
  78 /* CPUClass::reset() */
  79 static void arm_cpu_reset(CPUState *s)
  80 {
  81     ARMCPU *cpu = ARM_CPU(s);
  82     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  83     CPUARMState *env = &cpu->env;
  84
  85     acc->parent_reset(s);
  86
  87     memset(env, 0, offsetof(CPUARMState, features));
  88     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  89     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  90     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  91     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  92     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  93
  94     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  95         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  96     }
  97
  98     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  99         /* 64 bit CPUs always start in 64 bit mode */
 100         env->aarch64 = 1;
 101 #if defined(CONFIG_USER_ONLY)
 102         env->pstate = PSTATE_MODE_EL0t;
 103         /* Userspace expects access to CTL_EL0 and the cache ops */
 104         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 105         /* and to the FP/Neon instructions */
 106         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 107 #else
 108         env->pstate = PSTATE_MODE_EL1h;
 109         env->pc = cpu->rvbar;
 110 #endif
 111     } else {
 112 #if defined(CONFIG_USER_ONLY)
 113         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 115 #endif
 116     }
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     env->uncached_cpsr = ARM_CPU_MODE_USR;
 120     /* For user mode we must enable access to coprocessors */
 121     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 122     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 123         env->cp15.c15_cpar = 3;
 124     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 125         env->cp15.c15_cpar = 1;
 126     }
 127 #else
 128     /* SVC mode with interrupts disabled.  */
 129     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 130     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 131     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 132      * clear at reset. Initial SP and PC are loaded from ROM.
 133      */
 134     if (IS_M(env)) {
 135         uint32_t initial_msp; /* Loaded from 0x0 */
 136         uint32_t initial_pc; /* Loaded from 0x4 */
 137         uint8_t *rom;
 138
 139         env->daif &= ~PSTATE_I;
 140         rom = rom_ptr(0);
 141         if (rom) {
 142             /* Address zero is covered by ROM which hasn't yet been
 143              * copied into physical memory.
 144              */
 145             initial_msp = ldl_p(rom);
 146             initial_pc = ldl_p(rom + 4);
 147         } else {
 148             /* Address zero not covered by a ROM blob, or the ROM blob
 149              * is in non-modifiable memory and this is a second reset after
 150              * it got copied into memory. In the latter case, rom_ptr
 151              * will return a NULL pointer and we should use ldl_phys instead.
 152              */
 153             initial_msp = ldl_phys(s->as, 0);
 154             initial_pc = ldl_phys(s->as, 4);
 155         }
 156
 157         env->regs[13] = initial_msp & 0xFFFFFFFC;
 158         env->regs[15] = initial_pc & ~1;
 159         env->thumb = initial_pc & 1;
 160     }
 161
 162     if (env->cp15.c1_sys & SCTLR_V) {
 163         env->regs[15] = 0xFFFF0000;
 164     }
 165
 166     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 167 #endif
 168     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 169     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 170     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 171     set_float_detect_tininess(float_tininess_before_rounding,
 172                               &env->vfp.fp_status);
 173     set_float_detect_tininess(float_tininess_before_rounding,
 174                               &env->vfp.standard_fp_status);
 175     tlb_flush(s, 1);
 176     /* Reset is a state change for some CPUARMState fields which we
 177      * bake assumptions about into translated code, so we need to
 178      * tb_flush().
 179      */
 180     tb_flush(env);
 181
 182 #ifndef CONFIG_USER_ONLY
 183     if (kvm_enabled()) {
 184         kvm_arm_reset_vcpu(cpu);
 185     }
 186 #endif
 187
 188     hw_watchpoint_update_all(cpu);
 189 }
 190
 191 #ifndef CONFIG_USER_ONLY
 192 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 193 {
 194     ARMCPU *cpu = opaque;
 195     CPUState *cs = CPU(cpu);
 196
 197     switch (irq) {
 198     case ARM_CPU_IRQ:
 199         if (level) {
 200             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 201         } else {
 202             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 203         }
 204         break;
 205     case ARM_CPU_FIQ:
 206         if (level) {
 207             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 208         } else {
 209             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 210         }
 211         break;
 212     default:
 213         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 214     }
 215 }
 216
 217 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 218 {
 219 #ifdef CONFIG_KVM
 220     ARMCPU *cpu = opaque;
 221     CPUState *cs = CPU(cpu);
 222     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 223
 224     switch (irq) {
 225     case ARM_CPU_IRQ:
 226         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 227         break;
 228     case ARM_CPU_FIQ:
 229         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 230         break;
 231     default:
 232         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 233     }
 234     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 235     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 236 #endif
 237 }
 238 #endif
 239
 240 static inline void set_feature(CPUARMState *env, int feature)
 241 {
 242     env->features |= 1ULL << feature;
 243 }
 244
 245 static void arm_cpu_initfn(Object *obj)
 246 {
 247     CPUState *cs = CPU(obj);
 248     ARMCPU *cpu = ARM_CPU(obj);
 249     static bool inited;
 250
 251     cs->env_ptr = &cpu->env;
 252     cpu_exec_init(&cpu->env);
 253     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 254                                          g_free, g_free);
 255
 256 #ifndef CONFIG_USER_ONLY
 257     /* Our inbound IRQ and FIQ lines */
 258     if (kvm_enabled()) {
 259         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 260     } else {
 261         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 262     }
 263
 264     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 265                                                 arm_gt_ptimer_cb, cpu);
 266     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 267                                                 arm_gt_vtimer_cb, cpu);
 268     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 269                        ARRAY_SIZE(cpu->gt_timer_outputs));
 270 #endif
 271
 272     /* DTB consumers generally don't in fact care what the 'compatible'
 273      * string is, so always provide some string and trust that a hypothetical
 274      * picky DTB consumer will also provide a helpful error message.
 275      */
 276     cpu->dtb_compatible = "qemu,unknown";
 277     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 278     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 279
 280     if (tcg_enabled() && !inited) {
 281         inited = true;
 282         arm_translate_init();
 283     }
 284 }
 285
 286 static Property arm_cpu_reset_cbar_property =
 287             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 288
 289 static Property arm_cpu_reset_hivecs_property =
 290             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 291
 292 static Property arm_cpu_rvbar_property =
 293             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 294
 295 static void arm_cpu_post_init(Object *obj)
 296 {
 297     ARMCPU *cpu = ARM_CPU(obj);
 298
 299     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 300         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 301         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 302                                  &error_abort);
 303     }
 304
 305     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 306         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 307                                  &error_abort);
 308     }
 309
 310     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 311         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 312                                  &error_abort);
 313     }
 314 }
 315
 316 static void arm_cpu_finalizefn(Object *obj)
 317 {
 318     ARMCPU *cpu = ARM_CPU(obj);
 319     g_hash_table_destroy(cpu->cp_regs);
 320 }
 321
 322 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 323 {
 324     CPUState *cs = CPU(dev);
 325     ARMCPU *cpu = ARM_CPU(dev);
 326     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 327     CPUARMState *env = &cpu->env;
 328
 329     /* Some features automatically imply others: */
 330     if (arm_feature(env, ARM_FEATURE_V8)) {
 331         set_feature(env, ARM_FEATURE_V7);
 332         set_feature(env, ARM_FEATURE_ARM_DIV);
 333         set_feature(env, ARM_FEATURE_LPAE);
 334     }
 335     if (arm_feature(env, ARM_FEATURE_V7)) {
 336         set_feature(env, ARM_FEATURE_VAPA);
 337         set_feature(env, ARM_FEATURE_THUMB2);
 338         set_feature(env, ARM_FEATURE_MPIDR);
 339         if (!arm_feature(env, ARM_FEATURE_M)) {
 340             set_feature(env, ARM_FEATURE_V6K);
 341         } else {
 342             set_feature(env, ARM_FEATURE_V6);
 343         }
 344     }
 345     if (arm_feature(env, ARM_FEATURE_V6K)) {
 346         set_feature(env, ARM_FEATURE_V6);
 347         set_feature(env, ARM_FEATURE_MVFR);
 348     }
 349     if (arm_feature(env, ARM_FEATURE_V6)) {
 350         set_feature(env, ARM_FEATURE_V5);
 351         if (!arm_feature(env, ARM_FEATURE_M)) {
 352             set_feature(env, ARM_FEATURE_AUXCR);
 353         }
 354     }
 355     if (arm_feature(env, ARM_FEATURE_V5)) {
 356         set_feature(env, ARM_FEATURE_V4T);
 357     }
 358     if (arm_feature(env, ARM_FEATURE_M)) {
 359         set_feature(env, ARM_FEATURE_THUMB_DIV);
 360     }
 361     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 362         set_feature(env, ARM_FEATURE_THUMB_DIV);
 363     }
 364     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 365         set_feature(env, ARM_FEATURE_VFP3);
 366         set_feature(env, ARM_FEATURE_VFP_FP16);
 367     }
 368     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 369         set_feature(env, ARM_FEATURE_VFP);
 370     }
 371     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 372         set_feature(env, ARM_FEATURE_V7MP);
 373         set_feature(env, ARM_FEATURE_PXN);
 374     }
 375     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 376         set_feature(env, ARM_FEATURE_CBAR);
 377     }
 378
 379     if (cpu->reset_hivecs) {
 380             cpu->reset_sctlr |= (1 << 13);
 381     }
 382
 383     register_cp_regs_for_features(cpu);
 384     arm_cpu_register_gdb_regs_for_features(cpu);
 385
 386     init_cpreg_list(cpu);
 387
 388     qemu_init_vcpu(cs);
 389     cpu_reset(cs);
 390
 391     acc->parent_realize(dev, errp);
 392 }
 393
 394 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 395 {
 396     ObjectClass *oc;
 397     char *typename;
 398
 399     if (!cpu_model) {
 400         return NULL;
 401     }
 402
 403     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 404     oc = object_class_by_name(typename);
 405     g_free(typename);
 406     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 407         object_class_is_abstract(oc)) {
 408         return NULL;
 409     }
 410     return oc;
 411 }
 412
 413 /* CPU models. These are not needed for the AArch64 linux-user build. */
 414 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 415
 416 static void arm926_initfn(Object *obj)
 417 {
 418     ARMCPU *cpu = ARM_CPU(obj);
 419
 420     cpu->dtb_compatible = "arm,arm926";
 421     set_feature(&cpu->env, ARM_FEATURE_V5);
 422     set_feature(&cpu->env, ARM_FEATURE_VFP);
 423     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 424     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 425     cpu->midr = 0x41069265;
 426     cpu->reset_fpsid = 0x41011090;
 427     cpu->ctr = 0x1dd20d2;
 428     cpu->reset_sctlr = 0x00090078;
 429 }
 430
 431 static void arm946_initfn(Object *obj)
 432 {
 433     ARMCPU *cpu = ARM_CPU(obj);
 434
 435     cpu->dtb_compatible = "arm,arm946";
 436     set_feature(&cpu->env, ARM_FEATURE_V5);
 437     set_feature(&cpu->env, ARM_FEATURE_MPU);
 438     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 439     cpu->midr = 0x41059461;
 440     cpu->ctr = 0x0f004006;
 441     cpu->reset_sctlr = 0x00000078;
 442 }
 443
 444 static void arm1026_initfn(Object *obj)
 445 {
 446     ARMCPU *cpu = ARM_CPU(obj);
 447
 448     cpu->dtb_compatible = "arm,arm1026";
 449     set_feature(&cpu->env, ARM_FEATURE_V5);
 450     set_feature(&cpu->env, ARM_FEATURE_VFP);
 451     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 452     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 453     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 454     cpu->midr = 0x4106a262;
 455     cpu->reset_fpsid = 0x410110a0;
 456     cpu->ctr = 0x1dd20d2;
 457     cpu->reset_sctlr = 0x00090078;
 458     cpu->reset_auxcr = 1;
 459     {
 460         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 461         ARMCPRegInfo ifar = {
 462             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 463             .access = PL1_RW,
 464             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 465             .resetvalue = 0
 466         };
 467         define_one_arm_cp_reg(cpu, &ifar);
 468     }
 469 }
 470
 471 static void arm1136_r2_initfn(Object *obj)
 472 {
 473     ARMCPU *cpu = ARM_CPU(obj);
 474     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 475      * older core than plain "arm1136". In particular this does not
 476      * have the v6K features.
 477      * These ID register values are correct for 1136 but may be wrong
 478      * for 1136_r2 (in particular r0p2 does not actually implement most
 479      * of the ID registers).
 480      */
 481
 482     cpu->dtb_compatible = "arm,arm1136";
 483     set_feature(&cpu->env, ARM_FEATURE_V6);
 484     set_feature(&cpu->env, ARM_FEATURE_VFP);
 485     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 486     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 487     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 488     cpu->midr = 0x4107b362;
 489     cpu->reset_fpsid = 0x410120b4;
 490     cpu->mvfr0 = 0x11111111;
 491     cpu->mvfr1 = 0x00000000;
 492     cpu->ctr = 0x1dd20d2;
 493     cpu->reset_sctlr = 0x00050078;
 494     cpu->id_pfr0 = 0x111;
 495     cpu->id_pfr1 = 0x1;
 496     cpu->id_dfr0 = 0x2;
 497     cpu->id_afr0 = 0x3;
 498     cpu->id_mmfr0 = 0x01130003;
 499     cpu->id_mmfr1 = 0x10030302;
 500     cpu->id_mmfr2 = 0x01222110;
 501     cpu->id_isar0 = 0x00140011;
 502     cpu->id_isar1 = 0x12002111;
 503     cpu->id_isar2 = 0x11231111;
 504     cpu->id_isar3 = 0x01102131;
 505     cpu->id_isar4 = 0x141;
 506     cpu->reset_auxcr = 7;
 507 }
 508
 509 static void arm1136_initfn(Object *obj)
 510 {
 511     ARMCPU *cpu = ARM_CPU(obj);
 512
 513     cpu->dtb_compatible = "arm,arm1136";
 514     set_feature(&cpu->env, ARM_FEATURE_V6K);
 515     set_feature(&cpu->env, ARM_FEATURE_V6);
 516     set_feature(&cpu->env, ARM_FEATURE_VFP);
 517     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 518     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 519     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 520     cpu->midr = 0x4117b363;
 521     cpu->reset_fpsid = 0x410120b4;
 522     cpu->mvfr0 = 0x11111111;
 523     cpu->mvfr1 = 0x00000000;
 524     cpu->ctr = 0x1dd20d2;
 525     cpu->reset_sctlr = 0x00050078;
 526     cpu->id_pfr0 = 0x111;
 527     cpu->id_pfr1 = 0x1;
 528     cpu->id_dfr0 = 0x2;
 529     cpu->id_afr0 = 0x3;
 530     cpu->id_mmfr0 = 0x01130003;
 531     cpu->id_mmfr1 = 0x10030302;
 532     cpu->id_mmfr2 = 0x01222110;
 533     cpu->id_isar0 = 0x00140011;
 534     cpu->id_isar1 = 0x12002111;
 535     cpu->id_isar2 = 0x11231111;
 536     cpu->id_isar3 = 0x01102131;
 537     cpu->id_isar4 = 0x141;
 538     cpu->reset_auxcr = 7;
 539 }
 540
 541 static void arm1176_initfn(Object *obj)
 542 {
 543     ARMCPU *cpu = ARM_CPU(obj);
 544
 545     cpu->dtb_compatible = "arm,arm1176";
 546     set_feature(&cpu->env, ARM_FEATURE_V6K);
 547     set_feature(&cpu->env, ARM_FEATURE_VFP);
 548     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 549     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 550     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 551     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 552     cpu->midr = 0x410fb767;
 553     cpu->reset_fpsid = 0x410120b5;
 554     cpu->mvfr0 = 0x11111111;
 555     cpu->mvfr1 = 0x00000000;
 556     cpu->ctr = 0x1dd20d2;
 557     cpu->reset_sctlr = 0x00050078;
 558     cpu->id_pfr0 = 0x111;
 559     cpu->id_pfr1 = 0x11;
 560     cpu->id_dfr0 = 0x33;
 561     cpu->id_afr0 = 0;
 562     cpu->id_mmfr0 = 0x01130003;
 563     cpu->id_mmfr1 = 0x10030302;
 564     cpu->id_mmfr2 = 0x01222100;
 565     cpu->id_isar0 = 0x0140011;
 566     cpu->id_isar1 = 0x12002111;
 567     cpu->id_isar2 = 0x11231121;
 568     cpu->id_isar3 = 0x01102131;
 569     cpu->id_isar4 = 0x01141;
 570     cpu->reset_auxcr = 7;
 571 }
 572
 573 static void arm11mpcore_initfn(Object *obj)
 574 {
 575     ARMCPU *cpu = ARM_CPU(obj);
 576
 577     cpu->dtb_compatible = "arm,arm11mpcore";
 578     set_feature(&cpu->env, ARM_FEATURE_V6K);
 579     set_feature(&cpu->env, ARM_FEATURE_VFP);
 580     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 581     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 582     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 583     cpu->midr = 0x410fb022;
 584     cpu->reset_fpsid = 0x410120b4;
 585     cpu->mvfr0 = 0x11111111;
 586     cpu->mvfr1 = 0x00000000;
 587     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 588     cpu->id_pfr0 = 0x111;
 589     cpu->id_pfr1 = 0x1;
 590     cpu->id_dfr0 = 0;
 591     cpu->id_afr0 = 0x2;
 592     cpu->id_mmfr0 = 0x01100103;
 593     cpu->id_mmfr1 = 0x10020302;
 594     cpu->id_mmfr2 = 0x01222000;
 595     cpu->id_isar0 = 0x00100011;
 596     cpu->id_isar1 = 0x12002111;
 597     cpu->id_isar2 = 0x11221011;
 598     cpu->id_isar3 = 0x01102131;
 599     cpu->id_isar4 = 0x141;
 600     cpu->reset_auxcr = 1;
 601 }
 602
 603 static void cortex_m3_initfn(Object *obj)
 604 {
 605     ARMCPU *cpu = ARM_CPU(obj);
 606     set_feature(&cpu->env, ARM_FEATURE_V7);
 607     set_feature(&cpu->env, ARM_FEATURE_M);
 608     cpu->midr = 0x410fc231;
 609 }
 610
 611 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 612 {
 613 #ifndef CONFIG_USER_ONLY
 614     CPUClass *cc = CPU_CLASS(oc);
 615
 616     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 617 #endif
 618 }
 619
 620 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 621     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 622       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 623     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 624       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 625     REGINFO_SENTINEL
 626 };
 627
 628 static void cortex_a8_initfn(Object *obj)
 629 {
 630     ARMCPU *cpu = ARM_CPU(obj);
 631
 632     cpu->dtb_compatible = "arm,cortex-a8";
 633     set_feature(&cpu->env, ARM_FEATURE_V7);
 634     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 635     set_feature(&cpu->env, ARM_FEATURE_NEON);
 636     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 637     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 638     cpu->midr = 0x410fc080;
 639     cpu->reset_fpsid = 0x410330c0;
 640     cpu->mvfr0 = 0x11110222;
 641     cpu->mvfr1 = 0x00011100;
 642     cpu->ctr = 0x82048004;
 643     cpu->reset_sctlr = 0x00c50078;
 644     cpu->id_pfr0 = 0x1031;
 645     cpu->id_pfr1 = 0x11;
 646     cpu->id_dfr0 = 0x400;
 647     cpu->id_afr0 = 0;
 648     cpu->id_mmfr0 = 0x31100003;
 649     cpu->id_mmfr1 = 0x20000000;
 650     cpu->id_mmfr2 = 0x01202000;
 651     cpu->id_mmfr3 = 0x11;
 652     cpu->id_isar0 = 0x00101111;
 653     cpu->id_isar1 = 0x12112111;
 654     cpu->id_isar2 = 0x21232031;
 655     cpu->id_isar3 = 0x11112131;
 656     cpu->id_isar4 = 0x00111142;
 657     cpu->dbgdidr = 0x15141000;
 658     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 659     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 660     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 661     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 662     cpu->reset_auxcr = 2;
 663     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 664 }
 665
 666 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 667     /* power_control should be set to maximum latency. Again,
 668      * default to 0 and set by private hook
 669      */
 670     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 671       .access = PL1_RW, .resetvalue = 0,
 672       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 673     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 674       .access = PL1_RW, .resetvalue = 0,
 675       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 676     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 677       .access = PL1_RW, .resetvalue = 0,
 678       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 679     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 680       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 681     /* TLB lockdown control */
 682     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 683       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 684     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 685       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 686     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 687       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 688     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 689       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 690     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 691       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 692     REGINFO_SENTINEL
 693 };
 694
 695 static void cortex_a9_initfn(Object *obj)
 696 {
 697     ARMCPU *cpu = ARM_CPU(obj);
 698
 699     cpu->dtb_compatible = "arm,cortex-a9";
 700     set_feature(&cpu->env, ARM_FEATURE_V7);
 701     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 702     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 703     set_feature(&cpu->env, ARM_FEATURE_NEON);
 704     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 705     /* Note that A9 supports the MP extensions even for
 706      * A9UP and single-core A9MP (which are both different
 707      * and valid configurations; we don't model A9UP).
 708      */
 709     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 710     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 711     cpu->midr = 0x410fc090;
 712     cpu->reset_fpsid = 0x41033090;
 713     cpu->mvfr0 = 0x11110222;
 714     cpu->mvfr1 = 0x01111111;
 715     cpu->ctr = 0x80038003;
 716     cpu->reset_sctlr = 0x00c50078;
 717     cpu->id_pfr0 = 0x1031;
 718     cpu->id_pfr1 = 0x11;
 719     cpu->id_dfr0 = 0x000;
 720     cpu->id_afr0 = 0;
 721     cpu->id_mmfr0 = 0x00100103;
 722     cpu->id_mmfr1 = 0x20000000;
 723     cpu->id_mmfr2 = 0x01230000;
 724     cpu->id_mmfr3 = 0x00002111;
 725     cpu->id_isar0 = 0x00101111;
 726     cpu->id_isar1 = 0x13112111;
 727     cpu->id_isar2 = 0x21232041;
 728     cpu->id_isar3 = 0x11112131;
 729     cpu->id_isar4 = 0x00111142;
 730     cpu->dbgdidr = 0x35141000;
 731     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 732     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 733     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 734     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 735 }
 736
 737 #ifndef CONFIG_USER_ONLY
 738 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 739 {
 740     /* Linux wants the number of processors from here.
 741      * Might as well set the interrupt-controller bit too.
 742      */
 743     return ((smp_cpus - 1) << 24) | (1 << 23);
 744 }
 745 #endif
 746
 747 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 748 #ifndef CONFIG_USER_ONLY
 749     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 750       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 751       .writefn = arm_cp_write_ignore, },
 752 #endif
 753     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 754       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 755     REGINFO_SENTINEL
 756 };
 757
 758 static void cortex_a15_initfn(Object *obj)
 759 {
 760     ARMCPU *cpu = ARM_CPU(obj);
 761
 762     cpu->dtb_compatible = "arm,cortex-a15";
 763     set_feature(&cpu->env, ARM_FEATURE_V7);
 764     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 765     set_feature(&cpu->env, ARM_FEATURE_NEON);
 766     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 767     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 768     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 769     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 770     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 771     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 772     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 773     cpu->midr = 0x412fc0f1;
 774     cpu->reset_fpsid = 0x410430f0;
 775     cpu->mvfr0 = 0x10110222;
 776     cpu->mvfr1 = 0x11111111;
 777     cpu->ctr = 0x8444c004;
 778     cpu->reset_sctlr = 0x00c50078;
 779     cpu->id_pfr0 = 0x00001131;
 780     cpu->id_pfr1 = 0x00011011;
 781     cpu->id_dfr0 = 0x02010555;
 782     cpu->id_afr0 = 0x00000000;
 783     cpu->id_mmfr0 = 0x10201105;
 784     cpu->id_mmfr1 = 0x20000000;
 785     cpu->id_mmfr2 = 0x01240000;
 786     cpu->id_mmfr3 = 0x02102211;
 787     cpu->id_isar0 = 0x02101110;
 788     cpu->id_isar1 = 0x13112111;
 789     cpu->id_isar2 = 0x21232041;
 790     cpu->id_isar3 = 0x11112131;
 791     cpu->id_isar4 = 0x10011142;
 792     cpu->dbgdidr = 0x3515f021;
 793     cpu->clidr = 0x0a200023;
 794     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 795     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 796     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 797     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 798 }
 799
 800 static void ti925t_initfn(Object *obj)
 801 {
 802     ARMCPU *cpu = ARM_CPU(obj);
 803     set_feature(&cpu->env, ARM_FEATURE_V4T);
 804     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 805     cpu->midr = ARM_CPUID_TI925T;
 806     cpu->ctr = 0x5109149;
 807     cpu->reset_sctlr = 0x00000070;
 808 }
 809
 810 static void sa1100_initfn(Object *obj)
 811 {
 812     ARMCPU *cpu = ARM_CPU(obj);
 813
 814     cpu->dtb_compatible = "intel,sa1100";
 815     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 816     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 817     cpu->midr = 0x4401A11B;
 818     cpu->reset_sctlr = 0x00000070;
 819 }
 820
 821 static void sa1110_initfn(Object *obj)
 822 {
 823     ARMCPU *cpu = ARM_CPU(obj);
 824     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 825     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 826     cpu->midr = 0x6901B119;
 827     cpu->reset_sctlr = 0x00000070;
 828 }
 829
 830 static void pxa250_initfn(Object *obj)
 831 {
 832     ARMCPU *cpu = ARM_CPU(obj);
 833
 834     cpu->dtb_compatible = "marvell,xscale";
 835     set_feature(&cpu->env, ARM_FEATURE_V5);
 836     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 837     cpu->midr = 0x69052100;
 838     cpu->ctr = 0xd172172;
 839     cpu->reset_sctlr = 0x00000078;
 840 }
 841
 842 static void pxa255_initfn(Object *obj)
 843 {
 844     ARMCPU *cpu = ARM_CPU(obj);
 845
 846     cpu->dtb_compatible = "marvell,xscale";
 847     set_feature(&cpu->env, ARM_FEATURE_V5);
 848     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 849     cpu->midr = 0x69052d00;
 850     cpu->ctr = 0xd172172;
 851     cpu->reset_sctlr = 0x00000078;
 852 }
 853
 854 static void pxa260_initfn(Object *obj)
 855 {
 856     ARMCPU *cpu = ARM_CPU(obj);
 857
 858     cpu->dtb_compatible = "marvell,xscale";
 859     set_feature(&cpu->env, ARM_FEATURE_V5);
 860     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 861     cpu->midr = 0x69052903;
 862     cpu->ctr = 0xd172172;
 863     cpu->reset_sctlr = 0x00000078;
 864 }
 865
 866 static void pxa261_initfn(Object *obj)
 867 {
 868     ARMCPU *cpu = ARM_CPU(obj);
 869
 870     cpu->dtb_compatible = "marvell,xscale";
 871     set_feature(&cpu->env, ARM_FEATURE_V5);
 872     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 873     cpu->midr = 0x69052d05;
 874     cpu->ctr = 0xd172172;
 875     cpu->reset_sctlr = 0x00000078;
 876 }
 877
 878 static void pxa262_initfn(Object *obj)
 879 {
 880     ARMCPU *cpu = ARM_CPU(obj);
 881
 882     cpu->dtb_compatible = "marvell,xscale";
 883     set_feature(&cpu->env, ARM_FEATURE_V5);
 884     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 885     cpu->midr = 0x69052d06;
 886     cpu->ctr = 0xd172172;
 887     cpu->reset_sctlr = 0x00000078;
 888 }
 889
 890 static void pxa270a0_initfn(Object *obj)
 891 {
 892     ARMCPU *cpu = ARM_CPU(obj);
 893
 894     cpu->dtb_compatible = "marvell,xscale";
 895     set_feature(&cpu->env, ARM_FEATURE_V5);
 896     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 897     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 898     cpu->midr = 0x69054110;
 899     cpu->ctr = 0xd172172;
 900     cpu->reset_sctlr = 0x00000078;
 901 }
 902
 903 static void pxa270a1_initfn(Object *obj)
 904 {
 905     ARMCPU *cpu = ARM_CPU(obj);
 906
 907     cpu->dtb_compatible = "marvell,xscale";
 908     set_feature(&cpu->env, ARM_FEATURE_V5);
 909     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 910     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 911     cpu->midr = 0x69054111;
 912     cpu->ctr = 0xd172172;
 913     cpu->reset_sctlr = 0x00000078;
 914 }
 915
 916 static void pxa270b0_initfn(Object *obj)
 917 {
 918     ARMCPU *cpu = ARM_CPU(obj);
 919
 920     cpu->dtb_compatible = "marvell,xscale";
 921     set_feature(&cpu->env, ARM_FEATURE_V5);
 922     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 923     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 924     cpu->midr = 0x69054112;
 925     cpu->ctr = 0xd172172;
 926     cpu->reset_sctlr = 0x00000078;
 927 }
 928
 929 static void pxa270b1_initfn(Object *obj)
 930 {
 931     ARMCPU *cpu = ARM_CPU(obj);
 932
 933     cpu->dtb_compatible = "marvell,xscale";
 934     set_feature(&cpu->env, ARM_FEATURE_V5);
 935     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 936     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 937     cpu->midr = 0x69054113;
 938     cpu->ctr = 0xd172172;
 939     cpu->reset_sctlr = 0x00000078;
 940 }
 941
 942 static void pxa270c0_initfn(Object *obj)
 943 {
 944     ARMCPU *cpu = ARM_CPU(obj);
 945
 946     cpu->dtb_compatible = "marvell,xscale";
 947     set_feature(&cpu->env, ARM_FEATURE_V5);
 948     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 949     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 950     cpu->midr = 0x69054114;
 951     cpu->ctr = 0xd172172;
 952     cpu->reset_sctlr = 0x00000078;
 953 }
 954
 955 static void pxa270c5_initfn(Object *obj)
 956 {
 957     ARMCPU *cpu = ARM_CPU(obj);
 958
 959     cpu->dtb_compatible = "marvell,xscale";
 960     set_feature(&cpu->env, ARM_FEATURE_V5);
 961     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 962     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 963     cpu->midr = 0x69054117;
 964     cpu->ctr = 0xd172172;
 965     cpu->reset_sctlr = 0x00000078;
 966 }
 967
 968 #ifdef CONFIG_USER_ONLY
 969 static void arm_any_initfn(Object *obj)
 970 {
 971     ARMCPU *cpu = ARM_CPU(obj);
 972     set_feature(&cpu->env, ARM_FEATURE_V8);
 973     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 974     set_feature(&cpu->env, ARM_FEATURE_NEON);
 975     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 976     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 977     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 978     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 979     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 980     set_feature(&cpu->env, ARM_FEATURE_CRC);
 981     cpu->midr = 0xffffffff;
 982 }
 983 #endif
 984
 985 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 986
 987 typedef struct ARMCPUInfo {
 988     const char *name;
 989     void (*initfn)(Object *obj);
 990     void (*class_init)(ObjectClass *oc, void *data);
 991 } ARMCPUInfo;
 992
 993 static const ARMCPUInfo arm_cpus[] = {
 994 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 995     { .name = "arm926",      .initfn = arm926_initfn },
 996     { .name = "arm946",      .initfn = arm946_initfn },
 997     { .name = "arm1026",     .initfn = arm1026_initfn },
 998     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 999      * older core than plain "arm1136". In particular this does not
1000      * have the v6K features.
1001      */
1002     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1003     { .name = "arm1136",     .initfn = arm1136_initfn },
1004     { .name = "arm1176",     .initfn = arm1176_initfn },
1005     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1006     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1007                              .class_init = arm_v7m_class_init },
1008     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1009     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1010     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1011     { .name = "ti925t",      .initfn = ti925t_initfn },
1012     { .name = "sa1100",      .initfn = sa1100_initfn },
1013     { .name = "sa1110",      .initfn = sa1110_initfn },
1014     { .name = "pxa250",      .initfn = pxa250_initfn },
1015     { .name = "pxa255",      .initfn = pxa255_initfn },
1016     { .name = "pxa260",      .initfn = pxa260_initfn },
1017     { .name = "pxa261",      .initfn = pxa261_initfn },
1018     { .name = "pxa262",      .initfn = pxa262_initfn },
1019     /* "pxa270" is an alias for "pxa270-a0" */
1020     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1021     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1022     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1023     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1024     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1025     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1026     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1027 #ifdef CONFIG_USER_ONLY
1028     { .name = "any",         .initfn = arm_any_initfn },
1029 #endif
1030 #endif
1031     { .name = NULL }
1032 };
1033
1034 static Property arm_cpu_properties[] = {
1035     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1036     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1037     DEFINE_PROP_END_OF_LIST()
1038 };
1039
1040 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1041 {
1042     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1043     CPUClass *cc = CPU_CLASS(acc);
1044     DeviceClass *dc = DEVICE_CLASS(oc);
1045
1046     acc->parent_realize = dc->realize;
1047     dc->realize = arm_cpu_realizefn;
1048     dc->props = arm_cpu_properties;
1049
1050     acc->parent_reset = cc->reset;
1051     cc->reset = arm_cpu_reset;
1052
1053     cc->class_by_name = arm_cpu_class_by_name;
1054     cc->has_work = arm_cpu_has_work;
1055     cc->do_interrupt = arm_cpu_do_interrupt;
1056     cc->dump_state = arm_cpu_dump_state;
1057     cc->set_pc = arm_cpu_set_pc;
1058     cc->gdb_read_register = arm_cpu_gdb_read_register;
1059     cc->gdb_write_register = arm_cpu_gdb_write_register;
1060 #ifdef CONFIG_USER_ONLY
1061     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1062 #else
1063     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1064     cc->vmsd = &vmstate_arm_cpu;
1065 #endif
1066     cc->gdb_num_core_regs = 26;
1067     cc->gdb_core_xml_file = "arm-core.xml";
1068     cc->debug_excp_handler = arm_debug_excp_handler;
1069 }
1070
1071 static void cpu_register(const ARMCPUInfo *info)
1072 {
1073     TypeInfo type_info = {
1074         .parent = TYPE_ARM_CPU,
1075         .instance_size = sizeof(ARMCPU),
1076         .instance_init = info->initfn,
1077         .class_size = sizeof(ARMCPUClass),
1078         .class_init = info->class_init,
1079     };
1080
1081     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1082     type_register(&type_info);
1083     g_free((void *)type_info.name);
1084 }
1085
1086 static const TypeInfo arm_cpu_type_info = {
1087     .name = TYPE_ARM_CPU,
1088     .parent = TYPE_CPU,
1089     .instance_size = sizeof(ARMCPU),
1090     .instance_init = arm_cpu_initfn,
1091     .instance_post_init = arm_cpu_post_init,
1092     .instance_finalize = arm_cpu_finalizefn,
1093     .abstract = true,
1094     .class_size = sizeof(ARMCPUClass),
1095     .class_init = arm_cpu_class_init,
1096 };
1097
1098 static void arm_cpu_register_types(void)
1099 {
1100     const ARMCPUInfo *info = arm_cpus;
1101
1102     type_register_static(&arm_cpu_type_info);
1103
1104     while (info->name) {
1105         cpu_register(info);
1106         info++;
1107     }
1108 }
1109
1110 type_init(arm_cpu_register_types)