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block/vpc: make calculate_geometry spec conform
[qemu/kevin.git] / target-tricore / translate.c
blob27777be9c1fa0f42d596f39d85d106a62f3f107c
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 enum {
84 MODE_LL = 0,
85 MODE_LU = 1,
86 MODE_UL = 2,
87 MODE_UU = 3,
88 };
89
90 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
91 fprintf_function cpu_fprintf, int flags)
92 {
93 TriCoreCPU *cpu = TRICORE_CPU(cs);
94 CPUTriCoreState *env = &cpu->env;
95 uint32_t psw;
96 int i;
97
98 psw = psw_read(env);
99
100 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
101 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
102 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
103 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
104 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
105 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
106
107 for (i = 0; i < 16; ++i) {
108 if ((i & 3) == 0) {
109 cpu_fprintf(f, "\nGPR A%02d:", i);
110 }
111 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
112 }
113 for (i = 0; i < 16; ++i) {
114 if ((i & 3) == 0) {
115 cpu_fprintf(f, "\nGPR D%02d:", i);
116 }
117 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
118 }
119 cpu_fprintf(f, "\n");
120 }
121
122 /*
123 * Functions to generate micro-ops
124 */
125
126 /* Makros for generating helpers */
127
128 #define gen_helper_1arg(name, arg) do { \
129 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
130 gen_helper_##name(cpu_env, helper_tmp); \
131 tcg_temp_free_i32(helper_tmp); \
132 } while (0)
133
134 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
135 TCGv arg00 = tcg_temp_new(); \
136 TCGv arg01 = tcg_temp_new(); \
137 TCGv arg11 = tcg_temp_new(); \
138 tcg_gen_sari_tl(arg00, arg0, 16); \
139 tcg_gen_ext16s_tl(arg01, arg0); \
140 tcg_gen_ext16s_tl(arg11, arg1); \
141 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
142 tcg_temp_free(arg00); \
143 tcg_temp_free(arg01); \
144 tcg_temp_free(arg11); \
145 } while (0)
146
147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
148 TCGv arg00 = tcg_temp_new(); \
149 TCGv arg01 = tcg_temp_new(); \
150 TCGv arg10 = tcg_temp_new(); \
151 TCGv arg11 = tcg_temp_new(); \
152 tcg_gen_sari_tl(arg00, arg0, 16); \
153 tcg_gen_ext16s_tl(arg01, arg0); \
154 tcg_gen_sari_tl(arg11, arg1, 16); \
155 tcg_gen_ext16s_tl(arg10, arg1); \
156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
157 tcg_temp_free(arg00); \
158 tcg_temp_free(arg01); \
159 tcg_temp_free(arg10); \
160 tcg_temp_free(arg11); \
161 } while (0)
162
163 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
164 TCGv arg00 = tcg_temp_new(); \
165 TCGv arg01 = tcg_temp_new(); \
166 TCGv arg10 = tcg_temp_new(); \
167 TCGv arg11 = tcg_temp_new(); \
168 tcg_gen_sari_tl(arg00, arg0, 16); \
169 tcg_gen_ext16s_tl(arg01, arg0); \
170 tcg_gen_sari_tl(arg10, arg1, 16); \
171 tcg_gen_ext16s_tl(arg11, arg1); \
172 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
173 tcg_temp_free(arg00); \
174 tcg_temp_free(arg01); \
175 tcg_temp_free(arg10); \
176 tcg_temp_free(arg11); \
177 } while (0)
178
179 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
180 TCGv arg00 = tcg_temp_new(); \
181 TCGv arg01 = tcg_temp_new(); \
182 TCGv arg11 = tcg_temp_new(); \
183 tcg_gen_sari_tl(arg01, arg0, 16); \
184 tcg_gen_ext16s_tl(arg00, arg0); \
185 tcg_gen_sari_tl(arg11, arg1, 16); \
186 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
187 tcg_temp_free(arg00); \
188 tcg_temp_free(arg01); \
189 tcg_temp_free(arg11); \
190 } while (0)
191
192 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
193 TCGv_i64 ret = tcg_temp_new_i64(); \
194 TCGv_i64 arg1 = tcg_temp_new_i64(); \
195 \
196 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
197 gen_helper_##name(ret, arg1, arg2); \
198 tcg_gen_extr_i64_i32(rl, rh, ret); \
199 \
200 tcg_temp_free_i64(ret); \
201 tcg_temp_free_i64(arg1); \
202 } while (0)
203
204 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
205 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
206 ((offset & 0x0fffff) << 1))
207
208 /* Functions for load/save to/from memory */
209
210 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
211 int16_t con, TCGMemOp mop)
212 {
213 TCGv temp = tcg_temp_new();
214 tcg_gen_addi_tl(temp, r2, con);
215 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
216 tcg_temp_free(temp);
217 }
218
219 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
220 int16_t con, TCGMemOp mop)
221 {
222 TCGv temp = tcg_temp_new();
223 tcg_gen_addi_tl(temp, r2, con);
224 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
225 tcg_temp_free(temp);
226 }
227
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
229 {
230 TCGv_i64 temp = tcg_temp_new_i64();
231
232 tcg_gen_concat_i32_i64(temp, rl, rh);
233 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
234
235 tcg_temp_free_i64(temp);
236 }
237
238 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
239 DisasContext *ctx)
240 {
241 TCGv temp = tcg_temp_new();
242 tcg_gen_addi_tl(temp, base, con);
243 gen_st_2regs_64(rh, rl, temp, ctx);
244 tcg_temp_free(temp);
245 }
246
247 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
248 {
249 TCGv_i64 temp = tcg_temp_new_i64();
250
251 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
252 /* write back to two 32 bit regs */
253 tcg_gen_extr_i64_i32(rl, rh, temp);
254
255 tcg_temp_free_i64(temp);
256 }
257
258 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
259 DisasContext *ctx)
260 {
261 TCGv temp = tcg_temp_new();
262 tcg_gen_addi_tl(temp, base, con);
263 gen_ld_2regs_64(rh, rl, temp, ctx);
264 tcg_temp_free(temp);
265 }
266
267 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
268 TCGMemOp mop)
269 {
270 TCGv temp = tcg_temp_new();
271 tcg_gen_addi_tl(temp, r2, off);
272 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
273 tcg_gen_mov_tl(r2, temp);
274 tcg_temp_free(temp);
275 }
276
277 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
278 TCGMemOp mop)
279 {
280 TCGv temp = tcg_temp_new();
281 tcg_gen_addi_tl(temp, r2, off);
282 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
283 tcg_gen_mov_tl(r2, temp);
284 tcg_temp_free(temp);
285 }
286
287 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
288 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
289 {
290 TCGv temp = tcg_temp_new();
291 TCGv temp2 = tcg_temp_new();
292
293 /* temp = (M(EA, word) */
294 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
295 /* temp = temp & ~E[a][63:32]) */
296 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
297 /* temp2 = (E[a][31:0] & E[a][63:32]); */
298 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
299 /* temp = temp | temp2; */
300 tcg_gen_or_tl(temp, temp, temp2);
301 /* M(EA, word) = temp; */
302 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
303
304 tcg_temp_free(temp);
305 tcg_temp_free(temp2);
306 }
307
308 /* tmp = M(EA, word);
309 M(EA, word) = D[a];
310 D[a] = tmp[31:0];*/
311 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
312 {
313 TCGv temp = tcg_temp_new();
314
315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
316 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
317 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
318
319 tcg_temp_free(temp);
320 }
321
322 /* We generate loads and store to core special function register (csfr) through
323 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
324 makros R, A and E, which allow read-only, all and endinit protected access.
325 These makros also specify in which ISA version the csfr was introduced. */
326 #define R(ADDRESS, REG, FEATURE) \
327 case ADDRESS: \
328 if (tricore_feature(env, FEATURE)) { \
329 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
330 } \
331 break;
332 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
333 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
334 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
335 {
336 /* since we're caching PSW make this a special case */
337 if (offset == 0xfe04) {
338 gen_helper_psw_read(ret, cpu_env);
339 } else {
340 switch (offset) {
341 #include "csfr.def"
342 }
343 }
344 }
345 #undef R
346 #undef A
347 #undef E
348
349 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
350 since no execption occurs */
351 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
352 case ADDRESS: \
353 if (tricore_feature(env, FEATURE)) { \
354 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
355 } \
356 break;
357 /* Endinit protected registers
358 TODO: Since the endinit bit is in a register of a not yet implemented
359 watchdog device, we handle endinit protected registers like
360 all-access registers for now. */
361 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
362 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
363 int32_t offset)
364 {
365 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
366 /* since we're caching PSW make this a special case */
367 if (offset == 0xfe04) {
368 gen_helper_psw_write(cpu_env, r1);
369 } else {
370 switch (offset) {
371 #include "csfr.def"
372 }
373 }
374 } else {
375 /* generate privilege trap */
376 }
377 }
378
379 /* Functions for arithmetic instructions */
380
381 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
382 {
383 TCGv t0 = tcg_temp_new_i32();
384 TCGv result = tcg_temp_new_i32();
385 /* Addition and set V/SV bits */
386 tcg_gen_add_tl(result, r1, r2);
387 /* calc V bit */
388 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
389 tcg_gen_xor_tl(t0, r1, r2);
390 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
391 /* Calc SV bit */
392 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
393 /* Calc AV/SAV bits */
394 tcg_gen_add_tl(cpu_PSW_AV, result, result);
395 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
396 /* calc SAV */
397 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
398 /* write back result */
399 tcg_gen_mov_tl(ret, result);
400
401 tcg_temp_free(result);
402 tcg_temp_free(t0);
403 }
404
405 static inline void
406 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
407 {
408 TCGv temp = tcg_temp_new();
409 TCGv_i64 t0 = tcg_temp_new_i64();
410 TCGv_i64 t1 = tcg_temp_new_i64();
411 TCGv_i64 result = tcg_temp_new_i64();
412
413 tcg_gen_add_i64(result, r1, r2);
414 /* calc v bit */
415 tcg_gen_xor_i64(t1, result, r1);
416 tcg_gen_xor_i64(t0, r1, r2);
417 tcg_gen_andc_i64(t1, t1, t0);
418 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
419 /* calc SV bit */
420 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
421 /* calc AV/SAV bits */
422 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
423 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
424 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
425 /* calc SAV */
426 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
427 /* write back result */
428 tcg_gen_mov_i64(ret, result);
429
430 tcg_temp_free(temp);
431 tcg_temp_free_i64(result);
432 tcg_temp_free_i64(t0);
433 tcg_temp_free_i64(t1);
434 }
435
436 static inline void
437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
439 void(*op2)(TCGv, TCGv, TCGv))
440 {
441 TCGv temp = tcg_temp_new();
442 TCGv temp2 = tcg_temp_new();
443 TCGv temp3 = tcg_temp_new();
444 TCGv temp4 = tcg_temp_new();
445
446 (*op1)(temp, r1_low, r2);
447 /* calc V0 bit */
448 tcg_gen_xor_tl(temp2, temp, r1_low);
449 tcg_gen_xor_tl(temp3, r1_low, r2);
450 if (op1 == tcg_gen_add_tl) {
451 tcg_gen_andc_tl(temp2, temp2, temp3);
452 } else {
453 tcg_gen_and_tl(temp2, temp2, temp3);
454 }
455
456 (*op2)(temp3, r1_high, r3);
457 /* calc V1 bit */
458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
459 tcg_gen_xor_tl(temp4, r1_high, r3);
460 if (op2 == tcg_gen_add_tl) {
461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
462 } else {
463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
464 }
465 /* combine V0/V1 bits */
466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
467 /* calc sv bit */
468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
469 /* write result */
470 tcg_gen_mov_tl(ret_low, temp);
471 tcg_gen_mov_tl(ret_high, temp3);
472 /* calc AV bit */
473 tcg_gen_add_tl(temp, ret_low, ret_low);
474 tcg_gen_xor_tl(temp, temp, ret_low);
475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
478 /* calc SAV bit */
479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
480
481 tcg_temp_free(temp);
482 tcg_temp_free(temp2);
483 tcg_temp_free(temp3);
484 tcg_temp_free(temp4);
485 }
486
487 /* ret = r2 + (r1 * r3); */
488 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
489 {
490 TCGv_i64 t1 = tcg_temp_new_i64();
491 TCGv_i64 t2 = tcg_temp_new_i64();
492 TCGv_i64 t3 = tcg_temp_new_i64();
493
494 tcg_gen_ext_i32_i64(t1, r1);
495 tcg_gen_ext_i32_i64(t2, r2);
496 tcg_gen_ext_i32_i64(t3, r3);
497
498 tcg_gen_mul_i64(t1, t1, t3);
499 tcg_gen_add_i64(t1, t2, t1);
500
501 tcg_gen_trunc_i64_i32(ret, t1);
502 /* calc V
503 t1 > 0x7fffffff */
504 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
505 /* t1 < -0x80000000 */
506 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
507 tcg_gen_or_i64(t2, t2, t3);
508 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
509 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
510 /* Calc SV bit */
511 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
512 /* Calc AV/SAV bits */
513 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
514 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
515 /* calc SAV */
516 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
517
518 tcg_temp_free_i64(t1);
519 tcg_temp_free_i64(t2);
520 tcg_temp_free_i64(t3);
521 }
522
523 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
524 {
525 TCGv temp = tcg_const_i32(con);
526 gen_madd32_d(ret, r1, r2, temp);
527 tcg_temp_free(temp);
528 }
529
530 static inline void
531 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
532 TCGv r3)
533 {
534 TCGv t1 = tcg_temp_new();
535 TCGv t2 = tcg_temp_new();
536 TCGv t3 = tcg_temp_new();
537 TCGv t4 = tcg_temp_new();
538
539 tcg_gen_muls2_tl(t1, t2, r1, r3);
540 /* only the add can overflow */
541 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
542 /* calc V bit */
543 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
544 tcg_gen_xor_tl(t1, r2_high, t2);
545 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
546 /* Calc SV bit */
547 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
548 /* Calc AV/SAV bits */
549 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
550 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
551 /* calc SAV */
552 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
553 /* write back the result */
554 tcg_gen_mov_tl(ret_low, t3);
555 tcg_gen_mov_tl(ret_high, t4);
556
557 tcg_temp_free(t1);
558 tcg_temp_free(t2);
559 tcg_temp_free(t3);
560 tcg_temp_free(t4);
561 }
562
563 static inline void
564 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
565 TCGv r3)
566 {
567 TCGv_i64 t1 = tcg_temp_new_i64();
568 TCGv_i64 t2 = tcg_temp_new_i64();
569 TCGv_i64 t3 = tcg_temp_new_i64();
570
571 tcg_gen_extu_i32_i64(t1, r1);
572 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
573 tcg_gen_extu_i32_i64(t3, r3);
574
575 tcg_gen_mul_i64(t1, t1, t3);
576 tcg_gen_add_i64(t2, t2, t1);
577 /* write back result */
578 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
579 /* only the add overflows, if t2 < t1
580 calc V bit */
581 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
582 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
583 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
584 /* Calc SV bit */
585 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
586 /* Calc AV/SAV bits */
587 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
588 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
589 /* calc SAV */
590 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
591
592 tcg_temp_free_i64(t1);
593 tcg_temp_free_i64(t2);
594 tcg_temp_free_i64(t3);
595 }
596
597 static inline void
598 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
599 int32_t con)
600 {
601 TCGv temp = tcg_const_i32(con);
602 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
603 tcg_temp_free(temp);
604 }
605
606 static inline void
607 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
608 int32_t con)
609 {
610 TCGv temp = tcg_const_i32(con);
611 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
612 tcg_temp_free(temp);
613 }
614
615 static inline void
616 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
617 TCGv r3, uint32_t n, uint32_t mode)
618 {
619 TCGv temp = tcg_const_i32(n);
620 TCGv temp2 = tcg_temp_new();
621 TCGv_i64 temp64 = tcg_temp_new_i64();
622 switch (mode) {
623 case MODE_LL:
624 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
625 break;
626 case MODE_LU:
627 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
628 break;
629 case MODE_UL:
630 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
631 break;
632 case MODE_UU:
633 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
634 break;
635 }
636 tcg_gen_extr_i64_i32(temp, temp2, temp64);
637 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
638 tcg_gen_add_tl, tcg_gen_add_tl);
639 tcg_temp_free(temp);
640 tcg_temp_free(temp2);
641 tcg_temp_free_i64(temp64);
642 }
643
644 static inline void
645 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
646 TCGv r3, uint32_t n, uint32_t mode)
647 {
648 TCGv temp = tcg_const_i32(n);
649 TCGv temp2 = tcg_temp_new();
650 TCGv_i64 temp64 = tcg_temp_new_i64();
651 switch (mode) {
652 case MODE_LL:
653 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
654 break;
655 case MODE_LU:
656 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
657 break;
658 case MODE_UL:
659 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
660 break;
661 case MODE_UU:
662 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
663 break;
664 }
665 tcg_gen_extr_i64_i32(temp, temp2, temp64);
666 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
667 tcg_gen_sub_tl, tcg_gen_add_tl);
668 tcg_temp_free(temp);
669 tcg_temp_free(temp2);
670 tcg_temp_free_i64(temp64);
671 }
672
673 static inline void
674 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
675 TCGv r3, uint32_t n, uint32_t mode)
676 {
677 TCGv temp = tcg_const_i32(n);
678 TCGv_i64 temp64 = tcg_temp_new_i64();
679 TCGv_i64 temp64_2 = tcg_temp_new_i64();
680 TCGv_i64 temp64_3 = tcg_temp_new_i64();
681 switch (mode) {
682 case MODE_LL:
683 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
684 break;
685 case MODE_LU:
686 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
687 break;
688 case MODE_UL:
689 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
690 break;
691 case MODE_UU:
692 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
693 break;
694 }
695 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
696 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
697 tcg_gen_ext32s_i64(temp64, temp64); /* low */
698 tcg_gen_sub_i64(temp64, temp64_2, temp64);
699 tcg_gen_shli_i64(temp64, temp64, 16);
700
701 gen_add64_d(temp64_2, temp64_3, temp64);
702 /* write back result */
703 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
704
705 tcg_temp_free(temp);
706 tcg_temp_free_i64(temp64);
707 tcg_temp_free_i64(temp64_2);
708 tcg_temp_free_i64(temp64_3);
709 }
710
711 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
712
713 static inline void
714 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
715 TCGv r3, uint32_t n, uint32_t mode)
716 {
717 TCGv temp = tcg_const_i32(n);
718 TCGv temp2 = tcg_temp_new();
719 TCGv temp3 = tcg_temp_new();
720 TCGv_i64 temp64 = tcg_temp_new_i64();
721
722 switch (mode) {
723 case MODE_LL:
724 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
725 break;
726 case MODE_LU:
727 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
728 break;
729 case MODE_UL:
730 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
731 break;
732 case MODE_UU:
733 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
734 break;
735 }
736 tcg_gen_extr_i64_i32(temp, temp2, temp64);
737 gen_adds(ret_low, r1_low, temp);
738 tcg_gen_mov_tl(temp, cpu_PSW_V);
739 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
740 gen_adds(ret_high, r1_high, temp2);
741 /* combine v bits */
742 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
743 /* combine av bits */
744 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
745
746 tcg_temp_free(temp);
747 tcg_temp_free(temp2);
748 tcg_temp_free(temp3);
749 tcg_temp_free_i64(temp64);
750
751 }
752
753 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
754
755 static inline void
756 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
757 TCGv r3, uint32_t n, uint32_t mode)
758 {
759 TCGv temp = tcg_const_i32(n);
760 TCGv temp2 = tcg_temp_new();
761 TCGv temp3 = tcg_temp_new();
762 TCGv_i64 temp64 = tcg_temp_new_i64();
763
764 switch (mode) {
765 case MODE_LL:
766 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
767 break;
768 case MODE_LU:
769 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
770 break;
771 case MODE_UL:
772 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
773 break;
774 case MODE_UU:
775 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
776 break;
777 }
778 tcg_gen_extr_i64_i32(temp, temp2, temp64);
779 gen_subs(ret_low, r1_low, temp);
780 tcg_gen_mov_tl(temp, cpu_PSW_V);
781 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
782 gen_adds(ret_high, r1_high, temp2);
783 /* combine v bits */
784 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
785 /* combine av bits */
786 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
787
788 tcg_temp_free(temp);
789 tcg_temp_free(temp2);
790 tcg_temp_free(temp3);
791 tcg_temp_free_i64(temp64);
792
793 }
794
795 static inline void
796 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
797 TCGv r3, uint32_t n, uint32_t mode)
798 {
799 TCGv temp = tcg_const_i32(n);
800 TCGv_i64 temp64 = tcg_temp_new_i64();
801 TCGv_i64 temp64_2 = tcg_temp_new_i64();
802
803 switch (mode) {
804 case MODE_LL:
805 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
806 break;
807 case MODE_LU:
808 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
809 break;
810 case MODE_UL:
811 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
812 break;
813 case MODE_UU:
814 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
815 break;
816 }
817 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
818 tcg_gen_ext32s_i64(temp64, temp64); /* low */
819 tcg_gen_sub_i64(temp64, temp64_2, temp64);
820 tcg_gen_shli_i64(temp64, temp64, 16);
821 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
822
823 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
824 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
825
826 tcg_temp_free(temp);
827 tcg_temp_free_i64(temp64);
828 tcg_temp_free_i64(temp64_2);
829 }
830
831
832 static inline void
833 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
834 TCGv r3, uint32_t n, uint32_t mode)
835 {
836 TCGv temp = tcg_const_i32(n);
837 TCGv_i64 temp64 = tcg_temp_new_i64();
838 TCGv_i64 temp64_2 = tcg_temp_new_i64();
839 TCGv_i64 temp64_3 = tcg_temp_new_i64();
840 switch (mode) {
841 case MODE_LL:
842 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
843 break;
844 case MODE_LU:
845 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
846 break;
847 case MODE_UL:
848 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
849 break;
850 case MODE_UU:
851 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
852 break;
853 }
854 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
855 gen_add64_d(temp64_3, temp64_2, temp64);
856 /* write back result */
857 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
858
859 tcg_temp_free(temp);
860 tcg_temp_free_i64(temp64);
861 tcg_temp_free_i64(temp64_2);
862 tcg_temp_free_i64(temp64_3);
863 }
864
865 static inline void
866 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
867 TCGv r3, uint32_t n, uint32_t mode)
868 {
869 TCGv temp = tcg_const_i32(n);
870 TCGv_i64 temp64 = tcg_temp_new_i64();
871 TCGv_i64 temp64_2 = tcg_temp_new_i64();
872 switch (mode) {
873 case MODE_LL:
874 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
875 break;
876 case MODE_LU:
877 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
878 break;
879 case MODE_UL:
880 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
881 break;
882 case MODE_UU:
883 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
884 break;
885 }
886 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
887 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
888 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
889
890 tcg_temp_free(temp);
891 tcg_temp_free_i64(temp64);
892 tcg_temp_free_i64(temp64_2);
893 }
894
895 static inline void
896 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
897 uint32_t mode)
898 {
899 TCGv temp = tcg_const_i32(n);
900 TCGv_i64 temp64 = tcg_temp_new_i64();
901 switch (mode) {
902 case MODE_LL:
903 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
904 break;
905 case MODE_LU:
906 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
907 break;
908 case MODE_UL:
909 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
910 break;
911 case MODE_UU:
912 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
913 break;
914 }
915 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
916
917 tcg_temp_free(temp);
918 tcg_temp_free_i64(temp64);
919 }
920
921 static inline void
922 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
923 {
924 TCGv temp = tcg_temp_new();
925 TCGv temp2 = tcg_temp_new();
926
927 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
928 tcg_gen_shli_tl(temp, r1, 16);
929 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
930
931 tcg_temp_free(temp);
932 tcg_temp_free(temp2);
933 }
934
935 static inline void
936 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
937 {
938 TCGv temp = tcg_const_i32(n);
939 TCGv temp2 = tcg_temp_new();
940 TCGv_i64 temp64 = tcg_temp_new_i64();
941 switch (mode) {
942 case MODE_LL:
943 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
944 break;
945 case MODE_LU:
946 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
947 break;
948 case MODE_UL:
949 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
950 break;
951 case MODE_UU:
952 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
953 break;
954 }
955 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
956 tcg_gen_shli_tl(temp, r1, 16);
957 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
958
959 tcg_temp_free(temp);
960 tcg_temp_free(temp2);
961 tcg_temp_free_i64(temp64);
962 }
963
964
965 static inline void
966 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
967 uint32_t n, uint32_t mode)
968 {
969 TCGv temp = tcg_const_i32(n);
970 TCGv_i64 temp64 = tcg_temp_new_i64();
971 switch (mode) {
972 case MODE_LL:
973 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
974 break;
975 case MODE_LU:
976 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
977 break;
978 case MODE_UL:
979 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
980 break;
981 case MODE_UU:
982 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
983 break;
984 }
985 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
986
987 tcg_temp_free(temp);
988 tcg_temp_free_i64(temp64);
989 }
990
991 static inline void
992 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
993 {
994 TCGv temp = tcg_temp_new();
995 TCGv temp2 = tcg_temp_new();
996
997 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
998 tcg_gen_shli_tl(temp, r1, 16);
999 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1000
1001 tcg_temp_free(temp);
1002 tcg_temp_free(temp2);
1003 }
1004
1005 static inline void
1006 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1007 {
1008 TCGv temp = tcg_const_i32(n);
1009 TCGv temp2 = tcg_temp_new();
1010 TCGv_i64 temp64 = tcg_temp_new_i64();
1011 switch (mode) {
1012 case MODE_LL:
1013 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1014 break;
1015 case MODE_LU:
1016 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1017 break;
1018 case MODE_UL:
1019 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1020 break;
1021 case MODE_UU:
1022 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1023 break;
1024 }
1025 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1026 tcg_gen_shli_tl(temp, r1, 16);
1027 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1028
1029 tcg_temp_free(temp);
1030 tcg_temp_free(temp2);
1031 tcg_temp_free_i64(temp64);
1032 }
1033
1034 static inline void
1035 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1036 {
1037 TCGv temp = tcg_const_i32(n);
1038 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1039 tcg_temp_free(temp);
1040 }
1041
1042 static inline void
1043 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1044 {
1045 TCGv temp = tcg_const_i32(n);
1046 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1047 tcg_temp_free(temp);
1048 }
1049
1050 static inline void
1051 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1052 uint32_t up_shift, CPUTriCoreState *env)
1053 {
1054 TCGv temp = tcg_temp_new();
1055 TCGv temp2 = tcg_temp_new();
1056 TCGv temp3 = tcg_temp_new();
1057 TCGv_i64 t1 = tcg_temp_new_i64();
1058 TCGv_i64 t2 = tcg_temp_new_i64();
1059 TCGv_i64 t3 = tcg_temp_new_i64();
1060
1061 tcg_gen_ext_i32_i64(t2, arg2);
1062 tcg_gen_ext_i32_i64(t3, arg3);
1063
1064 tcg_gen_mul_i64(t2, t2, t3);
1065 tcg_gen_shli_i64(t2, t2, n);
1066
1067 tcg_gen_ext_i32_i64(t1, arg1);
1068 tcg_gen_sari_i64(t2, t2, up_shift);
1069
1070 tcg_gen_add_i64(t3, t1, t2);
1071 tcg_gen_trunc_i64_i32(temp3, t3);
1072 /* calc v bit */
1073 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1074 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1075 tcg_gen_or_i64(t1, t1, t2);
1076 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1077 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1078 /* We produce an overflow on the host if the mul before was
1079 (0x80000000 * 0x80000000) << 1). If this is the
1080 case, we negate the ovf. */
1081 if (n == 1) {
1082 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1083 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1084 tcg_gen_and_tl(temp, temp, temp2);
1085 tcg_gen_shli_tl(temp, temp, 31);
1086 /* negate v bit, if special condition */
1087 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1088 }
1089 /* Calc SV bit */
1090 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1091 /* Calc AV/SAV bits */
1092 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1093 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1094 /* calc SAV */
1095 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1096 /* write back result */
1097 tcg_gen_mov_tl(ret, temp3);
1098
1099 tcg_temp_free(temp);
1100 tcg_temp_free(temp2);
1101 tcg_temp_free(temp3);
1102 tcg_temp_free_i64(t1);
1103 tcg_temp_free_i64(t2);
1104 tcg_temp_free_i64(t3);
1105 }
1106
1107 static inline void
1108 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1109 {
1110 TCGv temp = tcg_temp_new();
1111 TCGv temp2 = tcg_temp_new();
1112 if (n == 0) {
1113 tcg_gen_mul_tl(temp, arg2, arg3);
1114 } else { /* n is exspected to be 1 */
1115 tcg_gen_mul_tl(temp, arg2, arg3);
1116 tcg_gen_shli_tl(temp, temp, 1);
1117 /* catch special case r1 = r2 = 0x8000 */
1118 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1119 tcg_gen_sub_tl(temp, temp, temp2);
1120 }
1121 gen_add_d(ret, arg1, temp);
1122
1123 tcg_temp_free(temp);
1124 tcg_temp_free(temp2);
1125 }
1126
1127 static inline void
1128 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1129 {
1130 TCGv temp = tcg_temp_new();
1131 TCGv temp2 = tcg_temp_new();
1132 if (n == 0) {
1133 tcg_gen_mul_tl(temp, arg2, arg3);
1134 } else { /* n is exspected to be 1 */
1135 tcg_gen_mul_tl(temp, arg2, arg3);
1136 tcg_gen_shli_tl(temp, temp, 1);
1137 /* catch special case r1 = r2 = 0x8000 */
1138 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1139 tcg_gen_sub_tl(temp, temp, temp2);
1140 }
1141 gen_adds(ret, arg1, temp);
1142
1143 tcg_temp_free(temp);
1144 tcg_temp_free(temp2);
1145 }
1146
1147 static inline void
1148 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1149 TCGv arg3, uint32_t n)
1150 {
1151 TCGv temp = tcg_temp_new();
1152 TCGv temp2 = tcg_temp_new();
1153 TCGv_i64 t1 = tcg_temp_new_i64();
1154 TCGv_i64 t2 = tcg_temp_new_i64();
1155 TCGv_i64 t3 = tcg_temp_new_i64();
1156
1157 if (n == 0) {
1158 tcg_gen_mul_tl(temp, arg2, arg3);
1159 } else { /* n is exspected to be 1 */
1160 tcg_gen_mul_tl(temp, arg2, arg3);
1161 tcg_gen_shli_tl(temp, temp, 1);
1162 /* catch special case r1 = r2 = 0x8000 */
1163 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1164 tcg_gen_sub_tl(temp, temp, temp2);
1165 }
1166 tcg_gen_ext_i32_i64(t2, temp);
1167 tcg_gen_shli_i64(t2, t2, 16);
1168 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1169 gen_add64_d(t3, t1, t2);
1170 /* write back result */
1171 tcg_gen_extr_i64_i32(rl, rh, t3);
1172
1173 tcg_temp_free_i64(t1);
1174 tcg_temp_free_i64(t2);
1175 tcg_temp_free_i64(t3);
1176 tcg_temp_free(temp);
1177 tcg_temp_free(temp2);
1178 }
1179
1180 static inline void
1181 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1182 TCGv arg3, uint32_t n)
1183 {
1184 TCGv temp = tcg_temp_new();
1185 TCGv temp2 = tcg_temp_new();
1186 TCGv_i64 t1 = tcg_temp_new_i64();
1187 TCGv_i64 t2 = tcg_temp_new_i64();
1188
1189 if (n == 0) {
1190 tcg_gen_mul_tl(temp, arg2, arg3);
1191 } else { /* n is exspected to be 1 */
1192 tcg_gen_mul_tl(temp, arg2, arg3);
1193 tcg_gen_shli_tl(temp, temp, 1);
1194 /* catch special case r1 = r2 = 0x8000 */
1195 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1196 tcg_gen_sub_tl(temp, temp, temp2);
1197 }
1198 tcg_gen_ext_i32_i64(t2, temp);
1199 tcg_gen_shli_i64(t2, t2, 16);
1200 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1201
1202 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1203 tcg_gen_extr_i64_i32(rl, rh, t1);
1204
1205 tcg_temp_free(temp);
1206 tcg_temp_free(temp2);
1207 tcg_temp_free_i64(t1);
1208 tcg_temp_free_i64(t2);
1209 }
1210
1211 static inline void
1212 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1213 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1214 {
1215 TCGv_i64 t1 = tcg_temp_new_i64();
1216 TCGv_i64 t2 = tcg_temp_new_i64();
1217 TCGv_i64 t3 = tcg_temp_new_i64();
1218 TCGv_i64 t4 = tcg_temp_new_i64();
1219 TCGv temp, temp2;
1220
1221 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1222 tcg_gen_ext_i32_i64(t2, arg2);
1223 tcg_gen_ext_i32_i64(t3, arg3);
1224
1225 tcg_gen_mul_i64(t2, t2, t3);
1226 if (n != 0) {
1227 tcg_gen_shli_i64(t2, t2, 1);
1228 }
1229 tcg_gen_add_i64(t4, t1, t2);
1230 /* calc v bit */
1231 tcg_gen_xor_i64(t3, t4, t1);
1232 tcg_gen_xor_i64(t2, t1, t2);
1233 tcg_gen_andc_i64(t3, t3, t2);
1234 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
1235 /* We produce an overflow on the host if the mul before was
1236 (0x80000000 * 0x80000000) << 1). If this is the
1237 case, we negate the ovf. */
1238 if (n == 1) {
1239 temp = tcg_temp_new();
1240 temp2 = tcg_temp_new();
1241 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1242 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1243 tcg_gen_and_tl(temp, temp, temp2);
1244 tcg_gen_shli_tl(temp, temp, 31);
1245 /* negate v bit, if special condition */
1246 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1247
1248 tcg_temp_free(temp);
1249 tcg_temp_free(temp2);
1250 }
1251 /* write back result */
1252 tcg_gen_extr_i64_i32(rl, rh, t4);
1253 /* Calc SV bit */
1254 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1255 /* Calc AV/SAV bits */
1256 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1257 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1258 /* calc SAV */
1259 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1260
1261 tcg_temp_free_i64(t1);
1262 tcg_temp_free_i64(t2);
1263 tcg_temp_free_i64(t3);
1264 tcg_temp_free_i64(t4);
1265 }
1266
1267 static inline void
1268 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1269 uint32_t up_shift)
1270 {
1271 TCGv_i64 t1 = tcg_temp_new_i64();
1272 TCGv_i64 t2 = tcg_temp_new_i64();
1273 TCGv_i64 t3 = tcg_temp_new_i64();
1274
1275 tcg_gen_ext_i32_i64(t1, arg1);
1276 tcg_gen_ext_i32_i64(t2, arg2);
1277 tcg_gen_ext_i32_i64(t3, arg3);
1278
1279 tcg_gen_mul_i64(t2, t2, t3);
1280 tcg_gen_sari_i64(t2, t2, up_shift - n);
1281
1282 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1283
1284 tcg_temp_free_i64(t1);
1285 tcg_temp_free_i64(t2);
1286 tcg_temp_free_i64(t3);
1287 }
1288
1289 static inline void
1290 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1291 TCGv arg3, uint32_t n)
1292 {
1293 TCGv_i64 r1 = tcg_temp_new_i64();
1294 TCGv temp = tcg_const_i32(n);
1295
1296 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1297 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1298 tcg_gen_extr_i64_i32(rl, rh, r1);
1299
1300 tcg_temp_free_i64(r1);
1301 tcg_temp_free(temp);
1302 }
1303 /* ret = r2 - (r1 * r3); */
1304 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1305 {
1306 TCGv_i64 t1 = tcg_temp_new_i64();
1307 TCGv_i64 t2 = tcg_temp_new_i64();
1308 TCGv_i64 t3 = tcg_temp_new_i64();
1309
1310 tcg_gen_ext_i32_i64(t1, r1);
1311 tcg_gen_ext_i32_i64(t2, r2);
1312 tcg_gen_ext_i32_i64(t3, r3);
1313
1314 tcg_gen_mul_i64(t1, t1, t3);
1315 tcg_gen_sub_i64(t1, t2, t1);
1316
1317 tcg_gen_trunc_i64_i32(ret, t1);
1318 /* calc V
1319 t2 > 0x7fffffff */
1320 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1321 /* result < -0x80000000 */
1322 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1323 tcg_gen_or_i64(t2, t2, t3);
1324 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
1325 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1326
1327 /* Calc SV bit */
1328 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1329 /* Calc AV/SAV bits */
1330 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1331 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1332 /* calc SAV */
1333 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1334
1335 tcg_temp_free_i64(t1);
1336 tcg_temp_free_i64(t2);
1337 tcg_temp_free_i64(t3);
1338 }
1339
1340 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1341 {
1342 TCGv temp = tcg_const_i32(con);
1343 gen_msub32_d(ret, r1, r2, temp);
1344 tcg_temp_free(temp);
1345 }
1346
1347 static inline void
1348 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1349 TCGv r3)
1350 {
1351 TCGv t1 = tcg_temp_new();
1352 TCGv t2 = tcg_temp_new();
1353 TCGv t3 = tcg_temp_new();
1354 TCGv t4 = tcg_temp_new();
1355
1356 tcg_gen_muls2_tl(t1, t2, r1, r3);
1357 /* only the sub can overflow */
1358 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1359 /* calc V bit */
1360 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1361 tcg_gen_xor_tl(t1, r2_high, t2);
1362 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1363 /* Calc SV bit */
1364 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1365 /* Calc AV/SAV bits */
1366 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1367 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1368 /* calc SAV */
1369 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1370 /* write back the result */
1371 tcg_gen_mov_tl(ret_low, t3);
1372 tcg_gen_mov_tl(ret_high, t4);
1373
1374 tcg_temp_free(t1);
1375 tcg_temp_free(t2);
1376 tcg_temp_free(t3);
1377 tcg_temp_free(t4);
1378 }
1379
1380 static inline void
1381 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1382 int32_t con)
1383 {
1384 TCGv temp = tcg_const_i32(con);
1385 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1386 tcg_temp_free(temp);
1387 }
1388
1389 static inline void
1390 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1391 TCGv r3)
1392 {
1393 TCGv_i64 t1 = tcg_temp_new_i64();
1394 TCGv_i64 t2 = tcg_temp_new_i64();
1395 TCGv_i64 t3 = tcg_temp_new_i64();
1396
1397 tcg_gen_extu_i32_i64(t1, r1);
1398 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1399 tcg_gen_extu_i32_i64(t3, r3);
1400
1401 tcg_gen_mul_i64(t1, t1, t3);
1402 tcg_gen_sub_i64(t3, t2, t1);
1403 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1404 /* calc V bit, only the sub can overflow, if t1 > t2 */
1405 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1406 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1407 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1408 /* Calc SV bit */
1409 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1410 /* Calc AV/SAV bits */
1411 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1412 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1413 /* calc SAV */
1414 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1415
1416 tcg_temp_free_i64(t1);
1417 tcg_temp_free_i64(t2);
1418 tcg_temp_free_i64(t3);
1419 }
1420
1421 static inline void
1422 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1423 int32_t con)
1424 {
1425 TCGv temp = tcg_const_i32(con);
1426 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1427 tcg_temp_free(temp);
1428 }
1429
1430 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1431 {
1432 TCGv temp = tcg_const_i32(r2);
1433 gen_add_d(ret, r1, temp);
1434 tcg_temp_free(temp);
1435 }
1436 /* calculate the carry bit too */
1437 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1438 {
1439 TCGv t0 = tcg_temp_new_i32();
1440 TCGv result = tcg_temp_new_i32();
1441
1442 tcg_gen_movi_tl(t0, 0);
1443 /* Addition and set C/V/SV bits */
1444 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1445 /* calc V bit */
1446 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1447 tcg_gen_xor_tl(t0, r1, r2);
1448 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1449 /* Calc SV bit */
1450 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1451 /* Calc AV/SAV bits */
1452 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1453 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1454 /* calc SAV */
1455 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1456 /* write back result */
1457 tcg_gen_mov_tl(ret, result);
1458
1459 tcg_temp_free(result);
1460 tcg_temp_free(t0);
1461 }
1462
1463 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1464 {
1465 TCGv temp = tcg_const_i32(con);
1466 gen_add_CC(ret, r1, temp);
1467 tcg_temp_free(temp);
1468 }
1469
1470 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1471 {
1472 TCGv carry = tcg_temp_new_i32();
1473 TCGv t0 = tcg_temp_new_i32();
1474 TCGv result = tcg_temp_new_i32();
1475
1476 tcg_gen_movi_tl(t0, 0);
1477 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1478 /* Addition, carry and set C/V/SV bits */
1479 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1480 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1481 /* calc V bit */
1482 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1483 tcg_gen_xor_tl(t0, r1, r2);
1484 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1485 /* Calc SV bit */
1486 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1487 /* Calc AV/SAV bits */
1488 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1489 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1490 /* calc SAV */
1491 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1492 /* write back result */
1493 tcg_gen_mov_tl(ret, result);
1494
1495 tcg_temp_free(result);
1496 tcg_temp_free(t0);
1497 tcg_temp_free(carry);
1498 }
1499
1500 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1501 {
1502 TCGv temp = tcg_const_i32(con);
1503 gen_addc_CC(ret, r1, temp);
1504 tcg_temp_free(temp);
1505 }
1506
1507 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1508 TCGv r4)
1509 {
1510 TCGv temp = tcg_temp_new();
1511 TCGv temp2 = tcg_temp_new();
1512 TCGv result = tcg_temp_new();
1513 TCGv mask = tcg_temp_new();
1514 TCGv t0 = tcg_const_i32(0);
1515
1516 /* create mask for sticky bits */
1517 tcg_gen_setcond_tl(cond, mask, r4, t0);
1518 tcg_gen_shli_tl(mask, mask, 31);
1519
1520 tcg_gen_add_tl(result, r1, r2);
1521 /* Calc PSW_V */
1522 tcg_gen_xor_tl(temp, result, r1);
1523 tcg_gen_xor_tl(temp2, r1, r2);
1524 tcg_gen_andc_tl(temp, temp, temp2);
1525 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1526 /* Set PSW_SV */
1527 tcg_gen_and_tl(temp, temp, mask);
1528 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1529 /* calc AV bit */
1530 tcg_gen_add_tl(temp, result, result);
1531 tcg_gen_xor_tl(temp, temp, result);
1532 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1533 /* calc SAV bit */
1534 tcg_gen_and_tl(temp, temp, mask);
1535 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1536 /* write back result */
1537 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1538
1539 tcg_temp_free(t0);
1540 tcg_temp_free(temp);
1541 tcg_temp_free(temp2);
1542 tcg_temp_free(result);
1543 tcg_temp_free(mask);
1544 }
1545
1546 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1547 TCGv r3, TCGv r4)
1548 {
1549 TCGv temp = tcg_const_i32(r2);
1550 gen_cond_add(cond, r1, temp, r3, r4);
1551 tcg_temp_free(temp);
1552 }
1553
1554 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1555 {
1556 TCGv temp = tcg_temp_new_i32();
1557 TCGv result = tcg_temp_new_i32();
1558
1559 tcg_gen_sub_tl(result, r1, r2);
1560 /* calc V bit */
1561 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1562 tcg_gen_xor_tl(temp, r1, r2);
1563 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1564 /* calc SV bit */
1565 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1566 /* Calc AV bit */
1567 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1568 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1569 /* calc SAV bit */
1570 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1571 /* write back result */
1572 tcg_gen_mov_tl(ret, result);
1573
1574 tcg_temp_free(temp);
1575 tcg_temp_free(result);
1576 }
1577
1578 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1579 {
1580 TCGv result = tcg_temp_new();
1581 TCGv temp = tcg_temp_new();
1582
1583 tcg_gen_sub_tl(result, r1, r2);
1584 /* calc C bit */
1585 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1586 /* calc V bit */
1587 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1588 tcg_gen_xor_tl(temp, r1, r2);
1589 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1590 /* calc SV bit */
1591 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1592 /* Calc AV bit */
1593 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1594 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1595 /* calc SAV bit */
1596 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1597 /* write back result */
1598 tcg_gen_mov_tl(ret, result);
1599
1600 tcg_temp_free(result);
1601 tcg_temp_free(temp);
1602 }
1603
1604 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1605 {
1606 TCGv temp = tcg_temp_new();
1607 tcg_gen_not_tl(temp, r2);
1608 gen_addc_CC(ret, r1, temp);
1609 tcg_temp_free(temp);
1610 }
1611
1612 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1613 TCGv r4)
1614 {
1615 TCGv temp = tcg_temp_new();
1616 TCGv temp2 = tcg_temp_new();
1617 TCGv result = tcg_temp_new();
1618 TCGv mask = tcg_temp_new();
1619 TCGv t0 = tcg_const_i32(0);
1620
1621 /* create mask for sticky bits */
1622 tcg_gen_setcond_tl(cond, mask, r4, t0);
1623 tcg_gen_shli_tl(mask, mask, 31);
1624
1625 tcg_gen_sub_tl(result, r1, r2);
1626 /* Calc PSW_V */
1627 tcg_gen_xor_tl(temp, result, r1);
1628 tcg_gen_xor_tl(temp2, r1, r2);
1629 tcg_gen_and_tl(temp, temp, temp2);
1630 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1631 /* Set PSW_SV */
1632 tcg_gen_and_tl(temp, temp, mask);
1633 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1634 /* calc AV bit */
1635 tcg_gen_add_tl(temp, result, result);
1636 tcg_gen_xor_tl(temp, temp, result);
1637 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1638 /* calc SAV bit */
1639 tcg_gen_and_tl(temp, temp, mask);
1640 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1641 /* write back result */
1642 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1643
1644 tcg_temp_free(t0);
1645 tcg_temp_free(temp);
1646 tcg_temp_free(temp2);
1647 tcg_temp_free(result);
1648 tcg_temp_free(mask);
1649 }
1650
1651 static inline void gen_abs(TCGv ret, TCGv r1)
1652 {
1653 TCGv temp = tcg_temp_new();
1654 TCGv t0 = tcg_const_i32(0);
1655
1656 tcg_gen_neg_tl(temp, r1);
1657 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
1658 /* overflow can only happen, if r1 = 0x80000000 */
1659 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
1660 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1661 /* calc SV bit */
1662 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1663 /* Calc AV bit */
1664 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1665 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1666 /* calc SAV bit */
1667 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1668
1669 tcg_temp_free(temp);
1670 tcg_temp_free(t0);
1671 }
1672
1673 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
1674 {
1675 TCGv temp = tcg_temp_new_i32();
1676 TCGv result = tcg_temp_new_i32();
1677
1678 tcg_gen_sub_tl(result, r1, r2);
1679 tcg_gen_sub_tl(temp, r2, r1);
1680 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
1681
1682 /* calc V bit */
1683 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1684 tcg_gen_xor_tl(temp, result, r2);
1685 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
1686 tcg_gen_xor_tl(temp, r1, r2);
1687 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1688 /* calc SV bit */
1689 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1690 /* Calc AV bit */
1691 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1692 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1693 /* calc SAV bit */
1694 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1695 /* write back result */
1696 tcg_gen_mov_tl(ret, result);
1697
1698 tcg_temp_free(temp);
1699 tcg_temp_free(result);
1700 }
1701
1702 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
1703 {
1704 TCGv temp = tcg_const_i32(con);
1705 gen_absdif(ret, r1, temp);
1706 tcg_temp_free(temp);
1707 }
1708
1709 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
1710 {
1711 TCGv temp = tcg_const_i32(con);
1712 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
1713 tcg_temp_free(temp);
1714 }
1715
1716 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
1717 {
1718 TCGv high = tcg_temp_new();
1719 TCGv low = tcg_temp_new();
1720
1721 tcg_gen_muls2_tl(low, high, r1, r2);
1722 tcg_gen_mov_tl(ret, low);
1723 /* calc V bit */
1724 tcg_gen_sari_tl(low, low, 31);
1725 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
1726 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1727 /* calc SV bit */
1728 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1729 /* Calc AV bit */
1730 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1731 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1732 /* calc SAV bit */
1733 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1734
1735 tcg_temp_free(high);
1736 tcg_temp_free(low);
1737 }
1738
1739 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
1740 {
1741 TCGv temp = tcg_const_i32(con);
1742 gen_mul_i32s(ret, r1, temp);
1743 tcg_temp_free(temp);
1744 }
1745
1746 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
1747 {
1748 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
1749 /* clear V bit */
1750 tcg_gen_movi_tl(cpu_PSW_V, 0);
1751 /* calc SV bit */
1752 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1753 /* Calc AV bit */
1754 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1755 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1756 /* calc SAV bit */
1757 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1758 }
1759
1760 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
1761 int32_t con)
1762 {
1763 TCGv temp = tcg_const_i32(con);
1764 gen_mul_i64s(ret_low, ret_high, r1, temp);
1765 tcg_temp_free(temp);
1766 }
1767
1768 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
1769 {
1770 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
1771 /* clear V bit */
1772 tcg_gen_movi_tl(cpu_PSW_V, 0);
1773 /* calc SV bit */
1774 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1775 /* Calc AV bit */
1776 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1777 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1778 /* calc SAV bit */
1779 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1780 }
1781
1782 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
1783 int32_t con)
1784 {
1785 TCGv temp = tcg_const_i32(con);
1786 gen_mul_i64u(ret_low, ret_high, r1, temp);
1787 tcg_temp_free(temp);
1788 }
1789
1790 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
1791 {
1792 TCGv temp = tcg_const_i32(con);
1793 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
1794 tcg_temp_free(temp);
1795 }
1796
1797 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
1798 {
1799 TCGv temp = tcg_const_i32(con);
1800 gen_helper_mul_suov(ret, cpu_env, r1, temp);
1801 tcg_temp_free(temp);
1802 }
1803 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
1804 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1805 {
1806 TCGv temp = tcg_const_i32(con);
1807 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
1808 tcg_temp_free(temp);
1809 }
1810
1811 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1812 {
1813 TCGv temp = tcg_const_i32(con);
1814 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
1815 tcg_temp_free(temp);
1816 }
1817
1818 static void
1819 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
1820 {
1821 TCGv temp = tcg_temp_new();
1822 TCGv_i64 temp_64 = tcg_temp_new_i64();
1823 TCGv_i64 temp2_64 = tcg_temp_new_i64();
1824
1825 if (n == 0) {
1826 if (up_shift == 32) {
1827 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
1828 } else if (up_shift == 16) {
1829 tcg_gen_ext_i32_i64(temp_64, arg1);
1830 tcg_gen_ext_i32_i64(temp2_64, arg2);
1831
1832 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
1833 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
1834 tcg_gen_extr_i64_i32(rl, rh, temp_64);
1835 } else {
1836 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
1837 }
1838 /* reset v bit */
1839 tcg_gen_movi_tl(cpu_PSW_V, 0);
1840 } else { /* n is exspected to be 1 */
1841 tcg_gen_ext_i32_i64(temp_64, arg1);
1842 tcg_gen_ext_i32_i64(temp2_64, arg2);
1843
1844 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
1845
1846 if (up_shift == 0) {
1847 tcg_gen_shli_i64(temp_64, temp_64, 1);
1848 } else {
1849 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
1850 }
1851 tcg_gen_extr_i64_i32(rl, rh, temp_64);
1852 /* overflow only occours if r1 = r2 = 0x8000 */
1853 if (up_shift == 0) {/* result is 64 bit */
1854 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
1855 0x80000000);
1856 } else { /* result is 32 bit */
1857 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
1858 0x80000000);
1859 }
1860 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1861 /* calc sv overflow bit */
1862 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1863 }
1864 /* calc av overflow bit */
1865 if (up_shift == 0) {
1866 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1867 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1868 } else {
1869 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
1870 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
1871 }
1872 /* calc sav overflow bit */
1873 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1874 tcg_temp_free(temp);
1875 tcg_temp_free_i64(temp_64);
1876 tcg_temp_free_i64(temp2_64);
1877 }
1878
1879 static void
1880 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
1881 {
1882 TCGv temp = tcg_temp_new();
1883 if (n == 0) {
1884 tcg_gen_mul_tl(ret, arg1, arg2);
1885 } else { /* n is exspected to be 1 */
1886 tcg_gen_mul_tl(ret, arg1, arg2);
1887 tcg_gen_shli_tl(ret, ret, 1);
1888 /* catch special case r1 = r2 = 0x8000 */
1889 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
1890 tcg_gen_sub_tl(ret, ret, temp);
1891 }
1892 /* reset v bit */
1893 tcg_gen_movi_tl(cpu_PSW_V, 0);
1894 /* calc av overflow bit */
1895 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1896 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1897 /* calc sav overflow bit */
1898 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1899
1900 tcg_temp_free(temp);
1901 }
1902
1903 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
1904 {
1905 TCGv temp = tcg_temp_new();
1906 if (n == 0) {
1907 tcg_gen_mul_tl(ret, arg1, arg2);
1908 tcg_gen_addi_tl(ret, ret, 0x8000);
1909 } else {
1910 tcg_gen_mul_tl(ret, arg1, arg2);
1911 tcg_gen_shli_tl(ret, ret, 1);
1912 tcg_gen_addi_tl(ret, ret, 0x8000);
1913 /* catch special case r1 = r2 = 0x8000 */
1914 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
1915 tcg_gen_muli_tl(temp, temp, 0x8001);
1916 tcg_gen_sub_tl(ret, ret, temp);
1917 }
1918 /* reset v bit */
1919 tcg_gen_movi_tl(cpu_PSW_V, 0);
1920 /* calc av overflow bit */
1921 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1922 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1923 /* calc sav overflow bit */
1924 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1925 /* cut halfword off */
1926 tcg_gen_andi_tl(ret, ret, 0xffff0000);
1927
1928 tcg_temp_free(temp);
1929 }
1930
1931 static inline void
1932 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1933 TCGv r3)
1934 {
1935 TCGv_i64 temp64 = tcg_temp_new_i64();
1936 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1937 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
1938 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1939 tcg_temp_free_i64(temp64);
1940 }
1941
1942 static inline void
1943 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1944 int32_t con)
1945 {
1946 TCGv temp = tcg_const_i32(con);
1947 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1948 tcg_temp_free(temp);
1949 }
1950
1951 static inline void
1952 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1953 TCGv r3)
1954 {
1955 TCGv_i64 temp64 = tcg_temp_new_i64();
1956 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1957 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
1958 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1959 tcg_temp_free_i64(temp64);
1960 }
1961
1962 static inline void
1963 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1964 int32_t con)
1965 {
1966 TCGv temp = tcg_const_i32(con);
1967 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1968 tcg_temp_free(temp);
1969 }
1970
1971 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1972 {
1973 TCGv temp = tcg_const_i32(con);
1974 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
1975 tcg_temp_free(temp);
1976 }
1977
1978 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1979 {
1980 TCGv temp = tcg_const_i32(con);
1981 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
1982 tcg_temp_free(temp);
1983 }
1984
1985 static inline void
1986 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1987 TCGv r3)
1988 {
1989 TCGv_i64 temp64 = tcg_temp_new_i64();
1990 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1991 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
1992 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1993 tcg_temp_free_i64(temp64);
1994 }
1995
1996 static inline void
1997 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1998 int32_t con)
1999 {
2000 TCGv temp = tcg_const_i32(con);
2001 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2002 tcg_temp_free(temp);
2003 }
2004
2005 static inline void
2006 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2007 TCGv r3)
2008 {
2009 TCGv_i64 temp64 = tcg_temp_new_i64();
2010 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2011 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2012 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2013 tcg_temp_free_i64(temp64);
2014 }
2015
2016 static inline void
2017 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2018 int32_t con)
2019 {
2020 TCGv temp = tcg_const_i32(con);
2021 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2022 tcg_temp_free(temp);
2023 }
2024
2025 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2026 {
2027 TCGv sat_neg = tcg_const_i32(low);
2028 TCGv temp = tcg_const_i32(up);
2029
2030 /* sat_neg = (arg < low ) ? low : arg; */
2031 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2032
2033 /* ret = (sat_neg > up ) ? up : sat_neg; */
2034 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2035
2036 tcg_temp_free(sat_neg);
2037 tcg_temp_free(temp);
2038 }
2039
2040 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2041 {
2042 TCGv temp = tcg_const_i32(up);
2043 /* sat_neg = (arg > up ) ? up : arg; */
2044 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2045 tcg_temp_free(temp);
2046 }
2047
2048 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2049 {
2050 if (shift_count == -32) {
2051 tcg_gen_movi_tl(ret, 0);
2052 } else if (shift_count >= 0) {
2053 tcg_gen_shli_tl(ret, r1, shift_count);
2054 } else {
2055 tcg_gen_shri_tl(ret, r1, -shift_count);
2056 }
2057 }
2058
2059 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2060 {
2061 TCGv temp_low, temp_high;
2062
2063 if (shiftcount == -16) {
2064 tcg_gen_movi_tl(ret, 0);
2065 } else {
2066 temp_high = tcg_temp_new();
2067 temp_low = tcg_temp_new();
2068
2069 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2070 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2071 gen_shi(temp_low, temp_low, shiftcount);
2072 gen_shi(ret, temp_high, shiftcount);
2073 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2074
2075 tcg_temp_free(temp_low);
2076 tcg_temp_free(temp_high);
2077 }
2078 }
2079
2080 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2081 {
2082 uint32_t msk, msk_start;
2083 TCGv temp = tcg_temp_new();
2084 TCGv temp2 = tcg_temp_new();
2085 TCGv t_0 = tcg_const_i32(0);
2086
2087 if (shift_count == 0) {
2088 /* Clear PSW.C and PSW.V */
2089 tcg_gen_movi_tl(cpu_PSW_C, 0);
2090 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2091 tcg_gen_mov_tl(ret, r1);
2092 } else if (shift_count == -32) {
2093 /* set PSW.C */
2094 tcg_gen_mov_tl(cpu_PSW_C, r1);
2095 /* fill ret completly with sign bit */
2096 tcg_gen_sari_tl(ret, r1, 31);
2097 /* clear PSW.V */
2098 tcg_gen_movi_tl(cpu_PSW_V, 0);
2099 } else if (shift_count > 0) {
2100 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2101 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2102
2103 /* calc carry */
2104 msk_start = 32 - shift_count;
2105 msk = ((1 << shift_count) - 1) << msk_start;
2106 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2107 /* calc v/sv bits */
2108 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2109 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2110 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2111 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2112 /* calc sv */
2113 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2114 /* do shift */
2115 tcg_gen_shli_tl(ret, r1, shift_count);
2116
2117 tcg_temp_free(t_max);
2118 tcg_temp_free(t_min);
2119 } else {
2120 /* clear PSW.V */
2121 tcg_gen_movi_tl(cpu_PSW_V, 0);
2122 /* calc carry */
2123 msk = (1 << -shift_count) - 1;
2124 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2125 /* do shift */
2126 tcg_gen_sari_tl(ret, r1, -shift_count);
2127 }
2128 /* calc av overflow bit */
2129 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2130 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2131 /* calc sav overflow bit */
2132 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2133
2134 tcg_temp_free(temp);
2135 tcg_temp_free(temp2);
2136 tcg_temp_free(t_0);
2137 }
2138
2139 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2140 {
2141 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2142 }
2143
2144 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2145 {
2146 TCGv temp = tcg_const_i32(con);
2147 gen_shas(ret, r1, temp);
2148 tcg_temp_free(temp);
2149 }
2150
2151 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2152 {
2153 TCGv low, high;
2154
2155 if (shift_count == 0) {
2156 tcg_gen_mov_tl(ret, r1);
2157 } else if (shift_count > 0) {
2158 low = tcg_temp_new();
2159 high = tcg_temp_new();
2160
2161 tcg_gen_andi_tl(high, r1, 0xffff0000);
2162 tcg_gen_shli_tl(low, r1, shift_count);
2163 tcg_gen_shli_tl(ret, high, shift_count);
2164 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2165
2166 tcg_temp_free(low);
2167 tcg_temp_free(high);
2168 } else {
2169 low = tcg_temp_new();
2170 high = tcg_temp_new();
2171
2172 tcg_gen_ext16s_tl(low, r1);
2173 tcg_gen_sari_tl(low, low, -shift_count);
2174 tcg_gen_sari_tl(ret, r1, -shift_count);
2175 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2176
2177 tcg_temp_free(low);
2178 tcg_temp_free(high);
2179 }
2180
2181 }
2182
2183 /* ret = {ret[30:0], (r1 cond r2)}; */
2184 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2185 {
2186 TCGv temp = tcg_temp_new();
2187 TCGv temp2 = tcg_temp_new();
2188
2189 tcg_gen_shli_tl(temp, ret, 1);
2190 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2191 tcg_gen_or_tl(ret, temp, temp2);
2192
2193 tcg_temp_free(temp);
2194 tcg_temp_free(temp2);
2195 }
2196
2197 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2198 {
2199 TCGv temp = tcg_const_i32(con);
2200 gen_sh_cond(cond, ret, r1, temp);
2201 tcg_temp_free(temp);
2202 }
2203
2204 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2205 {
2206 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2207 }
2208
2209 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2210 {
2211 TCGv temp = tcg_const_i32(con);
2212 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2213 tcg_temp_free(temp);
2214 }
2215
2216 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2217 {
2218 TCGv temp = tcg_const_i32(con);
2219 gen_helper_add_suov(ret, cpu_env, r1, temp);
2220 tcg_temp_free(temp);
2221 }
2222
2223 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2224 {
2225 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2226 }
2227
2228 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2229 {
2230 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2231 }
2232
2233 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2234 int pos1, int pos2,
2235 void(*op1)(TCGv, TCGv, TCGv),
2236 void(*op2)(TCGv, TCGv, TCGv))
2237 {
2238 TCGv temp1, temp2;
2239
2240 temp1 = tcg_temp_new();
2241 temp2 = tcg_temp_new();
2242
2243 tcg_gen_shri_tl(temp2, r2, pos2);
2244 tcg_gen_shri_tl(temp1, r1, pos1);
2245
2246 (*op1)(temp1, temp1, temp2);
2247 (*op2)(temp1 , ret, temp1);
2248
2249 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2250
2251 tcg_temp_free(temp1);
2252 tcg_temp_free(temp2);
2253 }
2254
2255 /* ret = r1[pos1] op1 r2[pos2]; */
2256 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2257 int pos1, int pos2,
2258 void(*op1)(TCGv, TCGv, TCGv))
2259 {
2260 TCGv temp1, temp2;
2261
2262 temp1 = tcg_temp_new();
2263 temp2 = tcg_temp_new();
2264
2265 tcg_gen_shri_tl(temp2, r2, pos2);
2266 tcg_gen_shri_tl(temp1, r1, pos1);
2267
2268 (*op1)(ret, temp1, temp2);
2269
2270 tcg_gen_andi_tl(ret, ret, 0x1);
2271
2272 tcg_temp_free(temp1);
2273 tcg_temp_free(temp2);
2274 }
2275
2276 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2277 void(*op)(TCGv, TCGv, TCGv))
2278 {
2279 TCGv temp = tcg_temp_new();
2280 TCGv temp2 = tcg_temp_new();
2281 /* temp = (arg1 cond arg2 )*/
2282 tcg_gen_setcond_tl(cond, temp, r1, r2);
2283 /* temp2 = ret[0]*/
2284 tcg_gen_andi_tl(temp2, ret, 0x1);
2285 /* temp = temp insn temp2 */
2286 (*op)(temp, temp, temp2);
2287 /* ret = {ret[31:1], temp} */
2288 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2289
2290 tcg_temp_free(temp);
2291 tcg_temp_free(temp2);
2292 }
2293
2294 static inline void
2295 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2296 void(*op)(TCGv, TCGv, TCGv))
2297 {
2298 TCGv temp = tcg_const_i32(con);
2299 gen_accumulating_cond(cond, ret, r1, temp, op);
2300 tcg_temp_free(temp);
2301 }
2302
2303 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2304 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
2305 {
2306 tcg_gen_setcond_tl(cond, ret, r1, r2);
2307 tcg_gen_neg_tl(ret, ret);
2308 }
2309
2310 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2311 {
2312 TCGv b0 = tcg_temp_new();
2313 TCGv b1 = tcg_temp_new();
2314 TCGv b2 = tcg_temp_new();
2315 TCGv b3 = tcg_temp_new();
2316
2317 /* byte 0 */
2318 tcg_gen_andi_tl(b0, r1, 0xff);
2319 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2320
2321 /* byte 1 */
2322 tcg_gen_andi_tl(b1, r1, 0xff00);
2323 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2324
2325 /* byte 2 */
2326 tcg_gen_andi_tl(b2, r1, 0xff0000);
2327 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2328
2329 /* byte 3 */
2330 tcg_gen_andi_tl(b3, r1, 0xff000000);
2331 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2332
2333 /* combine them */
2334 tcg_gen_or_tl(ret, b0, b1);
2335 tcg_gen_or_tl(ret, ret, b2);
2336 tcg_gen_or_tl(ret, ret, b3);
2337
2338 tcg_temp_free(b0);
2339 tcg_temp_free(b1);
2340 tcg_temp_free(b2);
2341 tcg_temp_free(b3);
2342 }
2343
2344 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2345 {
2346 TCGv h0 = tcg_temp_new();
2347 TCGv h1 = tcg_temp_new();
2348
2349 /* halfword 0 */
2350 tcg_gen_andi_tl(h0, r1, 0xffff);
2351 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2352
2353 /* halfword 1 */
2354 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2355 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2356
2357 /* combine them */
2358 tcg_gen_or_tl(ret, h0, h1);
2359
2360 tcg_temp_free(h0);
2361 tcg_temp_free(h1);
2362 }
2363 /* mask = ((1 << width) -1) << pos;
2364 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2365 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2366 {
2367 TCGv mask = tcg_temp_new();
2368 TCGv temp = tcg_temp_new();
2369 TCGv temp2 = tcg_temp_new();
2370
2371 tcg_gen_movi_tl(mask, 1);
2372 tcg_gen_shl_tl(mask, mask, width);
2373 tcg_gen_subi_tl(mask, mask, 1);
2374 tcg_gen_shl_tl(mask, mask, pos);
2375
2376 tcg_gen_shl_tl(temp, r2, pos);
2377 tcg_gen_and_tl(temp, temp, mask);
2378 tcg_gen_andc_tl(temp2, r1, mask);
2379 tcg_gen_or_tl(ret, temp, temp2);
2380
2381 tcg_temp_free(mask);
2382 tcg_temp_free(temp);
2383 tcg_temp_free(temp2);
2384 }
2385
2386 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2387 {
2388 TCGv_i64 temp = tcg_temp_new_i64();
2389
2390 gen_helper_bsplit(temp, r1);
2391 tcg_gen_extr_i64_i32(rl, rh, temp);
2392
2393 tcg_temp_free_i64(temp);
2394 }
2395
2396 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2397 {
2398 TCGv_i64 temp = tcg_temp_new_i64();
2399
2400 gen_helper_unpack(temp, r1);
2401 tcg_gen_extr_i64_i32(rl, rh, temp);
2402
2403 tcg_temp_free_i64(temp);
2404 }
2405
2406 static inline void
2407 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2408 {
2409 TCGv_i64 ret = tcg_temp_new_i64();
2410
2411 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
2412 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2413 } else {
2414 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2415 }
2416 tcg_gen_extr_i64_i32(rl, rh, ret);
2417
2418 tcg_temp_free_i64(ret);
2419 }
2420
2421 static inline void
2422 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2423 {
2424 TCGv_i64 ret = tcg_temp_new_i64();
2425
2426 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
2427 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2428 } else {
2429 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2430 }
2431 tcg_gen_extr_i64_i32(rl, rh, ret);
2432
2433 tcg_temp_free_i64(ret);
2434 }
2435
2436 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2437 {
2438 TCGv temp = tcg_temp_new();
2439 /* calc AV bit */
2440 tcg_gen_add_tl(temp, arg_low, arg_low);
2441 tcg_gen_xor_tl(temp, temp, arg_low);
2442 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2443 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2444 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2445 /* calc SAV bit */
2446 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2447 tcg_gen_movi_tl(cpu_PSW_V, 0);
2448 tcg_temp_free(temp);
2449 }
2450
2451 static void gen_calc_usb_mulr_h(TCGv arg)
2452 {
2453 TCGv temp = tcg_temp_new();
2454 /* calc AV bit */
2455 tcg_gen_add_tl(temp, arg, arg);
2456 tcg_gen_xor_tl(temp, temp, arg);
2457 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2458 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2459 /* calc SAV bit */
2460 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2461 /* clear V bit */
2462 tcg_gen_movi_tl(cpu_PSW_V, 0);
2463 tcg_temp_free(temp);
2464 }
2465
2466 /* helpers for generating program flow micro-ops */
2467
2468 static inline void gen_save_pc(target_ulong pc)
2469 {
2470 tcg_gen_movi_tl(cpu_PC, pc);
2471 }
2472
2473 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2474 {
2475 TranslationBlock *tb;
2476 tb = ctx->tb;
2477 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2478 likely(!ctx->singlestep_enabled)) {
2479 tcg_gen_goto_tb(n);
2480 gen_save_pc(dest);
2481 tcg_gen_exit_tb((uintptr_t)tb + n);
2482 } else {
2483 gen_save_pc(dest);
2484 if (ctx->singlestep_enabled) {
2485 /* raise exception debug */
2486 }
2487 tcg_gen_exit_tb(0);
2488 }
2489 }
2490
2491 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2492 TCGv r2, int16_t address)
2493 {
2494 TCGLabel *jumpLabel = gen_new_label();
2495 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2496
2497 gen_goto_tb(ctx, 1, ctx->next_pc);
2498
2499 gen_set_label(jumpLabel);
2500 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
2501 }
2502
2503 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2504 int r2, int16_t address)
2505 {
2506 TCGv temp = tcg_const_i32(r2);
2507 gen_branch_cond(ctx, cond, r1, temp, address);
2508 tcg_temp_free(temp);
2509 }
2510
2511 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2512 {
2513 TCGLabel *l1 = gen_new_label();
2514
2515 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2516 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2517 gen_goto_tb(ctx, 1, ctx->pc + offset);
2518 gen_set_label(l1);
2519 gen_goto_tb(ctx, 0, ctx->next_pc);
2520 }
2521
2522 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2523 int r2 , int32_t constant , int32_t offset)
2524 {
2525 TCGv temp, temp2;
2526 int n;
2527
2528 switch (opc) {
2529 /* SB-format jumps */
2530 case OPC1_16_SB_J:
2531 case OPC1_32_B_J:
2532 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2533 break;
2534 case OPC1_32_B_CALL:
2535 case OPC1_16_SB_CALL:
2536 gen_helper_1arg(call, ctx->next_pc);
2537 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2538 break;
2539 case OPC1_16_SB_JZ:
2540 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2541 break;
2542 case OPC1_16_SB_JNZ:
2543 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2544 break;
2545 /* SBC-format jumps */
2546 case OPC1_16_SBC_JEQ:
2547 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2548 break;
2549 case OPC1_16_SBC_JNE:
2550 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2551 break;
2552 /* SBRN-format jumps */
2553 case OPC1_16_SBRN_JZ_T:
2554 temp = tcg_temp_new();
2555 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2556 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2557 tcg_temp_free(temp);
2558 break;
2559 case OPC1_16_SBRN_JNZ_T:
2560 temp = tcg_temp_new();
2561 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2562 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2563 tcg_temp_free(temp);
2564 break;
2565 /* SBR-format jumps */
2566 case OPC1_16_SBR_JEQ:
2567 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2568 offset);
2569 break;
2570 case OPC1_16_SBR_JNE:
2571 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2572 offset);
2573 break;
2574 case OPC1_16_SBR_JNZ:
2575 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2576 break;
2577 case OPC1_16_SBR_JNZ_A:
2578 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2579 break;
2580 case OPC1_16_SBR_JGEZ:
2581 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2582 break;
2583 case OPC1_16_SBR_JGTZ:
2584 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2585 break;
2586 case OPC1_16_SBR_JLEZ:
2587 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2588 break;
2589 case OPC1_16_SBR_JLTZ:
2590 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2591 break;
2592 case OPC1_16_SBR_JZ:
2593 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2594 break;
2595 case OPC1_16_SBR_JZ_A:
2596 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2597 break;
2598 case OPC1_16_SBR_LOOP:
2599 gen_loop(ctx, r1, offset * 2 - 32);
2600 break;
2601 /* SR-format jumps */
2602 case OPC1_16_SR_JI:
2603 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
2604 tcg_gen_exit_tb(0);
2605 break;
2606 case OPC2_16_SR_RET:
2607 gen_helper_ret(cpu_env);
2608 tcg_gen_exit_tb(0);
2609 break;
2610 /* B-format */
2611 case OPC1_32_B_CALLA:
2612 gen_helper_1arg(call, ctx->next_pc);
2613 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
2614 break;
2615 case OPC1_32_B_JLA:
2616 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
2617 /* fall through */
2618 case OPC1_32_B_JA:
2619 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
2620 break;
2621 case OPC1_32_B_JL:
2622 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
2623 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2624 break;
2625 /* BOL format */
2626 case OPCM_32_BRC_EQ_NEQ:
2627 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
2628 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
2629 } else {
2630 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
2631 }
2632 break;
2633 case OPCM_32_BRC_GE:
2634 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
2635 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
2636 } else {
2637 constant = MASK_OP_BRC_CONST4(ctx->opcode);
2638 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
2639 offset);
2640 }
2641 break;
2642 case OPCM_32_BRC_JLT:
2643 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
2644 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
2645 } else {
2646 constant = MASK_OP_BRC_CONST4(ctx->opcode);
2647 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
2648 offset);
2649 }
2650 break;
2651 case OPCM_32_BRC_JNE:
2652 temp = tcg_temp_new();
2653 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
2654 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2655 /* subi is unconditional */
2656 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2657 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
2658 } else {
2659 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2660 /* addi is unconditional */
2661 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2662 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
2663 }
2664 tcg_temp_free(temp);
2665 break;
2666 /* BRN format */
2667 case OPCM_32_BRN_JTT:
2668 n = MASK_OP_BRN_N(ctx->opcode);
2669
2670 temp = tcg_temp_new();
2671 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
2672
2673 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
2674 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2675 } else {
2676 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2677 }
2678 tcg_temp_free(temp);
2679 break;
2680 /* BRR Format */
2681 case OPCM_32_BRR_EQ_NEQ:
2682 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
2683 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
2684 offset);
2685 } else {
2686 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
2687 offset);
2688 }
2689 break;
2690 case OPCM_32_BRR_ADDR_EQ_NEQ:
2691 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
2692 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
2693 offset);
2694 } else {
2695 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
2696 offset);
2697 }
2698 break;
2699 case OPCM_32_BRR_GE:
2700 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
2701 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
2702 offset);
2703 } else {
2704 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
2705 offset);
2706 }
2707 break;
2708 case OPCM_32_BRR_JLT:
2709 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
2710 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
2711 offset);
2712 } else {
2713 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
2714 offset);
2715 }
2716 break;
2717 case OPCM_32_BRR_LOOP:
2718 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
2719 gen_loop(ctx, r1, offset * 2);
2720 } else {
2721 /* OPC2_32_BRR_LOOPU */
2722 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2723 }
2724 break;
2725 case OPCM_32_BRR_JNE:
2726 temp = tcg_temp_new();
2727 temp2 = tcg_temp_new();
2728 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
2729 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2730 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2731 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
2732 /* subi is unconditional */
2733 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2734 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
2735 } else {
2736 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2737 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2738 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
2739 /* addi is unconditional */
2740 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2741 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
2742 }
2743 tcg_temp_free(temp);
2744 tcg_temp_free(temp2);
2745 break;
2746 case OPCM_32_BRR_JNZ:
2747 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
2748 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2749 } else {
2750 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2751 }
2752 break;
2753 default:
2754 printf("Branch Error at %x\n", ctx->pc);
2755 }
2756 ctx->bstate = BS_BRANCH;
2757 }
2758
2759
2760 /*
2761 * Functions for decoding instructions
2762 */
2763
2764 static void decode_src_opc(DisasContext *ctx, int op1)
2765 {
2766 int r1;
2767 int32_t const4;
2768 TCGv temp, temp2;
2769
2770 r1 = MASK_OP_SRC_S1D(ctx->opcode);
2771 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
2772
2773 switch (op1) {
2774 case OPC1_16_SRC_ADD:
2775 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2776 break;
2777 case OPC1_16_SRC_ADD_A15:
2778 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
2779 break;
2780 case OPC1_16_SRC_ADD_15A:
2781 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
2782 break;
2783 case OPC1_16_SRC_ADD_A:
2784 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
2785 break;
2786 case OPC1_16_SRC_CADD:
2787 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
2788 cpu_gpr_d[15]);
2789 break;
2790 case OPC1_16_SRC_CADDN:
2791 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
2792 cpu_gpr_d[15]);
2793 break;
2794 case OPC1_16_SRC_CMOV:
2795 temp = tcg_const_tl(0);
2796 temp2 = tcg_const_tl(const4);
2797 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2798 temp2, cpu_gpr_d[r1]);
2799 tcg_temp_free(temp);
2800 tcg_temp_free(temp2);
2801 break;
2802 case OPC1_16_SRC_CMOVN:
2803 temp = tcg_const_tl(0);
2804 temp2 = tcg_const_tl(const4);
2805 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2806 temp2, cpu_gpr_d[r1]);
2807 tcg_temp_free(temp);
2808 tcg_temp_free(temp2);
2809 break;
2810 case OPC1_16_SRC_EQ:
2811 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
2812 const4);
2813 break;
2814 case OPC1_16_SRC_LT:
2815 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
2816 const4);
2817 break;
2818 case OPC1_16_SRC_MOV:
2819 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
2820 break;
2821 case OPC1_16_SRC_MOV_A:
2822 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
2823 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
2824 break;
2825 case OPC1_16_SRC_SH:
2826 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2827 break;
2828 case OPC1_16_SRC_SHA:
2829 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2830 break;
2831 }
2832 }
2833
2834 static void decode_srr_opc(DisasContext *ctx, int op1)
2835 {
2836 int r1, r2;
2837 TCGv temp;
2838
2839 r1 = MASK_OP_SRR_S1D(ctx->opcode);
2840 r2 = MASK_OP_SRR_S2(ctx->opcode);
2841
2842 switch (op1) {
2843 case OPC1_16_SRR_ADD:
2844 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2845 break;
2846 case OPC1_16_SRR_ADD_A15:
2847 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
2848 break;
2849 case OPC1_16_SRR_ADD_15A:
2850 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2851 break;
2852 case OPC1_16_SRR_ADD_A:
2853 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
2854 break;
2855 case OPC1_16_SRR_ADDS:
2856 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2857 break;
2858 case OPC1_16_SRR_AND:
2859 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2860 break;
2861 case OPC1_16_SRR_CMOV:
2862 temp = tcg_const_tl(0);
2863 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2864 cpu_gpr_d[r2], cpu_gpr_d[r1]);
2865 tcg_temp_free(temp);
2866 break;
2867 case OPC1_16_SRR_CMOVN:
2868 temp = tcg_const_tl(0);
2869 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2870 cpu_gpr_d[r2], cpu_gpr_d[r1]);
2871 tcg_temp_free(temp);
2872 break;
2873 case OPC1_16_SRR_EQ:
2874 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
2875 cpu_gpr_d[r2]);
2876 break;
2877 case OPC1_16_SRR_LT:
2878 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
2879 cpu_gpr_d[r2]);
2880 break;
2881 case OPC1_16_SRR_MOV:
2882 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
2883 break;
2884 case OPC1_16_SRR_MOV_A:
2885 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
2886 break;
2887 case OPC1_16_SRR_MOV_AA:
2888 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
2889 break;
2890 case OPC1_16_SRR_MOV_D:
2891 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
2892 break;
2893 case OPC1_16_SRR_MUL:
2894 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2895 break;
2896 case OPC1_16_SRR_OR:
2897 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2898 break;
2899 case OPC1_16_SRR_SUB:
2900 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2901 break;
2902 case OPC1_16_SRR_SUB_A15B:
2903 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
2904 break;
2905 case OPC1_16_SRR_SUB_15AB:
2906 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2907 break;
2908 case OPC1_16_SRR_SUBS:
2909 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2910 break;
2911 case OPC1_16_SRR_XOR:
2912 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2913 break;
2914 }
2915 }
2916
2917 static void decode_ssr_opc(DisasContext *ctx, int op1)
2918 {
2919 int r1, r2;
2920
2921 r1 = MASK_OP_SSR_S1(ctx->opcode);
2922 r2 = MASK_OP_SSR_S2(ctx->opcode);
2923
2924 switch (op1) {
2925 case OPC1_16_SSR_ST_A:
2926 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2927 break;
2928 case OPC1_16_SSR_ST_A_POSTINC:
2929 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2930 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2931 break;
2932 case OPC1_16_SSR_ST_B:
2933 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2934 break;
2935 case OPC1_16_SSR_ST_B_POSTINC:
2936 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2937 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
2938 break;
2939 case OPC1_16_SSR_ST_H:
2940 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
2941 break;
2942 case OPC1_16_SSR_ST_H_POSTINC:
2943 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
2944 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
2945 break;
2946 case OPC1_16_SSR_ST_W:
2947 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2948 break;
2949 case OPC1_16_SSR_ST_W_POSTINC:
2950 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2951 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2952 break;
2953 }
2954 }
2955
2956 static void decode_sc_opc(DisasContext *ctx, int op1)
2957 {
2958 int32_t const16;
2959
2960 const16 = MASK_OP_SC_CONST8(ctx->opcode);
2961
2962 switch (op1) {
2963 case OPC1_16_SC_AND:
2964 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
2965 break;
2966 case OPC1_16_SC_BISR:
2967 gen_helper_1arg(bisr, const16 & 0xff);
2968 break;
2969 case OPC1_16_SC_LD_A:
2970 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2971 break;
2972 case OPC1_16_SC_LD_W:
2973 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2974 break;
2975 case OPC1_16_SC_MOV:
2976 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
2977 break;
2978 case OPC1_16_SC_OR:
2979 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
2980 break;
2981 case OPC1_16_SC_ST_A:
2982 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2983 break;
2984 case OPC1_16_SC_ST_W:
2985 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2986 break;
2987 case OPC1_16_SC_SUB_A:
2988 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
2989 break;
2990 }
2991 }
2992
2993 static void decode_slr_opc(DisasContext *ctx, int op1)
2994 {
2995 int r1, r2;
2996
2997 r1 = MASK_OP_SLR_D(ctx->opcode);
2998 r2 = MASK_OP_SLR_S2(ctx->opcode);
2999
3000 switch (op1) {
3001 /* SLR-format */
3002 case OPC1_16_SLR_LD_A:
3003 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3004 break;
3005 case OPC1_16_SLR_LD_A_POSTINC:
3006 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3007 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3008 break;
3009 case OPC1_16_SLR_LD_BU:
3010 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3011 break;
3012 case OPC1_16_SLR_LD_BU_POSTINC:
3013 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3014 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3015 break;
3016 case OPC1_16_SLR_LD_H:
3017 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3018 break;
3019 case OPC1_16_SLR_LD_H_POSTINC:
3020 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3021 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3022 break;
3023 case OPC1_16_SLR_LD_W:
3024 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3025 break;
3026 case OPC1_16_SLR_LD_W_POSTINC:
3027 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3028 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3029 break;
3030 }
3031 }
3032
3033 static void decode_sro_opc(DisasContext *ctx, int op1)
3034 {
3035 int r2;
3036 int32_t address;
3037
3038 r2 = MASK_OP_SRO_S2(ctx->opcode);
3039 address = MASK_OP_SRO_OFF4(ctx->opcode);
3040
3041 /* SRO-format */
3042 switch (op1) {
3043 case OPC1_16_SRO_LD_A:
3044 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3045 break;
3046 case OPC1_16_SRO_LD_BU:
3047 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3048 break;
3049 case OPC1_16_SRO_LD_H:
3050 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3051 break;
3052 case OPC1_16_SRO_LD_W:
3053 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3054 break;
3055 case OPC1_16_SRO_ST_A:
3056 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3057 break;
3058 case OPC1_16_SRO_ST_B:
3059 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3060 break;
3061 case OPC1_16_SRO_ST_H:
3062 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3063 break;
3064 case OPC1_16_SRO_ST_W:
3065 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3066 break;
3067 }
3068 }
3069
3070 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3071 {
3072 uint32_t op2;
3073 op2 = MASK_OP_SR_OP2(ctx->opcode);
3074
3075 switch (op2) {
3076 case OPC2_16_SR_NOP:
3077 break;
3078 case OPC2_16_SR_RET:
3079 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3080 break;
3081 case OPC2_16_SR_RFE:
3082 gen_helper_rfe(cpu_env);
3083 tcg_gen_exit_tb(0);
3084 ctx->bstate = BS_BRANCH;
3085 break;
3086 case OPC2_16_SR_DEBUG:
3087 /* raise EXCP_DEBUG */
3088 break;
3089 }
3090 }
3091
3092 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3093 {
3094 uint32_t op2;
3095 uint32_t r1;
3096 TCGv temp;
3097
3098 r1 = MASK_OP_SR_S1D(ctx->opcode);
3099 op2 = MASK_OP_SR_OP2(ctx->opcode);
3100
3101 switch (op2) {
3102 case OPC2_16_SR_RSUB:
3103 /* overflow only if r1 = -0x80000000 */
3104 temp = tcg_const_i32(-0x80000000);
3105 /* calc V bit */
3106 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3107 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3108 /* calc SV bit */
3109 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3110 /* sub */
3111 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3112 /* calc av */
3113 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3114 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3115 /* calc sav */
3116 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3117 tcg_temp_free(temp);
3118 break;
3119 case OPC2_16_SR_SAT_B:
3120 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3121 break;
3122 case OPC2_16_SR_SAT_BU:
3123 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3124 break;
3125 case OPC2_16_SR_SAT_H:
3126 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3127 break;
3128 case OPC2_16_SR_SAT_HU:
3129 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3130 break;
3131 }
3132 }
3133
3134 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3135 {
3136 int op1;
3137 int r1, r2;
3138 int32_t const16;
3139 int32_t address;
3140 TCGv temp;
3141
3142 op1 = MASK_OP_MAJOR(ctx->opcode);
3143
3144 /* handle ADDSC.A opcode only being 6 bit long */
3145 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3146 op1 = OPC1_16_SRRS_ADDSC_A;
3147 }
3148
3149 switch (op1) {
3150 case OPC1_16_SRC_ADD:
3151 case OPC1_16_SRC_ADD_A15:
3152 case OPC1_16_SRC_ADD_15A:
3153 case OPC1_16_SRC_ADD_A:
3154 case OPC1_16_SRC_CADD:
3155 case OPC1_16_SRC_CADDN:
3156 case OPC1_16_SRC_CMOV:
3157 case OPC1_16_SRC_CMOVN:
3158 case OPC1_16_SRC_EQ:
3159 case OPC1_16_SRC_LT:
3160 case OPC1_16_SRC_MOV:
3161 case OPC1_16_SRC_MOV_A:
3162 case OPC1_16_SRC_SH:
3163 case OPC1_16_SRC_SHA:
3164 decode_src_opc(ctx, op1);
3165 break;
3166 /* SRR-format */
3167 case OPC1_16_SRR_ADD:
3168 case OPC1_16_SRR_ADD_A15:
3169 case OPC1_16_SRR_ADD_15A:
3170 case OPC1_16_SRR_ADD_A:
3171 case OPC1_16_SRR_ADDS:
3172 case OPC1_16_SRR_AND:
3173 case OPC1_16_SRR_CMOV:
3174 case OPC1_16_SRR_CMOVN:
3175 case OPC1_16_SRR_EQ:
3176 case OPC1_16_SRR_LT:
3177 case OPC1_16_SRR_MOV:
3178 case OPC1_16_SRR_MOV_A:
3179 case OPC1_16_SRR_MOV_AA:
3180 case OPC1_16_SRR_MOV_D:
3181 case OPC1_16_SRR_MUL:
3182 case OPC1_16_SRR_OR:
3183 case OPC1_16_SRR_SUB:
3184 case OPC1_16_SRR_SUB_A15B:
3185 case OPC1_16_SRR_SUB_15AB:
3186 case OPC1_16_SRR_SUBS:
3187 case OPC1_16_SRR_XOR:
3188 decode_srr_opc(ctx, op1);
3189 break;
3190 /* SSR-format */
3191 case OPC1_16_SSR_ST_A:
3192 case OPC1_16_SSR_ST_A_POSTINC:
3193 case OPC1_16_SSR_ST_B:
3194 case OPC1_16_SSR_ST_B_POSTINC:
3195 case OPC1_16_SSR_ST_H:
3196 case OPC1_16_SSR_ST_H_POSTINC:
3197 case OPC1_16_SSR_ST_W:
3198 case OPC1_16_SSR_ST_W_POSTINC:
3199 decode_ssr_opc(ctx, op1);
3200 break;
3201 /* SRRS-format */
3202 case OPC1_16_SRRS_ADDSC_A:
3203 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3204 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3205 const16 = MASK_OP_SRRS_N(ctx->opcode);
3206 temp = tcg_temp_new();
3207 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3208 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3209 tcg_temp_free(temp);
3210 break;
3211 /* SLRO-format */
3212 case OPC1_16_SLRO_LD_A:
3213 r1 = MASK_OP_SLRO_D(ctx->opcode);
3214 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3215 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3216 break;
3217 case OPC1_16_SLRO_LD_BU:
3218 r1 = MASK_OP_SLRO_D(ctx->opcode);
3219 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3220 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3221 break;
3222 case OPC1_16_SLRO_LD_H:
3223 r1 = MASK_OP_SLRO_D(ctx->opcode);
3224 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3225 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3226 break;
3227 case OPC1_16_SLRO_LD_W:
3228 r1 = MASK_OP_SLRO_D(ctx->opcode);
3229 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3230 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3231 break;
3232 /* SB-format */
3233 case OPC1_16_SB_CALL:
3234 case OPC1_16_SB_J:
3235 case OPC1_16_SB_JNZ:
3236 case OPC1_16_SB_JZ:
3237 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3238 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3239 break;
3240 /* SBC-format */
3241 case OPC1_16_SBC_JEQ:
3242 case OPC1_16_SBC_JNE:
3243 address = MASK_OP_SBC_DISP4(ctx->opcode);
3244 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3245 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3246 break;
3247 /* SBRN-format */
3248 case OPC1_16_SBRN_JNZ_T:
3249 case OPC1_16_SBRN_JZ_T:
3250 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3251 const16 = MASK_OP_SBRN_N(ctx->opcode);
3252 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3253 break;
3254 /* SBR-format */
3255 case OPC1_16_SBR_JEQ:
3256 case OPC1_16_SBR_JGEZ:
3257 case OPC1_16_SBR_JGTZ:
3258 case OPC1_16_SBR_JLEZ:
3259 case OPC1_16_SBR_JLTZ:
3260 case OPC1_16_SBR_JNE:
3261 case OPC1_16_SBR_JNZ:
3262 case OPC1_16_SBR_JNZ_A:
3263 case OPC1_16_SBR_JZ:
3264 case OPC1_16_SBR_JZ_A:
3265 case OPC1_16_SBR_LOOP:
3266 r1 = MASK_OP_SBR_S2(ctx->opcode);
3267 address = MASK_OP_SBR_DISP4(ctx->opcode);
3268 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3269 break;
3270 /* SC-format */
3271 case OPC1_16_SC_AND:
3272 case OPC1_16_SC_BISR:
3273 case OPC1_16_SC_LD_A:
3274 case OPC1_16_SC_LD_W:
3275 case OPC1_16_SC_MOV:
3276 case OPC1_16_SC_OR:
3277 case OPC1_16_SC_ST_A:
3278 case OPC1_16_SC_ST_W:
3279 case OPC1_16_SC_SUB_A:
3280 decode_sc_opc(ctx, op1);
3281 break;
3282 /* SLR-format */
3283 case OPC1_16_SLR_LD_A:
3284 case OPC1_16_SLR_LD_A_POSTINC:
3285 case OPC1_16_SLR_LD_BU:
3286 case OPC1_16_SLR_LD_BU_POSTINC:
3287 case OPC1_16_SLR_LD_H:
3288 case OPC1_16_SLR_LD_H_POSTINC:
3289 case OPC1_16_SLR_LD_W:
3290 case OPC1_16_SLR_LD_W_POSTINC:
3291 decode_slr_opc(ctx, op1);
3292 break;
3293 /* SRO-format */
3294 case OPC1_16_SRO_LD_A:
3295 case OPC1_16_SRO_LD_BU:
3296 case OPC1_16_SRO_LD_H:
3297 case OPC1_16_SRO_LD_W:
3298 case OPC1_16_SRO_ST_A:
3299 case OPC1_16_SRO_ST_B:
3300 case OPC1_16_SRO_ST_H:
3301 case OPC1_16_SRO_ST_W:
3302 decode_sro_opc(ctx, op1);
3303 break;
3304 /* SSRO-format */
3305 case OPC1_16_SSRO_ST_A:
3306 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3307 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3308 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3309 break;
3310 case OPC1_16_SSRO_ST_B:
3311 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3312 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3313 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3314 break;
3315 case OPC1_16_SSRO_ST_H:
3316 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3317 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3318 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3319 break;
3320 case OPC1_16_SSRO_ST_W:
3321 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3322 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3323 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3324 break;
3325 /* SR-format */
3326 case OPCM_16_SR_SYSTEM:
3327 decode_sr_system(env, ctx);
3328 break;
3329 case OPCM_16_SR_ACCU:
3330 decode_sr_accu(env, ctx);
3331 break;
3332 case OPC1_16_SR_JI:
3333 r1 = MASK_OP_SR_S1D(ctx->opcode);
3334 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3335 break;
3336 case OPC1_16_SR_NOT:
3337 r1 = MASK_OP_SR_S1D(ctx->opcode);
3338 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3339 break;
3340 }
3341 }
3342
3343 /*
3344 * 32 bit instructions
3345 */
3346
3347 /* ABS-format */
3348 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
3349 {
3350 int32_t op2;
3351 int32_t r1;
3352 uint32_t address;
3353 TCGv temp;
3354
3355 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3356 address = MASK_OP_ABS_OFF18(ctx->opcode);
3357 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3358
3359 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3360
3361 switch (op2) {
3362 case OPC2_32_ABS_LD_A:
3363 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3364 break;
3365 case OPC2_32_ABS_LD_D:
3366 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3367 break;
3368 case OPC2_32_ABS_LD_DA:
3369 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3370 break;
3371 case OPC2_32_ABS_LD_W:
3372 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3373 break;
3374 }
3375
3376 tcg_temp_free(temp);
3377 }
3378
3379 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
3380 {
3381 int32_t op2;
3382 int32_t r1;
3383 uint32_t address;
3384 TCGv temp;
3385
3386 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3387 address = MASK_OP_ABS_OFF18(ctx->opcode);
3388 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3389
3390 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3391
3392 switch (op2) {
3393 case OPC2_32_ABS_LD_B:
3394 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3395 break;
3396 case OPC2_32_ABS_LD_BU:
3397 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3398 break;
3399 case OPC2_32_ABS_LD_H:
3400 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3401 break;
3402 case OPC2_32_ABS_LD_HU:
3403 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3404 break;
3405 }
3406
3407 tcg_temp_free(temp);
3408 }
3409
3410 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
3411 {
3412 int32_t op2;
3413 int32_t r1;
3414 uint32_t address;
3415 TCGv temp;
3416
3417 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3418 address = MASK_OP_ABS_OFF18(ctx->opcode);
3419 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3420
3421 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3422
3423 switch (op2) {
3424 case OPC2_32_ABS_LDMST:
3425 gen_ldmst(ctx, r1, temp);
3426 break;
3427 case OPC2_32_ABS_SWAP_W:
3428 gen_swap(ctx, r1, temp);
3429 break;
3430 }
3431
3432 tcg_temp_free(temp);
3433 }
3434
3435 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
3436 {
3437 uint32_t op2;
3438 int32_t off18;
3439
3440 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3441 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3442
3443 switch (op2) {
3444 case OPC2_32_ABS_LDLCX:
3445 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3446 break;
3447 case OPC2_32_ABS_LDUCX:
3448 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3449 break;
3450 case OPC2_32_ABS_STLCX:
3451 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3452 break;
3453 case OPC2_32_ABS_STUCX:
3454 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3455 break;
3456 }
3457 }
3458
3459 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
3460 {
3461 int32_t op2;
3462 int32_t r1;
3463 uint32_t address;
3464 TCGv temp;
3465
3466 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3467 address = MASK_OP_ABS_OFF18(ctx->opcode);
3468 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3469
3470 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3471
3472 switch (op2) {
3473 case OPC2_32_ABS_ST_A:
3474 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3475 break;
3476 case OPC2_32_ABS_ST_D:
3477 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3478 break;
3479 case OPC2_32_ABS_ST_DA:
3480 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3481 break;
3482 case OPC2_32_ABS_ST_W:
3483 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3484 break;
3485
3486 }
3487 tcg_temp_free(temp);
3488 }
3489
3490 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
3491 {
3492 int32_t op2;
3493 int32_t r1;
3494 uint32_t address;
3495 TCGv temp;
3496
3497 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3498 address = MASK_OP_ABS_OFF18(ctx->opcode);
3499 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3500
3501 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3502
3503 switch (op2) {
3504 case OPC2_32_ABS_ST_B:
3505 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3506 break;
3507 case OPC2_32_ABS_ST_H:
3508 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3509 break;
3510 }
3511 tcg_temp_free(temp);
3512 }
3513
3514 /* Bit-format */
3515
3516 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
3517 {
3518 uint32_t op2;
3519 int r1, r2, r3;
3520 int pos1, pos2;
3521
3522 r1 = MASK_OP_BIT_S1(ctx->opcode);
3523 r2 = MASK_OP_BIT_S2(ctx->opcode);
3524 r3 = MASK_OP_BIT_D(ctx->opcode);
3525 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3526 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3527 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3528
3529
3530 switch (op2) {
3531 case OPC2_32_BIT_AND_AND_T:
3532 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3533 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3534 break;
3535 case OPC2_32_BIT_AND_ANDN_T:
3536 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3537 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3538 break;
3539 case OPC2_32_BIT_AND_NOR_T:
3540 if (TCG_TARGET_HAS_andc_i32) {
3541 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3542 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3543 } else {
3544 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3545 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3546 }
3547 break;
3548 case OPC2_32_BIT_AND_OR_T:
3549 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3550 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
3551 break;
3552 }
3553 }
3554
3555 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
3556 {
3557 uint32_t op2;
3558 int r1, r2, r3;
3559 int pos1, pos2;
3560 r1 = MASK_OP_BIT_S1(ctx->opcode);
3561 r2 = MASK_OP_BIT_S2(ctx->opcode);
3562 r3 = MASK_OP_BIT_D(ctx->opcode);
3563 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3564 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3565 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3566
3567 switch (op2) {
3568 case OPC2_32_BIT_AND_T:
3569 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3570 pos1, pos2, &tcg_gen_and_tl);
3571 break;
3572 case OPC2_32_BIT_ANDN_T:
3573 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3574 pos1, pos2, &tcg_gen_andc_tl);
3575 break;
3576 case OPC2_32_BIT_NOR_T:
3577 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3578 pos1, pos2, &tcg_gen_nor_tl);
3579 break;
3580 case OPC2_32_BIT_OR_T:
3581 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3582 pos1, pos2, &tcg_gen_or_tl);
3583 break;
3584 }
3585 }
3586
3587 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
3588 {
3589 uint32_t op2;
3590 int r1, r2, r3;
3591 int pos1, pos2;
3592 TCGv temp;
3593 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3594 r1 = MASK_OP_BIT_S1(ctx->opcode);
3595 r2 = MASK_OP_BIT_S2(ctx->opcode);
3596 r3 = MASK_OP_BIT_D(ctx->opcode);
3597 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3598 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3599
3600 temp = tcg_temp_new();
3601
3602 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
3603 if (op2 == OPC2_32_BIT_INSN_T) {
3604 tcg_gen_not_tl(temp, temp);
3605 }
3606 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
3607 tcg_temp_free(temp);
3608 }
3609
3610 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
3611 {
3612 uint32_t op2;
3613
3614 int r1, r2, r3;
3615 int pos1, pos2;
3616
3617 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3618 r1 = MASK_OP_BIT_S1(ctx->opcode);
3619 r2 = MASK_OP_BIT_S2(ctx->opcode);
3620 r3 = MASK_OP_BIT_D(ctx->opcode);
3621 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3622 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3623
3624 switch (op2) {
3625 case OPC2_32_BIT_NAND_T:
3626 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3627 pos1, pos2, &tcg_gen_nand_tl);
3628 break;
3629 case OPC2_32_BIT_ORN_T:
3630 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3631 pos1, pos2, &tcg_gen_orc_tl);
3632 break;
3633 case OPC2_32_BIT_XNOR_T:
3634 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3635 pos1, pos2, &tcg_gen_eqv_tl);
3636 break;
3637 case OPC2_32_BIT_XOR_T:
3638 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3639 pos1, pos2, &tcg_gen_xor_tl);
3640 break;
3641 }
3642 }
3643
3644 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
3645 {
3646 uint32_t op2;
3647
3648 int r1, r2, r3;
3649 int pos1, pos2;
3650
3651 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3652 r1 = MASK_OP_BIT_S1(ctx->opcode);
3653 r2 = MASK_OP_BIT_S2(ctx->opcode);
3654 r3 = MASK_OP_BIT_D(ctx->opcode);
3655 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3656 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3657
3658 switch (op2) {
3659 case OPC2_32_BIT_OR_AND_T:
3660 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3661 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
3662 break;
3663 case OPC2_32_BIT_OR_ANDN_T:
3664 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3665 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
3666 break;
3667 case OPC2_32_BIT_OR_NOR_T:
3668 if (TCG_TARGET_HAS_orc_i32) {
3669 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3670 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
3671 } else {
3672 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3673 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
3674 }
3675 break;
3676 case OPC2_32_BIT_OR_OR_T:
3677 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3678 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
3679 break;
3680 }
3681 }
3682
3683 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
3684 {
3685 uint32_t op2;
3686 int r1, r2, r3;
3687 int pos1, pos2;
3688 TCGv temp;
3689
3690 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3691 r1 = MASK_OP_BIT_S1(ctx->opcode);
3692 r2 = MASK_OP_BIT_S2(ctx->opcode);
3693 r3 = MASK_OP_BIT_D(ctx->opcode);
3694 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3695 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3696
3697 temp = tcg_temp_new();
3698
3699 switch (op2) {
3700 case OPC2_32_BIT_SH_AND_T:
3701 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3702 pos1, pos2, &tcg_gen_and_tl);
3703 break;
3704 case OPC2_32_BIT_SH_ANDN_T:
3705 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3706 pos1, pos2, &tcg_gen_andc_tl);
3707 break;
3708 case OPC2_32_BIT_SH_NOR_T:
3709 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3710 pos1, pos2, &tcg_gen_nor_tl);
3711 break;
3712 case OPC2_32_BIT_SH_OR_T:
3713 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3714 pos1, pos2, &tcg_gen_or_tl);
3715 break;
3716 }
3717 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
3718 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
3719 tcg_temp_free(temp);
3720 }
3721
3722 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
3723 {
3724 uint32_t op2;
3725 int r1, r2, r3;
3726 int pos1, pos2;
3727 TCGv temp;
3728
3729 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3730 r1 = MASK_OP_BIT_S1(ctx->opcode);
3731 r2 = MASK_OP_BIT_S2(ctx->opcode);
3732 r3 = MASK_OP_BIT_D(ctx->opcode);
3733 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3734 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3735
3736 temp = tcg_temp_new();
3737
3738 switch (op2) {
3739 case OPC2_32_BIT_SH_NAND_T:
3740 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
3741 pos1, pos2, &tcg_gen_nand_tl);
3742 break;
3743 case OPC2_32_BIT_SH_ORN_T:
3744 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3745 pos1, pos2, &tcg_gen_orc_tl);
3746 break;
3747 case OPC2_32_BIT_SH_XNOR_T:
3748 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3749 pos1, pos2, &tcg_gen_eqv_tl);
3750 break;
3751 case OPC2_32_BIT_SH_XOR_T:
3752 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3753 pos1, pos2, &tcg_gen_xor_tl);
3754 break;
3755 }
3756 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
3757 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
3758 tcg_temp_free(temp);
3759 }
3760
3761 /* BO-format */
3762
3763
3764 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
3765 DisasContext *ctx)
3766 {
3767 uint32_t op2;
3768 uint32_t off10;
3769 int32_t r1, r2;
3770 TCGv temp;
3771
3772 r1 = MASK_OP_BO_S1D(ctx->opcode);
3773 r2 = MASK_OP_BO_S2(ctx->opcode);
3774 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3775 op2 = MASK_OP_BO_OP2(ctx->opcode);
3776
3777 switch (op2) {
3778 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
3779 case OPC2_32_BO_CACHEA_W_SHORTOFF:
3780 case OPC2_32_BO_CACHEA_I_SHORTOFF:
3781 /* instruction to access the cache */
3782 break;
3783 case OPC2_32_BO_CACHEA_WI_POSTINC:
3784 case OPC2_32_BO_CACHEA_W_POSTINC:
3785 case OPC2_32_BO_CACHEA_I_POSTINC:
3786 /* instruction to access the cache, but we still need to handle
3787 the addressing mode */
3788 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3789 break;
3790 case OPC2_32_BO_CACHEA_WI_PREINC:
3791 case OPC2_32_BO_CACHEA_W_PREINC:
3792 case OPC2_32_BO_CACHEA_I_PREINC:
3793 /* instruction to access the cache, but we still need to handle
3794 the addressing mode */
3795 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3796 break;
3797 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
3798 case OPC2_32_BO_CACHEI_W_SHORTOFF:
3799 /* TODO: Raise illegal opcode trap,
3800 if !tricore_feature(TRICORE_FEATURE_131) */
3801 break;
3802 case OPC2_32_BO_CACHEI_W_POSTINC:
3803 case OPC2_32_BO_CACHEI_WI_POSTINC:
3804 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3805 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3806 } /* TODO: else raise illegal opcode trap */
3807 break;
3808 case OPC2_32_BO_CACHEI_W_PREINC:
3809 case OPC2_32_BO_CACHEI_WI_PREINC:
3810 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3811 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3812 } /* TODO: else raise illegal opcode trap */
3813 break;
3814 case OPC2_32_BO_ST_A_SHORTOFF:
3815 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
3816 break;
3817 case OPC2_32_BO_ST_A_POSTINC:
3818 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
3819 MO_LESL);
3820 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3821 break;
3822 case OPC2_32_BO_ST_A_PREINC:
3823 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
3824 break;
3825 case OPC2_32_BO_ST_B_SHORTOFF:
3826 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
3827 break;
3828 case OPC2_32_BO_ST_B_POSTINC:
3829 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3830 MO_UB);
3831 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3832 break;
3833 case OPC2_32_BO_ST_B_PREINC:
3834 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
3835 break;
3836 case OPC2_32_BO_ST_D_SHORTOFF:
3837 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
3838 off10, ctx);
3839 break;
3840 case OPC2_32_BO_ST_D_POSTINC:
3841 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
3842 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3843 break;
3844 case OPC2_32_BO_ST_D_PREINC:
3845 temp = tcg_temp_new();
3846 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3847 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3848 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3849 tcg_temp_free(temp);
3850 break;
3851 case OPC2_32_BO_ST_DA_SHORTOFF:
3852 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
3853 off10, ctx);
3854 break;
3855 case OPC2_32_BO_ST_DA_POSTINC:
3856 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
3857 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3858 break;
3859 case OPC2_32_BO_ST_DA_PREINC:
3860 temp = tcg_temp_new();
3861 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3862 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3863 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3864 tcg_temp_free(temp);
3865 break;
3866 case OPC2_32_BO_ST_H_SHORTOFF:
3867 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3868 break;
3869 case OPC2_32_BO_ST_H_POSTINC:
3870 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3871 MO_LEUW);
3872 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3873 break;
3874 case OPC2_32_BO_ST_H_PREINC:
3875 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3876 break;
3877 case OPC2_32_BO_ST_Q_SHORTOFF:
3878 temp = tcg_temp_new();
3879 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3880 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
3881 tcg_temp_free(temp);
3882 break;
3883 case OPC2_32_BO_ST_Q_POSTINC:
3884 temp = tcg_temp_new();
3885 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3886 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
3887 MO_LEUW);
3888 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3889 tcg_temp_free(temp);
3890 break;
3891 case OPC2_32_BO_ST_Q_PREINC:
3892 temp = tcg_temp_new();
3893 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3894 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
3895 tcg_temp_free(temp);
3896 break;
3897 case OPC2_32_BO_ST_W_SHORTOFF:
3898 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3899 break;
3900 case OPC2_32_BO_ST_W_POSTINC:
3901 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3902 MO_LEUL);
3903 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3904 break;
3905 case OPC2_32_BO_ST_W_PREINC:
3906 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3907 break;
3908 }
3909 }
3910
3911 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
3912 DisasContext *ctx)
3913 {
3914 uint32_t op2;
3915 uint32_t off10;
3916 int32_t r1, r2;
3917 TCGv temp, temp2, temp3;
3918
3919 r1 = MASK_OP_BO_S1D(ctx->opcode);
3920 r2 = MASK_OP_BO_S2(ctx->opcode);
3921 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3922 op2 = MASK_OP_BO_OP2(ctx->opcode);
3923
3924 temp = tcg_temp_new();
3925 temp2 = tcg_temp_new();
3926 temp3 = tcg_const_i32(off10);
3927
3928 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
3929 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3930
3931 switch (op2) {
3932 case OPC2_32_BO_CACHEA_WI_BR:
3933 case OPC2_32_BO_CACHEA_W_BR:
3934 case OPC2_32_BO_CACHEA_I_BR:
3935 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3936 break;
3937 case OPC2_32_BO_CACHEA_WI_CIRC:
3938 case OPC2_32_BO_CACHEA_W_CIRC:
3939 case OPC2_32_BO_CACHEA_I_CIRC:
3940 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3941 break;
3942 case OPC2_32_BO_ST_A_BR:
3943 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3944 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3945 break;
3946 case OPC2_32_BO_ST_A_CIRC:
3947 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3948 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3949 break;
3950 case OPC2_32_BO_ST_B_BR:
3951 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3952 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3953 break;
3954 case OPC2_32_BO_ST_B_CIRC:
3955 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3956 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3957 break;
3958 case OPC2_32_BO_ST_D_BR:
3959 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
3960 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3961 break;
3962 case OPC2_32_BO_ST_D_CIRC:
3963 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
3964 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
3965 tcg_gen_addi_tl(temp, temp, 4);
3966 tcg_gen_rem_tl(temp, temp, temp2);
3967 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3968 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
3969 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3970 break;
3971 case OPC2_32_BO_ST_DA_BR:
3972 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
3973 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3974 break;
3975 case OPC2_32_BO_ST_DA_CIRC:
3976 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3977 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
3978 tcg_gen_addi_tl(temp, temp, 4);
3979 tcg_gen_rem_tl(temp, temp, temp2);
3980 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3981 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
3982 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3983 break;
3984 case OPC2_32_BO_ST_H_BR:
3985 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
3986 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3987 break;
3988 case OPC2_32_BO_ST_H_CIRC:
3989 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
3990 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3991 break;
3992 case OPC2_32_BO_ST_Q_BR:
3993 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3994 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
3995 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3996 break;
3997 case OPC2_32_BO_ST_Q_CIRC:
3998 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3999 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4000 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4001 break;
4002 case OPC2_32_BO_ST_W_BR:
4003 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4004 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4005 break;
4006 case OPC2_32_BO_ST_W_CIRC:
4007 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4008 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4009 break;
4010 }
4011 tcg_temp_free(temp);
4012 tcg_temp_free(temp2);
4013 tcg_temp_free(temp3);
4014 }
4015
4016 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4017 DisasContext *ctx)
4018 {
4019 uint32_t op2;
4020 uint32_t off10;
4021 int32_t r1, r2;
4022 TCGv temp;
4023
4024 r1 = MASK_OP_BO_S1D(ctx->opcode);
4025 r2 = MASK_OP_BO_S2(ctx->opcode);
4026 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4027 op2 = MASK_OP_BO_OP2(ctx->opcode);
4028
4029 switch (op2) {
4030 case OPC2_32_BO_LD_A_SHORTOFF:
4031 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4032 break;
4033 case OPC2_32_BO_LD_A_POSTINC:
4034 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4035 MO_LEUL);
4036 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4037 break;
4038 case OPC2_32_BO_LD_A_PREINC:
4039 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4040 break;
4041 case OPC2_32_BO_LD_B_SHORTOFF:
4042 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4043 break;
4044 case OPC2_32_BO_LD_B_POSTINC:
4045 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4046 MO_SB);
4047 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4048 break;
4049 case OPC2_32_BO_LD_B_PREINC:
4050 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4051 break;
4052 case OPC2_32_BO_LD_BU_SHORTOFF:
4053 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4054 break;
4055 case OPC2_32_BO_LD_BU_POSTINC:
4056 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4057 MO_UB);
4058 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4059 break;
4060 case OPC2_32_BO_LD_BU_PREINC:
4061 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4062 break;
4063 case OPC2_32_BO_LD_D_SHORTOFF:
4064 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4065 off10, ctx);
4066 break;
4067 case OPC2_32_BO_LD_D_POSTINC:
4068 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4069 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4070 break;
4071 case OPC2_32_BO_LD_D_PREINC:
4072 temp = tcg_temp_new();
4073 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4074 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4075 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4076 tcg_temp_free(temp);
4077 break;
4078 case OPC2_32_BO_LD_DA_SHORTOFF:
4079 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4080 off10, ctx);
4081 break;
4082 case OPC2_32_BO_LD_DA_POSTINC:
4083 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4084 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4085 break;
4086 case OPC2_32_BO_LD_DA_PREINC:
4087 temp = tcg_temp_new();
4088 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4089 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4090 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4091 tcg_temp_free(temp);
4092 break;
4093 case OPC2_32_BO_LD_H_SHORTOFF:
4094 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4095 break;
4096 case OPC2_32_BO_LD_H_POSTINC:
4097 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4098 MO_LESW);
4099 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4100 break;
4101 case OPC2_32_BO_LD_H_PREINC:
4102 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4103 break;
4104 case OPC2_32_BO_LD_HU_SHORTOFF:
4105 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4106 break;
4107 case OPC2_32_BO_LD_HU_POSTINC:
4108 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4109 MO_LEUW);
4110 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4111 break;
4112 case OPC2_32_BO_LD_HU_PREINC:
4113 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4114 break;
4115 case OPC2_32_BO_LD_Q_SHORTOFF:
4116 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4117 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4118 break;
4119 case OPC2_32_BO_LD_Q_POSTINC:
4120 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4121 MO_LEUW);
4122 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4123 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4124 break;
4125 case OPC2_32_BO_LD_Q_PREINC:
4126 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4127 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4128 break;
4129 case OPC2_32_BO_LD_W_SHORTOFF:
4130 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4131 break;
4132 case OPC2_32_BO_LD_W_POSTINC:
4133 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4134 MO_LEUL);
4135 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4136 break;
4137 case OPC2_32_BO_LD_W_PREINC:
4138 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4139 break;
4140 }
4141 }
4142
4143 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
4144 DisasContext *ctx)
4145 {
4146 uint32_t op2;
4147 uint32_t off10;
4148 int r1, r2;
4149
4150 TCGv temp, temp2, temp3;
4151
4152 r1 = MASK_OP_BO_S1D(ctx->opcode);
4153 r2 = MASK_OP_BO_S2(ctx->opcode);
4154 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4155 op2 = MASK_OP_BO_OP2(ctx->opcode);
4156
4157 temp = tcg_temp_new();
4158 temp2 = tcg_temp_new();
4159 temp3 = tcg_const_i32(off10);
4160
4161 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4162 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4163
4164
4165 switch (op2) {
4166 case OPC2_32_BO_LD_A_BR:
4167 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4168 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4169 break;
4170 case OPC2_32_BO_LD_A_CIRC:
4171 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4172 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4173 break;
4174 case OPC2_32_BO_LD_B_BR:
4175 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4176 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4177 break;
4178 case OPC2_32_BO_LD_B_CIRC:
4179 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4180 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4181 break;
4182 case OPC2_32_BO_LD_BU_BR:
4183 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4184 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4185 break;
4186 case OPC2_32_BO_LD_BU_CIRC:
4187 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4188 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4189 break;
4190 case OPC2_32_BO_LD_D_BR:
4191 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4192 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4193 break;
4194 case OPC2_32_BO_LD_D_CIRC:
4195 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4196 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4197 tcg_gen_addi_tl(temp, temp, 4);
4198 tcg_gen_rem_tl(temp, temp, temp2);
4199 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4200 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4201 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4202 break;
4203 case OPC2_32_BO_LD_DA_BR:
4204 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4205 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4206 break;
4207 case OPC2_32_BO_LD_DA_CIRC:
4208 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4209 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4210 tcg_gen_addi_tl(temp, temp, 4);
4211 tcg_gen_rem_tl(temp, temp, temp2);
4212 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4213 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4214 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4215 break;
4216 case OPC2_32_BO_LD_H_BR:
4217 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4218 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4219 break;
4220 case OPC2_32_BO_LD_H_CIRC:
4221 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4222 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4223 break;
4224 case OPC2_32_BO_LD_HU_BR:
4225 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4226 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4227 break;
4228 case OPC2_32_BO_LD_HU_CIRC:
4229 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4230 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4231 break;
4232 case OPC2_32_BO_LD_Q_BR:
4233 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4234 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4235 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4236 break;
4237 case OPC2_32_BO_LD_Q_CIRC:
4238 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4239 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4240 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4241 break;
4242 case OPC2_32_BO_LD_W_BR:
4243 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4244 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4245 break;
4246 case OPC2_32_BO_LD_W_CIRC:
4247 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4248 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4249 break;
4250 }
4251 tcg_temp_free(temp);
4252 tcg_temp_free(temp2);
4253 tcg_temp_free(temp3);
4254 }
4255
4256 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
4257 DisasContext *ctx)
4258 {
4259 uint32_t op2;
4260 uint32_t off10;
4261 int r1, r2;
4262
4263 TCGv temp, temp2;
4264
4265 r1 = MASK_OP_BO_S1D(ctx->opcode);
4266 r2 = MASK_OP_BO_S2(ctx->opcode);
4267 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4268 op2 = MASK_OP_BO_OP2(ctx->opcode);
4269
4270
4271 temp = tcg_temp_new();
4272 temp2 = tcg_temp_new();
4273
4274 switch (op2) {
4275 case OPC2_32_BO_LDLCX_SHORTOFF:
4276 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4277 gen_helper_ldlcx(cpu_env, temp);
4278 break;
4279 case OPC2_32_BO_LDMST_SHORTOFF:
4280 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4281 gen_ldmst(ctx, r1, temp);
4282 break;
4283 case OPC2_32_BO_LDMST_POSTINC:
4284 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4285 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4286 break;
4287 case OPC2_32_BO_LDMST_PREINC:
4288 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4289 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4290 break;
4291 case OPC2_32_BO_LDUCX_SHORTOFF:
4292 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4293 gen_helper_lducx(cpu_env, temp);
4294 break;
4295 case OPC2_32_BO_LEA_SHORTOFF:
4296 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4297 break;
4298 case OPC2_32_BO_STLCX_SHORTOFF:
4299 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4300 gen_helper_stlcx(cpu_env, temp);
4301 break;
4302 case OPC2_32_BO_STUCX_SHORTOFF:
4303 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4304 gen_helper_stucx(cpu_env, temp);
4305 break;
4306 case OPC2_32_BO_SWAP_W_SHORTOFF:
4307 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4308 gen_swap(ctx, r1, temp);
4309 break;
4310 case OPC2_32_BO_SWAP_W_POSTINC:
4311 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4312 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4313 break;
4314 case OPC2_32_BO_SWAP_W_PREINC:
4315 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4316 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4317 break;
4318 }
4319 tcg_temp_free(temp);
4320 tcg_temp_free(temp2);
4321 }
4322
4323 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
4324 DisasContext *ctx)
4325 {
4326 uint32_t op2;
4327 uint32_t off10;
4328 int r1, r2;
4329
4330 TCGv temp, temp2, temp3;
4331
4332 r1 = MASK_OP_BO_S1D(ctx->opcode);
4333 r2 = MASK_OP_BO_S2(ctx->opcode);
4334 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4335 op2 = MASK_OP_BO_OP2(ctx->opcode);
4336
4337 temp = tcg_temp_new();
4338 temp2 = tcg_temp_new();
4339 temp3 = tcg_const_i32(off10);
4340
4341 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4342 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4343
4344 switch (op2) {
4345 case OPC2_32_BO_LDMST_BR:
4346 gen_ldmst(ctx, r1, temp2);
4347 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4348 break;
4349 case OPC2_32_BO_LDMST_CIRC:
4350 gen_ldmst(ctx, r1, temp2);
4351 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4352 break;
4353 case OPC2_32_BO_SWAP_W_BR:
4354 gen_swap(ctx, r1, temp2);
4355 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4356 break;
4357 case OPC2_32_BO_SWAP_W_CIRC:
4358 gen_swap(ctx, r1, temp2);
4359 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4360 break;
4361 }
4362 tcg_temp_free(temp);
4363 tcg_temp_free(temp2);
4364 tcg_temp_free(temp3);
4365 }
4366
4367 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
4368 {
4369 int r1, r2;
4370 int32_t address;
4371 TCGv temp;
4372
4373 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4374 r2 = MASK_OP_BOL_S2(ctx->opcode);
4375 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4376
4377 switch (op1) {
4378 case OPC1_32_BOL_LD_A_LONGOFF:
4379 temp = tcg_temp_new();
4380 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4381 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4382 tcg_temp_free(temp);
4383 break;
4384 case OPC1_32_BOL_LD_W_LONGOFF:
4385 temp = tcg_temp_new();
4386 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4387 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4388 tcg_temp_free(temp);
4389 break;
4390 case OPC1_32_BOL_LEA_LONGOFF:
4391 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4392 break;
4393 case OPC1_32_BOL_ST_A_LONGOFF:
4394 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4395 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4396 } else {
4397 /* raise illegal opcode trap */
4398 }
4399 break;
4400 case OPC1_32_BOL_ST_W_LONGOFF:
4401 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4402 break;
4403 case OPC1_32_BOL_LD_B_LONGOFF:
4404 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4405 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4406 } else {
4407 /* raise illegal opcode trap */
4408 }
4409 break;
4410 case OPC1_32_BOL_LD_BU_LONGOFF:
4411 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4412 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4413 } else {
4414 /* raise illegal opcode trap */
4415 }
4416 break;
4417 case OPC1_32_BOL_LD_H_LONGOFF:
4418 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4419 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4420 } else {
4421 /* raise illegal opcode trap */
4422 }
4423 break;
4424 case OPC1_32_BOL_LD_HU_LONGOFF:
4425 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4426 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4427 } else {
4428 /* raise illegal opcode trap */
4429 }
4430 break;
4431 case OPC1_32_BOL_ST_B_LONGOFF:
4432 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4433 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4434 } else {
4435 /* raise illegal opcode trap */
4436 }
4437 break;
4438 case OPC1_32_BOL_ST_H_LONGOFF:
4439 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4440 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4441 } else {
4442 /* raise illegal opcode trap */
4443 }
4444 break;
4445 }
4446 }
4447
4448 /* RC format */
4449 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
4450 {
4451 uint32_t op2;
4452 int r1, r2;
4453 int32_t const9;
4454 TCGv temp;
4455
4456 r2 = MASK_OP_RC_D(ctx->opcode);
4457 r1 = MASK_OP_RC_S1(ctx->opcode);
4458 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4459 op2 = MASK_OP_RC_OP2(ctx->opcode);
4460
4461 temp = tcg_temp_new();
4462
4463 switch (op2) {
4464 case OPC2_32_RC_AND:
4465 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4466 break;
4467 case OPC2_32_RC_ANDN:
4468 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4469 break;
4470 case OPC2_32_RC_NAND:
4471 tcg_gen_movi_tl(temp, const9);
4472 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4473 break;
4474 case OPC2_32_RC_NOR:
4475 tcg_gen_movi_tl(temp, const9);
4476 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4477 break;
4478 case OPC2_32_RC_OR:
4479 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4480 break;
4481 case OPC2_32_RC_ORN:
4482 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4483 break;
4484 case OPC2_32_RC_SH:
4485 const9 = sextract32(const9, 0, 6);
4486 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4487 break;
4488 case OPC2_32_RC_SH_H:
4489 const9 = sextract32(const9, 0, 5);
4490 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4491 break;
4492 case OPC2_32_RC_SHA:
4493 const9 = sextract32(const9, 0, 6);
4494 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4495 break;
4496 case OPC2_32_RC_SHA_H:
4497 const9 = sextract32(const9, 0, 5);
4498 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4499 break;
4500 case OPC2_32_RC_SHAS:
4501 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4502 break;
4503 case OPC2_32_RC_XNOR:
4504 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4505 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
4506 break;
4507 case OPC2_32_RC_XOR:
4508 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4509 break;
4510 }
4511 tcg_temp_free(temp);
4512 }
4513
4514 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
4515 {
4516 uint32_t op2;
4517 int r1, r2;
4518 int16_t const9;
4519
4520 TCGv temp;
4521
4522 r2 = MASK_OP_RC_D(ctx->opcode);
4523 r1 = MASK_OP_RC_S1(ctx->opcode);
4524 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
4525
4526 op2 = MASK_OP_RC_OP2(ctx->opcode);
4527
4528 temp = tcg_temp_new();
4529
4530 switch (op2) {
4531 case OPC2_32_RC_ABSDIF:
4532 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4533 break;
4534 case OPC2_32_RC_ABSDIFS:
4535 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4536 break;
4537 case OPC2_32_RC_ADD:
4538 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4539 break;
4540 case OPC2_32_RC_ADDC:
4541 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4542 break;
4543 case OPC2_32_RC_ADDS:
4544 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4545 break;
4546 case OPC2_32_RC_ADDS_U:
4547 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4548 break;
4549 case OPC2_32_RC_ADDX:
4550 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4551 break;
4552 case OPC2_32_RC_AND_EQ:
4553 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4554 const9, &tcg_gen_and_tl);
4555 break;
4556 case OPC2_32_RC_AND_GE:
4557 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4558 const9, &tcg_gen_and_tl);
4559 break;
4560 case OPC2_32_RC_AND_GE_U:
4561 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4562 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4563 const9, &tcg_gen_and_tl);
4564 break;
4565 case OPC2_32_RC_AND_LT:
4566 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4567 const9, &tcg_gen_and_tl);
4568 break;
4569 case OPC2_32_RC_AND_LT_U:
4570 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4571 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4572 const9, &tcg_gen_and_tl);
4573 break;
4574 case OPC2_32_RC_AND_NE:
4575 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4576 const9, &tcg_gen_and_tl);
4577 break;
4578 case OPC2_32_RC_EQ:
4579 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4580 break;
4581 case OPC2_32_RC_EQANY_B:
4582 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4583 break;
4584 case OPC2_32_RC_EQANY_H:
4585 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4586 break;
4587 case OPC2_32_RC_GE:
4588 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4589 break;
4590 case OPC2_32_RC_GE_U:
4591 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4592 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4593 break;
4594 case OPC2_32_RC_LT:
4595 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4596 break;
4597 case OPC2_32_RC_LT_U:
4598 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4599 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4600 break;
4601 case OPC2_32_RC_MAX:
4602 tcg_gen_movi_tl(temp, const9);
4603 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4604 cpu_gpr_d[r1], temp);
4605 break;
4606 case OPC2_32_RC_MAX_U:
4607 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
4608 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4609 cpu_gpr_d[r1], temp);
4610 break;
4611 case OPC2_32_RC_MIN:
4612 tcg_gen_movi_tl(temp, const9);
4613 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4614 cpu_gpr_d[r1], temp);
4615 break;
4616 case OPC2_32_RC_MIN_U:
4617 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
4618 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4619 cpu_gpr_d[r1], temp);
4620 break;
4621 case OPC2_32_RC_NE:
4622 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4623 break;
4624 case OPC2_32_RC_OR_EQ:
4625 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4626 const9, &tcg_gen_or_tl);
4627 break;
4628 case OPC2_32_RC_OR_GE:
4629 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4630 const9, &tcg_gen_or_tl);
4631 break;
4632 case OPC2_32_RC_OR_GE_U:
4633 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4634 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4635 const9, &tcg_gen_or_tl);
4636 break;
4637 case OPC2_32_RC_OR_LT:
4638 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4639 const9, &tcg_gen_or_tl);
4640 break;
4641 case OPC2_32_RC_OR_LT_U:
4642 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4643 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4644 const9, &tcg_gen_or_tl);
4645 break;
4646 case OPC2_32_RC_OR_NE:
4647 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4648 const9, &tcg_gen_or_tl);
4649 break;
4650 case OPC2_32_RC_RSUB:
4651 tcg_gen_movi_tl(temp, const9);
4652 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4653 break;
4654 case OPC2_32_RC_RSUBS:
4655 tcg_gen_movi_tl(temp, const9);
4656 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4657 break;
4658 case OPC2_32_RC_RSUBS_U:
4659 tcg_gen_movi_tl(temp, const9);
4660 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4661 break;
4662 case OPC2_32_RC_SH_EQ:
4663 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4664 break;
4665 case OPC2_32_RC_SH_GE:
4666 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4667 break;
4668 case OPC2_32_RC_SH_GE_U:
4669 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4670 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4671 break;
4672 case OPC2_32_RC_SH_LT:
4673 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4674 break;
4675 case OPC2_32_RC_SH_LT_U:
4676 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4677 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4678 break;
4679 case OPC2_32_RC_SH_NE:
4680 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4681 break;
4682 case OPC2_32_RC_XOR_EQ:
4683 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4684 const9, &tcg_gen_xor_tl);
4685 break;
4686 case OPC2_32_RC_XOR_GE:
4687 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4688 const9, &tcg_gen_xor_tl);
4689 break;
4690 case OPC2_32_RC_XOR_GE_U:
4691 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4692 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4693 const9, &tcg_gen_xor_tl);
4694 break;
4695 case OPC2_32_RC_XOR_LT:
4696 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4697 const9, &tcg_gen_xor_tl);
4698 break;
4699 case OPC2_32_RC_XOR_LT_U:
4700 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4701 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4702 const9, &tcg_gen_xor_tl);
4703 break;
4704 case OPC2_32_RC_XOR_NE:
4705 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4706 const9, &tcg_gen_xor_tl);
4707 break;
4708 }
4709 tcg_temp_free(temp);
4710 }
4711
4712 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
4713 {
4714 uint32_t op2;
4715 uint32_t const9;
4716
4717 op2 = MASK_OP_RC_OP2(ctx->opcode);
4718 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4719
4720 switch (op2) {
4721 case OPC2_32_RC_BISR:
4722 gen_helper_1arg(bisr, const9);
4723 break;
4724 case OPC2_32_RC_SYSCALL:
4725 /* TODO: Add exception generation */
4726 break;
4727 }
4728 }
4729
4730 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
4731 {
4732 uint32_t op2;
4733 int r1, r2;
4734 int16_t const9;
4735
4736 r2 = MASK_OP_RC_D(ctx->opcode);
4737 r1 = MASK_OP_RC_S1(ctx->opcode);
4738 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
4739
4740 op2 = MASK_OP_RC_OP2(ctx->opcode);
4741
4742 switch (op2) {
4743 case OPC2_32_RC_MUL_32:
4744 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4745 break;
4746 case OPC2_32_RC_MUL_64:
4747 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
4748 break;
4749 case OPC2_32_RC_MULS_32:
4750 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4751 break;
4752 case OPC2_32_RC_MUL_U_64:
4753 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4754 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
4755 break;
4756 case OPC2_32_RC_MULS_U_32:
4757 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4758 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4759 break;
4760 }
4761 }
4762
4763 /* RCPW format */
4764 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
4765 {
4766 uint32_t op2;
4767 int r1, r2;
4768 int32_t pos, width, const4;
4769
4770 TCGv temp;
4771
4772 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
4773 r1 = MASK_OP_RCPW_S1(ctx->opcode);
4774 r2 = MASK_OP_RCPW_D(ctx->opcode);
4775 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
4776 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
4777 pos = MASK_OP_RCPW_POS(ctx->opcode);
4778
4779 switch (op2) {
4780 case OPC2_32_RCPW_IMASK:
4781 /* if pos + width > 31 undefined result */
4782 if (pos + width <= 31) {
4783 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
4784 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
4785 }
4786 break;
4787 case OPC2_32_RCPW_INSERT:
4788 /* if pos + width > 32 undefined result */
4789 if (pos + width <= 32) {
4790 temp = tcg_const_i32(const4);
4791 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
4792 tcg_temp_free(temp);
4793 }
4794 break;
4795 }
4796 }
4797
4798 /* RCRW format */
4799
4800 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
4801 {
4802 uint32_t op2;
4803 int r1, r3, r4;
4804 int32_t width, const4;
4805
4806 TCGv temp, temp2, temp3;
4807
4808 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
4809 r1 = MASK_OP_RCRW_S1(ctx->opcode);
4810 r3 = MASK_OP_RCRW_S3(ctx->opcode);
4811 r4 = MASK_OP_RCRW_D(ctx->opcode);
4812 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
4813 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
4814
4815 temp = tcg_temp_new();
4816 temp2 = tcg_temp_new();
4817
4818 switch (op2) {
4819 case OPC2_32_RCRW_IMASK:
4820 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
4821 tcg_gen_movi_tl(temp2, (1 << width) - 1);
4822 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
4823 tcg_gen_movi_tl(temp2, const4);
4824 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
4825 break;
4826 case OPC2_32_RCRW_INSERT:
4827 temp3 = tcg_temp_new();
4828
4829 tcg_gen_movi_tl(temp, width);
4830 tcg_gen_movi_tl(temp2, const4);
4831 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
4832 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
4833
4834 tcg_temp_free(temp3);
4835 break;
4836 }
4837 tcg_temp_free(temp);
4838 tcg_temp_free(temp2);
4839 }
4840
4841 /* RCR format */
4842
4843 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
4844 {
4845 uint32_t op2;
4846 int r1, r3, r4;
4847 int32_t const9;
4848
4849 TCGv temp, temp2;
4850
4851 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4852 r1 = MASK_OP_RCR_S1(ctx->opcode);
4853 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4854 r3 = MASK_OP_RCR_S3(ctx->opcode);
4855 r4 = MASK_OP_RCR_D(ctx->opcode);
4856
4857 switch (op2) {
4858 case OPC2_32_RCR_CADD:
4859 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
4860 cpu_gpr_d[r4]);
4861 break;
4862 case OPC2_32_RCR_CADDN:
4863 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
4864 cpu_gpr_d[r4]);
4865 break;
4866 case OPC2_32_RCR_SEL:
4867 temp = tcg_const_i32(0);
4868 temp2 = tcg_const_i32(const9);
4869 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
4870 cpu_gpr_d[r1], temp2);
4871 tcg_temp_free(temp);
4872 tcg_temp_free(temp2);
4873 break;
4874 case OPC2_32_RCR_SELN:
4875 temp = tcg_const_i32(0);
4876 temp2 = tcg_const_i32(const9);
4877 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
4878 cpu_gpr_d[r1], temp2);
4879 tcg_temp_free(temp);
4880 tcg_temp_free(temp2);
4881 break;
4882 }
4883 }
4884
4885 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
4886 {
4887 uint32_t op2;
4888 int r1, r3, r4;
4889 int32_t const9;
4890
4891
4892 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4893 r1 = MASK_OP_RCR_S1(ctx->opcode);
4894 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4895 r3 = MASK_OP_RCR_S3(ctx->opcode);
4896 r4 = MASK_OP_RCR_D(ctx->opcode);
4897
4898 switch (op2) {
4899 case OPC2_32_RCR_MADD_32:
4900 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4901 break;
4902 case OPC2_32_RCR_MADD_64:
4903 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4904 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4905 break;
4906 case OPC2_32_RCR_MADDS_32:
4907 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4908 break;
4909 case OPC2_32_RCR_MADDS_64:
4910 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4911 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4912 break;
4913 case OPC2_32_RCR_MADD_U_64:
4914 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4915 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4916 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4917 break;
4918 case OPC2_32_RCR_MADDS_U_32:
4919 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4920 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4921 break;
4922 case OPC2_32_RCR_MADDS_U_64:
4923 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4924 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4925 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4926 break;
4927 }
4928 }
4929
4930 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
4931 {
4932 uint32_t op2;
4933 int r1, r3, r4;
4934 int32_t const9;
4935
4936
4937 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4938 r1 = MASK_OP_RCR_S1(ctx->opcode);
4939 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4940 r3 = MASK_OP_RCR_S3(ctx->opcode);
4941 r4 = MASK_OP_RCR_D(ctx->opcode);
4942
4943 switch (op2) {
4944 case OPC2_32_RCR_MSUB_32:
4945 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4946 break;
4947 case OPC2_32_RCR_MSUB_64:
4948 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4949 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4950 break;
4951 case OPC2_32_RCR_MSUBS_32:
4952 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4953 break;
4954 case OPC2_32_RCR_MSUBS_64:
4955 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4956 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4957 break;
4958 case OPC2_32_RCR_MSUB_U_64:
4959 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4960 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4961 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4962 break;
4963 case OPC2_32_RCR_MSUBS_U_32:
4964 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4965 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4966 break;
4967 case OPC2_32_RCR_MSUBS_U_64:
4968 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4969 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4970 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4971 break;
4972 }
4973 }
4974
4975 /* RLC format */
4976
4977 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
4978 uint32_t op1)
4979 {
4980 int32_t const16;
4981 int r1, r2;
4982
4983 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
4984 r1 = MASK_OP_RLC_S1(ctx->opcode);
4985 r2 = MASK_OP_RLC_D(ctx->opcode);
4986
4987 switch (op1) {
4988 case OPC1_32_RLC_ADDI:
4989 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
4990 break;
4991 case OPC1_32_RLC_ADDIH:
4992 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
4993 break;
4994 case OPC1_32_RLC_ADDIH_A:
4995 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
4996 break;
4997 case OPC1_32_RLC_MFCR:
4998 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
4999 gen_mfcr(env, cpu_gpr_d[r2], const16);
5000 break;
5001 case OPC1_32_RLC_MOV:
5002 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5003 break;
5004 case OPC1_32_RLC_MOV_64:
5005 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5006 if ((r2 & 0x1) != 0) {
5007 /* TODO: raise OPD trap */
5008 }
5009 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5010 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5011 } else {
5012 /* TODO: raise illegal opcode trap */
5013 }
5014 break;
5015 case OPC1_32_RLC_MOV_U:
5016 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5017 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5018 break;
5019 case OPC1_32_RLC_MOV_H:
5020 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5021 break;
5022 case OPC1_32_RLC_MOVH_A:
5023 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5024 break;
5025 case OPC1_32_RLC_MTCR:
5026 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5027 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
5028 break;
5029 }
5030 }
5031
5032 /* RR format */
5033 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5034 {
5035 uint32_t op2;
5036 int r3, r2, r1;
5037
5038 r3 = MASK_OP_RR_D(ctx->opcode);
5039 r2 = MASK_OP_RR_S2(ctx->opcode);
5040 r1 = MASK_OP_RR_S1(ctx->opcode);
5041 op2 = MASK_OP_RR_OP2(ctx->opcode);
5042
5043 switch (op2) {
5044 case OPC2_32_RR_ABS:
5045 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5046 break;
5047 case OPC2_32_RR_ABS_B:
5048 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5049 break;
5050 case OPC2_32_RR_ABS_H:
5051 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5052 break;
5053 case OPC2_32_RR_ABSDIF:
5054 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5055 break;
5056 case OPC2_32_RR_ABSDIF_B:
5057 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5058 cpu_gpr_d[r2]);
5059 break;
5060 case OPC2_32_RR_ABSDIF_H:
5061 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5062 cpu_gpr_d[r2]);
5063 break;
5064 case OPC2_32_RR_ABSDIFS:
5065 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5066 cpu_gpr_d[r2]);
5067 break;
5068 case OPC2_32_RR_ABSDIFS_H:
5069 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5070 cpu_gpr_d[r2]);
5071 break;
5072 case OPC2_32_RR_ABSS:
5073 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5074 break;
5075 case OPC2_32_RR_ABSS_H:
5076 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5077 break;
5078 case OPC2_32_RR_ADD:
5079 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5080 break;
5081 case OPC2_32_RR_ADD_B:
5082 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5083 break;
5084 case OPC2_32_RR_ADD_H:
5085 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5086 break;
5087 case OPC2_32_RR_ADDC:
5088 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5089 break;
5090 case OPC2_32_RR_ADDS:
5091 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5092 break;
5093 case OPC2_32_RR_ADDS_H:
5094 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5095 cpu_gpr_d[r2]);
5096 break;
5097 case OPC2_32_RR_ADDS_HU:
5098 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5099 cpu_gpr_d[r2]);
5100 break;
5101 case OPC2_32_RR_ADDS_U:
5102 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5103 cpu_gpr_d[r2]);
5104 break;
5105 case OPC2_32_RR_ADDX:
5106 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5107 break;
5108 case OPC2_32_RR_AND_EQ:
5109 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5110 cpu_gpr_d[r2], &tcg_gen_and_tl);
5111 break;
5112 case OPC2_32_RR_AND_GE:
5113 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5114 cpu_gpr_d[r2], &tcg_gen_and_tl);
5115 break;
5116 case OPC2_32_RR_AND_GE_U:
5117 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5118 cpu_gpr_d[r2], &tcg_gen_and_tl);
5119 break;
5120 case OPC2_32_RR_AND_LT:
5121 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5122 cpu_gpr_d[r2], &tcg_gen_and_tl);
5123 break;
5124 case OPC2_32_RR_AND_LT_U:
5125 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5126 cpu_gpr_d[r2], &tcg_gen_and_tl);
5127 break;
5128 case OPC2_32_RR_AND_NE:
5129 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5130 cpu_gpr_d[r2], &tcg_gen_and_tl);
5131 break;
5132 case OPC2_32_RR_EQ:
5133 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5134 cpu_gpr_d[r2]);
5135 break;
5136 case OPC2_32_RR_EQ_B:
5137 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5138 break;
5139 case OPC2_32_RR_EQ_H:
5140 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5141 break;
5142 case OPC2_32_RR_EQ_W:
5143 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5144 break;
5145 case OPC2_32_RR_EQANY_B:
5146 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5147 break;
5148 case OPC2_32_RR_EQANY_H:
5149 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5150 break;
5151 case OPC2_32_RR_GE:
5152 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5153 cpu_gpr_d[r2]);
5154 break;
5155 case OPC2_32_RR_GE_U:
5156 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5157 cpu_gpr_d[r2]);
5158 break;
5159 case OPC2_32_RR_LT:
5160 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5161 cpu_gpr_d[r2]);
5162 break;
5163 case OPC2_32_RR_LT_U:
5164 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5165 cpu_gpr_d[r2]);
5166 break;
5167 case OPC2_32_RR_LT_B:
5168 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5169 break;
5170 case OPC2_32_RR_LT_BU:
5171 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5172 break;
5173 case OPC2_32_RR_LT_H:
5174 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5175 break;
5176 case OPC2_32_RR_LT_HU:
5177 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5178 break;
5179 case OPC2_32_RR_LT_W:
5180 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5181 break;
5182 case OPC2_32_RR_LT_WU:
5183 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5184 break;
5185 case OPC2_32_RR_MAX:
5186 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5187 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5188 break;
5189 case OPC2_32_RR_MAX_U:
5190 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5191 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5192 break;
5193 case OPC2_32_RR_MAX_B:
5194 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5195 break;
5196 case OPC2_32_RR_MAX_BU:
5197 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5198 break;
5199 case OPC2_32_RR_MAX_H:
5200 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5201 break;
5202 case OPC2_32_RR_MAX_HU:
5203 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5204 break;
5205 case OPC2_32_RR_MIN:
5206 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5207 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5208 break;
5209 case OPC2_32_RR_MIN_U:
5210 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5211 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5212 break;
5213 case OPC2_32_RR_MIN_B:
5214 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5215 break;
5216 case OPC2_32_RR_MIN_BU:
5217 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5218 break;
5219 case OPC2_32_RR_MIN_H:
5220 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5221 break;
5222 case OPC2_32_RR_MIN_HU:
5223 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5224 break;
5225 case OPC2_32_RR_MOV:
5226 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5227 break;
5228 case OPC2_32_RR_NE:
5229 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5230 cpu_gpr_d[r2]);
5231 break;
5232 case OPC2_32_RR_OR_EQ:
5233 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5234 cpu_gpr_d[r2], &tcg_gen_or_tl);
5235 break;
5236 case OPC2_32_RR_OR_GE:
5237 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5238 cpu_gpr_d[r2], &tcg_gen_or_tl);
5239 break;
5240 case OPC2_32_RR_OR_GE_U:
5241 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5242 cpu_gpr_d[r2], &tcg_gen_or_tl);
5243 break;
5244 case OPC2_32_RR_OR_LT:
5245 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5246 cpu_gpr_d[r2], &tcg_gen_or_tl);
5247 break;
5248 case OPC2_32_RR_OR_LT_U:
5249 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5250 cpu_gpr_d[r2], &tcg_gen_or_tl);
5251 break;
5252 case OPC2_32_RR_OR_NE:
5253 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5254 cpu_gpr_d[r2], &tcg_gen_or_tl);
5255 break;
5256 case OPC2_32_RR_SAT_B:
5257 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5258 break;
5259 case OPC2_32_RR_SAT_BU:
5260 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5261 break;
5262 case OPC2_32_RR_SAT_H:
5263 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5264 break;
5265 case OPC2_32_RR_SAT_HU:
5266 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5267 break;
5268 case OPC2_32_RR_SH_EQ:
5269 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5270 cpu_gpr_d[r2]);
5271 break;
5272 case OPC2_32_RR_SH_GE:
5273 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5274 cpu_gpr_d[r2]);
5275 break;
5276 case OPC2_32_RR_SH_GE_U:
5277 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5278 cpu_gpr_d[r2]);
5279 break;
5280 case OPC2_32_RR_SH_LT:
5281 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5282 cpu_gpr_d[r2]);
5283 break;
5284 case OPC2_32_RR_SH_LT_U:
5285 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5286 cpu_gpr_d[r2]);
5287 break;
5288 case OPC2_32_RR_SH_NE:
5289 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5290 cpu_gpr_d[r2]);
5291 break;
5292 case OPC2_32_RR_SUB:
5293 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5294 break;
5295 case OPC2_32_RR_SUB_B:
5296 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5297 break;
5298 case OPC2_32_RR_SUB_H:
5299 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5300 break;
5301 case OPC2_32_RR_SUBC:
5302 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5303 break;
5304 case OPC2_32_RR_SUBS:
5305 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5306 break;
5307 case OPC2_32_RR_SUBS_U:
5308 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5309 break;
5310 case OPC2_32_RR_SUBS_H:
5311 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5312 cpu_gpr_d[r2]);
5313 break;
5314 case OPC2_32_RR_SUBS_HU:
5315 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5316 cpu_gpr_d[r2]);
5317 break;
5318 case OPC2_32_RR_SUBX:
5319 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5320 break;
5321 case OPC2_32_RR_XOR_EQ:
5322 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5323 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5324 break;
5325 case OPC2_32_RR_XOR_GE:
5326 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5327 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5328 break;
5329 case OPC2_32_RR_XOR_GE_U:
5330 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5331 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5332 break;
5333 case OPC2_32_RR_XOR_LT:
5334 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5335 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5336 break;
5337 case OPC2_32_RR_XOR_LT_U:
5338 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5339 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5340 break;
5341 case OPC2_32_RR_XOR_NE:
5342 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5343 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5344 break;
5345 }
5346 }
5347
5348 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5349 {
5350 uint32_t op2;
5351 int r3, r2, r1;
5352 TCGv temp;
5353
5354 r3 = MASK_OP_RR_D(ctx->opcode);
5355 r2 = MASK_OP_RR_S2(ctx->opcode);
5356 r1 = MASK_OP_RR_S1(ctx->opcode);
5357
5358 temp = tcg_temp_new();
5359 op2 = MASK_OP_RR_OP2(ctx->opcode);
5360
5361 switch (op2) {
5362 case OPC2_32_RR_AND:
5363 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5364 break;
5365 case OPC2_32_RR_ANDN:
5366 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5367 break;
5368 case OPC2_32_RR_CLO:
5369 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5370 break;
5371 case OPC2_32_RR_CLO_H:
5372 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5373 break;
5374 case OPC2_32_RR_CLS:
5375 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5376 break;
5377 case OPC2_32_RR_CLS_H:
5378 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5379 break;
5380 case OPC2_32_RR_CLZ:
5381 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5382 break;
5383 case OPC2_32_RR_CLZ_H:
5384 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5385 break;
5386 case OPC2_32_RR_NAND:
5387 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5388 break;
5389 case OPC2_32_RR_NOR:
5390 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5391 break;
5392 case OPC2_32_RR_OR:
5393 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5394 break;
5395 case OPC2_32_RR_ORN:
5396 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5397 break;
5398 case OPC2_32_RR_SH:
5399 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5400 break;
5401 case OPC2_32_RR_SH_H:
5402 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5403 break;
5404 case OPC2_32_RR_SHA:
5405 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5406 break;
5407 case OPC2_32_RR_SHA_H:
5408 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5409 break;
5410 case OPC2_32_RR_SHAS:
5411 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5412 break;
5413 case OPC2_32_RR_XNOR:
5414 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5415 break;
5416 case OPC2_32_RR_XOR:
5417 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5418 break;
5419 }
5420 tcg_temp_free(temp);
5421 }
5422
5423 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
5424 {
5425 uint32_t op2, n;
5426 int r1, r2, r3;
5427 TCGv temp;
5428
5429 op2 = MASK_OP_RR_OP2(ctx->opcode);
5430 r3 = MASK_OP_RR_D(ctx->opcode);
5431 r2 = MASK_OP_RR_S2(ctx->opcode);
5432 r1 = MASK_OP_RR_S1(ctx->opcode);
5433 n = MASK_OP_RR_N(ctx->opcode);
5434
5435 switch (op2) {
5436 case OPC2_32_RR_ADD_A:
5437 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
5438 break;
5439 case OPC2_32_RR_ADDSC_A:
5440 temp = tcg_temp_new();
5441 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
5442 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
5443 tcg_temp_free(temp);
5444 break;
5445 case OPC2_32_RR_ADDSC_AT:
5446 temp = tcg_temp_new();
5447 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
5448 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
5449 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
5450 tcg_temp_free(temp);
5451 break;
5452 case OPC2_32_RR_EQ_A:
5453 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
5454 cpu_gpr_a[r2]);
5455 break;
5456 case OPC2_32_RR_EQZ:
5457 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
5458 break;
5459 case OPC2_32_RR_GE_A:
5460 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
5461 cpu_gpr_a[r2]);
5462 break;
5463 case OPC2_32_RR_LT_A:
5464 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
5465 cpu_gpr_a[r2]);
5466 break;
5467 case OPC2_32_RR_MOV_A:
5468 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
5469 break;
5470 case OPC2_32_RR_MOV_AA:
5471 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
5472 break;
5473 case OPC2_32_RR_MOV_D:
5474 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
5475 break;
5476 case OPC2_32_RR_NE_A:
5477 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
5478 cpu_gpr_a[r2]);
5479 break;
5480 case OPC2_32_RR_NEZ_A:
5481 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
5482 break;
5483 case OPC2_32_RR_SUB_A:
5484 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
5485 break;
5486 }
5487 }
5488
5489 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
5490 {
5491 uint32_t op2;
5492 int r1;
5493
5494 op2 = MASK_OP_RR_OP2(ctx->opcode);
5495 r1 = MASK_OP_RR_S1(ctx->opcode);
5496
5497 switch (op2) {
5498 case OPC2_32_RR_JI:
5499 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5500 break;
5501 case OPC2_32_RR_JLI:
5502 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
5503 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5504 break;
5505 case OPC2_32_RR_CALLI:
5506 gen_helper_1arg(call, ctx->next_pc);
5507 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5508 break;
5509 }
5510 tcg_gen_exit_tb(0);
5511 ctx->bstate = BS_BRANCH;
5512 }
5513
5514 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
5515 {
5516 uint32_t op2;
5517 int r1, r2, r3;
5518
5519 TCGv temp, temp2;
5520
5521 op2 = MASK_OP_RR_OP2(ctx->opcode);
5522 r3 = MASK_OP_RR_D(ctx->opcode);
5523 r2 = MASK_OP_RR_S2(ctx->opcode);
5524 r1 = MASK_OP_RR_S1(ctx->opcode);
5525
5526 switch (op2) {
5527 case OPC2_32_RR_BMERGE:
5528 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5529 break;
5530 case OPC2_32_RR_BSPLIT:
5531 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5532 break;
5533 case OPC2_32_RR_DVINIT_B:
5534 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5535 cpu_gpr_d[r2]);
5536 break;
5537 case OPC2_32_RR_DVINIT_BU:
5538 temp = tcg_temp_new();
5539 temp2 = tcg_temp_new();
5540 /* reset av */
5541 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5542 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
5543 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5544 tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
5545 /* use cpu_PSW_AV to compare against 0 */
5546 tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
5547 temp, cpu_gpr_d[r3+1]);
5548 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
5549 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
5550 temp2, cpu_gpr_d[r2]);
5551 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
5552 } else {
5553 /* overflow = (D[b] == 0) */
5554 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5555 }
5556 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5557 /* sv */
5558 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5559 /* write result */
5560 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8);
5561 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
5562 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
5563
5564 tcg_temp_free(temp);
5565 tcg_temp_free(temp2);
5566 break;
5567 case OPC2_32_RR_DVINIT_H:
5568 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5569 cpu_gpr_d[r2]);
5570 break;
5571 case OPC2_32_RR_DVINIT_HU:
5572 temp = tcg_temp_new();
5573 temp2 = tcg_temp_new();
5574 /* reset av */
5575 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5576 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
5577 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5578 tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
5579 /* use cpu_PSW_AV to compare against 0 */
5580 tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
5581 temp, cpu_gpr_d[r3+1]);
5582 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
5583 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
5584 temp2, cpu_gpr_d[r2]);
5585 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
5586 } else {
5587 /* overflow = (D[b] == 0) */
5588 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5589 }
5590 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5591 /* sv */
5592 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5593 /* write result */
5594 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5595 tcg_gen_shri_tl(cpu_gpr_d[r3+1], temp, 16);
5596 tcg_gen_shli_tl(cpu_gpr_d[r3], temp, 16);
5597 tcg_temp_free(temp);
5598 tcg_temp_free(temp2);
5599 break;
5600 case OPC2_32_RR_DVINIT:
5601 temp = tcg_temp_new();
5602 temp2 = tcg_temp_new();
5603 /* overflow = ((D[b] == 0) ||
5604 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
5605 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
5606 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
5607 tcg_gen_and_tl(temp, temp, temp2);
5608 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
5609 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
5610 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5611 /* sv */
5612 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5613 /* reset av */
5614 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5615 /* write result */
5616 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5617 /* sign extend to high reg */
5618 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
5619 tcg_temp_free(temp);
5620 tcg_temp_free(temp2);
5621 break;
5622 case OPC2_32_RR_DVINIT_U:
5623 /* overflow = (D[b] == 0) */
5624 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5625 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5626 /* sv */
5627 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5628 /* reset av */
5629 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5630 /* write result */
5631 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5632 /* zero extend to high reg*/
5633 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
5634 break;
5635 case OPC2_32_RR_PARITY:
5636 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5637 break;
5638 case OPC2_32_RR_UNPACK:
5639 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5640 break;
5641 }
5642 }
5643
5644 /* RR1 Format */
5645 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
5646 {
5647 uint32_t op2;
5648
5649 int r1, r2, r3;
5650 TCGv n;
5651 TCGv_i64 temp64;
5652
5653 r1 = MASK_OP_RR1_S1(ctx->opcode);
5654 r2 = MASK_OP_RR1_S2(ctx->opcode);
5655 r3 = MASK_OP_RR1_D(ctx->opcode);
5656 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
5657 op2 = MASK_OP_RR1_OP2(ctx->opcode);
5658
5659 switch (op2) {
5660 case OPC2_32_RR1_MUL_H_32_LL:
5661 temp64 = tcg_temp_new_i64();
5662 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5663 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5664 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5665 tcg_temp_free_i64(temp64);
5666 break;
5667 case OPC2_32_RR1_MUL_H_32_LU:
5668 temp64 = tcg_temp_new_i64();
5669 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5670 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5671 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5672 tcg_temp_free_i64(temp64);
5673 break;
5674 case OPC2_32_RR1_MUL_H_32_UL:
5675 temp64 = tcg_temp_new_i64();
5676 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5677 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5678 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5679 tcg_temp_free_i64(temp64);
5680 break;
5681 case OPC2_32_RR1_MUL_H_32_UU:
5682 temp64 = tcg_temp_new_i64();
5683 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5684 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5685 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5686 tcg_temp_free_i64(temp64);
5687 break;
5688 case OPC2_32_RR1_MULM_H_64_LL:
5689 temp64 = tcg_temp_new_i64();
5690 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5691 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5692 /* reset V bit */
5693 tcg_gen_movi_tl(cpu_PSW_V, 0);
5694 /* reset AV bit */
5695 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5696 tcg_temp_free_i64(temp64);
5697 break;
5698 case OPC2_32_RR1_MULM_H_64_LU:
5699 temp64 = tcg_temp_new_i64();
5700 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5701 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5702 /* reset V bit */
5703 tcg_gen_movi_tl(cpu_PSW_V, 0);
5704 /* reset AV bit */
5705 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5706 tcg_temp_free_i64(temp64);
5707 break;
5708 case OPC2_32_RR1_MULM_H_64_UL:
5709 temp64 = tcg_temp_new_i64();
5710 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5711 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5712 /* reset V bit */
5713 tcg_gen_movi_tl(cpu_PSW_V, 0);
5714 /* reset AV bit */
5715 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5716 tcg_temp_free_i64(temp64);
5717 break;
5718 case OPC2_32_RR1_MULM_H_64_UU:
5719 temp64 = tcg_temp_new_i64();
5720 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5721 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5722 /* reset V bit */
5723 tcg_gen_movi_tl(cpu_PSW_V, 0);
5724 /* reset AV bit */
5725 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5726 tcg_temp_free_i64(temp64);
5727
5728 break;
5729 case OPC2_32_RR1_MULR_H_16_LL:
5730 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5731 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5732 break;
5733 case OPC2_32_RR1_MULR_H_16_LU:
5734 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5735 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5736 break;
5737 case OPC2_32_RR1_MULR_H_16_UL:
5738 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5739 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5740 break;
5741 case OPC2_32_RR1_MULR_H_16_UU:
5742 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5743 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5744 break;
5745 }
5746 tcg_temp_free(n);
5747 }
5748
5749 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
5750 {
5751 uint32_t op2;
5752 int r1, r2, r3;
5753 uint32_t n;
5754
5755 TCGv temp, temp2;
5756
5757 r1 = MASK_OP_RR1_S1(ctx->opcode);
5758 r2 = MASK_OP_RR1_S2(ctx->opcode);
5759 r3 = MASK_OP_RR1_D(ctx->opcode);
5760 n = MASK_OP_RR1_N(ctx->opcode);
5761 op2 = MASK_OP_RR1_OP2(ctx->opcode);
5762
5763 temp = tcg_temp_new();
5764 temp2 = tcg_temp_new();
5765
5766 switch (op2) {
5767 case OPC2_32_RR1_MUL_Q_32:
5768 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
5769 break;
5770 case OPC2_32_RR1_MUL_Q_64:
5771 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
5772 n, 0);
5773 break;
5774 case OPC2_32_RR1_MUL_Q_32_L:
5775 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
5776 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
5777 break;
5778 case OPC2_32_RR1_MUL_Q_64_L:
5779 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
5780 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
5781 break;
5782 case OPC2_32_RR1_MUL_Q_32_U:
5783 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
5784 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
5785 break;
5786 case OPC2_32_RR1_MUL_Q_64_U:
5787 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
5788 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
5789 break;
5790 case OPC2_32_RR1_MUL_Q_32_LL:
5791 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
5792 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
5793 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
5794 break;
5795 case OPC2_32_RR1_MUL_Q_32_UU:
5796 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
5797 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
5798 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
5799 break;
5800 case OPC2_32_RR1_MULR_Q_32_L:
5801 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
5802 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
5803 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
5804 break;
5805 case OPC2_32_RR1_MULR_Q_32_U:
5806 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
5807 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
5808 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
5809 break;
5810 }
5811 tcg_temp_free(temp);
5812 tcg_temp_free(temp2);
5813 }
5814
5815 /* RR2 format */
5816 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
5817 {
5818 uint32_t op2;
5819 int r1, r2, r3;
5820
5821 op2 = MASK_OP_RR2_OP2(ctx->opcode);
5822 r1 = MASK_OP_RR2_S1(ctx->opcode);
5823 r2 = MASK_OP_RR2_S2(ctx->opcode);
5824 r3 = MASK_OP_RR2_D(ctx->opcode);
5825 switch (op2) {
5826 case OPC2_32_RR2_MUL_32:
5827 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5828 break;
5829 case OPC2_32_RR2_MUL_64:
5830 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5831 cpu_gpr_d[r2]);
5832 break;
5833 case OPC2_32_RR2_MULS_32:
5834 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5835 cpu_gpr_d[r2]);
5836 break;
5837 case OPC2_32_RR2_MUL_U_64:
5838 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5839 cpu_gpr_d[r2]);
5840 break;
5841 case OPC2_32_RR2_MULS_U_32:
5842 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5843 cpu_gpr_d[r2]);
5844 break;
5845 }
5846 }
5847
5848 /* RRPW format */
5849 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
5850 {
5851 uint32_t op2;
5852 int r1, r2, r3;
5853 int32_t pos, width;
5854
5855 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
5856 r1 = MASK_OP_RRPW_S1(ctx->opcode);
5857 r2 = MASK_OP_RRPW_S2(ctx->opcode);
5858 r3 = MASK_OP_RRPW_D(ctx->opcode);
5859 pos = MASK_OP_RRPW_POS(ctx->opcode);
5860 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
5861
5862 switch (op2) {
5863 case OPC2_32_RRPW_EXTR:
5864 if (pos + width <= 31) {
5865 /* optimize special cases */
5866 if ((pos == 0) && (width == 8)) {
5867 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5868 } else if ((pos == 0) && (width == 16)) {
5869 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5870 } else {
5871 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
5872 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
5873 }
5874 }
5875 break;
5876 case OPC2_32_RRPW_EXTR_U:
5877 if (width == 0) {
5878 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
5879 } else {
5880 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
5881 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
5882 }
5883 break;
5884 case OPC2_32_RRPW_IMASK:
5885 if (pos + width <= 31) {
5886 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
5887 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
5888 }
5889 break;
5890 case OPC2_32_RRPW_INSERT:
5891 if (pos + width <= 31) {
5892 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
5893 width, pos);
5894 }
5895 break;
5896 }
5897 }
5898
5899 /* RRR format */
5900 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5901 {
5902 uint32_t op2;
5903 int r1, r2, r3, r4;
5904 TCGv temp;
5905
5906 op2 = MASK_OP_RRR_OP2(ctx->opcode);
5907 r1 = MASK_OP_RRR_S1(ctx->opcode);
5908 r2 = MASK_OP_RRR_S2(ctx->opcode);
5909 r3 = MASK_OP_RRR_S3(ctx->opcode);
5910 r4 = MASK_OP_RRR_D(ctx->opcode);
5911
5912 switch (op2) {
5913 case OPC2_32_RRR_CADD:
5914 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
5915 cpu_gpr_d[r4], cpu_gpr_d[r3]);
5916 break;
5917 case OPC2_32_RRR_CADDN:
5918 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5919 cpu_gpr_d[r3]);
5920 break;
5921 case OPC2_32_RRR_CSUB:
5922 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5923 cpu_gpr_d[r3]);
5924 break;
5925 case OPC2_32_RRR_CSUBN:
5926 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5927 cpu_gpr_d[r3]);
5928 break;
5929 case OPC2_32_RRR_SEL:
5930 temp = tcg_const_i32(0);
5931 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5932 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5933 tcg_temp_free(temp);
5934 break;
5935 case OPC2_32_RRR_SELN:
5936 temp = tcg_const_i32(0);
5937 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5938 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5939 tcg_temp_free(temp);
5940 break;
5941 }
5942 }
5943
5944 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
5945 {
5946 uint32_t op2;
5947
5948 int r1, r2, r3, r4;
5949
5950 op2 = MASK_OP_RRR_OP2(ctx->opcode);
5951 r1 = MASK_OP_RRR_S1(ctx->opcode);
5952 r2 = MASK_OP_RRR_S2(ctx->opcode);
5953 r3 = MASK_OP_RRR_S3(ctx->opcode);
5954 r4 = MASK_OP_RRR_D(ctx->opcode);
5955
5956 switch (op2) {
5957 case OPC2_32_RRR_DVADJ:
5958 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5959 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5960 break;
5961 case OPC2_32_RRR_DVSTEP:
5962 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5963 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5964 break;
5965 case OPC2_32_RRR_DVSTEP_U:
5966 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5967 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5968 break;
5969 case OPC2_32_RRR_IXMAX:
5970 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5971 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5972 break;
5973 case OPC2_32_RRR_IXMAX_U:
5974 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5975 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5976 break;
5977 case OPC2_32_RRR_IXMIN:
5978 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5979 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5980 break;
5981 case OPC2_32_RRR_IXMIN_U:
5982 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5983 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5984 break;
5985 case OPC2_32_RRR_PACK:
5986 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
5987 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5988 break;
5989 }
5990 }
5991
5992 /* RRR2 format */
5993 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
5994 {
5995 uint32_t op2;
5996 uint32_t r1, r2, r3, r4;
5997
5998 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
5999 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6000 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6001 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6002 r4 = MASK_OP_RRR2_D(ctx->opcode);
6003 switch (op2) {
6004 case OPC2_32_RRR2_MADD_32:
6005 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6006 cpu_gpr_d[r2]);
6007 break;
6008 case OPC2_32_RRR2_MADD_64:
6009 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6010 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6011 break;
6012 case OPC2_32_RRR2_MADDS_32:
6013 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6014 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6015 break;
6016 case OPC2_32_RRR2_MADDS_64:
6017 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6018 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6019 break;
6020 case OPC2_32_RRR2_MADD_U_64:
6021 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6022 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6023 break;
6024 case OPC2_32_RRR2_MADDS_U_32:
6025 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6026 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6027 break;
6028 case OPC2_32_RRR2_MADDS_U_64:
6029 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6030 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6031 break;
6032 }
6033 }
6034
6035 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
6036 {
6037 uint32_t op2;
6038 uint32_t r1, r2, r3, r4;
6039
6040 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6041 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6042 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6043 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6044 r4 = MASK_OP_RRR2_D(ctx->opcode);
6045
6046 switch (op2) {
6047 case OPC2_32_RRR2_MSUB_32:
6048 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6049 cpu_gpr_d[r2]);
6050 break;
6051 case OPC2_32_RRR2_MSUB_64:
6052 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6053 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6054 break;
6055 case OPC2_32_RRR2_MSUBS_32:
6056 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6057 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6058 break;
6059 case OPC2_32_RRR2_MSUBS_64:
6060 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6061 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6062 break;
6063 case OPC2_32_RRR2_MSUB_U_64:
6064 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6065 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6066 break;
6067 case OPC2_32_RRR2_MSUBS_U_32:
6068 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6069 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6070 break;
6071 case OPC2_32_RRR2_MSUBS_U_64:
6072 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6073 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6074 break;
6075 }
6076 }
6077
6078 /* RRR1 format */
6079 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
6080 {
6081 uint32_t op2;
6082 uint32_t r1, r2, r3, r4, n;
6083
6084 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6085 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6086 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6087 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6088 r4 = MASK_OP_RRR1_D(ctx->opcode);
6089 n = MASK_OP_RRR1_N(ctx->opcode);
6090
6091 switch (op2) {
6092 case OPC2_32_RRR1_MADD_H_LL:
6093 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6094 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6095 break;
6096 case OPC2_32_RRR1_MADD_H_LU:
6097 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6098 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6099 break;
6100 case OPC2_32_RRR1_MADD_H_UL:
6101 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6102 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6103 break;
6104 case OPC2_32_RRR1_MADD_H_UU:
6105 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6106 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6107 break;
6108 case OPC2_32_RRR1_MADDS_H_LL:
6109 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6110 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6111 break;
6112 case OPC2_32_RRR1_MADDS_H_LU:
6113 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6114 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6115 break;
6116 case OPC2_32_RRR1_MADDS_H_UL:
6117 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6118 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6119 break;
6120 case OPC2_32_RRR1_MADDS_H_UU:
6121 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6122 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6123 break;
6124 case OPC2_32_RRR1_MADDM_H_LL:
6125 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6126 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6127 break;
6128 case OPC2_32_RRR1_MADDM_H_LU:
6129 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6130 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6131 break;
6132 case OPC2_32_RRR1_MADDM_H_UL:
6133 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6134 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6135 break;
6136 case OPC2_32_RRR1_MADDM_H_UU:
6137 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6138 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6139 break;
6140 case OPC2_32_RRR1_MADDMS_H_LL:
6141 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6142 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6143 break;
6144 case OPC2_32_RRR1_MADDMS_H_LU:
6145 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6146 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6147 break;
6148 case OPC2_32_RRR1_MADDMS_H_UL:
6149 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6150 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6151 break;
6152 case OPC2_32_RRR1_MADDMS_H_UU:
6153 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6154 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6155 break;
6156 case OPC2_32_RRR1_MADDR_H_LL:
6157 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6158 cpu_gpr_d[r2], n, MODE_LL);
6159 break;
6160 case OPC2_32_RRR1_MADDR_H_LU:
6161 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6162 cpu_gpr_d[r2], n, MODE_LU);
6163 break;
6164 case OPC2_32_RRR1_MADDR_H_UL:
6165 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6166 cpu_gpr_d[r2], n, MODE_UL);
6167 break;
6168 case OPC2_32_RRR1_MADDR_H_UU:
6169 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6170 cpu_gpr_d[r2], n, MODE_UU);
6171 break;
6172 case OPC2_32_RRR1_MADDRS_H_LL:
6173 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6174 cpu_gpr_d[r2], n, MODE_LL);
6175 break;
6176 case OPC2_32_RRR1_MADDRS_H_LU:
6177 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6178 cpu_gpr_d[r2], n, MODE_LU);
6179 break;
6180 case OPC2_32_RRR1_MADDRS_H_UL:
6181 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6182 cpu_gpr_d[r2], n, MODE_UL);
6183 break;
6184 case OPC2_32_RRR1_MADDRS_H_UU:
6185 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6186 cpu_gpr_d[r2], n, MODE_UU);
6187 break;
6188 }
6189 }
6190
6191 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
6192 {
6193 uint32_t op2;
6194 uint32_t r1, r2, r3, r4, n;
6195 TCGv temp, temp2;
6196
6197 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6198 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6199 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6200 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6201 r4 = MASK_OP_RRR1_D(ctx->opcode);
6202 n = MASK_OP_RRR1_N(ctx->opcode);
6203
6204 temp = tcg_const_i32(n);
6205 temp2 = tcg_temp_new();
6206
6207 switch (op2) {
6208 case OPC2_32_RRR1_MADD_Q_32:
6209 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6210 cpu_gpr_d[r2], n, 32, env);
6211 break;
6212 case OPC2_32_RRR1_MADD_Q_64:
6213 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6214 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6215 n, env);
6216 break;
6217 case OPC2_32_RRR1_MADD_Q_32_L:
6218 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6219 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6220 temp, n, 16, env);
6221 break;
6222 case OPC2_32_RRR1_MADD_Q_64_L:
6223 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6224 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6225 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6226 n, env);
6227 break;
6228 case OPC2_32_RRR1_MADD_Q_32_U:
6229 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6230 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6231 temp, n, 16, env);
6232 break;
6233 case OPC2_32_RRR1_MADD_Q_64_U:
6234 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6235 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6236 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6237 n, env);
6238 break;
6239 case OPC2_32_RRR1_MADD_Q_32_LL:
6240 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6241 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6242 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6243 break;
6244 case OPC2_32_RRR1_MADD_Q_64_LL:
6245 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6246 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6247 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6248 cpu_gpr_d[r3+1], temp, temp2, n);
6249 break;
6250 case OPC2_32_RRR1_MADD_Q_32_UU:
6251 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6252 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6253 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6254 break;
6255 case OPC2_32_RRR1_MADD_Q_64_UU:
6256 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6257 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6258 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6259 cpu_gpr_d[r3+1], temp, temp2, n);
6260 break;
6261 case OPC2_32_RRR1_MADDS_Q_32:
6262 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6263 cpu_gpr_d[r2], n, 32);
6264 break;
6265 case OPC2_32_RRR1_MADDS_Q_64:
6266 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6267 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6268 n);
6269 break;
6270 case OPC2_32_RRR1_MADDS_Q_32_L:
6271 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6272 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6273 temp, n, 16);
6274 break;
6275 case OPC2_32_RRR1_MADDS_Q_64_L:
6276 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6277 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6278 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6279 n);
6280 break;
6281 case OPC2_32_RRR1_MADDS_Q_32_U:
6282 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6283 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6284 temp, n, 16);
6285 break;
6286 case OPC2_32_RRR1_MADDS_Q_64_U:
6287 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6288 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6289 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6290 n);
6291 break;
6292 case OPC2_32_RRR1_MADDS_Q_32_LL:
6293 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6294 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6295 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6296 break;
6297 case OPC2_32_RRR1_MADDS_Q_64_LL:
6298 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6299 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6300 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6301 cpu_gpr_d[r3+1], temp, temp2, n);
6302 break;
6303 case OPC2_32_RRR1_MADDS_Q_32_UU:
6304 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6305 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6306 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6307 break;
6308 case OPC2_32_RRR1_MADDS_Q_64_UU:
6309 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6310 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6311 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6312 cpu_gpr_d[r3+1], temp, temp2, n);
6313 break;
6314 case OPC2_32_RRR1_MADDR_H_64_UL:
6315 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6316 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
6317 break;
6318 case OPC2_32_RRR1_MADDRS_H_64_UL:
6319 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6320 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
6321 break;
6322 case OPC2_32_RRR1_MADDR_Q_32_LL:
6323 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6324 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6325 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6326 break;
6327 case OPC2_32_RRR1_MADDR_Q_32_UU:
6328 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6329 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6330 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6331 break;
6332 case OPC2_32_RRR1_MADDRS_Q_32_LL:
6333 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6334 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6335 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6336 break;
6337 case OPC2_32_RRR1_MADDRS_Q_32_UU:
6338 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6339 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6340 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6341 break;
6342 }
6343 tcg_temp_free(temp);
6344 tcg_temp_free(temp2);
6345 }
6346
6347 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
6348 {
6349 uint32_t op2;
6350 uint32_t r1, r2, r3, r4, n;
6351
6352 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6353 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6354 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6355 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6356 r4 = MASK_OP_RRR1_D(ctx->opcode);
6357 n = MASK_OP_RRR1_N(ctx->opcode);
6358
6359 switch (op2) {
6360 case OPC2_32_RRR1_MADDSU_H_32_LL:
6361 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6362 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6363 break;
6364 case OPC2_32_RRR1_MADDSU_H_32_LU:
6365 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6366 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6367 break;
6368 case OPC2_32_RRR1_MADDSU_H_32_UL:
6369 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6370 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6371 break;
6372 case OPC2_32_RRR1_MADDSU_H_32_UU:
6373 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6374 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6375 break;
6376 case OPC2_32_RRR1_MADDSUS_H_32_LL:
6377 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6378 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6379 n, MODE_LL);
6380 break;
6381 case OPC2_32_RRR1_MADDSUS_H_32_LU:
6382 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6383 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6384 n, MODE_LU);
6385 break;
6386 case OPC2_32_RRR1_MADDSUS_H_32_UL:
6387 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6388 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6389 n, MODE_UL);
6390 break;
6391 case OPC2_32_RRR1_MADDSUS_H_32_UU:
6392 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6393 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6394 n, MODE_UU);
6395 break;
6396 case OPC2_32_RRR1_MADDSUM_H_64_LL:
6397 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6398 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6399 n, MODE_LL);
6400 break;
6401 case OPC2_32_RRR1_MADDSUM_H_64_LU:
6402 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6403 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6404 n, MODE_LU);
6405 break;
6406 case OPC2_32_RRR1_MADDSUM_H_64_UL:
6407 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6408 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6409 n, MODE_UL);
6410 break;
6411 case OPC2_32_RRR1_MADDSUM_H_64_UU:
6412 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6413 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6414 n, MODE_UU);
6415 break;
6416 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
6417 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6418 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6419 n, MODE_LL);
6420 break;
6421 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
6422 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6423 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6424 n, MODE_LU);
6425 break;
6426 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
6427 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6428 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6429 n, MODE_UL);
6430 break;
6431 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
6432 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6433 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6434 n, MODE_UU);
6435 break;
6436 case OPC2_32_RRR1_MADDSUR_H_16_LL:
6437 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6438 cpu_gpr_d[r2], n, MODE_LL);
6439 break;
6440 case OPC2_32_RRR1_MADDSUR_H_16_LU:
6441 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6442 cpu_gpr_d[r2], n, MODE_LU);
6443 break;
6444 case OPC2_32_RRR1_MADDSUR_H_16_UL:
6445 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6446 cpu_gpr_d[r2], n, MODE_UL);
6447 break;
6448 case OPC2_32_RRR1_MADDSUR_H_16_UU:
6449 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6450 cpu_gpr_d[r2], n, MODE_UU);
6451 break;
6452 case OPC2_32_RRR1_MADDSURS_H_16_LL:
6453 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6454 cpu_gpr_d[r2], n, MODE_LL);
6455 break;
6456 case OPC2_32_RRR1_MADDSURS_H_16_LU:
6457 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6458 cpu_gpr_d[r2], n, MODE_LU);
6459 break;
6460 case OPC2_32_RRR1_MADDSURS_H_16_UL:
6461 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6462 cpu_gpr_d[r2], n, MODE_UL);
6463 break;
6464 case OPC2_32_RRR1_MADDSURS_H_16_UU:
6465 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6466 cpu_gpr_d[r2], n, MODE_UU);
6467 break;
6468 }
6469 }
6470
6471 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
6472 {
6473 int op1;
6474 int32_t r1, r2, r3;
6475 int32_t address, const16;
6476 int8_t b, const4;
6477 int32_t bpos;
6478 TCGv temp, temp2, temp3;
6479
6480 op1 = MASK_OP_MAJOR(ctx->opcode);
6481
6482 /* handle JNZ.T opcode only being 7 bit long */
6483 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
6484 op1 = OPCM_32_BRN_JTT;
6485 }
6486
6487 switch (op1) {
6488 /* ABS-format */
6489 case OPCM_32_ABS_LDW:
6490 decode_abs_ldw(env, ctx);
6491 break;
6492 case OPCM_32_ABS_LDB:
6493 decode_abs_ldb(env, ctx);
6494 break;
6495 case OPCM_32_ABS_LDMST_SWAP:
6496 decode_abs_ldst_swap(env, ctx);
6497 break;
6498 case OPCM_32_ABS_LDST_CONTEXT:
6499 decode_abs_ldst_context(env, ctx);
6500 break;
6501 case OPCM_32_ABS_STORE:
6502 decode_abs_store(env, ctx);
6503 break;
6504 case OPCM_32_ABS_STOREB_H:
6505 decode_abs_storeb_h(env, ctx);
6506 break;
6507 case OPC1_32_ABS_STOREQ:
6508 address = MASK_OP_ABS_OFF18(ctx->opcode);
6509 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6510 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6511 temp2 = tcg_temp_new();
6512
6513 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
6514 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
6515
6516 tcg_temp_free(temp2);
6517 tcg_temp_free(temp);
6518 break;
6519 case OPC1_32_ABS_LD_Q:
6520 address = MASK_OP_ABS_OFF18(ctx->opcode);
6521 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6522 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6523
6524 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
6525 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
6526
6527 tcg_temp_free(temp);
6528 break;
6529 case OPC1_32_ABS_LEA:
6530 address = MASK_OP_ABS_OFF18(ctx->opcode);
6531 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6532 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
6533 break;
6534 /* ABSB-format */
6535 case OPC1_32_ABSB_ST_T:
6536 address = MASK_OP_ABS_OFF18(ctx->opcode);
6537 b = MASK_OP_ABSB_B(ctx->opcode);
6538 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
6539
6540 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6541 temp2 = tcg_temp_new();
6542
6543 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
6544 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
6545 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
6546 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
6547
6548 tcg_temp_free(temp);
6549 tcg_temp_free(temp2);
6550 break;
6551 /* B-format */
6552 case OPC1_32_B_CALL:
6553 case OPC1_32_B_CALLA:
6554 case OPC1_32_B_J:
6555 case OPC1_32_B_JA:
6556 case OPC1_32_B_JL:
6557 case OPC1_32_B_JLA:
6558 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
6559 gen_compute_branch(ctx, op1, 0, 0, 0, address);
6560 break;
6561 /* Bit-format */
6562 case OPCM_32_BIT_ANDACC:
6563 decode_bit_andacc(env, ctx);
6564 break;
6565 case OPCM_32_BIT_LOGICAL_T1:
6566 decode_bit_logical_t(env, ctx);
6567 break;
6568 case OPCM_32_BIT_INSERT:
6569 decode_bit_insert(env, ctx);
6570 break;
6571 case OPCM_32_BIT_LOGICAL_T2:
6572 decode_bit_logical_t2(env, ctx);
6573 break;
6574 case OPCM_32_BIT_ORAND:
6575 decode_bit_orand(env, ctx);
6576 break;
6577 case OPCM_32_BIT_SH_LOGIC1:
6578 decode_bit_sh_logic1(env, ctx);
6579 break;
6580 case OPCM_32_BIT_SH_LOGIC2:
6581 decode_bit_sh_logic2(env, ctx);
6582 break;
6583 /* BO Format */
6584 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
6585 decode_bo_addrmode_post_pre_base(env, ctx);
6586 break;
6587 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
6588 decode_bo_addrmode_bitreverse_circular(env, ctx);
6589 break;
6590 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
6591 decode_bo_addrmode_ld_post_pre_base(env, ctx);
6592 break;
6593 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
6594 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
6595 break;
6596 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
6597 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
6598 break;
6599 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
6600 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
6601 break;
6602 /* BOL-format */
6603 case OPC1_32_BOL_LD_A_LONGOFF:
6604 case OPC1_32_BOL_LD_W_LONGOFF:
6605 case OPC1_32_BOL_LEA_LONGOFF:
6606 case OPC1_32_BOL_ST_W_LONGOFF:
6607 case OPC1_32_BOL_ST_A_LONGOFF:
6608 case OPC1_32_BOL_LD_B_LONGOFF:
6609 case OPC1_32_BOL_LD_BU_LONGOFF:
6610 case OPC1_32_BOL_LD_H_LONGOFF:
6611 case OPC1_32_BOL_LD_HU_LONGOFF:
6612 case OPC1_32_BOL_ST_B_LONGOFF:
6613 case OPC1_32_BOL_ST_H_LONGOFF:
6614 decode_bol_opc(env, ctx, op1);
6615 break;
6616 /* BRC Format */
6617 case OPCM_32_BRC_EQ_NEQ:
6618 case OPCM_32_BRC_GE:
6619 case OPCM_32_BRC_JLT:
6620 case OPCM_32_BRC_JNE:
6621 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
6622 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
6623 r1 = MASK_OP_BRC_S1(ctx->opcode);
6624 gen_compute_branch(ctx, op1, r1, 0, const4, address);
6625 break;
6626 /* BRN Format */
6627 case OPCM_32_BRN_JTT:
6628 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
6629 r1 = MASK_OP_BRN_S1(ctx->opcode);
6630 gen_compute_branch(ctx, op1, r1, 0, 0, address);
6631 break;
6632 /* BRR Format */
6633 case OPCM_32_BRR_EQ_NEQ:
6634 case OPCM_32_BRR_ADDR_EQ_NEQ:
6635 case OPCM_32_BRR_GE:
6636 case OPCM_32_BRR_JLT:
6637 case OPCM_32_BRR_JNE:
6638 case OPCM_32_BRR_JNZ:
6639 case OPCM_32_BRR_LOOP:
6640 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
6641 r2 = MASK_OP_BRR_S2(ctx->opcode);
6642 r1 = MASK_OP_BRR_S1(ctx->opcode);
6643 gen_compute_branch(ctx, op1, r1, r2, 0, address);
6644 break;
6645 /* RC Format */
6646 case OPCM_32_RC_LOGICAL_SHIFT:
6647 decode_rc_logical_shift(env, ctx);
6648 break;
6649 case OPCM_32_RC_ACCUMULATOR:
6650 decode_rc_accumulator(env, ctx);
6651 break;
6652 case OPCM_32_RC_SERVICEROUTINE:
6653 decode_rc_serviceroutine(env, ctx);
6654 break;
6655 case OPCM_32_RC_MUL:
6656 decode_rc_mul(env, ctx);
6657 break;
6658 /* RCPW Format */
6659 case OPCM_32_RCPW_MASK_INSERT:
6660 decode_rcpw_insert(env, ctx);
6661 break;
6662 /* RCRR Format */
6663 case OPC1_32_RCRR_INSERT:
6664 r1 = MASK_OP_RCRR_S1(ctx->opcode);
6665 r2 = MASK_OP_RCRR_S3(ctx->opcode);
6666 r3 = MASK_OP_RCRR_D(ctx->opcode);
6667 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
6668 temp = tcg_const_i32(const16);
6669 temp2 = tcg_temp_new(); /* width*/
6670 temp3 = tcg_temp_new(); /* pos */
6671
6672 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
6673 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
6674
6675 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
6676
6677 tcg_temp_free(temp);
6678 tcg_temp_free(temp2);
6679 tcg_temp_free(temp3);
6680 break;
6681 /* RCRW Format */
6682 case OPCM_32_RCRW_MASK_INSERT:
6683 decode_rcrw_insert(env, ctx);
6684 break;
6685 /* RCR Format */
6686 case OPCM_32_RCR_COND_SELECT:
6687 decode_rcr_cond_select(env, ctx);
6688 break;
6689 case OPCM_32_RCR_MADD:
6690 decode_rcr_madd(env, ctx);
6691 break;
6692 case OPCM_32_RCR_MSUB:
6693 decode_rcr_msub(env, ctx);
6694 break;
6695 /* RLC Format */
6696 case OPC1_32_RLC_ADDI:
6697 case OPC1_32_RLC_ADDIH:
6698 case OPC1_32_RLC_ADDIH_A:
6699 case OPC1_32_RLC_MFCR:
6700 case OPC1_32_RLC_MOV:
6701 case OPC1_32_RLC_MOV_64:
6702 case OPC1_32_RLC_MOV_U:
6703 case OPC1_32_RLC_MOV_H:
6704 case OPC1_32_RLC_MOVH_A:
6705 case OPC1_32_RLC_MTCR:
6706 decode_rlc_opc(env, ctx, op1);
6707 break;
6708 /* RR Format */
6709 case OPCM_32_RR_ACCUMULATOR:
6710 decode_rr_accumulator(env, ctx);
6711 break;
6712 case OPCM_32_RR_LOGICAL_SHIFT:
6713 decode_rr_logical_shift(env, ctx);
6714 break;
6715 case OPCM_32_RR_ADDRESS:
6716 decode_rr_address(env, ctx);
6717 break;
6718 case OPCM_32_RR_IDIRECT:
6719 decode_rr_idirect(env, ctx);
6720 break;
6721 case OPCM_32_RR_DIVIDE:
6722 decode_rr_divide(env, ctx);
6723 break;
6724 /* RR1 Format */
6725 case OPCM_32_RR1_MUL:
6726 decode_rr1_mul(env, ctx);
6727 break;
6728 case OPCM_32_RR1_MULQ:
6729 decode_rr1_mulq(env, ctx);
6730 break;
6731 /* RR2 format */
6732 case OPCM_32_RR2_MUL:
6733 decode_rr2_mul(env, ctx);
6734 break;
6735 /* RRPW format */
6736 case OPCM_32_RRPW_EXTRACT_INSERT:
6737 decode_rrpw_extract_insert(env, ctx);
6738 break;
6739 case OPC1_32_RRPW_DEXTR:
6740 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6741 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6742 r3 = MASK_OP_RRPW_D(ctx->opcode);
6743 const16 = MASK_OP_RRPW_POS(ctx->opcode);
6744 if (r1 == r2) {
6745 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
6746 } else {
6747 temp = tcg_temp_new();
6748 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
6749 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
6750 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
6751 tcg_temp_free(temp);
6752 }
6753 break;
6754 /* RRR Format */
6755 case OPCM_32_RRR_COND_SELECT:
6756 decode_rrr_cond_select(env, ctx);
6757 break;
6758 case OPCM_32_RRR_DIVIDE:
6759 decode_rrr_divide(env, ctx);
6760 /* RRR2 Format */
6761 case OPCM_32_RRR2_MADD:
6762 decode_rrr2_madd(env, ctx);
6763 break;
6764 case OPCM_32_RRR2_MSUB:
6765 decode_rrr2_msub(env, ctx);
6766 break;
6767 /* RRR1 format */
6768 case OPCM_32_RRR1_MADD:
6769 decode_rrr1_madd(env, ctx);
6770 break;
6771 case OPCM_32_RRR1_MADDQ_H:
6772 decode_rrr1_maddq_h(env, ctx);
6773 break;
6774 case OPCM_32_RRR1_MADDSU_H:
6775 decode_rrr1_maddsu_h(env, ctx);
6776 break;
6777 }
6778 }
6779
6780 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
6781 {
6782 /* 16-Bit Instruction */
6783 if ((ctx->opcode & 0x1) == 0) {
6784 ctx->next_pc = ctx->pc + 2;
6785 decode_16Bit_opc(env, ctx);
6786 /* 32-Bit Instruction */
6787 } else {
6788 ctx->next_pc = ctx->pc + 4;
6789 decode_32Bit_opc(env, ctx);
6790 }
6791 }
6792
6793 static inline void
6794 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
6795 int search_pc)
6796 {
6797 CPUState *cs = CPU(cpu);
6798 CPUTriCoreState *env = &cpu->env;
6799 DisasContext ctx;
6800 target_ulong pc_start;
6801 int num_insns;
6802
6803 if (search_pc) {
6804 qemu_log("search pc %d\n", search_pc);
6805 }
6806
6807 num_insns = 0;
6808 pc_start = tb->pc;
6809 ctx.pc = pc_start;
6810 ctx.saved_pc = -1;
6811 ctx.tb = tb;
6812 ctx.singlestep_enabled = cs->singlestep_enabled;
6813 ctx.bstate = BS_NONE;
6814 ctx.mem_idx = cpu_mmu_index(env);
6815
6816 tcg_clear_temp_count();
6817 gen_tb_start(tb);
6818 while (ctx.bstate == BS_NONE) {
6819 ctx.opcode = cpu_ldl_code(env, ctx.pc);
6820 decode_opc(env, &ctx, 0);
6821
6822 num_insns++;
6823
6824 if (tcg_op_buf_full()) {
6825 gen_save_pc(ctx.next_pc);
6826 tcg_gen_exit_tb(0);
6827 break;
6828 }
6829 if (singlestep) {
6830 gen_save_pc(ctx.next_pc);
6831 tcg_gen_exit_tb(0);
6832 break;
6833 }
6834 ctx.pc = ctx.next_pc;
6835 }
6836
6837 gen_tb_end(tb, num_insns);
6838 if (search_pc) {
6839 printf("done_generating search pc\n");
6840 } else {
6841 tb->size = ctx.pc - pc_start;
6842 tb->icount = num_insns;
6843 }
6844 if (tcg_check_temp_count()) {
6845 printf("LEAK at %08x\n", env->PC);
6846 }
6847
6848 #ifdef DEBUG_DISAS
6849 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
6850 qemu_log("IN: %s\n", lookup_symbol(pc_start));
6851 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
6852 qemu_log("\n");
6853 }
6854 #endif
6855 }
6856
6857 void
6858 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
6859 {
6860 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
6861 }
6862
6863 void
6864 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
6865 {
6866 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
6867 }
6868
6869 void
6870 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
6871 {
6872 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
6873 }
6874 /*
6875 *
6876 * Initialization
6877 *
6878 */
6879
6880 void cpu_state_reset(CPUTriCoreState *env)
6881 {
6882 /* Reset Regs to Default Value */
6883 env->PSW = 0xb80;
6884 }
6885
6886 static void tricore_tcg_init_csfr(void)
6887 {
6888 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
6889 offsetof(CPUTriCoreState, PCXI), "PCXI");
6890 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
6891 offsetof(CPUTriCoreState, PSW), "PSW");
6892 cpu_PC = tcg_global_mem_new(TCG_AREG0,
6893 offsetof(CPUTriCoreState, PC), "PC");
6894 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
6895 offsetof(CPUTriCoreState, ICR), "ICR");
6896 }
6897
6898 void tricore_tcg_init(void)
6899 {
6900 int i;
6901 static int inited;
6902 if (inited) {
6903 return;
6904 }
6905 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
6906 /* reg init */
6907 for (i = 0 ; i < 16 ; i++) {
6908 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
6909 offsetof(CPUTriCoreState, gpr_a[i]),
6910 regnames_a[i]);
6911 }
6912 for (i = 0 ; i < 16 ; i++) {
6913 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
6914 offsetof(CPUTriCoreState, gpr_d[i]),
6915 regnames_d[i]);
6916 }
6917 tricore_tcg_init_csfr();
6918 /* init PSW flag cache */
6919 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
6920 offsetof(CPUTriCoreState, PSW_USB_C),
6921 "PSW_C");
6922 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
6923 offsetof(CPUTriCoreState, PSW_USB_V),
6924 "PSW_V");
6925 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
6926 offsetof(CPUTriCoreState, PSW_USB_SV),
6927 "PSW_SV");
6928 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
6929 offsetof(CPUTriCoreState, PSW_USB_AV),
6930 "PSW_AV");
6931 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
6932 offsetof(CPUTriCoreState, PSW_USB_SAV),
6933 "PSW_SAV");
6934 }
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