2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
38 #include <sys/ucontext.h>
41 //#define DEBUG_SIGNAL
43 static void exception_action(CPUState
*cpu
)
45 #if defined(TARGET_I386)
46 X86CPU
*x86_cpu
= X86_CPU(cpu
);
47 CPUX86State
*env1
= &x86_cpu
->env
;
49 raise_exception_err(env1
, cpu
->exception_index
, env1
->error_code
);
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
58 static void cpu_exit_tb_from_sighandler(CPUState
*cpu
, void *puc
)
61 struct ucontext
*uc
= puc
;
62 #elif defined(__OpenBSD__)
63 struct sigcontext
*uc
= puc
;
66 /* XXX: use siglongjmp ? */
69 sigprocmask(SIG_SETMASK
, (sigset_t
*)&uc
->uc_sigmask
, NULL
);
71 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 #elif defined(__OpenBSD__)
74 sigprocmask(SIG_SETMASK
, &uc
->sc_mask
, NULL
);
77 cpu_loop_exit_noexc(cpu
);
80 /* 'pc' is the host PC at which the exception was raised. 'address' is
81 the effective address of the memory exception. 'is_write' is 1 if a
82 write caused the exception and otherwise 0'. 'old_set' is the
83 signal set which should be restored */
84 static inline int handle_cpu_signal(uintptr_t pc
, unsigned long address
,
85 int is_write
, sigset_t
*old_set
,
92 #if defined(DEBUG_SIGNAL)
93 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
94 pc
, address
, is_write
, *(unsigned long *)old_set
);
96 /* XXX: locking issue */
97 if (is_write
&& h2g_valid(address
)) {
98 switch (page_unprotect(h2g(address
), pc
)) {
100 /* Fault not caused by a page marked unwritable to protect
101 * cached translations, must be the guest binary's problem
105 /* Fault caused by protection of cached translation; TBs
106 * invalidated, so resume execution
110 /* Fault caused by protection of cached translation, and the
111 * currently executing TB was modified and must be exited
114 cpu_exit_tb_from_sighandler(current_cpu
, puc
);
115 g_assert_not_reached();
117 g_assert_not_reached();
121 /* Convert forcefully to guest address space, invalid addresses
122 are still valid segv ones */
123 address
= h2g_nocheck(address
);
126 cc
= CPU_GET_CLASS(cpu
);
127 /* see if it is an MMU fault */
128 g_assert(cc
->handle_mmu_fault
);
129 ret
= cc
->handle_mmu_fault(cpu
, address
, is_write
, MMU_USER_IDX
);
131 return 0; /* not an MMU fault */
134 return 1; /* the MMU fault was handled without causing real CPU fault */
136 /* now we have a real cpu fault */
137 cpu_restore_state(cpu
, pc
);
139 /* we restore the process signal mask as the sigreturn should
140 do it (XXX: use sigsetjmp) */
141 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
142 exception_action(cpu
);
144 /* never comes here */
148 #if defined(__i386__)
150 #if defined(__APPLE__)
151 #include <sys/ucontext.h>
153 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
154 #define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
155 #define ERROR_sig(context) ((context)->uc_mcontext->es.err)
156 #define MASK_sig(context) ((context)->uc_sigmask)
157 #elif defined(__NetBSD__)
158 #include <ucontext.h>
160 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
161 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
162 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
163 #define MASK_sig(context) ((context)->uc_sigmask)
164 #elif defined(__FreeBSD__) || defined(__DragonFly__)
165 #include <ucontext.h>
167 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
168 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
169 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
170 #define MASK_sig(context) ((context)->uc_sigmask)
171 #elif defined(__OpenBSD__)
172 #define EIP_sig(context) ((context)->sc_eip)
173 #define TRAP_sig(context) ((context)->sc_trapno)
174 #define ERROR_sig(context) ((context)->sc_err)
175 #define MASK_sig(context) ((context)->sc_mask)
177 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
178 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
179 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
180 #define MASK_sig(context) ((context)->uc_sigmask)
183 int cpu_signal_handler(int host_signum
, void *pinfo
,
186 siginfo_t
*info
= pinfo
;
187 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
188 ucontext_t
*uc
= puc
;
189 #elif defined(__OpenBSD__)
190 struct sigcontext
*uc
= puc
;
192 struct ucontext
*uc
= puc
;
201 #define REG_TRAPNO TRAPNO
204 trapno
= TRAP_sig(uc
);
205 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
207 (ERROR_sig(uc
) >> 1) & 1 : 0,
211 #elif defined(__x86_64__)
214 #define PC_sig(context) _UC_MACHINE_PC(context)
215 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
216 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
217 #define MASK_sig(context) ((context)->uc_sigmask)
218 #elif defined(__OpenBSD__)
219 #define PC_sig(context) ((context)->sc_rip)
220 #define TRAP_sig(context) ((context)->sc_trapno)
221 #define ERROR_sig(context) ((context)->sc_err)
222 #define MASK_sig(context) ((context)->sc_mask)
223 #elif defined(__FreeBSD__) || defined(__DragonFly__)
224 #include <ucontext.h>
226 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
227 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
228 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
229 #define MASK_sig(context) ((context)->uc_sigmask)
231 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
232 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
233 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
234 #define MASK_sig(context) ((context)->uc_sigmask)
237 int cpu_signal_handler(int host_signum
, void *pinfo
,
240 siginfo_t
*info
= pinfo
;
242 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
243 ucontext_t
*uc
= puc
;
244 #elif defined(__OpenBSD__)
245 struct sigcontext
*uc
= puc
;
247 struct ucontext
*uc
= puc
;
251 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
252 TRAP_sig(uc
) == 0xe ?
253 (ERROR_sig(uc
) >> 1) & 1 : 0,
257 #elif defined(_ARCH_PPC)
259 /***********************************************************************
260 * signal context platform-specific definitions
264 /* All Registers access - only for local access */
265 #define REG_sig(reg_name, context) \
266 ((context)->uc_mcontext.regs->reg_name)
267 /* Gpr Registers access */
268 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
269 /* Program counter */
270 #define IAR_sig(context) REG_sig(nip, context)
271 /* Machine State Register (Supervisor) */
272 #define MSR_sig(context) REG_sig(msr, context)
274 #define CTR_sig(context) REG_sig(ctr, context)
275 /* User's integer exception register */
276 #define XER_sig(context) REG_sig(xer, context)
278 #define LR_sig(context) REG_sig(link, context)
279 /* Condition register */
280 #define CR_sig(context) REG_sig(ccr, context)
282 /* Float Registers access */
283 #define FLOAT_sig(reg_num, context) \
284 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
285 #define FPSCR_sig(context) \
286 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
287 /* Exception Registers access */
288 #define DAR_sig(context) REG_sig(dar, context)
289 #define DSISR_sig(context) REG_sig(dsisr, context)
290 #define TRAP_sig(context) REG_sig(trap, context)
293 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
294 #include <ucontext.h>
295 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
296 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
297 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
298 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
299 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
300 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
301 /* Exception Registers access */
302 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
303 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
304 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
305 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
308 #include <sys/ucontext.h>
309 typedef struct ucontext SIGCONTEXT
;
310 /* All Registers access - only for local access */
311 #define REG_sig(reg_name, context) \
312 ((context)->uc_mcontext->ss.reg_name)
313 #define FLOATREG_sig(reg_name, context) \
314 ((context)->uc_mcontext->fs.reg_name)
315 #define EXCEPREG_sig(reg_name, context) \
316 ((context)->uc_mcontext->es.reg_name)
317 #define VECREG_sig(reg_name, context) \
318 ((context)->uc_mcontext->vs.reg_name)
319 /* Gpr Registers access */
320 #define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
321 /* Program counter */
322 #define IAR_sig(context) REG_sig(srr0, context)
323 /* Machine State Register (Supervisor) */
324 #define MSR_sig(context) REG_sig(srr1, context)
325 #define CTR_sig(context) REG_sig(ctr, context)
327 #define XER_sig(context) REG_sig(xer, context)
328 /* User's integer exception register */
329 #define LR_sig(context) REG_sig(lr, context)
330 /* Condition register */
331 #define CR_sig(context) REG_sig(cr, context)
332 /* Float Registers access */
333 #define FLOAT_sig(reg_num, context) \
334 FLOATREG_sig(fpregs[reg_num], context)
335 #define FPSCR_sig(context) \
336 ((double)FLOATREG_sig(fpscr, context))
337 /* Exception Registers access */
338 /* Fault registers for coredump */
339 #define DAR_sig(context) EXCEPREG_sig(dar, context)
340 #define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
341 /* number of powerpc exception taken */
342 #define TRAP_sig(context) EXCEPREG_sig(exception, context)
343 #endif /* __APPLE__ */
345 int cpu_signal_handler(int host_signum
, void *pinfo
,
348 siginfo_t
*info
= pinfo
;
349 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
350 ucontext_t
*uc
= puc
;
352 struct ucontext
*uc
= puc
;
361 if (DSISR_sig(uc
) & 0x00800000) {
365 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
369 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
370 is_write
, &uc
->uc_sigmask
, puc
);
373 #elif defined(__alpha__)
375 int cpu_signal_handler(int host_signum
, void *pinfo
,
378 siginfo_t
*info
= pinfo
;
379 struct ucontext
*uc
= puc
;
380 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
384 /* XXX: need kernel patch to get write flag faster */
385 switch (insn
>> 26) {
388 case 0x0f: /* stq_u */
395 case 0x2e: /* stl_c */
396 case 0x2f: /* stq_c */
400 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
401 is_write
, &uc
->uc_sigmask
, puc
);
403 #elif defined(__sparc__)
405 int cpu_signal_handler(int host_signum
, void *pinfo
,
408 siginfo_t
*info
= pinfo
;
411 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
412 uint32_t *regs
= (uint32_t *)(info
+ 1);
413 void *sigmask
= (regs
+ 20);
414 /* XXX: is there a standard glibc define ? */
415 unsigned long pc
= regs
[1];
418 struct sigcontext
*sc
= puc
;
419 unsigned long pc
= sc
->sigc_regs
.tpc
;
420 void *sigmask
= (void *)sc
->sigc_mask
;
421 #elif defined(__OpenBSD__)
422 struct sigcontext
*uc
= puc
;
423 unsigned long pc
= uc
->sc_pc
;
424 void *sigmask
= (void *)(long)uc
->sc_mask
;
425 #elif defined(__NetBSD__)
426 ucontext_t
*uc
= puc
;
427 unsigned long pc
= _UC_MACHINE_PC(uc
);
428 void *sigmask
= (void *)&uc
->uc_sigmask
;
432 /* XXX: need kernel patch to get write flag faster */
434 insn
= *(uint32_t *)pc
;
435 if ((insn
>> 30) == 3) {
436 switch ((insn
>> 19) & 0x3f) {
438 case 0x15: /* stba */
440 case 0x16: /* stha */
444 case 0x17: /* stda */
446 case 0x1e: /* stxa */
448 case 0x34: /* stfa */
449 case 0x27: /* stdf */
450 case 0x37: /* stdfa */
451 case 0x26: /* stqf */
452 case 0x36: /* stqfa */
453 case 0x25: /* stfsr */
454 case 0x3c: /* casa */
455 case 0x3e: /* casxa */
460 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
461 is_write
, sigmask
, NULL
);
464 #elif defined(__arm__)
466 #if defined(__NetBSD__)
467 #include <ucontext.h>
470 int cpu_signal_handler(int host_signum
, void *pinfo
,
473 siginfo_t
*info
= pinfo
;
474 #if defined(__NetBSD__)
475 ucontext_t
*uc
= puc
;
477 struct ucontext
*uc
= puc
;
482 #if defined(__NetBSD__)
483 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
484 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
485 pc
= uc
->uc_mcontext
.gregs
[R15
];
487 pc
= uc
->uc_mcontext
.arm_pc
;
490 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
491 * later processor; on v5 we will always report this as a read).
493 is_write
= extract32(uc
->uc_mcontext
.error_code
, 11, 1);
494 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
496 &uc
->uc_sigmask
, puc
);
499 #elif defined(__aarch64__)
501 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
503 siginfo_t
*info
= pinfo
;
504 struct ucontext
*uc
= puc
;
505 uintptr_t pc
= uc
->uc_mcontext
.pc
;
506 uint32_t insn
= *(uint32_t *)pc
;
509 /* XXX: need kernel patch to get write flag faster. */
510 is_write
= ( (insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
511 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
512 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
513 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
514 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
515 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
516 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
517 /* Ingore bits 10, 11 & 21, controlling indexing. */
518 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
519 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
520 /* Ignore bits 23 & 24, controlling indexing. */
521 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
523 return handle_cpu_signal(pc
, (uintptr_t)info
->si_addr
,
524 is_write
, &uc
->uc_sigmask
, puc
);
527 #elif defined(__mc68000)
529 int cpu_signal_handler(int host_signum
, void *pinfo
,
532 siginfo_t
*info
= pinfo
;
533 struct ucontext
*uc
= puc
;
537 pc
= uc
->uc_mcontext
.gregs
[16];
538 /* XXX: compute is_write */
540 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
542 &uc
->uc_sigmask
, puc
);
545 #elif defined(__ia64)
548 /* This ought to be in <bits/siginfo.h>... */
549 # define __ISR_VALID 1
552 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
554 siginfo_t
*info
= pinfo
;
555 struct ucontext
*uc
= puc
;
559 ip
= uc
->uc_mcontext
.sc_ip
;
560 switch (host_signum
) {
566 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
)) {
567 /* ISR.W (write-access) is bit 33: */
568 is_write
= (info
->si_isr
>> 33) & 1;
575 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
577 (sigset_t
*)&uc
->uc_sigmask
, puc
);
580 #elif defined(__s390__)
582 int cpu_signal_handler(int host_signum
, void *pinfo
,
585 siginfo_t
*info
= pinfo
;
586 struct ucontext
*uc
= puc
;
591 pc
= uc
->uc_mcontext
.psw
.addr
;
593 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
594 of the normal 2 arguments. The 3rd argument contains the "int_code"
595 from the hardware which does in fact contain the is_write value.
596 The rt signal handler, as far as I can tell, does not give this value
597 at all. Not that we could get to it from here even if it were. */
598 /* ??? This is not even close to complete, since it ignores all
599 of the read-modify-write instructions. */
600 pinsn
= (uint16_t *)pc
;
601 switch (pinsn
[0] >> 8) {
607 case 0xc4: /* RIL format insns */
608 switch (pinsn
[0] & 0xf) {
610 case 0xb: /* STGRL */
611 case 0x7: /* STHRL */
615 case 0xe3: /* RXY format insns */
616 switch (pinsn
[2] & 0xff) {
619 case 0x72: /* STCY */
620 case 0x70: /* STHY */
621 case 0x8e: /* STPQ */
622 case 0x3f: /* STRVH */
623 case 0x3e: /* STRV */
624 case 0x2f: /* STRVG */
629 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
630 is_write
, &uc
->uc_sigmask
, puc
);
633 #elif defined(__mips__)
635 int cpu_signal_handler(int host_signum
, void *pinfo
,
638 siginfo_t
*info
= pinfo
;
639 struct ucontext
*uc
= puc
;
640 greg_t pc
= uc
->uc_mcontext
.pc
;
643 /* XXX: compute is_write */
645 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
646 is_write
, &uc
->uc_sigmask
, puc
);
649 #elif defined(__hppa__)
651 int cpu_signal_handler(int host_signum
, void *pinfo
,
654 siginfo_t
*info
= pinfo
;
655 struct ucontext
*uc
= puc
;
656 unsigned long pc
= uc
->uc_mcontext
.sc_iaoq
[0];
657 uint32_t insn
= *(uint32_t *)pc
;
660 /* XXX: need kernel patch to get write flag faster. */
661 switch (insn
>> 26) {
665 case 0x1b: /* STWM */
669 case 0x09: /* CSTWX, FSTWX, FSTWS */
670 case 0x0b: /* CSTDX, FSTDX, FSTDS */
671 /* Distinguish from coprocessor load ... */
672 is_write
= (insn
>> 9) & 1;
676 switch ((insn
>> 6) & 15) {
680 case 0xe: /* STWAS */
681 case 0xc: /* STBYS */
687 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
688 is_write
, &uc
->uc_sigmask
, puc
);
693 #error host CPU specific signal handler needed