2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/core/split-irq.h"
13 #include "hw/sysbus.h"
15 #include "hw/ssi/ssi.h"
16 #include "hw/arm/boot.h"
17 #include "qemu/timer.h"
18 #include "hw/i2c/i2c.h"
20 #include "hw/boards.h"
22 #include "exec/address-spaces.h"
23 #include "sysemu/sysemu.h"
24 #include "hw/arm/armv7m.h"
25 #include "hw/char/pl011.h"
26 #include "hw/input/gamepad.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
29 #include "migration/vmstate.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
33 #include "qom/object.h"
43 #define BP_OLED_I2C 0x01
44 #define BP_OLED_SSI 0x02
45 #define BP_GAMEPAD 0x04
47 #define NUM_IRQ_LINES 64
49 typedef const struct {
59 } stellaris_board_info
;
61 /* System controller. */
63 #define TYPE_STELLARIS_SYS "stellaris-sys"
64 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state
, STELLARIS_SYS
)
67 SysBusDevice parent_obj
;
84 /* Properties (all read-only registers) */
96 static void ssys_update(ssys_state
*s
)
98 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
101 static uint32_t pllcfg_sandstorm
[16] = {
103 0x1ae0, /* 1.8432 Mhz */
105 0xd573, /* 2.4576 Mhz */
106 0x37a6, /* 3.57954 Mhz */
107 0x1ae2, /* 3.6864 Mhz */
109 0x98bc, /* 4.906 Mhz */
110 0x935b, /* 4.9152 Mhz */
112 0x4dee, /* 5.12 Mhz */
114 0x75db, /* 6.144 Mhz */
115 0x1ae6, /* 7.3728 Mhz */
117 0x585b /* 8.192 Mhz */
120 static uint32_t pllcfg_fury
[16] = {
122 0x1b20, /* 1.8432 Mhz */
124 0xf42b, /* 2.4576 Mhz */
125 0x37e3, /* 3.57954 Mhz */
126 0x1b21, /* 3.6864 Mhz */
128 0x98ee, /* 4.906 Mhz */
129 0xd5b4, /* 4.9152 Mhz */
131 0x4e27, /* 5.12 Mhz */
133 0xec1c, /* 6.144 Mhz */
134 0x1b23, /* 7.3728 Mhz */
136 0xb11c /* 8.192 Mhz */
139 #define DID0_VER_MASK 0x70000000
140 #define DID0_VER_0 0x00000000
141 #define DID0_VER_1 0x10000000
143 #define DID0_CLASS_MASK 0x00FF0000
144 #define DID0_CLASS_SANDSTORM 0x00000000
145 #define DID0_CLASS_FURY 0x00010000
147 static int ssys_board_class(const ssys_state
*s
)
149 uint32_t did0
= s
->did0
;
150 switch (did0
& DID0_VER_MASK
) {
152 return DID0_CLASS_SANDSTORM
;
154 switch (did0
& DID0_CLASS_MASK
) {
155 case DID0_CLASS_SANDSTORM
:
156 case DID0_CLASS_FURY
:
157 return did0
& DID0_CLASS_MASK
;
159 /* for unknown classes, fall through */
161 /* This can only happen if the hardwired constant did0 value
162 * in this board's stellaris_board_info struct is wrong.
164 g_assert_not_reached();
168 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
171 ssys_state
*s
= (ssys_state
*)opaque
;
174 case 0x000: /* DID0 */
176 case 0x004: /* DID1 */
178 case 0x008: /* DC0 */
180 case 0x010: /* DC1 */
182 case 0x014: /* DC2 */
184 case 0x018: /* DC3 */
186 case 0x01c: /* DC4 */
188 case 0x030: /* PBORCTL */
190 case 0x034: /* LDOPCTL */
192 case 0x040: /* SRCR0 */
194 case 0x044: /* SRCR1 */
196 case 0x048: /* SRCR2 */
198 case 0x050: /* RIS */
199 return s
->int_status
;
200 case 0x054: /* IMC */
202 case 0x058: /* MISC */
203 return s
->int_status
& s
->int_mask
;
204 case 0x05c: /* RESC */
206 case 0x060: /* RCC */
208 case 0x064: /* PLLCFG */
211 xtal
= (s
->rcc
>> 6) & 0xf;
212 switch (ssys_board_class(s
)) {
213 case DID0_CLASS_FURY
:
214 return pllcfg_fury
[xtal
];
215 case DID0_CLASS_SANDSTORM
:
216 return pllcfg_sandstorm
[xtal
];
218 g_assert_not_reached();
221 case 0x070: /* RCC2 */
223 case 0x100: /* RCGC0 */
225 case 0x104: /* RCGC1 */
227 case 0x108: /* RCGC2 */
229 case 0x110: /* SCGC0 */
231 case 0x114: /* SCGC1 */
233 case 0x118: /* SCGC2 */
235 case 0x120: /* DCGC0 */
237 case 0x124: /* DCGC1 */
239 case 0x128: /* DCGC2 */
241 case 0x150: /* CLKVCLR */
243 case 0x160: /* LDOARST */
245 case 0x1e0: /* USER0 */
247 case 0x1e4: /* USER1 */
250 qemu_log_mask(LOG_GUEST_ERROR
,
251 "SSYS: read at bad offset 0x%x\n", (int)offset
);
256 static bool ssys_use_rcc2(ssys_state
*s
)
258 return (s
->rcc2
>> 31) & 0x1;
262 * Calculate the system clock period. We only want to propagate
263 * this change to the rest of the system if we're not being called
264 * from migration post-load.
266 static void ssys_calculate_system_clock(ssys_state
*s
, bool propagate_clock
)
270 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
271 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
272 * frequency by X is the same as multiplying the period by X.
274 if (ssys_use_rcc2(s
)) {
275 period_ns
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
277 period_ns
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
279 clock_set_ns(s
->sysclk
, period_ns
);
280 if (propagate_clock
) {
281 clock_propagate(s
->sysclk
);
285 static void ssys_write(void *opaque
, hwaddr offset
,
286 uint64_t value
, unsigned size
)
288 ssys_state
*s
= (ssys_state
*)opaque
;
291 case 0x030: /* PBORCTL */
292 s
->pborctl
= value
& 0xffff;
294 case 0x034: /* LDOPCTL */
295 s
->ldopctl
= value
& 0x1f;
297 case 0x040: /* SRCR0 */
298 case 0x044: /* SRCR1 */
299 case 0x048: /* SRCR2 */
300 qemu_log_mask(LOG_UNIMP
, "Peripheral reset not implemented\n");
302 case 0x054: /* IMC */
303 s
->int_mask
= value
& 0x7f;
305 case 0x058: /* MISC */
306 s
->int_status
&= ~value
;
308 case 0x05c: /* RESC */
309 s
->resc
= value
& 0x3f;
311 case 0x060: /* RCC */
312 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
314 s
->int_status
|= (1 << 6);
317 ssys_calculate_system_clock(s
, true);
319 case 0x070: /* RCC2 */
320 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
324 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
326 s
->int_status
|= (1 << 6);
329 ssys_calculate_system_clock(s
, true);
331 case 0x100: /* RCGC0 */
334 case 0x104: /* RCGC1 */
337 case 0x108: /* RCGC2 */
340 case 0x110: /* SCGC0 */
343 case 0x114: /* SCGC1 */
346 case 0x118: /* SCGC2 */
349 case 0x120: /* DCGC0 */
352 case 0x124: /* DCGC1 */
355 case 0x128: /* DCGC2 */
358 case 0x150: /* CLKVCLR */
361 case 0x160: /* LDOARST */
365 qemu_log_mask(LOG_GUEST_ERROR
,
366 "SSYS: write at bad offset 0x%x\n", (int)offset
);
371 static const MemoryRegionOps ssys_ops
= {
374 .endianness
= DEVICE_NATIVE_ENDIAN
,
377 static void stellaris_sys_reset_enter(Object
*obj
, ResetType type
)
379 ssys_state
*s
= STELLARIS_SYS(obj
);
384 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
387 s
->rcc2
= 0x07802810;
394 static void stellaris_sys_reset_hold(Object
*obj
)
396 ssys_state
*s
= STELLARIS_SYS(obj
);
398 /* OK to propagate clocks from the hold phase */
399 ssys_calculate_system_clock(s
, true);
402 static void stellaris_sys_reset_exit(Object
*obj
)
406 static int stellaris_sys_post_load(void *opaque
, int version_id
)
408 ssys_state
*s
= opaque
;
410 ssys_calculate_system_clock(s
, false);
415 static const VMStateDescription vmstate_stellaris_sys
= {
416 .name
= "stellaris_sys",
418 .minimum_version_id
= 1,
419 .post_load
= stellaris_sys_post_load
,
420 .fields
= (VMStateField
[]) {
421 VMSTATE_UINT32(pborctl
, ssys_state
),
422 VMSTATE_UINT32(ldopctl
, ssys_state
),
423 VMSTATE_UINT32(int_mask
, ssys_state
),
424 VMSTATE_UINT32(int_status
, ssys_state
),
425 VMSTATE_UINT32(resc
, ssys_state
),
426 VMSTATE_UINT32(rcc
, ssys_state
),
427 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
428 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
429 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
430 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
431 VMSTATE_UINT32(clkvclr
, ssys_state
),
432 VMSTATE_UINT32(ldoarst
, ssys_state
),
433 /* No field for sysclk -- handled in post-load instead */
434 VMSTATE_END_OF_LIST()
438 static Property stellaris_sys_properties
[] = {
439 DEFINE_PROP_UINT32("user0", ssys_state
, user0
, 0),
440 DEFINE_PROP_UINT32("user1", ssys_state
, user1
, 0),
441 DEFINE_PROP_UINT32("did0", ssys_state
, did0
, 0),
442 DEFINE_PROP_UINT32("did1", ssys_state
, did1
, 0),
443 DEFINE_PROP_UINT32("dc0", ssys_state
, dc0
, 0),
444 DEFINE_PROP_UINT32("dc1", ssys_state
, dc1
, 0),
445 DEFINE_PROP_UINT32("dc2", ssys_state
, dc2
, 0),
446 DEFINE_PROP_UINT32("dc3", ssys_state
, dc3
, 0),
447 DEFINE_PROP_UINT32("dc4", ssys_state
, dc4
, 0),
448 DEFINE_PROP_END_OF_LIST()
451 static void stellaris_sys_instance_init(Object
*obj
)
453 ssys_state
*s
= STELLARIS_SYS(obj
);
454 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
456 memory_region_init_io(&s
->iomem
, obj
, &ssys_ops
, s
, "ssys", 0x00001000);
457 sysbus_init_mmio(sbd
, &s
->iomem
);
458 sysbus_init_irq(sbd
, &s
->irq
);
459 s
->sysclk
= qdev_init_clock_out(DEVICE(s
), "SYSCLK");
462 /* I2C controller. */
464 #define TYPE_STELLARIS_I2C "stellaris-i2c"
465 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state
, STELLARIS_I2C
)
467 struct stellaris_i2c_state
{
468 SysBusDevice parent_obj
;
482 #define STELLARIS_I2C_MCS_BUSY 0x01
483 #define STELLARIS_I2C_MCS_ERROR 0x02
484 #define STELLARIS_I2C_MCS_ADRACK 0x04
485 #define STELLARIS_I2C_MCS_DATACK 0x08
486 #define STELLARIS_I2C_MCS_ARBLST 0x10
487 #define STELLARIS_I2C_MCS_IDLE 0x20
488 #define STELLARIS_I2C_MCS_BUSBSY 0x40
490 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
493 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
499 /* We don't emulate timing, so the controller is never busy. */
500 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
503 case 0x0c: /* MTPR */
505 case 0x10: /* MIMR */
507 case 0x14: /* MRIS */
509 case 0x18: /* MMIS */
510 return s
->mris
& s
->mimr
;
514 qemu_log_mask(LOG_GUEST_ERROR
,
515 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset
);
520 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
524 level
= (s
->mris
& s
->mimr
) != 0;
525 qemu_set_irq(s
->irq
, level
);
528 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
529 uint64_t value
, unsigned size
)
531 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
535 s
->msa
= value
& 0xff;
538 if ((s
->mcr
& 0x10) == 0) {
539 /* Disabled. Do nothing. */
542 /* Grab the bus if this is starting a transfer. */
543 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
544 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
545 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
547 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
548 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
551 /* If we don't have the bus then indicate an error. */
552 if (!i2c_bus_busy(s
->bus
)
553 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
554 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
557 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
559 /* Transfer a byte. */
560 /* TODO: Handle errors. */
563 s
->mdr
= i2c_recv(s
->bus
);
566 i2c_send(s
->bus
, s
->mdr
);
568 /* Raise an interrupt. */
572 /* Finish transfer. */
573 i2c_end_transfer(s
->bus
);
574 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
578 s
->mdr
= value
& 0xff;
580 case 0x0c: /* MTPR */
581 s
->mtpr
= value
& 0xff;
583 case 0x10: /* MIMR */
586 case 0x1c: /* MICR */
591 qemu_log_mask(LOG_UNIMP
,
592 "stellaris_i2c: Loopback not implemented\n");
595 qemu_log_mask(LOG_UNIMP
,
596 "stellaris_i2c: Slave mode not implemented\n");
598 s
->mcr
= value
& 0x31;
601 qemu_log_mask(LOG_GUEST_ERROR
,
602 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset
);
604 stellaris_i2c_update(s
);
607 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
609 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
610 i2c_end_transfer(s
->bus
);
619 stellaris_i2c_update(s
);
622 static const MemoryRegionOps stellaris_i2c_ops
= {
623 .read
= stellaris_i2c_read
,
624 .write
= stellaris_i2c_write
,
625 .endianness
= DEVICE_NATIVE_ENDIAN
,
628 static const VMStateDescription vmstate_stellaris_i2c
= {
629 .name
= "stellaris_i2c",
631 .minimum_version_id
= 1,
632 .fields
= (VMStateField
[]) {
633 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
634 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
635 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
636 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
637 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
638 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
639 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
640 VMSTATE_END_OF_LIST()
644 static void stellaris_i2c_init(Object
*obj
)
646 DeviceState
*dev
= DEVICE(obj
);
647 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
648 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
651 sysbus_init_irq(sbd
, &s
->irq
);
652 bus
= i2c_init_bus(dev
, "i2c");
655 memory_region_init_io(&s
->iomem
, obj
, &stellaris_i2c_ops
, s
,
657 sysbus_init_mmio(sbd
, &s
->iomem
);
658 /* ??? For now we only implement the master interface. */
659 stellaris_i2c_reset(s
);
662 /* Analogue to Digital Converter. This is only partially implemented,
663 enough for applications that use a combined ADC and timer tick. */
665 #define STELLARIS_ADC_EM_CONTROLLER 0
666 #define STELLARIS_ADC_EM_COMP 1
667 #define STELLARIS_ADC_EM_EXTERNAL 4
668 #define STELLARIS_ADC_EM_TIMER 5
669 #define STELLARIS_ADC_EM_PWM0 6
670 #define STELLARIS_ADC_EM_PWM1 7
671 #define STELLARIS_ADC_EM_PWM2 8
673 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
674 #define STELLARIS_ADC_FIFO_FULL 0x1000
676 #define TYPE_STELLARIS_ADC "stellaris-adc"
677 typedef struct StellarisADCState StellarisADCState
;
678 DECLARE_INSTANCE_CHECKER(StellarisADCState
, STELLARIS_ADC
, TYPE_STELLARIS_ADC
)
680 struct StellarisADCState
{
681 SysBusDevice parent_obj
;
702 static uint32_t stellaris_adc_fifo_read(StellarisADCState
*s
, int n
)
706 tail
= s
->fifo
[n
].state
& 0xf;
707 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
710 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
711 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
712 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
713 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
715 return s
->fifo
[n
].data
[tail
];
718 static void stellaris_adc_fifo_write(StellarisADCState
*s
, int n
,
723 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
724 FIFO fir each sequencer. */
725 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
726 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
730 s
->fifo
[n
].data
[head
] = value
;
731 head
= (head
+ 1) & 0xf;
732 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
733 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
734 if ((s
->fifo
[n
].state
& 0xf) == head
)
735 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
738 static void stellaris_adc_update(StellarisADCState
*s
)
743 for (n
= 0; n
< 4; n
++) {
744 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
745 qemu_set_irq(s
->irq
[n
], level
);
749 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
751 StellarisADCState
*s
= opaque
;
754 for (n
= 0; n
< 4; n
++) {
755 if ((s
->actss
& (1 << n
)) == 0) {
759 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
763 /* Some applications use the ADC as a random number source, so introduce
764 some variation into the signal. */
765 s
->noise
= s
->noise
* 314159 + 1;
766 /* ??? actual inputs not implemented. Return an arbitrary value. */
767 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
769 stellaris_adc_update(s
);
773 static void stellaris_adc_reset(StellarisADCState
*s
)
777 for (n
= 0; n
< 4; n
++) {
780 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
784 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
787 StellarisADCState
*s
= opaque
;
789 /* TODO: Implement this. */
790 if (offset
>= 0x40 && offset
< 0xc0) {
792 n
= (offset
- 0x40) >> 5;
793 switch (offset
& 0x1f) {
794 case 0x00: /* SSMUX */
796 case 0x04: /* SSCTL */
798 case 0x08: /* SSFIFO */
799 return stellaris_adc_fifo_read(s
, n
);
800 case 0x0c: /* SSFSTAT */
801 return s
->fifo
[n
].state
;
807 case 0x00: /* ACTSS */
814 return s
->ris
& s
->im
;
815 case 0x10: /* OSTAT */
817 case 0x14: /* EMUX */
819 case 0x18: /* USTAT */
821 case 0x20: /* SSPRI */
826 qemu_log_mask(LOG_GUEST_ERROR
,
827 "stellaris_adc: read at bad offset 0x%x\n", (int)offset
);
832 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
833 uint64_t value
, unsigned size
)
835 StellarisADCState
*s
= opaque
;
837 /* TODO: Implement this. */
838 if (offset
>= 0x40 && offset
< 0xc0) {
840 n
= (offset
- 0x40) >> 5;
841 switch (offset
& 0x1f) {
842 case 0x00: /* SSMUX */
843 s
->ssmux
[n
] = value
& 0x33333333;
845 case 0x04: /* SSCTL */
847 qemu_log_mask(LOG_UNIMP
,
848 "ADC: Unimplemented sequence %" PRIx64
"\n",
858 case 0x00: /* ACTSS */
859 s
->actss
= value
& 0xf;
867 case 0x10: /* OSTAT */
870 case 0x14: /* EMUX */
873 case 0x18: /* USTAT */
876 case 0x20: /* SSPRI */
879 case 0x28: /* PSSI */
880 qemu_log_mask(LOG_UNIMP
, "ADC: sample initiate unimplemented\n");
886 qemu_log_mask(LOG_GUEST_ERROR
,
887 "stellaris_adc: write at bad offset 0x%x\n", (int)offset
);
889 stellaris_adc_update(s
);
892 static const MemoryRegionOps stellaris_adc_ops
= {
893 .read
= stellaris_adc_read
,
894 .write
= stellaris_adc_write
,
895 .endianness
= DEVICE_NATIVE_ENDIAN
,
898 static const VMStateDescription vmstate_stellaris_adc
= {
899 .name
= "stellaris_adc",
901 .minimum_version_id
= 1,
902 .fields
= (VMStateField
[]) {
903 VMSTATE_UINT32(actss
, StellarisADCState
),
904 VMSTATE_UINT32(ris
, StellarisADCState
),
905 VMSTATE_UINT32(im
, StellarisADCState
),
906 VMSTATE_UINT32(emux
, StellarisADCState
),
907 VMSTATE_UINT32(ostat
, StellarisADCState
),
908 VMSTATE_UINT32(ustat
, StellarisADCState
),
909 VMSTATE_UINT32(sspri
, StellarisADCState
),
910 VMSTATE_UINT32(sac
, StellarisADCState
),
911 VMSTATE_UINT32(fifo
[0].state
, StellarisADCState
),
912 VMSTATE_UINT32_ARRAY(fifo
[0].data
, StellarisADCState
, 16),
913 VMSTATE_UINT32(ssmux
[0], StellarisADCState
),
914 VMSTATE_UINT32(ssctl
[0], StellarisADCState
),
915 VMSTATE_UINT32(fifo
[1].state
, StellarisADCState
),
916 VMSTATE_UINT32_ARRAY(fifo
[1].data
, StellarisADCState
, 16),
917 VMSTATE_UINT32(ssmux
[1], StellarisADCState
),
918 VMSTATE_UINT32(ssctl
[1], StellarisADCState
),
919 VMSTATE_UINT32(fifo
[2].state
, StellarisADCState
),
920 VMSTATE_UINT32_ARRAY(fifo
[2].data
, StellarisADCState
, 16),
921 VMSTATE_UINT32(ssmux
[2], StellarisADCState
),
922 VMSTATE_UINT32(ssctl
[2], StellarisADCState
),
923 VMSTATE_UINT32(fifo
[3].state
, StellarisADCState
),
924 VMSTATE_UINT32_ARRAY(fifo
[3].data
, StellarisADCState
, 16),
925 VMSTATE_UINT32(ssmux
[3], StellarisADCState
),
926 VMSTATE_UINT32(ssctl
[3], StellarisADCState
),
927 VMSTATE_UINT32(noise
, StellarisADCState
),
928 VMSTATE_END_OF_LIST()
932 static void stellaris_adc_init(Object
*obj
)
934 DeviceState
*dev
= DEVICE(obj
);
935 StellarisADCState
*s
= STELLARIS_ADC(obj
);
936 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
939 for (n
= 0; n
< 4; n
++) {
940 sysbus_init_irq(sbd
, &s
->irq
[n
]);
943 memory_region_init_io(&s
->iomem
, obj
, &stellaris_adc_ops
, s
,
945 sysbus_init_mmio(sbd
, &s
->iomem
);
946 stellaris_adc_reset(s
);
947 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
951 static stellaris_board_info stellaris_boards
[] = {
955 0x001f001f, /* dc0 */
965 0x00ff007f, /* dc0 */
970 BP_OLED_SSI
| BP_GAMEPAD
974 static void stellaris_init(MachineState
*ms
, stellaris_board_info
*board
)
976 static const int uart_irq
[] = {5, 6, 33, 34};
977 static const int timer_irq
[] = {19, 21, 23, 35};
978 static const uint32_t gpio_addr
[7] =
979 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
980 0x40024000, 0x40025000, 0x40026000};
981 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
983 /* Memory map of SoC devices, from
984 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
985 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
988 * 40002000 i2c (unimplemented)
998 * 40021000 i2c (unimplemented)
1002 * 40028000 PWM (unimplemented)
1003 * 4002c000 QEI (unimplemented)
1004 * 4002d000 QEI (unimplemented)
1010 * 4003c000 analogue comparator (unimplemented)
1012 * 400fc000 hibernation module (unimplemented)
1013 * 400fd000 flash memory control (unimplemented)
1014 * 400fe000 system control
1017 DeviceState
*gpio_dev
[7], *nvic
;
1018 qemu_irq gpio_in
[7][8];
1019 qemu_irq gpio_out
[7][8];
1025 DeviceState
*ssys_dev
;
1028 const uint8_t *macaddr
;
1030 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1031 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1032 MemoryRegion
*system_memory
= get_system_memory();
1034 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1035 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1037 /* Flash programming is done via the SCU, so pretend it is ROM. */
1038 memory_region_init_rom(flash
, NULL
, "stellaris.flash", flash_size
,
1040 memory_region_add_subregion(system_memory
, 0, flash
);
1042 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1044 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1047 * Create the system-registers object early, because we will
1048 * need its sysclk output.
1050 ssys_dev
= qdev_new(TYPE_STELLARIS_SYS
);
1051 /* Most devices come preprogrammed with a MAC address in the user data. */
1052 macaddr
= nd_table
[0].macaddr
.a
;
1053 qdev_prop_set_uint32(ssys_dev
, "user0",
1054 macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16));
1055 qdev_prop_set_uint32(ssys_dev
, "user1",
1056 macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16));
1057 qdev_prop_set_uint32(ssys_dev
, "did0", board
->did0
);
1058 qdev_prop_set_uint32(ssys_dev
, "did1", board
->did1
);
1059 qdev_prop_set_uint32(ssys_dev
, "dc0", board
->dc0
);
1060 qdev_prop_set_uint32(ssys_dev
, "dc1", board
->dc1
);
1061 qdev_prop_set_uint32(ssys_dev
, "dc2", board
->dc2
);
1062 qdev_prop_set_uint32(ssys_dev
, "dc3", board
->dc3
);
1063 qdev_prop_set_uint32(ssys_dev
, "dc4", board
->dc4
);
1064 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev
), &error_fatal
);
1066 nvic
= qdev_new(TYPE_ARMV7M
);
1067 qdev_prop_set_uint32(nvic
, "num-irq", NUM_IRQ_LINES
);
1068 qdev_prop_set_string(nvic
, "cpu-type", ms
->cpu_type
);
1069 qdev_prop_set_bit(nvic
, "enable-bitband", true);
1070 qdev_connect_clock_in(nvic
, "cpuclk",
1071 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1072 /* This SoC does not connect the systick reference clock */
1073 object_property_set_link(OBJECT(nvic
), "memory",
1074 OBJECT(get_system_memory()), &error_abort
);
1075 /* This will exit with an error if the user passed us a bad cpu_type */
1076 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic
), &error_fatal
);
1078 /* Now we can wire up the IRQ and MMIO of the system registers */
1079 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev
), 0, 0x400fe000);
1080 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev
), 0, qdev_get_gpio_in(nvic
, 28));
1082 if (board
->dc1
& (1 << 16)) {
1083 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1084 qdev_get_gpio_in(nvic
, 14),
1085 qdev_get_gpio_in(nvic
, 15),
1086 qdev_get_gpio_in(nvic
, 16),
1087 qdev_get_gpio_in(nvic
, 17),
1089 adc
= qdev_get_gpio_in(dev
, 0);
1093 for (i
= 0; i
< 4; i
++) {
1094 if (board
->dc2
& (0x10000 << i
)) {
1097 dev
= qdev_new(TYPE_STELLARIS_GPTM
);
1098 sbd
= SYS_BUS_DEVICE(dev
);
1099 qdev_connect_clock_in(dev
, "clk",
1100 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1101 sysbus_realize_and_unref(sbd
, &error_fatal
);
1102 sysbus_mmio_map(sbd
, 0, 0x40030000 + i
* 0x1000);
1103 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1104 /* TODO: This is incorrect, but we get away with it because
1105 the ADC output is only ever pulsed. */
1106 qdev_connect_gpio_out(dev
, 0, adc
);
1110 if (board
->dc1
& (1 << 3)) { /* watchdog present */
1111 dev
= qdev_new(TYPE_LUMINARY_WATCHDOG
);
1113 qdev_connect_clock_in(dev
, "WDOGCLK",
1114 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1117 sysbus_mmio_map(SYS_BUS_DEVICE(dev
),
1120 sysbus_connect_irq(SYS_BUS_DEVICE(dev
),
1122 qdev_get_gpio_in(nvic
, 18));
1126 for (i
= 0; i
< 7; i
++) {
1127 if (board
->dc4
& (1 << i
)) {
1128 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1129 qdev_get_gpio_in(nvic
,
1131 for (j
= 0; j
< 8; j
++) {
1132 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1133 gpio_out
[i
][j
] = NULL
;
1138 if (board
->dc2
& (1 << 12)) {
1139 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1140 qdev_get_gpio_in(nvic
, 8));
1141 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1142 if (board
->peripherals
& BP_OLED_I2C
) {
1143 i2c_slave_create_simple(i2c
, "ssd0303", 0x3d);
1147 for (i
= 0; i
< 4; i
++) {
1148 if (board
->dc2
& (1 << i
)) {
1149 pl011_luminary_create(0x4000c000 + i
* 0x1000,
1150 qdev_get_gpio_in(nvic
, uart_irq
[i
]),
1154 if (board
->dc2
& (1 << 4)) {
1155 dev
= sysbus_create_simple("pl022", 0x40008000,
1156 qdev_get_gpio_in(nvic
, 7));
1157 if (board
->peripherals
& BP_OLED_SSI
) {
1160 DeviceState
*ssddev
;
1162 DeviceState
*carddev
;
1163 DeviceState
*gpio_d_splitter
;
1167 * Some boards have both an OLED controller and SD card connected to
1168 * the same SSI port, with the SD card chip select connected to a
1169 * GPIO pin. Technically the OLED chip select is connected to the
1170 * SSI Fss pin. We do not bother emulating that as both devices
1171 * should never be selected simultaneously, and our OLED controller
1172 * ignores stray 0xff commands that occur when deselecting the SD
1175 * The h/w wiring is:
1176 * - GPIO pin D0 is wired to the active-low SD card chip select
1177 * - GPIO pin A3 is wired to the active-low OLED chip select
1178 * - The SoC wiring of the PL061 "auxiliary function" for A3 is
1179 * SSI0Fss ("frame signal"), which is an output from the SoC's
1180 * SSI controller. The SSI controller takes SSI0Fss low when it
1181 * transmits a frame, so it can work as a chip-select signal.
1182 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
1183 * (the OLED never sends data to the CPU, so no wiring needed)
1184 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
1185 * and the OLED display-data-in
1186 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
1187 * serial-clock input
1188 * So a guest that wants to use the OLED can configure the PL061
1189 * to make pins A2, A3, A5 aux-function, so they are connected
1190 * directly to the SSI controller. When the SSI controller sends
1191 * data it asserts SSI0Fss which selects the OLED.
1192 * A guest that wants to use the SD card configures A2, A4 and A5
1193 * as aux-function, but leaves A3 as a software-controlled GPIO
1194 * line. It asserts the SD card chip-select by using the PL061
1195 * to control pin D0, and lets the SSI controller handle Clk, Tx
1196 * and Rx. (The SSI controller asserts Fss during tx cycles as
1197 * usual, but because A3 is not set to aux-function this is not
1198 * forwarded to the OLED, and so the OLED stays unselected.)
1200 * The QEMU implementation instead is:
1201 * - GPIO pin D0 is wired to the active-low SD card chip select,
1202 * and also to the OLED chip-select which is implemented
1204 * - SSI controller signals go to the devices regardless of
1205 * whether the guest programs A2, A4, A5 as aux-function or not
1207 * The problem with this implementation is if the guest doesn't
1208 * care about the SD card and only uses the OLED. In that case it
1209 * may choose never to do anything with D0 (leaving it in its
1210 * default floating state, which reliably leaves the card disabled
1211 * because an SD card has a pullup on CS within the card itself),
1212 * and only set up A2, A3, A5. This for us would mean the OLED
1213 * never gets the chip-select assert it needs. We work around
1214 * this with a manual raise of D0 here (despite board creation
1215 * code being the wrong place to raise IRQ lines) to put the OLED
1216 * into an initially selected state.
1218 * In theory the right way to model this would be:
1219 * - Implement aux-function support in the PL061, with an
1220 * extra set of AFIN and AFOUT GPIO lines (set up so that
1221 * if a GPIO line is in auxfn mode the main GPIO in and out
1222 * track the AFIN and AFOUT lines)
1223 * - Wire the AFOUT for D0 up to either a line from the
1224 * SSI controller that's pulled low around every transmit,
1225 * or at least to an always-0 line here on the board
1226 * - Make the ssd0323 OLED controller chipselect active-low
1228 bus
= qdev_get_child_bus(dev
, "ssi");
1229 sddev
= ssi_create_peripheral(bus
, "ssi-sd");
1231 dinfo
= drive_get(IF_SD
, 0, 0);
1232 blk
= dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
;
1233 carddev
= qdev_new(TYPE_SD_CARD
);
1234 qdev_prop_set_drive_err(carddev
, "drive", blk
, &error_fatal
);
1235 qdev_prop_set_bit(carddev
, "spi", true);
1236 qdev_realize_and_unref(carddev
,
1237 qdev_get_child_bus(sddev
, "sd-bus"),
1240 ssddev
= ssi_create_peripheral(bus
, "ssd0323");
1242 gpio_d_splitter
= qdev_new(TYPE_SPLIT_IRQ
);
1243 qdev_prop_set_uint32(gpio_d_splitter
, "num-lines", 2);
1244 qdev_realize_and_unref(gpio_d_splitter
, NULL
, &error_fatal
);
1245 qdev_connect_gpio_out(
1247 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0));
1248 qdev_connect_gpio_out(
1250 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1251 gpio_out
[GPIO_D
][0] = qdev_get_gpio_in(gpio_d_splitter
, 0);
1253 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1255 /* Make sure the select pin is high. */
1256 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1259 if (board
->dc4
& (1 << 28)) {
1262 qemu_check_nic_model(&nd_table
[0], "stellaris");
1264 enet
= qdev_new("stellaris_enet");
1265 qdev_set_nic_properties(enet
, &nd_table
[0]);
1266 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet
), &error_fatal
);
1267 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1268 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1270 if (board
->peripherals
& BP_GAMEPAD
) {
1271 qemu_irq gpad_irq
[5];
1272 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1274 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1275 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1276 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1277 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1278 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1280 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1282 for (i
= 0; i
< 7; i
++) {
1283 if (board
->dc4
& (1 << i
)) {
1284 for (j
= 0; j
< 8; j
++) {
1285 if (gpio_out
[i
][j
]) {
1286 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1292 /* Add dummy regions for the devices we don't implement yet,
1293 * so guest accesses don't cause unlogged crashes.
1295 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1296 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1297 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1298 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1299 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1300 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1301 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1302 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1304 armv7m_load_kernel(ARM_CPU(first_cpu
), ms
->kernel_filename
, 0, flash_size
);
1307 /* FIXME: Figure out how to generate these from stellaris_boards. */
1308 static void lm3s811evb_init(MachineState
*machine
)
1310 stellaris_init(machine
, &stellaris_boards
[0]);
1313 static void lm3s6965evb_init(MachineState
*machine
)
1315 stellaris_init(machine
, &stellaris_boards
[1]);
1318 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1320 MachineClass
*mc
= MACHINE_CLASS(oc
);
1322 mc
->desc
= "Stellaris LM3S811EVB (Cortex-M3)";
1323 mc
->init
= lm3s811evb_init
;
1324 mc
->ignore_memory_transaction_failures
= true;
1325 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1328 static const TypeInfo lm3s811evb_type
= {
1329 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1330 .parent
= TYPE_MACHINE
,
1331 .class_init
= lm3s811evb_class_init
,
1334 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1336 MachineClass
*mc
= MACHINE_CLASS(oc
);
1338 mc
->desc
= "Stellaris LM3S6965EVB (Cortex-M3)";
1339 mc
->init
= lm3s6965evb_init
;
1340 mc
->ignore_memory_transaction_failures
= true;
1341 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1344 static const TypeInfo lm3s6965evb_type
= {
1345 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1346 .parent
= TYPE_MACHINE
,
1347 .class_init
= lm3s6965evb_class_init
,
1350 static void stellaris_machine_init(void)
1352 type_register_static(&lm3s811evb_type
);
1353 type_register_static(&lm3s6965evb_type
);
1356 type_init(stellaris_machine_init
)
1358 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1360 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1362 dc
->vmsd
= &vmstate_stellaris_i2c
;
1365 static const TypeInfo stellaris_i2c_info
= {
1366 .name
= TYPE_STELLARIS_I2C
,
1367 .parent
= TYPE_SYS_BUS_DEVICE
,
1368 .instance_size
= sizeof(stellaris_i2c_state
),
1369 .instance_init
= stellaris_i2c_init
,
1370 .class_init
= stellaris_i2c_class_init
,
1373 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1375 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1377 dc
->vmsd
= &vmstate_stellaris_adc
;
1380 static const TypeInfo stellaris_adc_info
= {
1381 .name
= TYPE_STELLARIS_ADC
,
1382 .parent
= TYPE_SYS_BUS_DEVICE
,
1383 .instance_size
= sizeof(StellarisADCState
),
1384 .instance_init
= stellaris_adc_init
,
1385 .class_init
= stellaris_adc_class_init
,
1388 static void stellaris_sys_class_init(ObjectClass
*klass
, void *data
)
1390 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1391 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1393 dc
->vmsd
= &vmstate_stellaris_sys
;
1394 rc
->phases
.enter
= stellaris_sys_reset_enter
;
1395 rc
->phases
.hold
= stellaris_sys_reset_hold
;
1396 rc
->phases
.exit
= stellaris_sys_reset_exit
;
1397 device_class_set_props(dc
, stellaris_sys_properties
);
1400 static const TypeInfo stellaris_sys_info
= {
1401 .name
= TYPE_STELLARIS_SYS
,
1402 .parent
= TYPE_SYS_BUS_DEVICE
,
1403 .instance_size
= sizeof(ssys_state
),
1404 .instance_init
= stellaris_sys_instance_init
,
1405 .class_init
= stellaris_sys_class_init
,
1408 static void stellaris_register_types(void)
1410 type_register_static(&stellaris_i2c_info
);
1411 type_register_static(&stellaris_adc_info
);
1412 type_register_static(&stellaris_sys_info
);
1415 type_init(stellaris_register_types
)