target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26 #include "exec/memattrs.h"
  27
  28 #define DEBUG_KVM 0
  29
  30 #define DPRINTF(fmt, ...) \
  31     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  32
  33 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  34     KVM_CAP_LAST_INFO
  35 };
  36
  37 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  38
  39 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  40 {
  41     return cs->cpu_index;
  42 }
  43
  44 int kvm_arch_init(MachineState *ms, KVMState *s)
  45 {
  46     /* MIPS has 128 signals */
  47     kvm_set_sigmask_len(s, 16);
  48
  49     DPRINTF("%s\n", __func__);
  50     return 0;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     int ret = 0;
  56
  57     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  58
  59     DPRINTF("%s\n", __func__);
  60     return ret;
  61 }
  62
  63 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  64 {
  65     CPUMIPSState *env = &cpu->env;
  66
  67     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  68         fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
  69         env->CP0_Config1 &= ~(1 << CP0C1_FP);
  70     }
  71
  72     DPRINTF("%s\n", __func__);
  73 }
  74
  75 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  76 {
  77     DPRINTF("%s\n", __func__);
  78     return 0;
  79 }
  80
  81 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  82 {
  83     DPRINTF("%s\n", __func__);
  84     return 0;
  85 }
  86
  87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  88 {
  89     CPUMIPSState *env = &cpu->env;
  90
  91     DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
  92     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  93 }
  94
  95
  96 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  97 {
  98     MIPSCPU *cpu = MIPS_CPU(cs);
  99     int r;
 100     struct kvm_mips_interrupt intr;
 101
 102     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 103             cpu_mips_io_interrupts_pending(cpu)) {
 104         intr.cpu = -1;
 105         intr.irq = 2;
 106         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 107         if (r < 0) {
 108             error_report("%s: cpu %d: failed to inject IRQ %x",
 109                          __func__, cs->cpu_index, intr.irq);
 110         }
 111     }
 112 }
 113
 114 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 115 {
 116     DPRINTF("%s\n", __func__);
 117     return MEMTXATTRS_UNSPECIFIED;
 118 }
 119
 120 int kvm_arch_process_async_events(CPUState *cs)
 121 {
 122     return cs->halted;
 123 }
 124
 125 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 126 {
 127     int ret;
 128
 129     DPRINTF("%s\n", __func__);
 130     switch (run->exit_reason) {
 131     default:
 132         error_report("%s: unknown exit reason %d",
 133                      __func__, run->exit_reason);
 134         ret = -1;
 135         break;
 136     }
 137
 138     return ret;
 139 }
 140
 141 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 142 {
 143     DPRINTF("%s\n", __func__);
 144     return true;
 145 }
 146
 147 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 148 {
 149     DPRINTF("%s\n", __func__);
 150     return 1;
 151 }
 152
 153 int kvm_arch_on_sigbus(int code, void *addr)
 154 {
 155     DPRINTF("%s\n", __func__);
 156     return 1;
 157 }
 158
 159 void kvm_arch_init_irq_routing(KVMState *s)
 160 {
 161 }
 162
 163 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 164 {
 165     CPUState *cs = CPU(cpu);
 166     struct kvm_mips_interrupt intr;
 167
 168     if (!kvm_enabled()) {
 169         return 0;
 170     }
 171
 172     intr.cpu = -1;
 173
 174     if (level) {
 175         intr.irq = irq;
 176     } else {
 177         intr.irq = -irq;
 178     }
 179
 180     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 181
 182     return 0;
 183 }
 184
 185 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 186 {
 187     CPUState *cs = current_cpu;
 188     CPUState *dest_cs = CPU(cpu);
 189     struct kvm_mips_interrupt intr;
 190
 191     if (!kvm_enabled()) {
 192         return 0;
 193     }
 194
 195     intr.cpu = dest_cs->cpu_index;
 196
 197     if (level) {
 198         intr.irq = irq;
 199     } else {
 200         intr.irq = -irq;
 201     }
 202
 203     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 204
 205     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 206
 207     return 0;
 208 }
 209
 210 #define MIPS_CP0_32(_R, _S)                                     \
 211     (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
 212
 213 #define MIPS_CP0_64(_R, _S)                                     \
 214     (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
 215
 216 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 217 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 218 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 219 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 220 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 221 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 222 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 223 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 224 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 225 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 226 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 227 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 228 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 229 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 230
 231 /* CP0_Count control */
 232 #define KVM_REG_MIPS_COUNT_CTL          (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 233                                          0x20000 | 0)
 234 #define KVM_REG_MIPS_COUNT_CTL_DC       0x00000001      /* master disable */
 235 /* CP0_Count resume monotonic nanoseconds */
 236 #define KVM_REG_MIPS_COUNT_RESUME       (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 237                                          0x20000 | 1)
 238 /* CP0_Count rate in Hz */
 239 #define KVM_REG_MIPS_COUNT_HZ           (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 240                                          0x20000 | 2)
 241
 242 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 243                                        int32_t *addr)
 244 {
 245     uint64_t val64 = *addr;
 246     struct kvm_one_reg cp0reg = {
 247         .id = reg_id,
 248         .addr = (uintptr_t)&val64
 249     };
 250
 251     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 252 }
 253
 254 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 255                                          target_ulong *addr)
 256 {
 257     uint64_t val64 = *addr;
 258     struct kvm_one_reg cp0reg = {
 259         .id = reg_id,
 260         .addr = (uintptr_t)&val64
 261     };
 262
 263     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 264 }
 265
 266 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 267                                          uint64_t *addr)
 268 {
 269     struct kvm_one_reg cp0reg = {
 270         .id = reg_id,
 271         .addr = (uintptr_t)addr
 272     };
 273
 274     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 275 }
 276
 277 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 278                                        int32_t *addr)
 279 {
 280     int ret;
 281     uint64_t val64 = 0;
 282     struct kvm_one_reg cp0reg = {
 283         .id = reg_id,
 284         .addr = (uintptr_t)&val64
 285     };
 286
 287     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 288     if (ret >= 0) {
 289         *addr = val64;
 290     }
 291     return ret;
 292 }
 293
 294 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,
 295                                          target_ulong *addr)
 296 {
 297     int ret;
 298     uint64_t val64 = 0;
 299     struct kvm_one_reg cp0reg = {
 300         .id = reg_id,
 301         .addr = (uintptr_t)&val64
 302     };
 303
 304     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 305     if (ret >= 0) {
 306         *addr = val64;
 307     }
 308     return ret;
 309 }
 310
 311 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id,
 312                                          uint64_t *addr)
 313 {
 314     struct kvm_one_reg cp0reg = {
 315         .id = reg_id,
 316         .addr = (uintptr_t)addr
 317     };
 318
 319     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 320 }
 321
 322 /*
 323  * We freeze the KVM timer when either the VM clock is stopped or the state is
 324  * saved (the state is dirty).
 325  */
 326
 327 /*
 328  * Save the state of the KVM timer when VM clock is stopped or state is synced
 329  * to QEMU.
 330  */
 331 static int kvm_mips_save_count(CPUState *cs)
 332 {
 333     MIPSCPU *cpu = MIPS_CPU(cs);
 334     CPUMIPSState *env = &cpu->env;
 335     uint64_t count_ctl;
 336     int err, ret = 0;
 337
 338     /* freeze KVM timer */
 339     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 340     if (err < 0) {
 341         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 342         ret = err;
 343     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 344         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 345         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 346         if (err < 0) {
 347             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 348             ret = err;
 349         }
 350     }
 351
 352     /* read CP0_Cause */
 353     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 354     if (err < 0) {
 355         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 356         ret = err;
 357     }
 358
 359     /* read CP0_Count */
 360     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 361     if (err < 0) {
 362         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 363         ret = err;
 364     }
 365
 366     return ret;
 367 }
 368
 369 /*
 370  * Restore the state of the KVM timer when VM clock is restarted or state is
 371  * synced to KVM.
 372  */
 373 static int kvm_mips_restore_count(CPUState *cs)
 374 {
 375     MIPSCPU *cpu = MIPS_CPU(cs);
 376     CPUMIPSState *env = &cpu->env;
 377     uint64_t count_ctl;
 378     int err_dc, err, ret = 0;
 379
 380     /* check the timer is frozen */
 381     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 382     if (err_dc < 0) {
 383         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 384         ret = err_dc;
 385     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 386         /* freeze timer (sets COUNT_RESUME for us) */
 387         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 388         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 389         if (err < 0) {
 390             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 391             ret = err;
 392         }
 393     }
 394
 395     /* load CP0_Cause */
 396     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 397     if (err < 0) {
 398         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 399         ret = err;
 400     }
 401
 402     /* load CP0_Count */
 403     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 404     if (err < 0) {
 405         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 406         ret = err;
 407     }
 408
 409     /* resume KVM timer */
 410     if (err_dc >= 0) {
 411         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 412         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 413         if (err < 0) {
 414             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 415             ret = err;
 416         }
 417     }
 418
 419     return ret;
 420 }
 421
 422 /*
 423  * Handle the VM clock being started or stopped
 424  */
 425 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 426 {
 427     CPUState *cs = opaque;
 428     int ret;
 429     uint64_t count_resume;
 430
 431     /*
 432      * If state is already dirty (synced to QEMU) then the KVM timer state is
 433      * already saved and can be restored when it is synced back to KVM.
 434      */
 435     if (!running) {
 436         if (!cs->kvm_vcpu_dirty) {
 437             ret = kvm_mips_save_count(cs);
 438             if (ret < 0) {
 439                 fprintf(stderr, "Failed saving count\n");
 440             }
 441         }
 442     } else {
 443         /* Set clock restore time to now */
 444         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 445         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 446                                      &count_resume);
 447         if (ret < 0) {
 448             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 449             return;
 450         }
 451
 452         if (!cs->kvm_vcpu_dirty) {
 453             ret = kvm_mips_restore_count(cs);
 454             if (ret < 0) {
 455                 fprintf(stderr, "Failed restoring count\n");
 456             }
 457         }
 458     }
 459 }
 460
 461 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 462 {
 463     MIPSCPU *cpu = MIPS_CPU(cs);
 464     CPUMIPSState *env = &cpu->env;
 465     int err, ret = 0;
 466
 467     (void)level;
 468
 469     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 470     if (err < 0) {
 471         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 472         ret = err;
 473     }
 474     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 475                                  &env->CP0_Context);
 476     if (err < 0) {
 477         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 478         ret = err;
 479     }
 480     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 481                                  &env->active_tc.CP0_UserLocal);
 482     if (err < 0) {
 483         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 484         ret = err;
 485     }
 486     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 487                                &env->CP0_PageMask);
 488     if (err < 0) {
 489         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 490         ret = err;
 491     }
 492     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 493     if (err < 0) {
 494         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 495         ret = err;
 496     }
 497     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 498     if (err < 0) {
 499         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 500         ret = err;
 501     }
 502     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 503                                  &env->CP0_BadVAddr);
 504     if (err < 0) {
 505         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 506         ret = err;
 507     }
 508
 509     /* If VM clock stopped then state will be restored when it is restarted */
 510     if (runstate_is_running()) {
 511         err = kvm_mips_restore_count(cs);
 512         if (err < 0) {
 513             ret = err;
 514         }
 515     }
 516
 517     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 518                                  &env->CP0_EntryHi);
 519     if (err < 0) {
 520         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 521         ret = err;
 522     }
 523     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 524                                &env->CP0_Compare);
 525     if (err < 0) {
 526         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 527         ret = err;
 528     }
 529     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 530     if (err < 0) {
 531         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 532         ret = err;
 533     }
 534     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 535     if (err < 0) {
 536         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 537         ret = err;
 538     }
 539     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 540                                  &env->CP0_ErrorEPC);
 541     if (err < 0) {
 542         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 543         ret = err;
 544     }
 545
 546     return ret;
 547 }
 548
 549 static int kvm_mips_get_cp0_registers(CPUState *cs)
 550 {
 551     MIPSCPU *cpu = MIPS_CPU(cs);
 552     CPUMIPSState *env = &cpu->env;
 553     int err, ret = 0;
 554
 555     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 556     if (err < 0) {
 557         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 558         ret = err;
 559     }
 560     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 561                                  &env->CP0_Context);
 562     if (err < 0) {
 563         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 564         ret = err;
 565     }
 566     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 567                                  &env->active_tc.CP0_UserLocal);
 568     if (err < 0) {
 569         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 570         ret = err;
 571     }
 572     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 573                                &env->CP0_PageMask);
 574     if (err < 0) {
 575         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 576         ret = err;
 577     }
 578     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 579     if (err < 0) {
 580         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 581         ret = err;
 582     }
 583     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 584     if (err < 0) {
 585         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 586         ret = err;
 587     }
 588     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 589                                  &env->CP0_BadVAddr);
 590     if (err < 0) {
 591         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 592         ret = err;
 593     }
 594     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 595                                  &env->CP0_EntryHi);
 596     if (err < 0) {
 597         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 598         ret = err;
 599     }
 600     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 601                                &env->CP0_Compare);
 602     if (err < 0) {
 603         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 604         ret = err;
 605     }
 606     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 607     if (err < 0) {
 608         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 609         ret = err;
 610     }
 611
 612     /* If VM clock stopped then state was already saved when it was stopped */
 613     if (runstate_is_running()) {
 614         err = kvm_mips_save_count(cs);
 615         if (err < 0) {
 616             ret = err;
 617         }
 618     }
 619
 620     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 621     if (err < 0) {
 622         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 623         ret = err;
 624     }
 625     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 626                                  &env->CP0_ErrorEPC);
 627     if (err < 0) {
 628         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 629         ret = err;
 630     }
 631
 632     return ret;
 633 }
 634
 635 int kvm_arch_put_registers(CPUState *cs, int level)
 636 {
 637     MIPSCPU *cpu = MIPS_CPU(cs);
 638     CPUMIPSState *env = &cpu->env;
 639     struct kvm_regs regs;
 640     int ret;
 641     int i;
 642
 643     /* Set the registers based on QEMU's view of things */
 644     for (i = 0; i < 32; i++) {
 645         regs.gpr[i] = env->active_tc.gpr[i];
 646     }
 647
 648     regs.hi = env->active_tc.HI[0];
 649     regs.lo = env->active_tc.LO[0];
 650     regs.pc = env->active_tc.PC;
 651
 652     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 653
 654     if (ret < 0) {
 655         return ret;
 656     }
 657
 658     ret = kvm_mips_put_cp0_registers(cs, level);
 659     if (ret < 0) {
 660         return ret;
 661     }
 662
 663     return ret;
 664 }
 665
 666 int kvm_arch_get_registers(CPUState *cs)
 667 {
 668     MIPSCPU *cpu = MIPS_CPU(cs);
 669     CPUMIPSState *env = &cpu->env;
 670     int ret = 0;
 671     struct kvm_regs regs;
 672     int i;
 673
 674     /* Get the current register set as KVM seems it */
 675     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 676
 677     if (ret < 0) {
 678         return ret;
 679     }
 680
 681     for (i = 0; i < 32; i++) {
 682         env->active_tc.gpr[i] = regs.gpr[i];
 683     }
 684
 685     env->active_tc.HI[0] = regs.hi;
 686     env->active_tc.LO[0] = regs.lo;
 687     env->active_tc.PC = regs.pc;
 688
 689     kvm_mips_get_cp0_registers(cs);
 690
 691     return ret;
 692 }
 693
 694 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 695                              uint64_t address, uint32_t data)
 696 {
 697     return 0;
 698 }