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ppc: Use a helper to generate "LE unsupported" alignment interrupts
[qemu/kevin.git] / target-ppc / translate.c
blob1315656448560f94c5d77af543b4574dab3a013f
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* Bit count */
502 EXTRACT_HELPER(NB, 11, 5);
503 /* Shift count */
504 EXTRACT_HELPER(SH, 11, 5);
505 /* Vector shift count */
506 EXTRACT_HELPER(VSH, 6, 4);
507 /* Mask start */
508 EXTRACT_HELPER(MB, 6, 5);
509 /* Mask end */
510 EXTRACT_HELPER(ME, 1, 5);
511 /* Trap operand */
512 EXTRACT_HELPER(TO, 21, 5);
513
514 EXTRACT_HELPER(CRM, 12, 8);
515
516 #ifndef CONFIG_USER_ONLY
517 EXTRACT_HELPER(SR, 16, 4);
518 #endif
519
520 /* mtfsf/mtfsfi */
521 EXTRACT_HELPER(FPBF, 23, 3);
522 EXTRACT_HELPER(FPIMM, 12, 4);
523 EXTRACT_HELPER(FPL, 25, 1);
524 EXTRACT_HELPER(FPFLM, 17, 8);
525 EXTRACT_HELPER(FPW, 16, 1);
526
527 /* addpcis */
528 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
529
530 /*** Jump target decoding ***/
531 /* Immediate address */
532 static inline target_ulong LI(uint32_t opcode)
533 {
534 return (opcode >> 0) & 0x03FFFFFC;
535 }
536
537 static inline uint32_t BD(uint32_t opcode)
538 {
539 return (opcode >> 0) & 0xFFFC;
540 }
541
542 EXTRACT_HELPER(BO, 21, 5);
543 EXTRACT_HELPER(BI, 16, 5);
544 /* Absolute/relative address */
545 EXTRACT_HELPER(AA, 1, 1);
546 /* Link */
547 EXTRACT_HELPER(LK, 0, 1);
548
549 /* DFP Z22-form */
550 EXTRACT_HELPER(DCM, 10, 6)
551
552 /* DFP Z23-form */
553 EXTRACT_HELPER(RMC, 9, 2)
554
555 /* Create a mask between <start> and <end> bits */
556 static inline target_ulong MASK(uint32_t start, uint32_t end)
557 {
558 target_ulong ret;
559
560 #if defined(TARGET_PPC64)
561 if (likely(start == 0)) {
562 ret = UINT64_MAX << (63 - end);
563 } else if (likely(end == 63)) {
564 ret = UINT64_MAX >> start;
565 }
566 #else
567 if (likely(start == 0)) {
568 ret = UINT32_MAX << (31 - end);
569 } else if (likely(end == 31)) {
570 ret = UINT32_MAX >> start;
571 }
572 #endif
573 else {
574 ret = (((target_ulong)(-1ULL)) >> (start)) ^
575 (((target_ulong)(-1ULL) >> (end)) >> 1);
576 if (unlikely(start > end))
577 return ~ret;
578 }
579
580 return ret;
581 }
582
583 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
585 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
586 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
587 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
588 EXTRACT_HELPER(DM, 8, 2);
589 EXTRACT_HELPER(UIM, 16, 2);
590 EXTRACT_HELPER(SHW, 8, 2);
591 EXTRACT_HELPER(SP, 19, 2);
592 /*****************************************************************************/
593 /* PowerPC instructions table */
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .opc4 = 0xff, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl1, \
619 .inval2 = invl2, \
620 .type = _typ, \
621 .type2 = _typ2, \
622 .handler = &gen_##name, \
623 .oname = stringify(name), \
624 }, \
625 .oname = stringify(name), \
626 }
627 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
628 { \
629 .opc1 = op1, \
630 .opc2 = op2, \
631 .opc3 = op3, \
632 .opc4 = 0xff, \
633 .handler = { \
634 .inval1 = invl, \
635 .type = _typ, \
636 .type2 = _typ2, \
637 .handler = &gen_##name, \
638 .oname = onam, \
639 }, \
640 .oname = onam, \
641 }
642 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
643 { \
644 .opc1 = op1, \
645 .opc2 = op2, \
646 .opc3 = op3, \
647 .opc4 = op4, \
648 .handler = { \
649 .inval1 = invl, \
650 .type = _typ, \
651 .type2 = _typ2, \
652 .handler = &gen_##name, \
653 .oname = stringify(name), \
654 }, \
655 .oname = stringify(name), \
656 }
657 #else
658 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
659 { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .opc4 = 0xff, \
664 .handler = { \
665 .inval1 = invl, \
666 .type = _typ, \
667 .type2 = _typ2, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = stringify(name), \
671 }
672 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
673 { \
674 .opc1 = op1, \
675 .opc2 = op2, \
676 .opc3 = op3, \
677 .opc4 = 0xff, \
678 .handler = { \
679 .inval1 = invl1, \
680 .inval2 = invl2, \
681 .type = _typ, \
682 .type2 = _typ2, \
683 .handler = &gen_##name, \
684 }, \
685 .oname = stringify(name), \
686 }
687 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
688 { \
689 .opc1 = op1, \
690 .opc2 = op2, \
691 .opc3 = op3, \
692 .opc4 = 0xff, \
693 .handler = { \
694 .inval1 = invl, \
695 .type = _typ, \
696 .type2 = _typ2, \
697 .handler = &gen_##name, \
698 }, \
699 .oname = onam, \
700 }
701 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
702 { \
703 .opc1 = op1, \
704 .opc2 = op2, \
705 .opc3 = op3, \
706 .opc4 = op4, \
707 .handler = { \
708 .inval1 = invl, \
709 .type = _typ, \
710 .type2 = _typ2, \
711 .handler = &gen_##name, \
712 }, \
713 .oname = stringify(name), \
714 }
715 #endif
716
717 /* SPR load/store helpers */
718 static inline void gen_load_spr(TCGv t, int reg)
719 {
720 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
721 }
722
723 static inline void gen_store_spr(int reg, TCGv t)
724 {
725 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
726 }
727
728 /* Invalid instruction */
729 static void gen_invalid(DisasContext *ctx)
730 {
731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
732 }
733
734 static opc_handler_t invalid_handler = {
735 .inval1 = 0xFFFFFFFF,
736 .inval2 = 0xFFFFFFFF,
737 .type = PPC_NONE,
738 .type2 = PPC_NONE,
739 .handler = gen_invalid,
740 };
741
742 /*** Integer comparison ***/
743
744 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_temp_new();
747 TCGv_i32 t1 = tcg_temp_new_i32();
748
749 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
750
751 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
752 tcg_gen_trunc_tl_i32(t1, t0);
753 tcg_gen_shli_i32(t1, t1, CRF_LT);
754 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
755
756 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
757 tcg_gen_trunc_tl_i32(t1, t0);
758 tcg_gen_shli_i32(t1, t1, CRF_GT);
759 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
760
761 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
762 tcg_gen_trunc_tl_i32(t1, t0);
763 tcg_gen_shli_i32(t1, t1, CRF_EQ);
764 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
765
766 tcg_temp_free(t0);
767 tcg_temp_free_i32(t1);
768 }
769
770 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
771 {
772 TCGv t0 = tcg_const_tl(arg1);
773 gen_op_cmp(arg0, t0, s, crf);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
778 {
779 TCGv t0, t1;
780 t0 = tcg_temp_new();
781 t1 = tcg_temp_new();
782 if (s) {
783 tcg_gen_ext32s_tl(t0, arg0);
784 tcg_gen_ext32s_tl(t1, arg1);
785 } else {
786 tcg_gen_ext32u_tl(t0, arg0);
787 tcg_gen_ext32u_tl(t1, arg1);
788 }
789 gen_op_cmp(t0, t1, s, crf);
790 tcg_temp_free(t1);
791 tcg_temp_free(t0);
792 }
793
794 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
795 {
796 TCGv t0 = tcg_const_tl(arg1);
797 gen_op_cmp32(arg0, t0, s, crf);
798 tcg_temp_free(t0);
799 }
800
801 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
802 {
803 if (NARROW_MODE(ctx)) {
804 gen_op_cmpi32(reg, 0, 1, 0);
805 } else {
806 gen_op_cmpi(reg, 0, 1, 0);
807 }
808 }
809
810 /* cmp */
811 static void gen_cmp(DisasContext *ctx)
812 {
813 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 1, crfD(ctx->opcode));
816 } else {
817 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 1, crfD(ctx->opcode));
819 }
820 }
821
822 /* cmpi */
823 static void gen_cmpi(DisasContext *ctx)
824 {
825 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
826 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
827 1, crfD(ctx->opcode));
828 } else {
829 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
830 1, crfD(ctx->opcode));
831 }
832 }
833
834 /* cmpl */
835 static void gen_cmpl(DisasContext *ctx)
836 {
837 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
838 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
839 0, crfD(ctx->opcode));
840 } else {
841 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
842 0, crfD(ctx->opcode));
843 }
844 }
845
846 /* cmpli */
847 static void gen_cmpli(DisasContext *ctx)
848 {
849 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
850 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
851 0, crfD(ctx->opcode));
852 } else {
853 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
854 0, crfD(ctx->opcode));
855 }
856 }
857
858 /* cmprb - range comparison: isupper, isaplha, islower*/
859 static void gen_cmprb(DisasContext *ctx)
860 {
861 TCGv_i32 src1 = tcg_temp_new_i32();
862 TCGv_i32 src2 = tcg_temp_new_i32();
863 TCGv_i32 src2lo = tcg_temp_new_i32();
864 TCGv_i32 src2hi = tcg_temp_new_i32();
865 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
866
867 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
868 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
869
870 tcg_gen_andi_i32(src1, src1, 0xFF);
871 tcg_gen_ext8u_i32(src2lo, src2);
872 tcg_gen_shri_i32(src2, src2, 8);
873 tcg_gen_ext8u_i32(src2hi, src2);
874
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
876 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
877 tcg_gen_and_i32(crf, src2lo, src2hi);
878
879 if (ctx->opcode & 0x00200000) {
880 tcg_gen_shri_i32(src2, src2, 8);
881 tcg_gen_ext8u_i32(src2lo, src2);
882 tcg_gen_shri_i32(src2, src2, 8);
883 tcg_gen_ext8u_i32(src2hi, src2);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
885 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
886 tcg_gen_and_i32(src2lo, src2lo, src2hi);
887 tcg_gen_or_i32(crf, crf, src2lo);
888 }
889 tcg_gen_shli_i32(crf, crf, CRF_GT);
890 tcg_temp_free_i32(src1);
891 tcg_temp_free_i32(src2);
892 tcg_temp_free_i32(src2lo);
893 tcg_temp_free_i32(src2hi);
894 }
895
896 #if defined(TARGET_PPC64)
897 /* cmpeqb */
898 static void gen_cmpeqb(DisasContext *ctx)
899 {
900 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
901 cpu_gpr[rB(ctx->opcode)]);
902 }
903 #endif
904
905 /* isel (PowerPC 2.03 specification) */
906 static void gen_isel(DisasContext *ctx)
907 {
908 uint32_t bi = rC(ctx->opcode);
909 uint32_t mask = 0x08 >> (bi & 0x03);
910 TCGv t0 = tcg_temp_new();
911 TCGv zr;
912
913 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
914 tcg_gen_andi_tl(t0, t0, mask);
915
916 zr = tcg_const_tl(0);
917 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
918 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
919 cpu_gpr[rB(ctx->opcode)]);
920 tcg_temp_free(zr);
921 tcg_temp_free(t0);
922 }
923
924 /* cmpb: PowerPC 2.05 specification */
925 static void gen_cmpb(DisasContext *ctx)
926 {
927 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
928 cpu_gpr[rB(ctx->opcode)]);
929 }
930
931 /*** Integer arithmetic ***/
932
933 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
934 TCGv arg1, TCGv arg2, int sub)
935 {
936 TCGv t0 = tcg_temp_new();
937
938 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
939 tcg_gen_xor_tl(t0, arg1, arg2);
940 if (sub) {
941 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
942 } else {
943 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
944 }
945 tcg_temp_free(t0);
946 if (NARROW_MODE(ctx)) {
947 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
948 }
949 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
950 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
951 }
952
953 /* Common add function */
954 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, bool add_ca, bool compute_ca,
956 bool compute_ov, bool compute_rc0)
957 {
958 TCGv t0 = ret;
959
960 if (compute_ca || compute_ov) {
961 t0 = tcg_temp_new();
962 }
963
964 if (compute_ca) {
965 if (NARROW_MODE(ctx)) {
966 /* Caution: a non-obvious corner case of the spec is that we
967 must produce the *entire* 64-bit addition, but produce the
968 carry into bit 32. */
969 TCGv t1 = tcg_temp_new();
970 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
971 tcg_gen_add_tl(t0, arg1, arg2);
972 if (add_ca) {
973 tcg_gen_add_tl(t0, t0, cpu_ca);
974 }
975 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
976 tcg_temp_free(t1);
977 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
978 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
979 } else {
980 TCGv zero = tcg_const_tl(0);
981 if (add_ca) {
982 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
983 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
984 } else {
985 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
986 }
987 tcg_temp_free(zero);
988 }
989 } else {
990 tcg_gen_add_tl(t0, arg1, arg2);
991 if (add_ca) {
992 tcg_gen_add_tl(t0, t0, cpu_ca);
993 }
994 }
995
996 if (compute_ov) {
997 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
998 }
999 if (unlikely(compute_rc0)) {
1000 gen_set_Rc0(ctx, t0);
1001 }
1002
1003 if (!TCGV_EQUAL(t0, ret)) {
1004 tcg_gen_mov_tl(ret, t0);
1005 tcg_temp_free(t0);
1006 }
1007 }
1008 /* Add functions with two operands */
1009 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1015 }
1016 /* Add functions with one operand and one immediate */
1017 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1018 add_ca, compute_ca, compute_ov) \
1019 static void glue(gen_, name)(DisasContext *ctx) \
1020 { \
1021 TCGv t0 = tcg_const_tl(const_val); \
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1023 cpu_gpr[rA(ctx->opcode)], t0, \
1024 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1025 tcg_temp_free(t0); \
1026 }
1027
1028 /* add add. addo addo. */
1029 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1030 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1031 /* addc addc. addco addco. */
1032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1034 /* adde adde. addeo addeo. */
1035 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1036 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1037 /* addme addme. addmeo addmeo. */
1038 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1039 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1040 /* addze addze. addzeo addzeo.*/
1041 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1042 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1043 /* addi */
1044 static void gen_addi(DisasContext *ctx)
1045 {
1046 target_long simm = SIMM(ctx->opcode);
1047
1048 if (rA(ctx->opcode) == 0) {
1049 /* li case */
1050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1051 } else {
1052 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1053 cpu_gpr[rA(ctx->opcode)], simm);
1054 }
1055 }
1056 /* addic addic.*/
1057 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1058 {
1059 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1060 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1061 c, 0, 1, 0, compute_rc0);
1062 tcg_temp_free(c);
1063 }
1064
1065 static void gen_addic(DisasContext *ctx)
1066 {
1067 gen_op_addic(ctx, 0);
1068 }
1069
1070 static void gen_addic_(DisasContext *ctx)
1071 {
1072 gen_op_addic(ctx, 1);
1073 }
1074
1075 /* addis */
1076 static void gen_addis(DisasContext *ctx)
1077 {
1078 target_long simm = SIMM(ctx->opcode);
1079
1080 if (rA(ctx->opcode) == 0) {
1081 /* lis case */
1082 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1083 } else {
1084 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], simm << 16);
1086 }
1087 }
1088
1089 /* addpcis */
1090 static void gen_addpcis(DisasContext *ctx)
1091 {
1092 target_long d = DX(ctx->opcode);
1093
1094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1095 }
1096
1097 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1098 TCGv arg2, int sign, int compute_ov)
1099 {
1100 TCGLabel *l1 = gen_new_label();
1101 TCGLabel *l2 = gen_new_label();
1102 TCGv_i32 t0 = tcg_temp_local_new_i32();
1103 TCGv_i32 t1 = tcg_temp_local_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, arg1);
1106 tcg_gen_trunc_tl_i32(t1, arg2);
1107 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1108 if (sign) {
1109 TCGLabel *l3 = gen_new_label();
1110 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1111 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1112 gen_set_label(l3);
1113 tcg_gen_div_i32(t0, t0, t1);
1114 } else {
1115 tcg_gen_divu_i32(t0, t0, t1);
1116 }
1117 if (compute_ov) {
1118 tcg_gen_movi_tl(cpu_ov, 0);
1119 }
1120 tcg_gen_br(l2);
1121 gen_set_label(l1);
1122 if (sign) {
1123 tcg_gen_sari_i32(t0, t0, 31);
1124 } else {
1125 tcg_gen_movi_i32(t0, 0);
1126 }
1127 if (compute_ov) {
1128 tcg_gen_movi_tl(cpu_ov, 1);
1129 tcg_gen_movi_tl(cpu_so, 1);
1130 }
1131 gen_set_label(l2);
1132 tcg_gen_extu_i32_tl(ret, t0);
1133 tcg_temp_free_i32(t0);
1134 tcg_temp_free_i32(t1);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, ret);
1137 }
1138 /* Div functions */
1139 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1140 static void glue(gen_, name)(DisasContext *ctx) \
1141 { \
1142 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1143 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1144 sign, compute_ov); \
1145 }
1146 /* divwu divwu. divwuo divwuo. */
1147 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1148 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1149 /* divw divw. divwo divwo. */
1150 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1151 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1152
1153 /* div[wd]eu[o][.] */
1154 #define GEN_DIVE(name, hlpr, compute_ov) \
1155 static void gen_##name(DisasContext *ctx) \
1156 { \
1157 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1158 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1160 tcg_temp_free_i32(t0); \
1161 if (unlikely(Rc(ctx->opcode) != 0)) { \
1162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1163 } \
1164 }
1165
1166 GEN_DIVE(divweu, divweu, 0);
1167 GEN_DIVE(divweuo, divweu, 1);
1168 GEN_DIVE(divwe, divwe, 0);
1169 GEN_DIVE(divweo, divwe, 1);
1170
1171 #if defined(TARGET_PPC64)
1172 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1173 TCGv arg2, int sign, int compute_ov)
1174 {
1175 TCGLabel *l1 = gen_new_label();
1176 TCGLabel *l2 = gen_new_label();
1177
1178 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1179 if (sign) {
1180 TCGLabel *l3 = gen_new_label();
1181 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1182 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1183 gen_set_label(l3);
1184 tcg_gen_div_i64(ret, arg1, arg2);
1185 } else {
1186 tcg_gen_divu_i64(ret, arg1, arg2);
1187 }
1188 if (compute_ov) {
1189 tcg_gen_movi_tl(cpu_ov, 0);
1190 }
1191 tcg_gen_br(l2);
1192 gen_set_label(l1);
1193 if (sign) {
1194 tcg_gen_sari_i64(ret, arg1, 63);
1195 } else {
1196 tcg_gen_movi_i64(ret, 0);
1197 }
1198 if (compute_ov) {
1199 tcg_gen_movi_tl(cpu_ov, 1);
1200 tcg_gen_movi_tl(cpu_so, 1);
1201 }
1202 gen_set_label(l2);
1203 if (unlikely(Rc(ctx->opcode) != 0))
1204 gen_set_Rc0(ctx, ret);
1205 }
1206 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1207 static void glue(gen_, name)(DisasContext *ctx) \
1208 { \
1209 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1210 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1211 sign, compute_ov); \
1212 }
1213 /* divwu divwu. divwuo divwuo. */
1214 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1215 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1216 /* divw divw. divwo divwo. */
1217 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1218 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1219
1220 GEN_DIVE(divdeu, divdeu, 0);
1221 GEN_DIVE(divdeuo, divdeu, 1);
1222 GEN_DIVE(divde, divde, 0);
1223 GEN_DIVE(divdeo, divde, 1);
1224 #endif
1225
1226 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1227 TCGv arg2, int sign)
1228 {
1229 TCGv_i32 t0 = tcg_temp_new_i32();
1230 TCGv_i32 t1 = tcg_temp_new_i32();
1231
1232 tcg_gen_trunc_tl_i32(t0, arg1);
1233 tcg_gen_trunc_tl_i32(t1, arg2);
1234 if (sign) {
1235 TCGv_i32 t2 = tcg_temp_new_i32();
1236 TCGv_i32 t3 = tcg_temp_new_i32();
1237 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1238 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1239 tcg_gen_and_i32(t2, t2, t3);
1240 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1241 tcg_gen_or_i32(t2, t2, t3);
1242 tcg_gen_movi_i32(t3, 0);
1243 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1244 tcg_gen_rem_i32(t3, t0, t1);
1245 tcg_gen_ext_i32_tl(ret, t3);
1246 tcg_temp_free_i32(t2);
1247 tcg_temp_free_i32(t3);
1248 } else {
1249 TCGv_i32 t2 = tcg_const_i32(1);
1250 TCGv_i32 t3 = tcg_const_i32(0);
1251 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1252 tcg_gen_remu_i32(t3, t0, t1);
1253 tcg_gen_extu_i32_tl(ret, t3);
1254 tcg_temp_free_i32(t2);
1255 tcg_temp_free_i32(t3);
1256 }
1257 tcg_temp_free_i32(t0);
1258 tcg_temp_free_i32(t1);
1259 }
1260
1261 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1262 static void glue(gen_, name)(DisasContext *ctx) \
1263 { \
1264 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1265 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1266 sign); \
1267 }
1268
1269 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1270 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1271
1272 #if defined(TARGET_PPC64)
1273 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1274 TCGv arg2, int sign)
1275 {
1276 TCGv_i64 t0 = tcg_temp_new_i64();
1277 TCGv_i64 t1 = tcg_temp_new_i64();
1278
1279 tcg_gen_mov_i64(t0, arg1);
1280 tcg_gen_mov_i64(t1, arg2);
1281 if (sign) {
1282 TCGv_i64 t2 = tcg_temp_new_i64();
1283 TCGv_i64 t3 = tcg_temp_new_i64();
1284 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1285 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1286 tcg_gen_and_i64(t2, t2, t3);
1287 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1288 tcg_gen_or_i64(t2, t2, t3);
1289 tcg_gen_movi_i64(t3, 0);
1290 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1291 tcg_gen_rem_i64(ret, t0, t1);
1292 tcg_temp_free_i64(t2);
1293 tcg_temp_free_i64(t3);
1294 } else {
1295 TCGv_i64 t2 = tcg_const_i64(1);
1296 TCGv_i64 t3 = tcg_const_i64(0);
1297 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1298 tcg_gen_remu_i64(ret, t0, t1);
1299 tcg_temp_free_i64(t2);
1300 tcg_temp_free_i64(t3);
1301 }
1302 tcg_temp_free_i64(t0);
1303 tcg_temp_free_i64(t1);
1304 }
1305
1306 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1310 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1311 sign); \
1312 }
1313
1314 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1315 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1316 #endif
1317
1318 /* mulhw mulhw. */
1319 static void gen_mulhw(DisasContext *ctx)
1320 {
1321 TCGv_i32 t0 = tcg_temp_new_i32();
1322 TCGv_i32 t1 = tcg_temp_new_i32();
1323
1324 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1325 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1326 tcg_gen_muls2_i32(t0, t1, t0, t1);
1327 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1328 tcg_temp_free_i32(t0);
1329 tcg_temp_free_i32(t1);
1330 if (unlikely(Rc(ctx->opcode) != 0))
1331 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1332 }
1333
1334 /* mulhwu mulhwu. */
1335 static void gen_mulhwu(DisasContext *ctx)
1336 {
1337 TCGv_i32 t0 = tcg_temp_new_i32();
1338 TCGv_i32 t1 = tcg_temp_new_i32();
1339
1340 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1341 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1342 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1343 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1344 tcg_temp_free_i32(t0);
1345 tcg_temp_free_i32(t1);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mullw mullw. */
1351 static void gen_mullw(DisasContext *ctx)
1352 {
1353 #if defined(TARGET_PPC64)
1354 TCGv_i64 t0, t1;
1355 t0 = tcg_temp_new_i64();
1356 t1 = tcg_temp_new_i64();
1357 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1358 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1359 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1360 tcg_temp_free(t0);
1361 tcg_temp_free(t1);
1362 #else
1363 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 cpu_gpr[rB(ctx->opcode)]);
1365 #endif
1366 if (unlikely(Rc(ctx->opcode) != 0))
1367 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1368 }
1369
1370 /* mullwo mullwo. */
1371 static void gen_mullwo(DisasContext *ctx)
1372 {
1373 TCGv_i32 t0 = tcg_temp_new_i32();
1374 TCGv_i32 t1 = tcg_temp_new_i32();
1375
1376 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1377 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1378 tcg_gen_muls2_i32(t0, t1, t0, t1);
1379 #if defined(TARGET_PPC64)
1380 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1381 #else
1382 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1383 #endif
1384
1385 tcg_gen_sari_i32(t0, t0, 31);
1386 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1387 tcg_gen_extu_i32_tl(cpu_ov, t0);
1388 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1389
1390 tcg_temp_free_i32(t0);
1391 tcg_temp_free_i32(t1);
1392 if (unlikely(Rc(ctx->opcode) != 0))
1393 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1394 }
1395
1396 /* mulli */
1397 static void gen_mulli(DisasContext *ctx)
1398 {
1399 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1400 SIMM(ctx->opcode));
1401 }
1402
1403 #if defined(TARGET_PPC64)
1404 /* mulhd mulhd. */
1405 static void gen_mulhd(DisasContext *ctx)
1406 {
1407 TCGv lo = tcg_temp_new();
1408 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1410 tcg_temp_free(lo);
1411 if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1413 }
1414 }
1415
1416 /* mulhdu mulhdu. */
1417 static void gen_mulhdu(DisasContext *ctx)
1418 {
1419 TCGv lo = tcg_temp_new();
1420 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1421 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1422 tcg_temp_free(lo);
1423 if (unlikely(Rc(ctx->opcode) != 0)) {
1424 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1425 }
1426 }
1427
1428 /* mulld mulld. */
1429 static void gen_mulld(DisasContext *ctx)
1430 {
1431 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1432 cpu_gpr[rB(ctx->opcode)]);
1433 if (unlikely(Rc(ctx->opcode) != 0))
1434 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1435 }
1436
1437 /* mulldo mulldo. */
1438 static void gen_mulldo(DisasContext *ctx)
1439 {
1440 TCGv_i64 t0 = tcg_temp_new_i64();
1441 TCGv_i64 t1 = tcg_temp_new_i64();
1442
1443 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1444 cpu_gpr[rB(ctx->opcode)]);
1445 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1446
1447 tcg_gen_sari_i64(t0, t0, 63);
1448 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1449 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1450
1451 tcg_temp_free_i64(t0);
1452 tcg_temp_free_i64(t1);
1453
1454 if (unlikely(Rc(ctx->opcode) != 0)) {
1455 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1456 }
1457 }
1458 #endif
1459
1460 /* Common subf function */
1461 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1462 TCGv arg2, bool add_ca, bool compute_ca,
1463 bool compute_ov, bool compute_rc0)
1464 {
1465 TCGv t0 = ret;
1466
1467 if (compute_ca || compute_ov) {
1468 t0 = tcg_temp_new();
1469 }
1470
1471 if (compute_ca) {
1472 /* dest = ~arg1 + arg2 [+ ca]. */
1473 if (NARROW_MODE(ctx)) {
1474 /* Caution: a non-obvious corner case of the spec is that we
1475 must produce the *entire* 64-bit addition, but produce the
1476 carry into bit 32. */
1477 TCGv inv1 = tcg_temp_new();
1478 TCGv t1 = tcg_temp_new();
1479 tcg_gen_not_tl(inv1, arg1);
1480 if (add_ca) {
1481 tcg_gen_add_tl(t0, arg2, cpu_ca);
1482 } else {
1483 tcg_gen_addi_tl(t0, arg2, 1);
1484 }
1485 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1486 tcg_gen_add_tl(t0, t0, inv1);
1487 tcg_temp_free(inv1);
1488 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1489 tcg_temp_free(t1);
1490 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1491 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1492 } else if (add_ca) {
1493 TCGv zero, inv1 = tcg_temp_new();
1494 tcg_gen_not_tl(inv1, arg1);
1495 zero = tcg_const_tl(0);
1496 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1497 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1498 tcg_temp_free(zero);
1499 tcg_temp_free(inv1);
1500 } else {
1501 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1502 tcg_gen_sub_tl(t0, arg2, arg1);
1503 }
1504 } else if (add_ca) {
1505 /* Since we're ignoring carry-out, we can simplify the
1506 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1507 tcg_gen_sub_tl(t0, arg2, arg1);
1508 tcg_gen_add_tl(t0, t0, cpu_ca);
1509 tcg_gen_subi_tl(t0, t0, 1);
1510 } else {
1511 tcg_gen_sub_tl(t0, arg2, arg1);
1512 }
1513
1514 if (compute_ov) {
1515 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1516 }
1517 if (unlikely(compute_rc0)) {
1518 gen_set_Rc0(ctx, t0);
1519 }
1520
1521 if (!TCGV_EQUAL(t0, ret)) {
1522 tcg_gen_mov_tl(ret, t0);
1523 tcg_temp_free(t0);
1524 }
1525 }
1526 /* Sub functions with Two operands functions */
1527 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1528 static void glue(gen_, name)(DisasContext *ctx) \
1529 { \
1530 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1531 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1532 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1533 }
1534 /* Sub functions with one operand and one immediate */
1535 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1536 add_ca, compute_ca, compute_ov) \
1537 static void glue(gen_, name)(DisasContext *ctx) \
1538 { \
1539 TCGv t0 = tcg_const_tl(const_val); \
1540 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1541 cpu_gpr[rA(ctx->opcode)], t0, \
1542 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1543 tcg_temp_free(t0); \
1544 }
1545 /* subf subf. subfo subfo. */
1546 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1547 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1548 /* subfc subfc. subfco subfco. */
1549 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1550 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1551 /* subfe subfe. subfeo subfo. */
1552 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1553 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1554 /* subfme subfme. subfmeo subfmeo. */
1555 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1556 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1557 /* subfze subfze. subfzeo subfzeo.*/
1558 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1559 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1560
1561 /* subfic */
1562 static void gen_subfic(DisasContext *ctx)
1563 {
1564 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1565 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1566 c, 0, 1, 0, 0);
1567 tcg_temp_free(c);
1568 }
1569
1570 /* neg neg. nego nego. */
1571 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1572 {
1573 TCGv zero = tcg_const_tl(0);
1574 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1575 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1576 tcg_temp_free(zero);
1577 }
1578
1579 static void gen_neg(DisasContext *ctx)
1580 {
1581 gen_op_arith_neg(ctx, 0);
1582 }
1583
1584 static void gen_nego(DisasContext *ctx)
1585 {
1586 gen_op_arith_neg(ctx, 1);
1587 }
1588
1589 /*** Integer logical ***/
1590 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1591 static void glue(gen_, name)(DisasContext *ctx) \
1592 { \
1593 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1594 cpu_gpr[rB(ctx->opcode)]); \
1595 if (unlikely(Rc(ctx->opcode) != 0)) \
1596 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1597 }
1598
1599 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1600 static void glue(gen_, name)(DisasContext *ctx) \
1601 { \
1602 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1603 if (unlikely(Rc(ctx->opcode) != 0)) \
1604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1605 }
1606
1607 /* and & and. */
1608 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1609 /* andc & andc. */
1610 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1611
1612 /* andi. */
1613 static void gen_andi_(DisasContext *ctx)
1614 {
1615 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1616 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1617 }
1618
1619 /* andis. */
1620 static void gen_andis_(DisasContext *ctx)
1621 {
1622 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625
1626 /* cntlzw */
1627 static void gen_cntlzw(DisasContext *ctx)
1628 {
1629 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632 }
1633
1634 /* cnttzw */
1635 static void gen_cnttzw(DisasContext *ctx)
1636 {
1637 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1638 if (unlikely(Rc(ctx->opcode) != 0)) {
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641 }
1642
1643 /* eqv & eqv. */
1644 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1645 /* extsb & extsb. */
1646 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1647 /* extsh & extsh. */
1648 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1649 /* nand & nand. */
1650 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1651 /* nor & nor. */
1652 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1653
1654 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1655 static void gen_pause(DisasContext *ctx)
1656 {
1657 TCGv_i32 t0 = tcg_const_i32(0);
1658 tcg_gen_st_i32(t0, cpu_env,
1659 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1660 tcg_temp_free_i32(t0);
1661
1662 /* Stop translation, this gives other CPUs a chance to run */
1663 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1664 }
1665 #endif /* defined(TARGET_PPC64) */
1666
1667 /* or & or. */
1668 static void gen_or(DisasContext *ctx)
1669 {
1670 int rs, ra, rb;
1671
1672 rs = rS(ctx->opcode);
1673 ra = rA(ctx->opcode);
1674 rb = rB(ctx->opcode);
1675 /* Optimisation for mr. ri case */
1676 if (rs != ra || rs != rb) {
1677 if (rs != rb)
1678 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1679 else
1680 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[ra]);
1683 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1684 gen_set_Rc0(ctx, cpu_gpr[rs]);
1685 #if defined(TARGET_PPC64)
1686 } else if (rs != 0) { /* 0 is nop */
1687 int prio = 0;
1688
1689 switch (rs) {
1690 case 1:
1691 /* Set process priority to low */
1692 prio = 2;
1693 break;
1694 case 6:
1695 /* Set process priority to medium-low */
1696 prio = 3;
1697 break;
1698 case 2:
1699 /* Set process priority to normal */
1700 prio = 4;
1701 break;
1702 #if !defined(CONFIG_USER_ONLY)
1703 case 31:
1704 if (!ctx->pr) {
1705 /* Set process priority to very low */
1706 prio = 1;
1707 }
1708 break;
1709 case 5:
1710 if (!ctx->pr) {
1711 /* Set process priority to medium-hight */
1712 prio = 5;
1713 }
1714 break;
1715 case 3:
1716 if (!ctx->pr) {
1717 /* Set process priority to high */
1718 prio = 6;
1719 }
1720 break;
1721 case 7:
1722 if (ctx->hv && !ctx->pr) {
1723 /* Set process priority to very high */
1724 prio = 7;
1725 }
1726 break;
1727 #endif
1728 default:
1729 break;
1730 }
1731 if (prio) {
1732 TCGv t0 = tcg_temp_new();
1733 gen_load_spr(t0, SPR_PPR);
1734 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1735 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1736 gen_store_spr(SPR_PPR, t0);
1737 tcg_temp_free(t0);
1738 }
1739 #if !defined(CONFIG_USER_ONLY)
1740 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1741 * CPU and the kernel hangs. This applies to all encodings other
1742 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1743 * and all currently undefined.
1744 */
1745 gen_pause(ctx);
1746 #endif
1747 #endif
1748 }
1749 }
1750 /* orc & orc. */
1751 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1752
1753 /* xor & xor. */
1754 static void gen_xor(DisasContext *ctx)
1755 {
1756 /* Optimisation for "set to zero" case */
1757 if (rS(ctx->opcode) != rB(ctx->opcode))
1758 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1759 else
1760 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1761 if (unlikely(Rc(ctx->opcode) != 0))
1762 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1763 }
1764
1765 /* ori */
1766 static void gen_ori(DisasContext *ctx)
1767 {
1768 target_ulong uimm = UIMM(ctx->opcode);
1769
1770 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1771 return;
1772 }
1773 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1774 }
1775
1776 /* oris */
1777 static void gen_oris(DisasContext *ctx)
1778 {
1779 target_ulong uimm = UIMM(ctx->opcode);
1780
1781 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1782 /* NOP */
1783 return;
1784 }
1785 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1786 }
1787
1788 /* xori */
1789 static void gen_xori(DisasContext *ctx)
1790 {
1791 target_ulong uimm = UIMM(ctx->opcode);
1792
1793 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1794 /* NOP */
1795 return;
1796 }
1797 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1798 }
1799
1800 /* xoris */
1801 static void gen_xoris(DisasContext *ctx)
1802 {
1803 target_ulong uimm = UIMM(ctx->opcode);
1804
1805 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1806 /* NOP */
1807 return;
1808 }
1809 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1810 }
1811
1812 /* popcntb : PowerPC 2.03 specification */
1813 static void gen_popcntb(DisasContext *ctx)
1814 {
1815 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1816 }
1817
1818 static void gen_popcntw(DisasContext *ctx)
1819 {
1820 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1821 }
1822
1823 #if defined(TARGET_PPC64)
1824 /* popcntd: PowerPC 2.06 specification */
1825 static void gen_popcntd(DisasContext *ctx)
1826 {
1827 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 }
1829 #endif
1830
1831 /* prtyw: PowerPC 2.05 specification */
1832 static void gen_prtyw(DisasContext *ctx)
1833 {
1834 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1835 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1836 TCGv t0 = tcg_temp_new();
1837 tcg_gen_shri_tl(t0, rs, 16);
1838 tcg_gen_xor_tl(ra, rs, t0);
1839 tcg_gen_shri_tl(t0, ra, 8);
1840 tcg_gen_xor_tl(ra, ra, t0);
1841 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1842 tcg_temp_free(t0);
1843 }
1844
1845 #if defined(TARGET_PPC64)
1846 /* prtyd: PowerPC 2.05 specification */
1847 static void gen_prtyd(DisasContext *ctx)
1848 {
1849 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1850 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1851 TCGv t0 = tcg_temp_new();
1852 tcg_gen_shri_tl(t0, rs, 32);
1853 tcg_gen_xor_tl(ra, rs, t0);
1854 tcg_gen_shri_tl(t0, ra, 16);
1855 tcg_gen_xor_tl(ra, ra, t0);
1856 tcg_gen_shri_tl(t0, ra, 8);
1857 tcg_gen_xor_tl(ra, ra, t0);
1858 tcg_gen_andi_tl(ra, ra, 1);
1859 tcg_temp_free(t0);
1860 }
1861 #endif
1862
1863 #if defined(TARGET_PPC64)
1864 /* bpermd */
1865 static void gen_bpermd(DisasContext *ctx)
1866 {
1867 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1868 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1869 }
1870 #endif
1871
1872 #if defined(TARGET_PPC64)
1873 /* extsw & extsw. */
1874 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1875
1876 /* cntlzd */
1877 static void gen_cntlzd(DisasContext *ctx)
1878 {
1879 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* cnttzd */
1885 static void gen_cnttzd(DisasContext *ctx)
1886 {
1887 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1888 if (unlikely(Rc(ctx->opcode) != 0)) {
1889 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1890 }
1891 }
1892 #endif
1893
1894 /*** Integer rotate ***/
1895
1896 /* rlwimi & rlwimi. */
1897 static void gen_rlwimi(DisasContext *ctx)
1898 {
1899 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1900 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1901 uint32_t sh = SH(ctx->opcode);
1902 uint32_t mb = MB(ctx->opcode);
1903 uint32_t me = ME(ctx->opcode);
1904
1905 if (sh == (31-me) && mb <= me) {
1906 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1907 } else {
1908 target_ulong mask;
1909 TCGv t1;
1910
1911 #if defined(TARGET_PPC64)
1912 mb += 32;
1913 me += 32;
1914 #endif
1915 mask = MASK(mb, me);
1916
1917 t1 = tcg_temp_new();
1918 if (mask <= 0xffffffffu) {
1919 TCGv_i32 t0 = tcg_temp_new_i32();
1920 tcg_gen_trunc_tl_i32(t0, t_rs);
1921 tcg_gen_rotli_i32(t0, t0, sh);
1922 tcg_gen_extu_i32_tl(t1, t0);
1923 tcg_temp_free_i32(t0);
1924 } else {
1925 #if defined(TARGET_PPC64)
1926 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1927 tcg_gen_rotli_i64(t1, t1, sh);
1928 #else
1929 g_assert_not_reached();
1930 #endif
1931 }
1932
1933 tcg_gen_andi_tl(t1, t1, mask);
1934 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1935 tcg_gen_or_tl(t_ra, t_ra, t1);
1936 tcg_temp_free(t1);
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, t_ra);
1940 }
1941 }
1942
1943 /* rlwinm & rlwinm. */
1944 static void gen_rlwinm(DisasContext *ctx)
1945 {
1946 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1947 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1948 uint32_t sh = SH(ctx->opcode);
1949 uint32_t mb = MB(ctx->opcode);
1950 uint32_t me = ME(ctx->opcode);
1951
1952 if (mb == 0 && me == (31 - sh)) {
1953 tcg_gen_shli_tl(t_ra, t_rs, sh);
1954 tcg_gen_ext32u_tl(t_ra, t_ra);
1955 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1956 tcg_gen_ext32u_tl(t_ra, t_rs);
1957 tcg_gen_shri_tl(t_ra, t_ra, mb);
1958 } else {
1959 target_ulong mask;
1960 #if defined(TARGET_PPC64)
1961 mb += 32;
1962 me += 32;
1963 #endif
1964 mask = MASK(mb, me);
1965
1966 if (mask <= 0xffffffffu) {
1967 TCGv_i32 t0 = tcg_temp_new_i32();
1968 tcg_gen_trunc_tl_i32(t0, t_rs);
1969 tcg_gen_rotli_i32(t0, t0, sh);
1970 tcg_gen_andi_i32(t0, t0, mask);
1971 tcg_gen_extu_i32_tl(t_ra, t0);
1972 tcg_temp_free_i32(t0);
1973 } else {
1974 #if defined(TARGET_PPC64)
1975 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1976 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1977 tcg_gen_andi_i64(t_ra, t_ra, mask);
1978 #else
1979 g_assert_not_reached();
1980 #endif
1981 }
1982 }
1983 if (unlikely(Rc(ctx->opcode) != 0)) {
1984 gen_set_Rc0(ctx, t_ra);
1985 }
1986 }
1987
1988 /* rlwnm & rlwnm. */
1989 static void gen_rlwnm(DisasContext *ctx)
1990 {
1991 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1992 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1993 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1994 uint32_t mb = MB(ctx->opcode);
1995 uint32_t me = ME(ctx->opcode);
1996 target_ulong mask;
1997
1998 #if defined(TARGET_PPC64)
1999 mb += 32;
2000 me += 32;
2001 #endif
2002 mask = MASK(mb, me);
2003
2004 if (mask <= 0xffffffffu) {
2005 TCGv_i32 t0 = tcg_temp_new_i32();
2006 TCGv_i32 t1 = tcg_temp_new_i32();
2007 tcg_gen_trunc_tl_i32(t0, t_rb);
2008 tcg_gen_trunc_tl_i32(t1, t_rs);
2009 tcg_gen_andi_i32(t0, t0, 0x1f);
2010 tcg_gen_rotl_i32(t1, t1, t0);
2011 tcg_gen_extu_i32_tl(t_ra, t1);
2012 tcg_temp_free_i32(t0);
2013 tcg_temp_free_i32(t1);
2014 } else {
2015 #if defined(TARGET_PPC64)
2016 TCGv_i64 t0 = tcg_temp_new_i64();
2017 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2018 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2019 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2020 tcg_temp_free_i64(t0);
2021 #else
2022 g_assert_not_reached();
2023 #endif
2024 }
2025
2026 tcg_gen_andi_tl(t_ra, t_ra, mask);
2027
2028 if (unlikely(Rc(ctx->opcode) != 0)) {
2029 gen_set_Rc0(ctx, t_ra);
2030 }
2031 }
2032
2033 #if defined(TARGET_PPC64)
2034 #define GEN_PPC64_R2(name, opc1, opc2) \
2035 static void glue(gen_, name##0)(DisasContext *ctx) \
2036 { \
2037 gen_##name(ctx, 0); \
2038 } \
2039 \
2040 static void glue(gen_, name##1)(DisasContext *ctx) \
2041 { \
2042 gen_##name(ctx, 1); \
2043 }
2044 #define GEN_PPC64_R4(name, opc1, opc2) \
2045 static void glue(gen_, name##0)(DisasContext *ctx) \
2046 { \
2047 gen_##name(ctx, 0, 0); \
2048 } \
2049 \
2050 static void glue(gen_, name##1)(DisasContext *ctx) \
2051 { \
2052 gen_##name(ctx, 0, 1); \
2053 } \
2054 \
2055 static void glue(gen_, name##2)(DisasContext *ctx) \
2056 { \
2057 gen_##name(ctx, 1, 0); \
2058 } \
2059 \
2060 static void glue(gen_, name##3)(DisasContext *ctx) \
2061 { \
2062 gen_##name(ctx, 1, 1); \
2063 }
2064
2065 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2066 {
2067 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2068 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2069
2070 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2071 tcg_gen_shli_tl(t_ra, t_rs, sh);
2072 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2073 tcg_gen_shri_tl(t_ra, t_rs, mb);
2074 } else {
2075 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2076 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2077 }
2078 if (unlikely(Rc(ctx->opcode) != 0)) {
2079 gen_set_Rc0(ctx, t_ra);
2080 }
2081 }
2082
2083 /* rldicl - rldicl. */
2084 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2085 {
2086 uint32_t sh, mb;
2087
2088 sh = SH(ctx->opcode) | (shn << 5);
2089 mb = MB(ctx->opcode) | (mbn << 5);
2090 gen_rldinm(ctx, mb, 63, sh);
2091 }
2092 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2093
2094 /* rldicr - rldicr. */
2095 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2096 {
2097 uint32_t sh, me;
2098
2099 sh = SH(ctx->opcode) | (shn << 5);
2100 me = MB(ctx->opcode) | (men << 5);
2101 gen_rldinm(ctx, 0, me, sh);
2102 }
2103 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2104
2105 /* rldic - rldic. */
2106 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2107 {
2108 uint32_t sh, mb;
2109
2110 sh = SH(ctx->opcode) | (shn << 5);
2111 mb = MB(ctx->opcode) | (mbn << 5);
2112 gen_rldinm(ctx, mb, 63 - sh, sh);
2113 }
2114 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2115
2116 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2117 {
2118 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2119 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2120 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2121 TCGv t0;
2122
2123 t0 = tcg_temp_new();
2124 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2125 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2126 tcg_temp_free(t0);
2127
2128 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2129 if (unlikely(Rc(ctx->opcode) != 0)) {
2130 gen_set_Rc0(ctx, t_ra);
2131 }
2132 }
2133
2134 /* rldcl - rldcl. */
2135 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2136 {
2137 uint32_t mb;
2138
2139 mb = MB(ctx->opcode) | (mbn << 5);
2140 gen_rldnm(ctx, mb, 63);
2141 }
2142 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2143
2144 /* rldcr - rldcr. */
2145 static inline void gen_rldcr(DisasContext *ctx, int men)
2146 {
2147 uint32_t me;
2148
2149 me = MB(ctx->opcode) | (men << 5);
2150 gen_rldnm(ctx, 0, me);
2151 }
2152 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2153
2154 /* rldimi - rldimi. */
2155 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2156 {
2157 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2158 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2159 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2160 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2161 uint32_t me = 63 - sh;
2162
2163 if (mb <= me) {
2164 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2165 } else {
2166 target_ulong mask = MASK(mb, me);
2167 TCGv t1 = tcg_temp_new();
2168
2169 tcg_gen_rotli_tl(t1, t_rs, sh);
2170 tcg_gen_andi_tl(t1, t1, mask);
2171 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2172 tcg_gen_or_tl(t_ra, t_ra, t1);
2173 tcg_temp_free(t1);
2174 }
2175 if (unlikely(Rc(ctx->opcode) != 0)) {
2176 gen_set_Rc0(ctx, t_ra);
2177 }
2178 }
2179 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2180 #endif
2181
2182 /*** Integer shift ***/
2183
2184 /* slw & slw. */
2185 static void gen_slw(DisasContext *ctx)
2186 {
2187 TCGv t0, t1;
2188
2189 t0 = tcg_temp_new();
2190 /* AND rS with a mask that is 0 when rB >= 0x20 */
2191 #if defined(TARGET_PPC64)
2192 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2193 tcg_gen_sari_tl(t0, t0, 0x3f);
2194 #else
2195 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2196 tcg_gen_sari_tl(t0, t0, 0x1f);
2197 #endif
2198 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2199 t1 = tcg_temp_new();
2200 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2201 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2202 tcg_temp_free(t1);
2203 tcg_temp_free(t0);
2204 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2205 if (unlikely(Rc(ctx->opcode) != 0))
2206 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2207 }
2208
2209 /* sraw & sraw. */
2210 static void gen_sraw(DisasContext *ctx)
2211 {
2212 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2213 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2214 if (unlikely(Rc(ctx->opcode) != 0))
2215 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2216 }
2217
2218 /* srawi & srawi. */
2219 static void gen_srawi(DisasContext *ctx)
2220 {
2221 int sh = SH(ctx->opcode);
2222 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2223 TCGv src = cpu_gpr[rS(ctx->opcode)];
2224 if (sh == 0) {
2225 tcg_gen_ext32s_tl(dst, src);
2226 tcg_gen_movi_tl(cpu_ca, 0);
2227 } else {
2228 TCGv t0;
2229 tcg_gen_ext32s_tl(dst, src);
2230 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2231 t0 = tcg_temp_new();
2232 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2233 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2234 tcg_temp_free(t0);
2235 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2236 tcg_gen_sari_tl(dst, dst, sh);
2237 }
2238 if (unlikely(Rc(ctx->opcode) != 0)) {
2239 gen_set_Rc0(ctx, dst);
2240 }
2241 }
2242
2243 /* srw & srw. */
2244 static void gen_srw(DisasContext *ctx)
2245 {
2246 TCGv t0, t1;
2247
2248 t0 = tcg_temp_new();
2249 /* AND rS with a mask that is 0 when rB >= 0x20 */
2250 #if defined(TARGET_PPC64)
2251 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2252 tcg_gen_sari_tl(t0, t0, 0x3f);
2253 #else
2254 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2255 tcg_gen_sari_tl(t0, t0, 0x1f);
2256 #endif
2257 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2258 tcg_gen_ext32u_tl(t0, t0);
2259 t1 = tcg_temp_new();
2260 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2261 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2262 tcg_temp_free(t1);
2263 tcg_temp_free(t0);
2264 if (unlikely(Rc(ctx->opcode) != 0))
2265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2266 }
2267
2268 #if defined(TARGET_PPC64)
2269 /* sld & sld. */
2270 static void gen_sld(DisasContext *ctx)
2271 {
2272 TCGv t0, t1;
2273
2274 t0 = tcg_temp_new();
2275 /* AND rS with a mask that is 0 when rB >= 0x40 */
2276 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2277 tcg_gen_sari_tl(t0, t0, 0x3f);
2278 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2279 t1 = tcg_temp_new();
2280 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2281 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2282 tcg_temp_free(t1);
2283 tcg_temp_free(t0);
2284 if (unlikely(Rc(ctx->opcode) != 0))
2285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2286 }
2287
2288 /* srad & srad. */
2289 static void gen_srad(DisasContext *ctx)
2290 {
2291 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2292 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2293 if (unlikely(Rc(ctx->opcode) != 0))
2294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2295 }
2296 /* sradi & sradi. */
2297 static inline void gen_sradi(DisasContext *ctx, int n)
2298 {
2299 int sh = SH(ctx->opcode) + (n << 5);
2300 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2301 TCGv src = cpu_gpr[rS(ctx->opcode)];
2302 if (sh == 0) {
2303 tcg_gen_mov_tl(dst, src);
2304 tcg_gen_movi_tl(cpu_ca, 0);
2305 } else {
2306 TCGv t0;
2307 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2308 t0 = tcg_temp_new();
2309 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2310 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2311 tcg_temp_free(t0);
2312 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2313 tcg_gen_sari_tl(dst, src, sh);
2314 }
2315 if (unlikely(Rc(ctx->opcode) != 0)) {
2316 gen_set_Rc0(ctx, dst);
2317 }
2318 }
2319
2320 static void gen_sradi0(DisasContext *ctx)
2321 {
2322 gen_sradi(ctx, 0);
2323 }
2324
2325 static void gen_sradi1(DisasContext *ctx)
2326 {
2327 gen_sradi(ctx, 1);
2328 }
2329
2330 /* srd & srd. */
2331 static void gen_srd(DisasContext *ctx)
2332 {
2333 TCGv t0, t1;
2334
2335 t0 = tcg_temp_new();
2336 /* AND rS with a mask that is 0 when rB >= 0x40 */
2337 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2338 tcg_gen_sari_tl(t0, t0, 0x3f);
2339 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2340 t1 = tcg_temp_new();
2341 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2342 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2343 tcg_temp_free(t1);
2344 tcg_temp_free(t0);
2345 if (unlikely(Rc(ctx->opcode) != 0))
2346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2347 }
2348 #endif
2349
2350 /*** Addressing modes ***/
2351 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2352 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2353 target_long maskl)
2354 {
2355 target_long simm = SIMM(ctx->opcode);
2356
2357 simm &= ~maskl;
2358 if (rA(ctx->opcode) == 0) {
2359 if (NARROW_MODE(ctx)) {
2360 simm = (uint32_t)simm;
2361 }
2362 tcg_gen_movi_tl(EA, simm);
2363 } else if (likely(simm != 0)) {
2364 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 } else {
2369 if (NARROW_MODE(ctx)) {
2370 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2371 } else {
2372 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2373 }
2374 }
2375 }
2376
2377 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2378 {
2379 if (rA(ctx->opcode) == 0) {
2380 if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2382 } else {
2383 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2384 }
2385 } else {
2386 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2387 if (NARROW_MODE(ctx)) {
2388 tcg_gen_ext32u_tl(EA, EA);
2389 }
2390 }
2391 }
2392
2393 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2394 {
2395 if (rA(ctx->opcode) == 0) {
2396 tcg_gen_movi_tl(EA, 0);
2397 } else if (NARROW_MODE(ctx)) {
2398 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2399 } else {
2400 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 }
2402 }
2403
2404 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2405 target_long val)
2406 {
2407 tcg_gen_addi_tl(ret, arg1, val);
2408 if (NARROW_MODE(ctx)) {
2409 tcg_gen_ext32u_tl(ret, ret);
2410 }
2411 }
2412
2413 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2414 {
2415 TCGLabel *l1 = gen_new_label();
2416 TCGv t0 = tcg_temp_new();
2417 TCGv_i32 t1, t2;
2418 tcg_gen_andi_tl(t0, EA, mask);
2419 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2420 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2421 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2422 gen_update_nip(ctx, ctx->nip - 4);
2423 gen_helper_raise_exception_err(cpu_env, t1, t2);
2424 tcg_temp_free_i32(t1);
2425 tcg_temp_free_i32(t2);
2426 gen_set_label(l1);
2427 tcg_temp_free(t0);
2428 }
2429
2430 static inline void gen_align_no_le(DisasContext *ctx)
2431 {
2432 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2433 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2434 }
2435
2436 /*** Integer load ***/
2437 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2438 {
2439 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2440 }
2441
2442 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2445 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2446 }
2447
2448 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449 {
2450 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2451 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2452 }
2453
2454 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2455 {
2456 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2457 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2458 }
2459
2460 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2461 {
2462 TCGv tmp = tcg_temp_new();
2463 gen_qemu_ld32u(ctx, tmp, addr);
2464 tcg_gen_extu_tl_i64(val, tmp);
2465 tcg_temp_free(tmp);
2466 }
2467
2468 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2469 {
2470 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2471 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2472 }
2473
2474 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2475 {
2476 TCGv tmp = tcg_temp_new();
2477 gen_qemu_ld32s(ctx, tmp, addr);
2478 tcg_gen_ext_tl_i64(val, tmp);
2479 tcg_temp_free(tmp);
2480 }
2481
2482 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2483 {
2484 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2485 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2486 }
2487
2488 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2489 {
2490 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2491 }
2492
2493 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2494 {
2495 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2496 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2497 }
2498
2499 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2500 {
2501 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2502 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2503 }
2504
2505 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2506 {
2507 TCGv tmp = tcg_temp_new();
2508 tcg_gen_trunc_i64_tl(tmp, val);
2509 gen_qemu_st32(ctx, tmp, addr);
2510 tcg_temp_free(tmp);
2511 }
2512
2513 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2514 {
2515 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2516 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2517 }
2518
2519 #define GEN_LD(name, ldop, opc, type) \
2520 static void glue(gen_, name)(DisasContext *ctx) \
2521 { \
2522 TCGv EA; \
2523 gen_set_access_type(ctx, ACCESS_INT); \
2524 EA = tcg_temp_new(); \
2525 gen_addr_imm_index(ctx, EA, 0); \
2526 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2527 tcg_temp_free(EA); \
2528 }
2529
2530 #define GEN_LDU(name, ldop, opc, type) \
2531 static void glue(gen_, name##u)(DisasContext *ctx) \
2532 { \
2533 TCGv EA; \
2534 if (unlikely(rA(ctx->opcode) == 0 || \
2535 rA(ctx->opcode) == rD(ctx->opcode))) { \
2536 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 return; \
2538 } \
2539 gen_set_access_type(ctx, ACCESS_INT); \
2540 EA = tcg_temp_new(); \
2541 if (type == PPC_64B) \
2542 gen_addr_imm_index(ctx, EA, 0x03); \
2543 else \
2544 gen_addr_imm_index(ctx, EA, 0); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2548 }
2549
2550 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2551 static void glue(gen_, name##ux)(DisasContext *ctx) \
2552 { \
2553 TCGv EA; \
2554 if (unlikely(rA(ctx->opcode) == 0 || \
2555 rA(ctx->opcode) == rD(ctx->opcode))) { \
2556 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2557 return; \
2558 } \
2559 gen_set_access_type(ctx, ACCESS_INT); \
2560 EA = tcg_temp_new(); \
2561 gen_addr_reg_index(ctx, EA); \
2562 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2563 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2564 tcg_temp_free(EA); \
2565 }
2566
2567 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2568 static void glue(gen_, name##x)(DisasContext *ctx) \
2569 { \
2570 TCGv EA; \
2571 chk; \
2572 gen_set_access_type(ctx, ACCESS_INT); \
2573 EA = tcg_temp_new(); \
2574 gen_addr_reg_index(ctx, EA); \
2575 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2576 tcg_temp_free(EA); \
2577 }
2578
2579 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2580 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2581
2582 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2583 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2584
2585 #define GEN_LDS(name, ldop, op, type) \
2586 GEN_LD(name, ldop, op | 0x20, type); \
2587 GEN_LDU(name, ldop, op | 0x21, type); \
2588 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2589 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2590
2591 /* lbz lbzu lbzux lbzx */
2592 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2593 /* lha lhau lhaux lhax */
2594 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2595 /* lhz lhzu lhzux lhzx */
2596 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2597 /* lwz lwzu lwzux lwzx */
2598 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2599 #if defined(TARGET_PPC64)
2600 /* lwaux */
2601 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2602 /* lwax */
2603 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2604 /* ldux */
2605 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2606 /* ldx */
2607 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2608
2609 /* CI load/store variants */
2610 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2611 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2612 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2613 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2614
2615 static void gen_ld(DisasContext *ctx)
2616 {
2617 TCGv EA;
2618 if (Rc(ctx->opcode)) {
2619 if (unlikely(rA(ctx->opcode) == 0 ||
2620 rA(ctx->opcode) == rD(ctx->opcode))) {
2621 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2622 return;
2623 }
2624 }
2625 gen_set_access_type(ctx, ACCESS_INT);
2626 EA = tcg_temp_new();
2627 gen_addr_imm_index(ctx, EA, 0x03);
2628 if (ctx->opcode & 0x02) {
2629 /* lwa (lwau is undefined) */
2630 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2631 } else {
2632 /* ld - ldu */
2633 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2634 }
2635 if (Rc(ctx->opcode))
2636 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2637 tcg_temp_free(EA);
2638 }
2639
2640 /* lq */
2641 static void gen_lq(DisasContext *ctx)
2642 {
2643 int ra, rd;
2644 TCGv EA;
2645
2646 /* lq is a legal user mode instruction starting in ISA 2.07 */
2647 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2648 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2649
2650 if (!legal_in_user_mode && ctx->pr) {
2651 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2652 return;
2653 }
2654
2655 if (!le_is_supported && ctx->le_mode) {
2656 gen_align_no_le(ctx);
2657 return;
2658 }
2659 ra = rA(ctx->opcode);
2660 rd = rD(ctx->opcode);
2661 if (unlikely((rd & 1) || rd == ra)) {
2662 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2663 return;
2664 }
2665
2666 gen_set_access_type(ctx, ACCESS_INT);
2667 EA = tcg_temp_new();
2668 gen_addr_imm_index(ctx, EA, 0x0F);
2669
2670 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2671 64-bit byteswap already. */
2672 if (unlikely(ctx->le_mode)) {
2673 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2674 gen_addr_add(ctx, EA, EA, 8);
2675 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2676 } else {
2677 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2678 gen_addr_add(ctx, EA, EA, 8);
2679 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2680 }
2681 tcg_temp_free(EA);
2682 }
2683 #endif
2684
2685 /*** Integer store ***/
2686 #define GEN_ST(name, stop, opc, type) \
2687 static void glue(gen_, name)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STU(name, stop, opc, type) \
2698 static void glue(gen_, stop##u)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 if (type == PPC_64B) \
2708 gen_addr_imm_index(ctx, EA, 0x03); \
2709 else \
2710 gen_addr_imm_index(ctx, EA, 0); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2714 }
2715
2716 #define GEN_STUX(name, stop, opc2, opc3, type) \
2717 static void glue(gen_, name##ux)(DisasContext *ctx) \
2718 { \
2719 TCGv EA; \
2720 if (unlikely(rA(ctx->opcode) == 0)) { \
2721 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2722 return; \
2723 } \
2724 gen_set_access_type(ctx, ACCESS_INT); \
2725 EA = tcg_temp_new(); \
2726 gen_addr_reg_index(ctx, EA); \
2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2729 tcg_temp_free(EA); \
2730 }
2731
2732 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2733 static void glue(gen_, name##x)(DisasContext *ctx) \
2734 { \
2735 TCGv EA; \
2736 chk; \
2737 gen_set_access_type(ctx, ACCESS_INT); \
2738 EA = tcg_temp_new(); \
2739 gen_addr_reg_index(ctx, EA); \
2740 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2741 tcg_temp_free(EA); \
2742 }
2743 #define GEN_STX(name, stop, opc2, opc3, type) \
2744 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2745
2746 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2747 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2748
2749 #define GEN_STS(name, stop, op, type) \
2750 GEN_ST(name, stop, op | 0x20, type); \
2751 GEN_STU(name, stop, op | 0x21, type); \
2752 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2753 GEN_STX(name, stop, 0x17, op | 0x00, type)
2754
2755 /* stb stbu stbux stbx */
2756 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2757 /* sth sthu sthux sthx */
2758 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2759 /* stw stwu stwux stwx */
2760 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2761 #if defined(TARGET_PPC64)
2762 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2763 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2764 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2765 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2766 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2767 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2768
2769 static void gen_std(DisasContext *ctx)
2770 {
2771 int rs;
2772 TCGv EA;
2773
2774 rs = rS(ctx->opcode);
2775 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2776 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2777 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2778
2779 if (!(ctx->insns_flags & PPC_64BX)) {
2780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2781 }
2782
2783 if (!legal_in_user_mode && ctx->pr) {
2784 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2785 return;
2786 }
2787
2788 if (!le_is_supported && ctx->le_mode) {
2789 gen_align_no_le(ctx);
2790 return;
2791 }
2792
2793 if (unlikely(rs & 1)) {
2794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2795 return;
2796 }
2797 gen_set_access_type(ctx, ACCESS_INT);
2798 EA = tcg_temp_new();
2799 gen_addr_imm_index(ctx, EA, 0x03);
2800
2801 /* We only need to swap high and low halves. gen_qemu_st64 does
2802 necessary 64-bit byteswap already. */
2803 if (unlikely(ctx->le_mode)) {
2804 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2805 gen_addr_add(ctx, EA, EA, 8);
2806 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2807 } else {
2808 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2809 gen_addr_add(ctx, EA, EA, 8);
2810 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2811 }
2812 tcg_temp_free(EA);
2813 } else {
2814 /* std / stdu*/
2815 if (Rc(ctx->opcode)) {
2816 if (unlikely(rA(ctx->opcode) == 0)) {
2817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2818 return;
2819 }
2820 }
2821 gen_set_access_type(ctx, ACCESS_INT);
2822 EA = tcg_temp_new();
2823 gen_addr_imm_index(ctx, EA, 0x03);
2824 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2825 if (Rc(ctx->opcode))
2826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2827 tcg_temp_free(EA);
2828 }
2829 }
2830 #endif
2831 /*** Integer load and store with byte reverse ***/
2832
2833 /* lhbrx */
2834 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2835 {
2836 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2837 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2838 }
2839 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2840
2841 /* lwbrx */
2842 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2843 {
2844 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2845 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2846 }
2847 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2848
2849 #if defined(TARGET_PPC64)
2850 /* ldbrx */
2851 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2852 {
2853 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2854 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2855 }
2856 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2857 #endif /* TARGET_PPC64 */
2858
2859 /* sthbrx */
2860 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2861 {
2862 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2863 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2864 }
2865 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2866
2867 /* stwbrx */
2868 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2869 {
2870 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2871 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2872 }
2873 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2874
2875 #if defined(TARGET_PPC64)
2876 /* stdbrx */
2877 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2878 {
2879 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2880 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2881 }
2882 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2883 #endif /* TARGET_PPC64 */
2884
2885 /*** Integer load and store multiple ***/
2886
2887 /* lmw */
2888 static void gen_lmw(DisasContext *ctx)
2889 {
2890 TCGv t0;
2891 TCGv_i32 t1;
2892 gen_set_access_type(ctx, ACCESS_INT);
2893 t0 = tcg_temp_new();
2894 t1 = tcg_const_i32(rD(ctx->opcode));
2895 gen_addr_imm_index(ctx, t0, 0);
2896 gen_helper_lmw(cpu_env, t0, t1);
2897 tcg_temp_free(t0);
2898 tcg_temp_free_i32(t1);
2899 }
2900
2901 /* stmw */
2902 static void gen_stmw(DisasContext *ctx)
2903 {
2904 TCGv t0;
2905 TCGv_i32 t1;
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 t0 = tcg_temp_new();
2908 t1 = tcg_const_i32(rS(ctx->opcode));
2909 gen_addr_imm_index(ctx, t0, 0);
2910 gen_helper_stmw(cpu_env, t0, t1);
2911 tcg_temp_free(t0);
2912 tcg_temp_free_i32(t1);
2913 }
2914
2915 /*** Integer load and store strings ***/
2916
2917 /* lswi */
2918 /* PowerPC32 specification says we must generate an exception if
2919 * rA is in the range of registers to be loaded.
2920 * In an other hand, IBM says this is valid, but rA won't be loaded.
2921 * For now, I'll follow the spec...
2922 */
2923 static void gen_lswi(DisasContext *ctx)
2924 {
2925 TCGv t0;
2926 TCGv_i32 t1, t2;
2927 int nb = NB(ctx->opcode);
2928 int start = rD(ctx->opcode);
2929 int ra = rA(ctx->opcode);
2930 int nr;
2931
2932 if (nb == 0)
2933 nb = 32;
2934 nr = (nb + 3) / 4;
2935 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2936 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2937 return;
2938 }
2939 gen_set_access_type(ctx, ACCESS_INT);
2940 t0 = tcg_temp_new();
2941 gen_addr_register(ctx, t0);
2942 t1 = tcg_const_i32(nb);
2943 t2 = tcg_const_i32(start);
2944 gen_helper_lsw(cpu_env, t0, t1, t2);
2945 tcg_temp_free(t0);
2946 tcg_temp_free_i32(t1);
2947 tcg_temp_free_i32(t2);
2948 }
2949
2950 /* lswx */
2951 static void gen_lswx(DisasContext *ctx)
2952 {
2953 TCGv t0;
2954 TCGv_i32 t1, t2, t3;
2955 gen_set_access_type(ctx, ACCESS_INT);
2956 t0 = tcg_temp_new();
2957 gen_addr_reg_index(ctx, t0);
2958 t1 = tcg_const_i32(rD(ctx->opcode));
2959 t2 = tcg_const_i32(rA(ctx->opcode));
2960 t3 = tcg_const_i32(rB(ctx->opcode));
2961 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2962 tcg_temp_free(t0);
2963 tcg_temp_free_i32(t1);
2964 tcg_temp_free_i32(t2);
2965 tcg_temp_free_i32(t3);
2966 }
2967
2968 /* stswi */
2969 static void gen_stswi(DisasContext *ctx)
2970 {
2971 TCGv t0;
2972 TCGv_i32 t1, t2;
2973 int nb = NB(ctx->opcode);
2974 gen_set_access_type(ctx, ACCESS_INT);
2975 t0 = tcg_temp_new();
2976 gen_addr_register(ctx, t0);
2977 if (nb == 0)
2978 nb = 32;
2979 t1 = tcg_const_i32(nb);
2980 t2 = tcg_const_i32(rS(ctx->opcode));
2981 gen_helper_stsw(cpu_env, t0, t1, t2);
2982 tcg_temp_free(t0);
2983 tcg_temp_free_i32(t1);
2984 tcg_temp_free_i32(t2);
2985 }
2986
2987 /* stswx */
2988 static void gen_stswx(DisasContext *ctx)
2989 {
2990 TCGv t0;
2991 TCGv_i32 t1, t2;
2992 gen_set_access_type(ctx, ACCESS_INT);
2993 t0 = tcg_temp_new();
2994 gen_addr_reg_index(ctx, t0);
2995 t1 = tcg_temp_new_i32();
2996 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2997 tcg_gen_andi_i32(t1, t1, 0x7F);
2998 t2 = tcg_const_i32(rS(ctx->opcode));
2999 gen_helper_stsw(cpu_env, t0, t1, t2);
3000 tcg_temp_free(t0);
3001 tcg_temp_free_i32(t1);
3002 tcg_temp_free_i32(t2);
3003 }
3004
3005 /*** Memory synchronisation ***/
3006 /* eieio */
3007 static void gen_eieio(DisasContext *ctx)
3008 {
3009 }
3010
3011 #if !defined(CONFIG_USER_ONLY)
3012 static inline void gen_check_tlb_flush(DisasContext *ctx)
3013 {
3014 TCGv_i32 t;
3015 TCGLabel *l;
3016
3017 if (!ctx->lazy_tlb_flush) {
3018 return;
3019 }
3020 l = gen_new_label();
3021 t = tcg_temp_new_i32();
3022 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3023 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3024 gen_helper_check_tlb_flush(cpu_env);
3025 gen_set_label(l);
3026 tcg_temp_free_i32(t);
3027 }
3028 #else
3029 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3030 #endif
3031
3032 /* isync */
3033 static void gen_isync(DisasContext *ctx)
3034 {
3035 /*
3036 * We need to check for a pending TLB flush. This can only happen in
3037 * kernel mode however so check MSR_PR
3038 */
3039 if (!ctx->pr) {
3040 gen_check_tlb_flush(ctx);
3041 }
3042 gen_stop_exception(ctx);
3043 }
3044
3045 #define LARX(name, len, loadop) \
3046 static void gen_##name(DisasContext *ctx) \
3047 { \
3048 TCGv t0; \
3049 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3050 gen_set_access_type(ctx, ACCESS_RES); \
3051 t0 = tcg_temp_local_new(); \
3052 gen_addr_reg_index(ctx, t0); \
3053 if ((len) > 1) { \
3054 gen_check_align(ctx, t0, (len)-1); \
3055 } \
3056 gen_qemu_##loadop(ctx, gpr, t0); \
3057 tcg_gen_mov_tl(cpu_reserve, t0); \
3058 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3059 tcg_temp_free(t0); \
3060 }
3061
3062 /* lwarx */
3063 LARX(lbarx, 1, ld8u);
3064 LARX(lharx, 2, ld16u);
3065 LARX(lwarx, 4, ld32u);
3066
3067
3068 #if defined(CONFIG_USER_ONLY)
3069 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3070 int reg, int size)
3071 {
3072 TCGv t0 = tcg_temp_new();
3073
3074 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3075 tcg_gen_movi_tl(t0, (size << 5) | reg);
3076 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3077 tcg_temp_free(t0);
3078 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3079 }
3080 #else
3081 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3082 int reg, int size)
3083 {
3084 TCGLabel *l1;
3085
3086 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3087 l1 = gen_new_label();
3088 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3089 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3090 #if defined(TARGET_PPC64)
3091 if (size == 8) {
3092 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3093 } else
3094 #endif
3095 if (size == 4) {
3096 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3097 } else if (size == 2) {
3098 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3099 #if defined(TARGET_PPC64)
3100 } else if (size == 16) {
3101 TCGv gpr1, gpr2 , EA8;
3102 if (unlikely(ctx->le_mode)) {
3103 gpr1 = cpu_gpr[reg+1];
3104 gpr2 = cpu_gpr[reg];
3105 } else {
3106 gpr1 = cpu_gpr[reg];
3107 gpr2 = cpu_gpr[reg+1];
3108 }
3109 gen_qemu_st64(ctx, gpr1, EA);
3110 EA8 = tcg_temp_local_new();
3111 gen_addr_add(ctx, EA8, EA, 8);
3112 gen_qemu_st64(ctx, gpr2, EA8);
3113 tcg_temp_free(EA8);
3114 #endif
3115 } else {
3116 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3117 }
3118 gen_set_label(l1);
3119 tcg_gen_movi_tl(cpu_reserve, -1);
3120 }
3121 #endif
3122
3123 #define STCX(name, len) \
3124 static void gen_##name(DisasContext *ctx) \
3125 { \
3126 TCGv t0; \
3127 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3128 gen_inval_exception(ctx, \
3129 POWERPC_EXCP_INVAL_INVAL); \
3130 return; \
3131 } \
3132 gen_set_access_type(ctx, ACCESS_RES); \
3133 t0 = tcg_temp_local_new(); \
3134 gen_addr_reg_index(ctx, t0); \
3135 if (len > 1) { \
3136 gen_check_align(ctx, t0, (len)-1); \
3137 } \
3138 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3139 tcg_temp_free(t0); \
3140 }
3141
3142 STCX(stbcx_, 1);
3143 STCX(sthcx_, 2);
3144 STCX(stwcx_, 4);
3145
3146 #if defined(TARGET_PPC64)
3147 /* ldarx */
3148 LARX(ldarx, 8, ld64);
3149
3150 /* lqarx */
3151 static void gen_lqarx(DisasContext *ctx)
3152 {
3153 TCGv EA;
3154 int rd = rD(ctx->opcode);
3155 TCGv gpr1, gpr2;
3156
3157 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3158 (rd == rB(ctx->opcode)))) {
3159 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3160 return;
3161 }
3162
3163 gen_set_access_type(ctx, ACCESS_RES);
3164 EA = tcg_temp_local_new();
3165 gen_addr_reg_index(ctx, EA);
3166 gen_check_align(ctx, EA, 15);
3167 if (unlikely(ctx->le_mode)) {
3168 gpr1 = cpu_gpr[rd+1];
3169 gpr2 = cpu_gpr[rd];
3170 } else {
3171 gpr1 = cpu_gpr[rd];
3172 gpr2 = cpu_gpr[rd+1];
3173 }
3174 gen_qemu_ld64(ctx, gpr1, EA);
3175 tcg_gen_mov_tl(cpu_reserve, EA);
3176
3177 gen_addr_add(ctx, EA, EA, 8);
3178 gen_qemu_ld64(ctx, gpr2, EA);
3179
3180 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3181 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3182
3183 tcg_temp_free(EA);
3184 }
3185
3186 /* stdcx. */
3187 STCX(stdcx_, 8);
3188 STCX(stqcx_, 16);
3189 #endif /* defined(TARGET_PPC64) */
3190
3191 /* sync */
3192 static void gen_sync(DisasContext *ctx)
3193 {
3194 uint32_t l = (ctx->opcode >> 21) & 3;
3195
3196 /*
3197 * We may need to check for a pending TLB flush.
3198 *
3199 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3200 *
3201 * Additionally, this can only happen in kernel mode however so
3202 * check MSR_PR as well.
3203 */
3204 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3205 gen_check_tlb_flush(ctx);
3206 }
3207 }
3208
3209 /* wait */
3210 static void gen_wait(DisasContext *ctx)
3211 {
3212 TCGv_i32 t0 = tcg_const_i32(1);
3213 tcg_gen_st_i32(t0, cpu_env,
3214 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3215 tcg_temp_free_i32(t0);
3216 /* Stop translation, as the CPU is supposed to sleep from now */
3217 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3218 }
3219
3220 #if defined(TARGET_PPC64)
3221 static void gen_doze(DisasContext *ctx)
3222 {
3223 #if defined(CONFIG_USER_ONLY)
3224 GEN_PRIV;
3225 #else
3226 TCGv_i32 t;
3227
3228 CHK_HV;
3229 t = tcg_const_i32(PPC_PM_DOZE);
3230 gen_helper_pminsn(cpu_env, t);
3231 tcg_temp_free_i32(t);
3232 gen_stop_exception(ctx);
3233 #endif /* defined(CONFIG_USER_ONLY) */
3234 }
3235
3236 static void gen_nap(DisasContext *ctx)
3237 {
3238 #if defined(CONFIG_USER_ONLY)
3239 GEN_PRIV;
3240 #else
3241 TCGv_i32 t;
3242
3243 CHK_HV;
3244 t = tcg_const_i32(PPC_PM_NAP);
3245 gen_helper_pminsn(cpu_env, t);
3246 tcg_temp_free_i32(t);
3247 gen_stop_exception(ctx);
3248 #endif /* defined(CONFIG_USER_ONLY) */
3249 }
3250
3251 static void gen_sleep(DisasContext *ctx)
3252 {
3253 #if defined(CONFIG_USER_ONLY)
3254 GEN_PRIV;
3255 #else
3256 TCGv_i32 t;
3257
3258 CHK_HV;
3259 t = tcg_const_i32(PPC_PM_SLEEP);
3260 gen_helper_pminsn(cpu_env, t);
3261 tcg_temp_free_i32(t);
3262 gen_stop_exception(ctx);
3263 #endif /* defined(CONFIG_USER_ONLY) */
3264 }
3265
3266 static void gen_rvwinkle(DisasContext *ctx)
3267 {
3268 #if defined(CONFIG_USER_ONLY)
3269 GEN_PRIV;
3270 #else
3271 TCGv_i32 t;
3272
3273 CHK_HV;
3274 t = tcg_const_i32(PPC_PM_RVWINKLE);
3275 gen_helper_pminsn(cpu_env, t);
3276 tcg_temp_free_i32(t);
3277 gen_stop_exception(ctx);
3278 #endif /* defined(CONFIG_USER_ONLY) */
3279 }
3280 #endif /* #if defined(TARGET_PPC64) */
3281
3282 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3283 {
3284 #if defined(TARGET_PPC64)
3285 if (ctx->has_cfar)
3286 tcg_gen_movi_tl(cpu_cfar, nip);
3287 #endif
3288 }
3289
3290 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3291 {
3292 if (unlikely(ctx->singlestep_enabled)) {
3293 return false;
3294 }
3295
3296 #ifndef CONFIG_USER_ONLY
3297 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3298 #else
3299 return true;
3300 #endif
3301 }
3302
3303 /*** Branch ***/
3304 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3305 {
3306 if (NARROW_MODE(ctx)) {
3307 dest = (uint32_t) dest;
3308 }
3309 if (use_goto_tb(ctx, dest)) {
3310 tcg_gen_goto_tb(n);
3311 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3312 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3313 } else {
3314 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3315 if (unlikely(ctx->singlestep_enabled)) {
3316 if ((ctx->singlestep_enabled &
3317 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3318 (ctx->exception == POWERPC_EXCP_BRANCH ||
3319 ctx->exception == POWERPC_EXCP_TRACE)) {
3320 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3321 }
3322 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3323 gen_debug_exception(ctx);
3324 }
3325 }
3326 tcg_gen_exit_tb(0);
3327 }
3328 }
3329
3330 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3331 {
3332 if (NARROW_MODE(ctx)) {
3333 nip = (uint32_t)nip;
3334 }
3335 tcg_gen_movi_tl(cpu_lr, nip);
3336 }
3337
3338 /* b ba bl bla */
3339 static void gen_b(DisasContext *ctx)
3340 {
3341 target_ulong li, target;
3342
3343 ctx->exception = POWERPC_EXCP_BRANCH;
3344 /* sign extend LI */
3345 li = LI(ctx->opcode);
3346 li = (li ^ 0x02000000) - 0x02000000;
3347 if (likely(AA(ctx->opcode) == 0)) {
3348 target = ctx->nip + li - 4;
3349 } else {
3350 target = li;
3351 }
3352 if (LK(ctx->opcode)) {
3353 gen_setlr(ctx, ctx->nip);
3354 }
3355 gen_update_cfar(ctx, ctx->nip - 4);
3356 gen_goto_tb(ctx, 0, target);
3357 }
3358
3359 #define BCOND_IM 0
3360 #define BCOND_LR 1
3361 #define BCOND_CTR 2
3362 #define BCOND_TAR 3
3363
3364 static inline void gen_bcond(DisasContext *ctx, int type)
3365 {
3366 uint32_t bo = BO(ctx->opcode);
3367 TCGLabel *l1;
3368 TCGv target;
3369
3370 ctx->exception = POWERPC_EXCP_BRANCH;
3371 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3372 target = tcg_temp_local_new();
3373 if (type == BCOND_CTR)
3374 tcg_gen_mov_tl(target, cpu_ctr);
3375 else if (type == BCOND_TAR)
3376 gen_load_spr(target, SPR_TAR);
3377 else
3378 tcg_gen_mov_tl(target, cpu_lr);
3379 } else {
3380 TCGV_UNUSED(target);
3381 }
3382 if (LK(ctx->opcode))
3383 gen_setlr(ctx, ctx->nip);
3384 l1 = gen_new_label();
3385 if ((bo & 0x4) == 0) {
3386 /* Decrement and test CTR */
3387 TCGv temp = tcg_temp_new();
3388 if (unlikely(type == BCOND_CTR)) {
3389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3390 return;
3391 }
3392 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3393 if (NARROW_MODE(ctx)) {
3394 tcg_gen_ext32u_tl(temp, cpu_ctr);
3395 } else {
3396 tcg_gen_mov_tl(temp, cpu_ctr);
3397 }
3398 if (bo & 0x2) {
3399 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3400 } else {
3401 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3402 }
3403 tcg_temp_free(temp);
3404 }
3405 if ((bo & 0x10) == 0) {
3406 /* Test CR */
3407 uint32_t bi = BI(ctx->opcode);
3408 uint32_t mask = 0x08 >> (bi & 0x03);
3409 TCGv_i32 temp = tcg_temp_new_i32();
3410
3411 if (bo & 0x8) {
3412 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3413 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3414 } else {
3415 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3416 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3417 }
3418 tcg_temp_free_i32(temp);
3419 }
3420 gen_update_cfar(ctx, ctx->nip - 4);
3421 if (type == BCOND_IM) {
3422 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3423 if (likely(AA(ctx->opcode) == 0)) {
3424 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3425 } else {
3426 gen_goto_tb(ctx, 0, li);
3427 }
3428 gen_set_label(l1);
3429 gen_goto_tb(ctx, 1, ctx->nip);
3430 } else {
3431 if (NARROW_MODE(ctx)) {
3432 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3433 } else {
3434 tcg_gen_andi_tl(cpu_nip, target, ~3);
3435 }
3436 tcg_gen_exit_tb(0);
3437 gen_set_label(l1);
3438 gen_update_nip(ctx, ctx->nip);
3439 tcg_gen_exit_tb(0);
3440 }
3441 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3442 tcg_temp_free(target);
3443 }
3444 }
3445
3446 static void gen_bc(DisasContext *ctx)
3447 {
3448 gen_bcond(ctx, BCOND_IM);
3449 }
3450
3451 static void gen_bcctr(DisasContext *ctx)
3452 {
3453 gen_bcond(ctx, BCOND_CTR);
3454 }
3455
3456 static void gen_bclr(DisasContext *ctx)
3457 {
3458 gen_bcond(ctx, BCOND_LR);
3459 }
3460
3461 static void gen_bctar(DisasContext *ctx)
3462 {
3463 gen_bcond(ctx, BCOND_TAR);
3464 }
3465
3466 /*** Condition register logical ***/
3467 #define GEN_CRLOGIC(name, tcg_op, opc) \
3468 static void glue(gen_, name)(DisasContext *ctx) \
3469 { \
3470 uint8_t bitmask; \
3471 int sh; \
3472 TCGv_i32 t0, t1; \
3473 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3474 t0 = tcg_temp_new_i32(); \
3475 if (sh > 0) \
3476 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3477 else if (sh < 0) \
3478 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3479 else \
3480 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3481 t1 = tcg_temp_new_i32(); \
3482 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3483 if (sh > 0) \
3484 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3485 else if (sh < 0) \
3486 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3487 else \
3488 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3489 tcg_op(t0, t0, t1); \
3490 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3491 tcg_gen_andi_i32(t0, t0, bitmask); \
3492 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3493 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3494 tcg_temp_free_i32(t0); \
3495 tcg_temp_free_i32(t1); \
3496 }
3497
3498 /* crand */
3499 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3500 /* crandc */
3501 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3502 /* creqv */
3503 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3504 /* crnand */
3505 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3506 /* crnor */
3507 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3508 /* cror */
3509 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3510 /* crorc */
3511 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3512 /* crxor */
3513 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3514
3515 /* mcrf */
3516 static void gen_mcrf(DisasContext *ctx)
3517 {
3518 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3519 }
3520
3521 /*** System linkage ***/
3522
3523 /* rfi (supervisor only) */
3524 static void gen_rfi(DisasContext *ctx)
3525 {
3526 #if defined(CONFIG_USER_ONLY)
3527 GEN_PRIV;
3528 #else
3529 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3530 * processors compliant with arch 2.x, we should remove it there,
3531 * but we need to fix OpenBIOS not to use it on 970 first
3532 */
3533 /* Restore CPU state */
3534 CHK_SV;
3535 gen_update_cfar(ctx, ctx->nip - 4);
3536 gen_helper_rfi(cpu_env);
3537 gen_sync_exception(ctx);
3538 #endif
3539 }
3540
3541 #if defined(TARGET_PPC64)
3542 static void gen_rfid(DisasContext *ctx)
3543 {
3544 #if defined(CONFIG_USER_ONLY)
3545 GEN_PRIV;
3546 #else
3547 /* Restore CPU state */
3548 CHK_SV;
3549 gen_update_cfar(ctx, ctx->nip - 4);
3550 gen_helper_rfid(cpu_env);
3551 gen_sync_exception(ctx);
3552 #endif
3553 }
3554
3555 static void gen_hrfid(DisasContext *ctx)
3556 {
3557 #if defined(CONFIG_USER_ONLY)
3558 GEN_PRIV;
3559 #else
3560 /* Restore CPU state */
3561 CHK_HV;
3562 gen_helper_hrfid(cpu_env);
3563 gen_sync_exception(ctx);
3564 #endif
3565 }
3566 #endif
3567
3568 /* sc */
3569 #if defined(CONFIG_USER_ONLY)
3570 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3571 #else
3572 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3573 #endif
3574 static void gen_sc(DisasContext *ctx)
3575 {
3576 uint32_t lev;
3577
3578 lev = (ctx->opcode >> 5) & 0x7F;
3579 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3580 }
3581
3582 /*** Trap ***/
3583
3584 /* Check for unconditional traps (always or never) */
3585 static bool check_unconditional_trap(DisasContext *ctx)
3586 {
3587 /* Trap never */
3588 if (TO(ctx->opcode) == 0) {
3589 return true;
3590 }
3591 /* Trap always */
3592 if (TO(ctx->opcode) == 31) {
3593 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3594 return true;
3595 }
3596 return false;
3597 }
3598
3599 /* tw */
3600 static void gen_tw(DisasContext *ctx)
3601 {
3602 TCGv_i32 t0;
3603
3604 if (check_unconditional_trap(ctx)) {
3605 return;
3606 }
3607 t0 = tcg_const_i32(TO(ctx->opcode));
3608 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3609 t0);
3610 tcg_temp_free_i32(t0);
3611 }
3612
3613 /* twi */
3614 static void gen_twi(DisasContext *ctx)
3615 {
3616 TCGv t0;
3617 TCGv_i32 t1;
3618
3619 if (check_unconditional_trap(ctx)) {
3620 return;
3621 }
3622 t0 = tcg_const_tl(SIMM(ctx->opcode));
3623 t1 = tcg_const_i32(TO(ctx->opcode));
3624 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3625 tcg_temp_free(t0);
3626 tcg_temp_free_i32(t1);
3627 }
3628
3629 #if defined(TARGET_PPC64)
3630 /* td */
3631 static void gen_td(DisasContext *ctx)
3632 {
3633 TCGv_i32 t0;
3634
3635 if (check_unconditional_trap(ctx)) {
3636 return;
3637 }
3638 t0 = tcg_const_i32(TO(ctx->opcode));
3639 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3640 t0);
3641 tcg_temp_free_i32(t0);
3642 }
3643
3644 /* tdi */
3645 static void gen_tdi(DisasContext *ctx)
3646 {
3647 TCGv t0;
3648 TCGv_i32 t1;
3649
3650 if (check_unconditional_trap(ctx)) {
3651 return;
3652 }
3653 t0 = tcg_const_tl(SIMM(ctx->opcode));
3654 t1 = tcg_const_i32(TO(ctx->opcode));
3655 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3656 tcg_temp_free(t0);
3657 tcg_temp_free_i32(t1);
3658 }
3659 #endif
3660
3661 /*** Processor control ***/
3662
3663 static void gen_read_xer(TCGv dst)
3664 {
3665 TCGv t0 = tcg_temp_new();
3666 TCGv t1 = tcg_temp_new();
3667 TCGv t2 = tcg_temp_new();
3668 tcg_gen_mov_tl(dst, cpu_xer);
3669 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3670 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3671 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3672 tcg_gen_or_tl(t0, t0, t1);
3673 tcg_gen_or_tl(dst, dst, t2);
3674 tcg_gen_or_tl(dst, dst, t0);
3675 tcg_temp_free(t0);
3676 tcg_temp_free(t1);
3677 tcg_temp_free(t2);
3678 }
3679
3680 static void gen_write_xer(TCGv src)
3681 {
3682 tcg_gen_andi_tl(cpu_xer, src,
3683 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3684 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3685 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3686 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3687 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3688 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3689 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3690 }
3691
3692 /* mcrxr */
3693 static void gen_mcrxr(DisasContext *ctx)
3694 {
3695 TCGv_i32 t0 = tcg_temp_new_i32();
3696 TCGv_i32 t1 = tcg_temp_new_i32();
3697 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3698
3699 tcg_gen_trunc_tl_i32(t0, cpu_so);
3700 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3701 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3702 tcg_gen_shli_i32(t0, t0, 3);
3703 tcg_gen_shli_i32(t1, t1, 2);
3704 tcg_gen_shli_i32(dst, dst, 1);
3705 tcg_gen_or_i32(dst, dst, t0);
3706 tcg_gen_or_i32(dst, dst, t1);
3707 tcg_temp_free_i32(t0);
3708 tcg_temp_free_i32(t1);
3709
3710 tcg_gen_movi_tl(cpu_so, 0);
3711 tcg_gen_movi_tl(cpu_ov, 0);
3712 tcg_gen_movi_tl(cpu_ca, 0);
3713 }
3714
3715 /* mfcr mfocrf */
3716 static void gen_mfcr(DisasContext *ctx)
3717 {
3718 uint32_t crm, crn;
3719
3720 if (likely(ctx->opcode & 0x00100000)) {
3721 crm = CRM(ctx->opcode);
3722 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3723 crn = ctz32 (crm);
3724 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3725 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3726 cpu_gpr[rD(ctx->opcode)], crn * 4);
3727 }
3728 } else {
3729 TCGv_i32 t0 = tcg_temp_new_i32();
3730 tcg_gen_mov_i32(t0, cpu_crf[0]);
3731 tcg_gen_shli_i32(t0, t0, 4);
3732 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3733 tcg_gen_shli_i32(t0, t0, 4);
3734 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3735 tcg_gen_shli_i32(t0, t0, 4);
3736 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3739 tcg_gen_shli_i32(t0, t0, 4);
3740 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3741 tcg_gen_shli_i32(t0, t0, 4);
3742 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3743 tcg_gen_shli_i32(t0, t0, 4);
3744 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3745 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3746 tcg_temp_free_i32(t0);
3747 }
3748 }
3749
3750 /* mfmsr */
3751 static void gen_mfmsr(DisasContext *ctx)
3752 {
3753 CHK_SV;
3754 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3755 }
3756
3757 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3758 {
3759 #if 0
3760 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3761 printf("ERROR: try to access SPR %d !\n", sprn);
3762 #endif
3763 }
3764 #define SPR_NOACCESS (&spr_noaccess)
3765
3766 /* mfspr */
3767 static inline void gen_op_mfspr(DisasContext *ctx)
3768 {
3769 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3770 uint32_t sprn = SPR(ctx->opcode);
3771
3772 #if defined(CONFIG_USER_ONLY)
3773 read_cb = ctx->spr_cb[sprn].uea_read;
3774 #else
3775 if (ctx->pr) {
3776 read_cb = ctx->spr_cb[sprn].uea_read;
3777 } else if (ctx->hv) {
3778 read_cb = ctx->spr_cb[sprn].hea_read;
3779 } else {
3780 read_cb = ctx->spr_cb[sprn].oea_read;
3781 }
3782 #endif
3783 if (likely(read_cb != NULL)) {
3784 if (likely(read_cb != SPR_NOACCESS)) {
3785 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3786 } else {
3787 /* Privilege exception */
3788 /* This is a hack to avoid warnings when running Linux:
3789 * this OS breaks the PowerPC virtualisation model,
3790 * allowing userland application to read the PVR
3791 */
3792 if (sprn != SPR_PVR) {
3793 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3794 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3795 if (qemu_log_separate()) {
3796 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3797 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3798 }
3799 }
3800 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3801 }
3802 } else {
3803 /* ISA 2.07 defines these as no-ops */
3804 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3805 (sprn >= 808 && sprn <= 811)) {
3806 /* This is a nop */
3807 return;
3808 }
3809 /* Not defined */
3810 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3811 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3812 if (qemu_log_separate()) {
3813 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3814 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3815 }
3816
3817 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3818 * it can generate a priv, a hv emu or a no-op
3819 */
3820 if (sprn & 0x10) {
3821 if (ctx->pr) {
3822 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3823 }
3824 } else {
3825 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3826 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3827 }
3828 }
3829 }
3830 }
3831
3832 static void gen_mfspr(DisasContext *ctx)
3833 {
3834 gen_op_mfspr(ctx);
3835 }
3836
3837 /* mftb */
3838 static void gen_mftb(DisasContext *ctx)
3839 {
3840 gen_op_mfspr(ctx);
3841 }
3842
3843 /* mtcrf mtocrf*/
3844 static void gen_mtcrf(DisasContext *ctx)
3845 {
3846 uint32_t crm, crn;
3847
3848 crm = CRM(ctx->opcode);
3849 if (likely((ctx->opcode & 0x00100000))) {
3850 if (crm && ((crm & (crm - 1)) == 0)) {
3851 TCGv_i32 temp = tcg_temp_new_i32();
3852 crn = ctz32 (crm);
3853 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3854 tcg_gen_shri_i32(temp, temp, crn * 4);
3855 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3856 tcg_temp_free_i32(temp);
3857 }
3858 } else {
3859 TCGv_i32 temp = tcg_temp_new_i32();
3860 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3861 for (crn = 0 ; crn < 8 ; crn++) {
3862 if (crm & (1 << crn)) {
3863 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3864 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3865 }
3866 }
3867 tcg_temp_free_i32(temp);
3868 }
3869 }
3870
3871 /* mtmsr */
3872 #if defined(TARGET_PPC64)
3873 static void gen_mtmsrd(DisasContext *ctx)
3874 {
3875 CHK_SV;
3876
3877 #if !defined(CONFIG_USER_ONLY)
3878 if (ctx->opcode & 0x00010000) {
3879 /* Special form that does not need any synchronisation */
3880 TCGv t0 = tcg_temp_new();
3881 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3882 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3883 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3884 tcg_temp_free(t0);
3885 } else {
3886 /* XXX: we need to update nip before the store
3887 * if we enter power saving mode, we will exit the loop
3888 * directly from ppc_store_msr
3889 */
3890 gen_update_nip(ctx, ctx->nip);
3891 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3892 /* Must stop the translation as machine state (may have) changed */
3893 /* Note that mtmsr is not always defined as context-synchronizing */
3894 gen_stop_exception(ctx);
3895 }
3896 #endif /* !defined(CONFIG_USER_ONLY) */
3897 }
3898 #endif /* defined(TARGET_PPC64) */
3899
3900 static void gen_mtmsr(DisasContext *ctx)
3901 {
3902 CHK_SV;
3903
3904 #if !defined(CONFIG_USER_ONLY)
3905 if (ctx->opcode & 0x00010000) {
3906 /* Special form that does not need any synchronisation */
3907 TCGv t0 = tcg_temp_new();
3908 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3909 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3910 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3911 tcg_temp_free(t0);
3912 } else {
3913 TCGv msr = tcg_temp_new();
3914
3915 /* XXX: we need to update nip before the store
3916 * if we enter power saving mode, we will exit the loop
3917 * directly from ppc_store_msr
3918 */
3919 gen_update_nip(ctx, ctx->nip);
3920 #if defined(TARGET_PPC64)
3921 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3922 #else
3923 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3924 #endif
3925 gen_helper_store_msr(cpu_env, msr);
3926 tcg_temp_free(msr);
3927 /* Must stop the translation as machine state (may have) changed */
3928 /* Note that mtmsr is not always defined as context-synchronizing */
3929 gen_stop_exception(ctx);
3930 }
3931 #endif
3932 }
3933
3934 /* mtspr */
3935 static void gen_mtspr(DisasContext *ctx)
3936 {
3937 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3938 uint32_t sprn = SPR(ctx->opcode);
3939
3940 #if defined(CONFIG_USER_ONLY)
3941 write_cb = ctx->spr_cb[sprn].uea_write;
3942 #else
3943 if (ctx->pr) {
3944 write_cb = ctx->spr_cb[sprn].uea_write;
3945 } else if (ctx->hv) {
3946 write_cb = ctx->spr_cb[sprn].hea_write;
3947 } else {
3948 write_cb = ctx->spr_cb[sprn].oea_write;
3949 }
3950 #endif
3951 if (likely(write_cb != NULL)) {
3952 if (likely(write_cb != SPR_NOACCESS)) {
3953 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3954 } else {
3955 /* Privilege exception */
3956 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3957 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3958 if (qemu_log_separate()) {
3959 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3960 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3961 }
3962 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3963 }
3964 } else {
3965 /* ISA 2.07 defines these as no-ops */
3966 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3967 (sprn >= 808 && sprn <= 811)) {
3968 /* This is a nop */
3969 return;
3970 }
3971
3972 /* Not defined */
3973 if (qemu_log_separate()) {
3974 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3975 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3976 }
3977 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3978 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3979
3980
3981 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3982 * it can generate a priv, a hv emu or a no-op
3983 */
3984 if (sprn & 0x10) {
3985 if (ctx->pr) {
3986 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3987 }
3988 } else {
3989 if (ctx->pr || sprn == 0) {
3990 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3991 }
3992 }
3993 }
3994 }
3995
3996 #if defined(TARGET_PPC64)
3997 /* setb */
3998 static void gen_setb(DisasContext *ctx)
3999 {
4000 TCGv_i32 t0 = tcg_temp_new_i32();
4001 TCGv_i32 t8 = tcg_temp_new_i32();
4002 TCGv_i32 tm1 = tcg_temp_new_i32();
4003 int crf = crfS(ctx->opcode);
4004
4005 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4006 tcg_gen_movi_i32(t8, 8);
4007 tcg_gen_movi_i32(tm1, -1);
4008 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4009 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4010
4011 tcg_temp_free_i32(t0);
4012 tcg_temp_free_i32(t8);
4013 tcg_temp_free_i32(tm1);
4014 }
4015 #endif
4016
4017 /*** Cache management ***/
4018
4019 /* dcbf */
4020 static void gen_dcbf(DisasContext *ctx)
4021 {
4022 /* XXX: specification says this is treated as a load by the MMU */
4023 TCGv t0;
4024 gen_set_access_type(ctx, ACCESS_CACHE);
4025 t0 = tcg_temp_new();
4026 gen_addr_reg_index(ctx, t0);
4027 gen_qemu_ld8u(ctx, t0, t0);
4028 tcg_temp_free(t0);
4029 }
4030
4031 /* dcbi (Supervisor only) */
4032 static void gen_dcbi(DisasContext *ctx)
4033 {
4034 #if defined(CONFIG_USER_ONLY)
4035 GEN_PRIV;
4036 #else
4037 TCGv EA, val;
4038
4039 CHK_SV;
4040 EA = tcg_temp_new();
4041 gen_set_access_type(ctx, ACCESS_CACHE);
4042 gen_addr_reg_index(ctx, EA);
4043 val = tcg_temp_new();
4044 /* XXX: specification says this should be treated as a store by the MMU */
4045 gen_qemu_ld8u(ctx, val, EA);
4046 gen_qemu_st8(ctx, val, EA);
4047 tcg_temp_free(val);
4048 tcg_temp_free(EA);
4049 #endif /* defined(CONFIG_USER_ONLY) */
4050 }
4051
4052 /* dcdst */
4053 static void gen_dcbst(DisasContext *ctx)
4054 {
4055 /* XXX: specification say this is treated as a load by the MMU */
4056 TCGv t0;
4057 gen_set_access_type(ctx, ACCESS_CACHE);
4058 t0 = tcg_temp_new();
4059 gen_addr_reg_index(ctx, t0);
4060 gen_qemu_ld8u(ctx, t0, t0);
4061 tcg_temp_free(t0);
4062 }
4063
4064 /* dcbt */
4065 static void gen_dcbt(DisasContext *ctx)
4066 {
4067 /* interpreted as no-op */
4068 /* XXX: specification say this is treated as a load by the MMU
4069 * but does not generate any exception
4070 */
4071 }
4072
4073 /* dcbtst */
4074 static void gen_dcbtst(DisasContext *ctx)
4075 {
4076 /* interpreted as no-op */
4077 /* XXX: specification say this is treated as a load by the MMU
4078 * but does not generate any exception
4079 */
4080 }
4081
4082 /* dcbtls */
4083 static void gen_dcbtls(DisasContext *ctx)
4084 {
4085 /* Always fails locking the cache */
4086 TCGv t0 = tcg_temp_new();
4087 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4088 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4089 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4090 tcg_temp_free(t0);
4091 }
4092
4093 /* dcbz */
4094 static void gen_dcbz(DisasContext *ctx)
4095 {
4096 TCGv tcgv_addr;
4097 TCGv_i32 tcgv_op;
4098
4099 gen_set_access_type(ctx, ACCESS_CACHE);
4100 tcgv_addr = tcg_temp_new();
4101 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4102 gen_addr_reg_index(ctx, tcgv_addr);
4103 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4104 tcg_temp_free(tcgv_addr);
4105 tcg_temp_free_i32(tcgv_op);
4106 }
4107
4108 /* dst / dstt */
4109 static void gen_dst(DisasContext *ctx)
4110 {
4111 if (rA(ctx->opcode) == 0) {
4112 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4113 } else {
4114 /* interpreted as no-op */
4115 }
4116 }
4117
4118 /* dstst /dststt */
4119 static void gen_dstst(DisasContext *ctx)
4120 {
4121 if (rA(ctx->opcode) == 0) {
4122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4123 } else {
4124 /* interpreted as no-op */
4125 }
4126
4127 }
4128
4129 /* dss / dssall */
4130 static void gen_dss(DisasContext *ctx)
4131 {
4132 /* interpreted as no-op */
4133 }
4134
4135 /* icbi */
4136 static void gen_icbi(DisasContext *ctx)
4137 {
4138 TCGv t0;
4139 gen_set_access_type(ctx, ACCESS_CACHE);
4140 t0 = tcg_temp_new();
4141 gen_addr_reg_index(ctx, t0);
4142 gen_helper_icbi(cpu_env, t0);
4143 tcg_temp_free(t0);
4144 }
4145
4146 /* Optional: */
4147 /* dcba */
4148 static void gen_dcba(DisasContext *ctx)
4149 {
4150 /* interpreted as no-op */
4151 /* XXX: specification say this is treated as a store by the MMU
4152 * but does not generate any exception
4153 */
4154 }
4155
4156 /*** Segment register manipulation ***/
4157 /* Supervisor only: */
4158
4159 /* mfsr */
4160 static void gen_mfsr(DisasContext *ctx)
4161 {
4162 #if defined(CONFIG_USER_ONLY)
4163 GEN_PRIV;
4164 #else
4165 TCGv t0;
4166
4167 CHK_SV;
4168 t0 = tcg_const_tl(SR(ctx->opcode));
4169 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4170 tcg_temp_free(t0);
4171 #endif /* defined(CONFIG_USER_ONLY) */
4172 }
4173
4174 /* mfsrin */
4175 static void gen_mfsrin(DisasContext *ctx)
4176 {
4177 #if defined(CONFIG_USER_ONLY)
4178 GEN_PRIV;
4179 #else
4180 TCGv t0;
4181
4182 CHK_SV;
4183 t0 = tcg_temp_new();
4184 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4185 tcg_gen_andi_tl(t0, t0, 0xF);
4186 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4187 tcg_temp_free(t0);
4188 #endif /* defined(CONFIG_USER_ONLY) */
4189 }
4190
4191 /* mtsr */
4192 static void gen_mtsr(DisasContext *ctx)
4193 {
4194 #if defined(CONFIG_USER_ONLY)
4195 GEN_PRIV;
4196 #else
4197 TCGv t0;
4198
4199 CHK_SV;
4200 t0 = tcg_const_tl(SR(ctx->opcode));
4201 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4202 tcg_temp_free(t0);
4203 #endif /* defined(CONFIG_USER_ONLY) */
4204 }
4205
4206 /* mtsrin */
4207 static void gen_mtsrin(DisasContext *ctx)
4208 {
4209 #if defined(CONFIG_USER_ONLY)
4210 GEN_PRIV;
4211 #else
4212 TCGv t0;
4213 CHK_SV;
4214
4215 t0 = tcg_temp_new();
4216 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4217 tcg_gen_andi_tl(t0, t0, 0xF);
4218 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4219 tcg_temp_free(t0);
4220 #endif /* defined(CONFIG_USER_ONLY) */
4221 }
4222
4223 #if defined(TARGET_PPC64)
4224 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4225
4226 /* mfsr */
4227 static void gen_mfsr_64b(DisasContext *ctx)
4228 {
4229 #if defined(CONFIG_USER_ONLY)
4230 GEN_PRIV;
4231 #else
4232 TCGv t0;
4233
4234 CHK_SV;
4235 t0 = tcg_const_tl(SR(ctx->opcode));
4236 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4237 tcg_temp_free(t0);
4238 #endif /* defined(CONFIG_USER_ONLY) */
4239 }
4240
4241 /* mfsrin */
4242 static void gen_mfsrin_64b(DisasContext *ctx)
4243 {
4244 #if defined(CONFIG_USER_ONLY)
4245 GEN_PRIV;
4246 #else
4247 TCGv t0;
4248
4249 CHK_SV;
4250 t0 = tcg_temp_new();
4251 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4252 tcg_gen_andi_tl(t0, t0, 0xF);
4253 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4254 tcg_temp_free(t0);
4255 #endif /* defined(CONFIG_USER_ONLY) */
4256 }
4257
4258 /* mtsr */
4259 static void gen_mtsr_64b(DisasContext *ctx)
4260 {
4261 #if defined(CONFIG_USER_ONLY)
4262 GEN_PRIV;
4263 #else
4264 TCGv t0;
4265
4266 CHK_SV;
4267 t0 = tcg_const_tl(SR(ctx->opcode));
4268 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4269 tcg_temp_free(t0);
4270 #endif /* defined(CONFIG_USER_ONLY) */
4271 }
4272
4273 /* mtsrin */
4274 static void gen_mtsrin_64b(DisasContext *ctx)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 GEN_PRIV;
4278 #else
4279 TCGv t0;
4280
4281 CHK_SV;
4282 t0 = tcg_temp_new();
4283 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4284 tcg_gen_andi_tl(t0, t0, 0xF);
4285 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4286 tcg_temp_free(t0);
4287 #endif /* defined(CONFIG_USER_ONLY) */
4288 }
4289
4290 /* slbmte */
4291 static void gen_slbmte(DisasContext *ctx)
4292 {
4293 #if defined(CONFIG_USER_ONLY)
4294 GEN_PRIV;
4295 #else
4296 CHK_SV;
4297
4298 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4299 cpu_gpr[rS(ctx->opcode)]);
4300 #endif /* defined(CONFIG_USER_ONLY) */
4301 }
4302
4303 static void gen_slbmfee(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 GEN_PRIV;
4307 #else
4308 CHK_SV;
4309
4310 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4311 cpu_gpr[rB(ctx->opcode)]);
4312 #endif /* defined(CONFIG_USER_ONLY) */
4313 }
4314
4315 static void gen_slbmfev(DisasContext *ctx)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 GEN_PRIV;
4319 #else
4320 CHK_SV;
4321
4322 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4323 cpu_gpr[rB(ctx->opcode)]);
4324 #endif /* defined(CONFIG_USER_ONLY) */
4325 }
4326
4327 static void gen_slbfee_(DisasContext *ctx)
4328 {
4329 #if defined(CONFIG_USER_ONLY)
4330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4331 #else
4332 TCGLabel *l1, *l2;
4333
4334 if (unlikely(ctx->pr)) {
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4336 return;
4337 }
4338 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4339 cpu_gpr[rB(ctx->opcode)]);
4340 l1 = gen_new_label();
4341 l2 = gen_new_label();
4342 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4343 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4344 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4345 tcg_gen_br(l2);
4346 gen_set_label(l1);
4347 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4348 gen_set_label(l2);
4349 #endif
4350 }
4351 #endif /* defined(TARGET_PPC64) */
4352
4353 /*** Lookaside buffer management ***/
4354 /* Optional & supervisor only: */
4355
4356 /* tlbia */
4357 static void gen_tlbia(DisasContext *ctx)
4358 {
4359 #if defined(CONFIG_USER_ONLY)
4360 GEN_PRIV;
4361 #else
4362 CHK_HV;
4363
4364 gen_helper_tlbia(cpu_env);
4365 #endif /* defined(CONFIG_USER_ONLY) */
4366 }
4367
4368 /* tlbiel */
4369 static void gen_tlbiel(DisasContext *ctx)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 GEN_PRIV;
4373 #else
4374 CHK_SV;
4375
4376 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4377 #endif /* defined(CONFIG_USER_ONLY) */
4378 }
4379
4380 /* tlbie */
4381 static void gen_tlbie(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_PRIV;
4385 #else
4386 CHK_HV;
4387
4388 if (NARROW_MODE(ctx)) {
4389 TCGv t0 = tcg_temp_new();
4390 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4391 gen_helper_tlbie(cpu_env, t0);
4392 tcg_temp_free(t0);
4393 } else {
4394 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4395 }
4396 #endif /* defined(CONFIG_USER_ONLY) */
4397 }
4398
4399 /* tlbsync */
4400 static void gen_tlbsync(DisasContext *ctx)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 GEN_PRIV;
4404 #else
4405 CHK_HV;
4406
4407 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4408 * embedded however needs to deal with tlbsync. We don't try to be
4409 * fancy and swallow the overhead of checking for both.
4410 */
4411 gen_check_tlb_flush(ctx);
4412 #endif /* defined(CONFIG_USER_ONLY) */
4413 }
4414
4415 #if defined(TARGET_PPC64)
4416 /* slbia */
4417 static void gen_slbia(DisasContext *ctx)
4418 {
4419 #if defined(CONFIG_USER_ONLY)
4420 GEN_PRIV;
4421 #else
4422 CHK_SV;
4423
4424 gen_helper_slbia(cpu_env);
4425 #endif /* defined(CONFIG_USER_ONLY) */
4426 }
4427
4428 /* slbie */
4429 static void gen_slbie(DisasContext *ctx)
4430 {
4431 #if defined(CONFIG_USER_ONLY)
4432 GEN_PRIV;
4433 #else
4434 CHK_SV;
4435
4436 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4437 #endif /* defined(CONFIG_USER_ONLY) */
4438 }
4439 #endif /* defined(TARGET_PPC64) */
4440
4441 /*** External control ***/
4442 /* Optional: */
4443
4444 /* eciwx */
4445 static void gen_eciwx(DisasContext *ctx)
4446 {
4447 TCGv t0;
4448 /* Should check EAR[E] ! */
4449 gen_set_access_type(ctx, ACCESS_EXT);
4450 t0 = tcg_temp_new();
4451 gen_addr_reg_index(ctx, t0);
4452 gen_check_align(ctx, t0, 0x03);
4453 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4454 tcg_temp_free(t0);
4455 }
4456
4457 /* ecowx */
4458 static void gen_ecowx(DisasContext *ctx)
4459 {
4460 TCGv t0;
4461 /* Should check EAR[E] ! */
4462 gen_set_access_type(ctx, ACCESS_EXT);
4463 t0 = tcg_temp_new();
4464 gen_addr_reg_index(ctx, t0);
4465 gen_check_align(ctx, t0, 0x03);
4466 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4467 tcg_temp_free(t0);
4468 }
4469
4470 /* PowerPC 601 specific instructions */
4471
4472 /* abs - abs. */
4473 static void gen_abs(DisasContext *ctx)
4474 {
4475 TCGLabel *l1 = gen_new_label();
4476 TCGLabel *l2 = gen_new_label();
4477 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4478 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4479 tcg_gen_br(l2);
4480 gen_set_label(l1);
4481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4482 gen_set_label(l2);
4483 if (unlikely(Rc(ctx->opcode) != 0))
4484 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4485 }
4486
4487 /* abso - abso. */
4488 static void gen_abso(DisasContext *ctx)
4489 {
4490 TCGLabel *l1 = gen_new_label();
4491 TCGLabel *l2 = gen_new_label();
4492 TCGLabel *l3 = gen_new_label();
4493 /* Start with XER OV disabled, the most likely case */
4494 tcg_gen_movi_tl(cpu_ov, 0);
4495 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4496 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4497 tcg_gen_movi_tl(cpu_ov, 1);
4498 tcg_gen_movi_tl(cpu_so, 1);
4499 tcg_gen_br(l2);
4500 gen_set_label(l1);
4501 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4502 tcg_gen_br(l3);
4503 gen_set_label(l2);
4504 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4505 gen_set_label(l3);
4506 if (unlikely(Rc(ctx->opcode) != 0))
4507 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4508 }
4509
4510 /* clcs */
4511 static void gen_clcs(DisasContext *ctx)
4512 {
4513 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4514 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4515 tcg_temp_free_i32(t0);
4516 /* Rc=1 sets CR0 to an undefined state */
4517 }
4518
4519 /* div - div. */
4520 static void gen_div(DisasContext *ctx)
4521 {
4522 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4523 cpu_gpr[rB(ctx->opcode)]);
4524 if (unlikely(Rc(ctx->opcode) != 0))
4525 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4526 }
4527
4528 /* divo - divo. */
4529 static void gen_divo(DisasContext *ctx)
4530 {
4531 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4532 cpu_gpr[rB(ctx->opcode)]);
4533 if (unlikely(Rc(ctx->opcode) != 0))
4534 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4535 }
4536
4537 /* divs - divs. */
4538 static void gen_divs(DisasContext *ctx)
4539 {
4540 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4541 cpu_gpr[rB(ctx->opcode)]);
4542 if (unlikely(Rc(ctx->opcode) != 0))
4543 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4544 }
4545
4546 /* divso - divso. */
4547 static void gen_divso(DisasContext *ctx)
4548 {
4549 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4550 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4551 if (unlikely(Rc(ctx->opcode) != 0))
4552 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4553 }
4554
4555 /* doz - doz. */
4556 static void gen_doz(DisasContext *ctx)
4557 {
4558 TCGLabel *l1 = gen_new_label();
4559 TCGLabel *l2 = gen_new_label();
4560 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4561 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4562 tcg_gen_br(l2);
4563 gen_set_label(l1);
4564 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4565 gen_set_label(l2);
4566 if (unlikely(Rc(ctx->opcode) != 0))
4567 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4568 }
4569
4570 /* dozo - dozo. */
4571 static void gen_dozo(DisasContext *ctx)
4572 {
4573 TCGLabel *l1 = gen_new_label();
4574 TCGLabel *l2 = gen_new_label();
4575 TCGv t0 = tcg_temp_new();
4576 TCGv t1 = tcg_temp_new();
4577 TCGv t2 = tcg_temp_new();
4578 /* Start with XER OV disabled, the most likely case */
4579 tcg_gen_movi_tl(cpu_ov, 0);
4580 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4581 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4582 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4583 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4584 tcg_gen_andc_tl(t1, t1, t2);
4585 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4586 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4587 tcg_gen_movi_tl(cpu_ov, 1);
4588 tcg_gen_movi_tl(cpu_so, 1);
4589 tcg_gen_br(l2);
4590 gen_set_label(l1);
4591 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4592 gen_set_label(l2);
4593 tcg_temp_free(t0);
4594 tcg_temp_free(t1);
4595 tcg_temp_free(t2);
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4598 }
4599
4600 /* dozi */
4601 static void gen_dozi(DisasContext *ctx)
4602 {
4603 target_long simm = SIMM(ctx->opcode);
4604 TCGLabel *l1 = gen_new_label();
4605 TCGLabel *l2 = gen_new_label();
4606 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4607 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4608 tcg_gen_br(l2);
4609 gen_set_label(l1);
4610 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4611 gen_set_label(l2);
4612 if (unlikely(Rc(ctx->opcode) != 0))
4613 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4614 }
4615
4616 /* lscbx - lscbx. */
4617 static void gen_lscbx(DisasContext *ctx)
4618 {
4619 TCGv t0 = tcg_temp_new();
4620 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4621 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4622 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4623
4624 gen_addr_reg_index(ctx, t0);
4625 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4626 tcg_temp_free_i32(t1);
4627 tcg_temp_free_i32(t2);
4628 tcg_temp_free_i32(t3);
4629 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4630 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4631 if (unlikely(Rc(ctx->opcode) != 0))
4632 gen_set_Rc0(ctx, t0);
4633 tcg_temp_free(t0);
4634 }
4635
4636 /* maskg - maskg. */
4637 static void gen_maskg(DisasContext *ctx)
4638 {
4639 TCGLabel *l1 = gen_new_label();
4640 TCGv t0 = tcg_temp_new();
4641 TCGv t1 = tcg_temp_new();
4642 TCGv t2 = tcg_temp_new();
4643 TCGv t3 = tcg_temp_new();
4644 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4645 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4646 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4647 tcg_gen_addi_tl(t2, t0, 1);
4648 tcg_gen_shr_tl(t2, t3, t2);
4649 tcg_gen_shr_tl(t3, t3, t1);
4650 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4651 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4652 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4653 gen_set_label(l1);
4654 tcg_temp_free(t0);
4655 tcg_temp_free(t1);
4656 tcg_temp_free(t2);
4657 tcg_temp_free(t3);
4658 if (unlikely(Rc(ctx->opcode) != 0))
4659 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4660 }
4661
4662 /* maskir - maskir. */
4663 static void gen_maskir(DisasContext *ctx)
4664 {
4665 TCGv t0 = tcg_temp_new();
4666 TCGv t1 = tcg_temp_new();
4667 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4668 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4669 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4670 tcg_temp_free(t0);
4671 tcg_temp_free(t1);
4672 if (unlikely(Rc(ctx->opcode) != 0))
4673 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4674 }
4675
4676 /* mul - mul. */
4677 static void gen_mul(DisasContext *ctx)
4678 {
4679 TCGv_i64 t0 = tcg_temp_new_i64();
4680 TCGv_i64 t1 = tcg_temp_new_i64();
4681 TCGv t2 = tcg_temp_new();
4682 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4683 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4684 tcg_gen_mul_i64(t0, t0, t1);
4685 tcg_gen_trunc_i64_tl(t2, t0);
4686 gen_store_spr(SPR_MQ, t2);
4687 tcg_gen_shri_i64(t1, t0, 32);
4688 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4689 tcg_temp_free_i64(t0);
4690 tcg_temp_free_i64(t1);
4691 tcg_temp_free(t2);
4692 if (unlikely(Rc(ctx->opcode) != 0))
4693 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4694 }
4695
4696 /* mulo - mulo. */
4697 static void gen_mulo(DisasContext *ctx)
4698 {
4699 TCGLabel *l1 = gen_new_label();
4700 TCGv_i64 t0 = tcg_temp_new_i64();
4701 TCGv_i64 t1 = tcg_temp_new_i64();
4702 TCGv t2 = tcg_temp_new();
4703 /* Start with XER OV disabled, the most likely case */
4704 tcg_gen_movi_tl(cpu_ov, 0);
4705 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4706 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4707 tcg_gen_mul_i64(t0, t0, t1);
4708 tcg_gen_trunc_i64_tl(t2, t0);
4709 gen_store_spr(SPR_MQ, t2);
4710 tcg_gen_shri_i64(t1, t0, 32);
4711 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4712 tcg_gen_ext32s_i64(t1, t0);
4713 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4714 tcg_gen_movi_tl(cpu_ov, 1);
4715 tcg_gen_movi_tl(cpu_so, 1);
4716 gen_set_label(l1);
4717 tcg_temp_free_i64(t0);
4718 tcg_temp_free_i64(t1);
4719 tcg_temp_free(t2);
4720 if (unlikely(Rc(ctx->opcode) != 0))
4721 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4722 }
4723
4724 /* nabs - nabs. */
4725 static void gen_nabs(DisasContext *ctx)
4726 {
4727 TCGLabel *l1 = gen_new_label();
4728 TCGLabel *l2 = gen_new_label();
4729 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4731 tcg_gen_br(l2);
4732 gen_set_label(l1);
4733 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4734 gen_set_label(l2);
4735 if (unlikely(Rc(ctx->opcode) != 0))
4736 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4737 }
4738
4739 /* nabso - nabso. */
4740 static void gen_nabso(DisasContext *ctx)
4741 {
4742 TCGLabel *l1 = gen_new_label();
4743 TCGLabel *l2 = gen_new_label();
4744 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4746 tcg_gen_br(l2);
4747 gen_set_label(l1);
4748 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4749 gen_set_label(l2);
4750 /* nabs never overflows */
4751 tcg_gen_movi_tl(cpu_ov, 0);
4752 if (unlikely(Rc(ctx->opcode) != 0))
4753 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4754 }
4755
4756 /* rlmi - rlmi. */
4757 static void gen_rlmi(DisasContext *ctx)
4758 {
4759 uint32_t mb = MB(ctx->opcode);
4760 uint32_t me = ME(ctx->opcode);
4761 TCGv t0 = tcg_temp_new();
4762 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4763 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4764 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4765 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4766 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4767 tcg_temp_free(t0);
4768 if (unlikely(Rc(ctx->opcode) != 0))
4769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4770 }
4771
4772 /* rrib - rrib. */
4773 static void gen_rrib(DisasContext *ctx)
4774 {
4775 TCGv t0 = tcg_temp_new();
4776 TCGv t1 = tcg_temp_new();
4777 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4778 tcg_gen_movi_tl(t1, 0x80000000);
4779 tcg_gen_shr_tl(t1, t1, t0);
4780 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4781 tcg_gen_and_tl(t0, t0, t1);
4782 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4783 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4784 tcg_temp_free(t0);
4785 tcg_temp_free(t1);
4786 if (unlikely(Rc(ctx->opcode) != 0))
4787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4788 }
4789
4790 /* sle - sle. */
4791 static void gen_sle(DisasContext *ctx)
4792 {
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4796 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4797 tcg_gen_subfi_tl(t1, 32, t1);
4798 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4799 tcg_gen_or_tl(t1, t0, t1);
4800 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4801 gen_store_spr(SPR_MQ, t1);
4802 tcg_temp_free(t0);
4803 tcg_temp_free(t1);
4804 if (unlikely(Rc(ctx->opcode) != 0))
4805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4806 }
4807
4808 /* sleq - sleq. */
4809 static void gen_sleq(DisasContext *ctx)
4810 {
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 TCGv t2 = tcg_temp_new();
4814 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4815 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4816 tcg_gen_shl_tl(t2, t2, t0);
4817 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4818 gen_load_spr(t1, SPR_MQ);
4819 gen_store_spr(SPR_MQ, t0);
4820 tcg_gen_and_tl(t0, t0, t2);
4821 tcg_gen_andc_tl(t1, t1, t2);
4822 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4823 tcg_temp_free(t0);
4824 tcg_temp_free(t1);
4825 tcg_temp_free(t2);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828 }
4829
4830 /* sliq - sliq. */
4831 static void gen_sliq(DisasContext *ctx)
4832 {
4833 int sh = SH(ctx->opcode);
4834 TCGv t0 = tcg_temp_new();
4835 TCGv t1 = tcg_temp_new();
4836 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4837 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4838 tcg_gen_or_tl(t1, t0, t1);
4839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4840 gen_store_spr(SPR_MQ, t1);
4841 tcg_temp_free(t0);
4842 tcg_temp_free(t1);
4843 if (unlikely(Rc(ctx->opcode) != 0))
4844 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4845 }
4846
4847 /* slliq - slliq. */
4848 static void gen_slliq(DisasContext *ctx)
4849 {
4850 int sh = SH(ctx->opcode);
4851 TCGv t0 = tcg_temp_new();
4852 TCGv t1 = tcg_temp_new();
4853 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4854 gen_load_spr(t1, SPR_MQ);
4855 gen_store_spr(SPR_MQ, t0);
4856 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4857 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4858 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
4861 if (unlikely(Rc(ctx->opcode) != 0))
4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4863 }
4864
4865 /* sllq - sllq. */
4866 static void gen_sllq(DisasContext *ctx)
4867 {
4868 TCGLabel *l1 = gen_new_label();
4869 TCGLabel *l2 = gen_new_label();
4870 TCGv t0 = tcg_temp_local_new();
4871 TCGv t1 = tcg_temp_local_new();
4872 TCGv t2 = tcg_temp_local_new();
4873 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4874 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4875 tcg_gen_shl_tl(t1, t1, t2);
4876 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4877 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4878 gen_load_spr(t0, SPR_MQ);
4879 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4880 tcg_gen_br(l2);
4881 gen_set_label(l1);
4882 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4883 gen_load_spr(t2, SPR_MQ);
4884 tcg_gen_andc_tl(t1, t2, t1);
4885 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4886 gen_set_label(l2);
4887 tcg_temp_free(t0);
4888 tcg_temp_free(t1);
4889 tcg_temp_free(t2);
4890 if (unlikely(Rc(ctx->opcode) != 0))
4891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4892 }
4893
4894 /* slq - slq. */
4895 static void gen_slq(DisasContext *ctx)
4896 {
4897 TCGLabel *l1 = gen_new_label();
4898 TCGv t0 = tcg_temp_new();
4899 TCGv t1 = tcg_temp_new();
4900 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4901 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4902 tcg_gen_subfi_tl(t1, 32, t1);
4903 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4904 tcg_gen_or_tl(t1, t0, t1);
4905 gen_store_spr(SPR_MQ, t1);
4906 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4907 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4908 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4909 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4910 gen_set_label(l1);
4911 tcg_temp_free(t0);
4912 tcg_temp_free(t1);
4913 if (unlikely(Rc(ctx->opcode) != 0))
4914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4915 }
4916
4917 /* sraiq - sraiq. */
4918 static void gen_sraiq(DisasContext *ctx)
4919 {
4920 int sh = SH(ctx->opcode);
4921 TCGLabel *l1 = gen_new_label();
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_new();
4924 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4925 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4926 tcg_gen_or_tl(t0, t0, t1);
4927 gen_store_spr(SPR_MQ, t0);
4928 tcg_gen_movi_tl(cpu_ca, 0);
4929 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4930 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4931 tcg_gen_movi_tl(cpu_ca, 1);
4932 gen_set_label(l1);
4933 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4934 tcg_temp_free(t0);
4935 tcg_temp_free(t1);
4936 if (unlikely(Rc(ctx->opcode) != 0))
4937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4938 }
4939
4940 /* sraq - sraq. */
4941 static void gen_sraq(DisasContext *ctx)
4942 {
4943 TCGLabel *l1 = gen_new_label();
4944 TCGLabel *l2 = gen_new_label();
4945 TCGv t0 = tcg_temp_new();
4946 TCGv t1 = tcg_temp_local_new();
4947 TCGv t2 = tcg_temp_local_new();
4948 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4949 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4950 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4951 tcg_gen_subfi_tl(t2, 32, t2);
4952 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4953 tcg_gen_or_tl(t0, t0, t2);
4954 gen_store_spr(SPR_MQ, t0);
4955 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4956 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4957 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4958 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4959 gen_set_label(l1);
4960 tcg_temp_free(t0);
4961 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4962 tcg_gen_movi_tl(cpu_ca, 0);
4963 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4964 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4965 tcg_gen_movi_tl(cpu_ca, 1);
4966 gen_set_label(l2);
4967 tcg_temp_free(t1);
4968 tcg_temp_free(t2);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4971 }
4972
4973 /* sre - sre. */
4974 static void gen_sre(DisasContext *ctx)
4975 {
4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_new();
4978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4979 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4980 tcg_gen_subfi_tl(t1, 32, t1);
4981 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4982 tcg_gen_or_tl(t1, t0, t1);
4983 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4984 gen_store_spr(SPR_MQ, t1);
4985 tcg_temp_free(t0);
4986 tcg_temp_free(t1);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4989 }
4990
4991 /* srea - srea. */
4992 static void gen_srea(DisasContext *ctx)
4993 {
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4998 gen_store_spr(SPR_MQ, t0);
4999 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5000 tcg_temp_free(t0);
5001 tcg_temp_free(t1);
5002 if (unlikely(Rc(ctx->opcode) != 0))
5003 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5004 }
5005
5006 /* sreq */
5007 static void gen_sreq(DisasContext *ctx)
5008 {
5009 TCGv t0 = tcg_temp_new();
5010 TCGv t1 = tcg_temp_new();
5011 TCGv t2 = tcg_temp_new();
5012 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5013 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5014 tcg_gen_shr_tl(t1, t1, t0);
5015 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5016 gen_load_spr(t2, SPR_MQ);
5017 gen_store_spr(SPR_MQ, t0);
5018 tcg_gen_and_tl(t0, t0, t1);
5019 tcg_gen_andc_tl(t2, t2, t1);
5020 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5021 tcg_temp_free(t0);
5022 tcg_temp_free(t1);
5023 tcg_temp_free(t2);
5024 if (unlikely(Rc(ctx->opcode) != 0))
5025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5026 }
5027
5028 /* sriq */
5029 static void gen_sriq(DisasContext *ctx)
5030 {
5031 int sh = SH(ctx->opcode);
5032 TCGv t0 = tcg_temp_new();
5033 TCGv t1 = tcg_temp_new();
5034 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5035 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5036 tcg_gen_or_tl(t1, t0, t1);
5037 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5038 gen_store_spr(SPR_MQ, t1);
5039 tcg_temp_free(t0);
5040 tcg_temp_free(t1);
5041 if (unlikely(Rc(ctx->opcode) != 0))
5042 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5043 }
5044
5045 /* srliq */
5046 static void gen_srliq(DisasContext *ctx)
5047 {
5048 int sh = SH(ctx->opcode);
5049 TCGv t0 = tcg_temp_new();
5050 TCGv t1 = tcg_temp_new();
5051 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5052 gen_load_spr(t1, SPR_MQ);
5053 gen_store_spr(SPR_MQ, t0);
5054 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5055 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5056 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5057 tcg_temp_free(t0);
5058 tcg_temp_free(t1);
5059 if (unlikely(Rc(ctx->opcode) != 0))
5060 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5061 }
5062
5063 /* srlq */
5064 static void gen_srlq(DisasContext *ctx)
5065 {
5066 TCGLabel *l1 = gen_new_label();
5067 TCGLabel *l2 = gen_new_label();
5068 TCGv t0 = tcg_temp_local_new();
5069 TCGv t1 = tcg_temp_local_new();
5070 TCGv t2 = tcg_temp_local_new();
5071 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5073 tcg_gen_shr_tl(t2, t1, t2);
5074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5075 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5076 gen_load_spr(t0, SPR_MQ);
5077 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5078 tcg_gen_br(l2);
5079 gen_set_label(l1);
5080 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5081 tcg_gen_and_tl(t0, t0, t2);
5082 gen_load_spr(t1, SPR_MQ);
5083 tcg_gen_andc_tl(t1, t1, t2);
5084 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5085 gen_set_label(l2);
5086 tcg_temp_free(t0);
5087 tcg_temp_free(t1);
5088 tcg_temp_free(t2);
5089 if (unlikely(Rc(ctx->opcode) != 0))
5090 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5091 }
5092
5093 /* srq */
5094 static void gen_srq(DisasContext *ctx)
5095 {
5096 TCGLabel *l1 = gen_new_label();
5097 TCGv t0 = tcg_temp_new();
5098 TCGv t1 = tcg_temp_new();
5099 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5100 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5101 tcg_gen_subfi_tl(t1, 32, t1);
5102 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5103 tcg_gen_or_tl(t1, t0, t1);
5104 gen_store_spr(SPR_MQ, t1);
5105 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5106 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5107 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5108 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5109 gen_set_label(l1);
5110 tcg_temp_free(t0);
5111 tcg_temp_free(t1);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5114 }
5115
5116 /* PowerPC 602 specific instructions */
5117
5118 /* dsa */
5119 static void gen_dsa(DisasContext *ctx)
5120 {
5121 /* XXX: TODO */
5122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5123 }
5124
5125 /* esa */
5126 static void gen_esa(DisasContext *ctx)
5127 {
5128 /* XXX: TODO */
5129 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5130 }
5131
5132 /* mfrom */
5133 static void gen_mfrom(DisasContext *ctx)
5134 {
5135 #if defined(CONFIG_USER_ONLY)
5136 GEN_PRIV;
5137 #else
5138 CHK_SV;
5139 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5140 #endif /* defined(CONFIG_USER_ONLY) */
5141 }
5142
5143 /* 602 - 603 - G2 TLB management */
5144
5145 /* tlbld */
5146 static void gen_tlbld_6xx(DisasContext *ctx)
5147 {
5148 #if defined(CONFIG_USER_ONLY)
5149 GEN_PRIV;
5150 #else
5151 CHK_SV;
5152 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5153 #endif /* defined(CONFIG_USER_ONLY) */
5154 }
5155
5156 /* tlbli */
5157 static void gen_tlbli_6xx(DisasContext *ctx)
5158 {
5159 #if defined(CONFIG_USER_ONLY)
5160 GEN_PRIV;
5161 #else
5162 CHK_SV;
5163 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5164 #endif /* defined(CONFIG_USER_ONLY) */
5165 }
5166
5167 /* 74xx TLB management */
5168
5169 /* tlbld */
5170 static void gen_tlbld_74xx(DisasContext *ctx)
5171 {
5172 #if defined(CONFIG_USER_ONLY)
5173 GEN_PRIV;
5174 #else
5175 CHK_SV;
5176 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5177 #endif /* defined(CONFIG_USER_ONLY) */
5178 }
5179
5180 /* tlbli */
5181 static void gen_tlbli_74xx(DisasContext *ctx)
5182 {
5183 #if defined(CONFIG_USER_ONLY)
5184 GEN_PRIV;
5185 #else
5186 CHK_SV;
5187 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5188 #endif /* defined(CONFIG_USER_ONLY) */
5189 }
5190
5191 /* POWER instructions not in PowerPC 601 */
5192
5193 /* clf */
5194 static void gen_clf(DisasContext *ctx)
5195 {
5196 /* Cache line flush: implemented as no-op */
5197 }
5198
5199 /* cli */
5200 static void gen_cli(DisasContext *ctx)
5201 {
5202 #if defined(CONFIG_USER_ONLY)
5203 GEN_PRIV;
5204 #else
5205 /* Cache line invalidate: privileged and treated as no-op */
5206 CHK_SV;
5207 #endif /* defined(CONFIG_USER_ONLY) */
5208 }
5209
5210 /* dclst */
5211 static void gen_dclst(DisasContext *ctx)
5212 {
5213 /* Data cache line store: treated as no-op */
5214 }
5215
5216 static void gen_mfsri(DisasContext *ctx)
5217 {
5218 #if defined(CONFIG_USER_ONLY)
5219 GEN_PRIV;
5220 #else
5221 int ra = rA(ctx->opcode);
5222 int rd = rD(ctx->opcode);
5223 TCGv t0;
5224
5225 CHK_SV;
5226 t0 = tcg_temp_new();
5227 gen_addr_reg_index(ctx, t0);
5228 tcg_gen_shri_tl(t0, t0, 28);
5229 tcg_gen_andi_tl(t0, t0, 0xF);
5230 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5231 tcg_temp_free(t0);
5232 if (ra != 0 && ra != rd)
5233 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5234 #endif /* defined(CONFIG_USER_ONLY) */
5235 }
5236
5237 static void gen_rac(DisasContext *ctx)
5238 {
5239 #if defined(CONFIG_USER_ONLY)
5240 GEN_PRIV;
5241 #else
5242 TCGv t0;
5243
5244 CHK_SV;
5245 t0 = tcg_temp_new();
5246 gen_addr_reg_index(ctx, t0);
5247 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5248 tcg_temp_free(t0);
5249 #endif /* defined(CONFIG_USER_ONLY) */
5250 }
5251
5252 static void gen_rfsvc(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 GEN_PRIV;
5256 #else
5257 CHK_SV;
5258
5259 gen_helper_rfsvc(cpu_env);
5260 gen_sync_exception(ctx);
5261 #endif /* defined(CONFIG_USER_ONLY) */
5262 }
5263
5264 #include "translate/fp-impl.c"
5265
5266 #include "translate/vmx-impl.c"
5267
5268 #include "translate/vsx-impl.c"
5269
5270 /* svc is not implemented for now */
5271
5272 /* BookE specific instructions */
5273
5274 /* XXX: not implemented on 440 ? */
5275 static void gen_mfapidi(DisasContext *ctx)
5276 {
5277 /* XXX: TODO */
5278 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5279 }
5280
5281 /* XXX: not implemented on 440 ? */
5282 static void gen_tlbiva(DisasContext *ctx)
5283 {
5284 #if defined(CONFIG_USER_ONLY)
5285 GEN_PRIV;
5286 #else
5287 TCGv t0;
5288
5289 CHK_SV;
5290 t0 = tcg_temp_new();
5291 gen_addr_reg_index(ctx, t0);
5292 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5293 tcg_temp_free(t0);
5294 #endif /* defined(CONFIG_USER_ONLY) */
5295 }
5296
5297 /* All 405 MAC instructions are translated here */
5298 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5299 int ra, int rb, int rt, int Rc)
5300 {
5301 TCGv t0, t1;
5302
5303 t0 = tcg_temp_local_new();
5304 t1 = tcg_temp_local_new();
5305
5306 switch (opc3 & 0x0D) {
5307 case 0x05:
5308 /* macchw - macchw. - macchwo - macchwo. */
5309 /* macchws - macchws. - macchwso - macchwso. */
5310 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5311 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5312 /* mulchw - mulchw. */
5313 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5314 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5315 tcg_gen_ext16s_tl(t1, t1);
5316 break;
5317 case 0x04:
5318 /* macchwu - macchwu. - macchwuo - macchwuo. */
5319 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5320 /* mulchwu - mulchwu. */
5321 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5322 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5323 tcg_gen_ext16u_tl(t1, t1);
5324 break;
5325 case 0x01:
5326 /* machhw - machhw. - machhwo - machhwo. */
5327 /* machhws - machhws. - machhwso - machhwso. */
5328 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5329 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5330 /* mulhhw - mulhhw. */
5331 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5332 tcg_gen_ext16s_tl(t0, t0);
5333 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5334 tcg_gen_ext16s_tl(t1, t1);
5335 break;
5336 case 0x00:
5337 /* machhwu - machhwu. - machhwuo - machhwuo. */
5338 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5339 /* mulhhwu - mulhhwu. */
5340 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5341 tcg_gen_ext16u_tl(t0, t0);
5342 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5343 tcg_gen_ext16u_tl(t1, t1);
5344 break;
5345 case 0x0D:
5346 /* maclhw - maclhw. - maclhwo - maclhwo. */
5347 /* maclhws - maclhws. - maclhwso - maclhwso. */
5348 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5349 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5350 /* mullhw - mullhw. */
5351 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5352 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5353 break;
5354 case 0x0C:
5355 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5356 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5357 /* mullhwu - mullhwu. */
5358 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5359 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5360 break;
5361 }
5362 if (opc2 & 0x04) {
5363 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5364 tcg_gen_mul_tl(t1, t0, t1);
5365 if (opc2 & 0x02) {
5366 /* nmultiply-and-accumulate (0x0E) */
5367 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5368 } else {
5369 /* multiply-and-accumulate (0x0C) */
5370 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5371 }
5372
5373 if (opc3 & 0x12) {
5374 /* Check overflow and/or saturate */
5375 TCGLabel *l1 = gen_new_label();
5376
5377 if (opc3 & 0x10) {
5378 /* Start with XER OV disabled, the most likely case */
5379 tcg_gen_movi_tl(cpu_ov, 0);
5380 }
5381 if (opc3 & 0x01) {
5382 /* Signed */
5383 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5384 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5385 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5386 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5387 if (opc3 & 0x02) {
5388 /* Saturate */
5389 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5390 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5391 }
5392 } else {
5393 /* Unsigned */
5394 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5395 if (opc3 & 0x02) {
5396 /* Saturate */
5397 tcg_gen_movi_tl(t0, UINT32_MAX);
5398 }
5399 }
5400 if (opc3 & 0x10) {
5401 /* Check overflow */
5402 tcg_gen_movi_tl(cpu_ov, 1);
5403 tcg_gen_movi_tl(cpu_so, 1);
5404 }
5405 gen_set_label(l1);
5406 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5407 }
5408 } else {
5409 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5410 }
5411 tcg_temp_free(t0);
5412 tcg_temp_free(t1);
5413 if (unlikely(Rc) != 0) {
5414 /* Update Rc0 */
5415 gen_set_Rc0(ctx, cpu_gpr[rt]);
5416 }
5417 }
5418
5419 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5420 static void glue(gen_, name)(DisasContext *ctx) \
5421 { \
5422 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5423 rD(ctx->opcode), Rc(ctx->opcode)); \
5424 }
5425
5426 /* macchw - macchw. */
5427 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5428 /* macchwo - macchwo. */
5429 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5430 /* macchws - macchws. */
5431 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5432 /* macchwso - macchwso. */
5433 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5434 /* macchwsu - macchwsu. */
5435 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5436 /* macchwsuo - macchwsuo. */
5437 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5438 /* macchwu - macchwu. */
5439 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5440 /* macchwuo - macchwuo. */
5441 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5442 /* machhw - machhw. */
5443 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5444 /* machhwo - machhwo. */
5445 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5446 /* machhws - machhws. */
5447 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5448 /* machhwso - machhwso. */
5449 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5450 /* machhwsu - machhwsu. */
5451 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5452 /* machhwsuo - machhwsuo. */
5453 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5454 /* machhwu - machhwu. */
5455 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5456 /* machhwuo - machhwuo. */
5457 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5458 /* maclhw - maclhw. */
5459 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5460 /* maclhwo - maclhwo. */
5461 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5462 /* maclhws - maclhws. */
5463 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5464 /* maclhwso - maclhwso. */
5465 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5466 /* maclhwu - maclhwu. */
5467 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5468 /* maclhwuo - maclhwuo. */
5469 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5470 /* maclhwsu - maclhwsu. */
5471 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5472 /* maclhwsuo - maclhwsuo. */
5473 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5474 /* nmacchw - nmacchw. */
5475 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5476 /* nmacchwo - nmacchwo. */
5477 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5478 /* nmacchws - nmacchws. */
5479 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5480 /* nmacchwso - nmacchwso. */
5481 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5482 /* nmachhw - nmachhw. */
5483 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5484 /* nmachhwo - nmachhwo. */
5485 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5486 /* nmachhws - nmachhws. */
5487 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5488 /* nmachhwso - nmachhwso. */
5489 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5490 /* nmaclhw - nmaclhw. */
5491 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5492 /* nmaclhwo - nmaclhwo. */
5493 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5494 /* nmaclhws - nmaclhws. */
5495 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5496 /* nmaclhwso - nmaclhwso. */
5497 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5498
5499 /* mulchw - mulchw. */
5500 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5501 /* mulchwu - mulchwu. */
5502 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5503 /* mulhhw - mulhhw. */
5504 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5505 /* mulhhwu - mulhhwu. */
5506 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5507 /* mullhw - mullhw. */
5508 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5509 /* mullhwu - mullhwu. */
5510 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5511
5512 /* mfdcr */
5513 static void gen_mfdcr(DisasContext *ctx)
5514 {
5515 #if defined(CONFIG_USER_ONLY)
5516 GEN_PRIV;
5517 #else
5518 TCGv dcrn;
5519
5520 CHK_SV;
5521 dcrn = tcg_const_tl(SPR(ctx->opcode));
5522 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5523 tcg_temp_free(dcrn);
5524 #endif /* defined(CONFIG_USER_ONLY) */
5525 }
5526
5527 /* mtdcr */
5528 static void gen_mtdcr(DisasContext *ctx)
5529 {
5530 #if defined(CONFIG_USER_ONLY)
5531 GEN_PRIV;
5532 #else
5533 TCGv dcrn;
5534
5535 CHK_SV;
5536 dcrn = tcg_const_tl(SPR(ctx->opcode));
5537 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5538 tcg_temp_free(dcrn);
5539 #endif /* defined(CONFIG_USER_ONLY) */
5540 }
5541
5542 /* mfdcrx */
5543 /* XXX: not implemented on 440 ? */
5544 static void gen_mfdcrx(DisasContext *ctx)
5545 {
5546 #if defined(CONFIG_USER_ONLY)
5547 GEN_PRIV;
5548 #else
5549 CHK_SV;
5550 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5551 cpu_gpr[rA(ctx->opcode)]);
5552 /* Note: Rc update flag set leads to undefined state of Rc0 */
5553 #endif /* defined(CONFIG_USER_ONLY) */
5554 }
5555
5556 /* mtdcrx */
5557 /* XXX: not implemented on 440 ? */
5558 static void gen_mtdcrx(DisasContext *ctx)
5559 {
5560 #if defined(CONFIG_USER_ONLY)
5561 GEN_PRIV;
5562 #else
5563 CHK_SV;
5564 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5565 cpu_gpr[rS(ctx->opcode)]);
5566 /* Note: Rc update flag set leads to undefined state of Rc0 */
5567 #endif /* defined(CONFIG_USER_ONLY) */
5568 }
5569
5570 /* mfdcrux (PPC 460) : user-mode access to DCR */
5571 static void gen_mfdcrux(DisasContext *ctx)
5572 {
5573 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5574 cpu_gpr[rA(ctx->opcode)]);
5575 /* Note: Rc update flag set leads to undefined state of Rc0 */
5576 }
5577
5578 /* mtdcrux (PPC 460) : user-mode access to DCR */
5579 static void gen_mtdcrux(DisasContext *ctx)
5580 {
5581 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5582 cpu_gpr[rS(ctx->opcode)]);
5583 /* Note: Rc update flag set leads to undefined state of Rc0 */
5584 }
5585
5586 /* dccci */
5587 static void gen_dccci(DisasContext *ctx)
5588 {
5589 CHK_SV;
5590 /* interpreted as no-op */
5591 }
5592
5593 /* dcread */
5594 static void gen_dcread(DisasContext *ctx)
5595 {
5596 #if defined(CONFIG_USER_ONLY)
5597 GEN_PRIV;
5598 #else
5599 TCGv EA, val;
5600
5601 CHK_SV;
5602 gen_set_access_type(ctx, ACCESS_CACHE);
5603 EA = tcg_temp_new();
5604 gen_addr_reg_index(ctx, EA);
5605 val = tcg_temp_new();
5606 gen_qemu_ld32u(ctx, val, EA);
5607 tcg_temp_free(val);
5608 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5609 tcg_temp_free(EA);
5610 #endif /* defined(CONFIG_USER_ONLY) */
5611 }
5612
5613 /* icbt */
5614 static void gen_icbt_40x(DisasContext *ctx)
5615 {
5616 /* interpreted as no-op */
5617 /* XXX: specification say this is treated as a load by the MMU
5618 * but does not generate any exception
5619 */
5620 }
5621
5622 /* iccci */
5623 static void gen_iccci(DisasContext *ctx)
5624 {
5625 CHK_SV;
5626 /* interpreted as no-op */
5627 }
5628
5629 /* icread */
5630 static void gen_icread(DisasContext *ctx)
5631 {
5632 CHK_SV;
5633 /* interpreted as no-op */
5634 }
5635
5636 /* rfci (supervisor only) */
5637 static void gen_rfci_40x(DisasContext *ctx)
5638 {
5639 #if defined(CONFIG_USER_ONLY)
5640 GEN_PRIV;
5641 #else
5642 CHK_SV;
5643 /* Restore CPU state */
5644 gen_helper_40x_rfci(cpu_env);
5645 gen_sync_exception(ctx);
5646 #endif /* defined(CONFIG_USER_ONLY) */
5647 }
5648
5649 static void gen_rfci(DisasContext *ctx)
5650 {
5651 #if defined(CONFIG_USER_ONLY)
5652 GEN_PRIV;
5653 #else
5654 CHK_SV;
5655 /* Restore CPU state */
5656 gen_helper_rfci(cpu_env);
5657 gen_sync_exception(ctx);
5658 #endif /* defined(CONFIG_USER_ONLY) */
5659 }
5660
5661 /* BookE specific */
5662
5663 /* XXX: not implemented on 440 ? */
5664 static void gen_rfdi(DisasContext *ctx)
5665 {
5666 #if defined(CONFIG_USER_ONLY)
5667 GEN_PRIV;
5668 #else
5669 CHK_SV;
5670 /* Restore CPU state */
5671 gen_helper_rfdi(cpu_env);
5672 gen_sync_exception(ctx);
5673 #endif /* defined(CONFIG_USER_ONLY) */
5674 }
5675
5676 /* XXX: not implemented on 440 ? */
5677 static void gen_rfmci(DisasContext *ctx)
5678 {
5679 #if defined(CONFIG_USER_ONLY)
5680 GEN_PRIV;
5681 #else
5682 CHK_SV;
5683 /* Restore CPU state */
5684 gen_helper_rfmci(cpu_env);
5685 gen_sync_exception(ctx);
5686 #endif /* defined(CONFIG_USER_ONLY) */
5687 }
5688
5689 /* TLB management - PowerPC 405 implementation */
5690
5691 /* tlbre */
5692 static void gen_tlbre_40x(DisasContext *ctx)
5693 {
5694 #if defined(CONFIG_USER_ONLY)
5695 GEN_PRIV;
5696 #else
5697 CHK_SV;
5698 switch (rB(ctx->opcode)) {
5699 case 0:
5700 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5701 cpu_gpr[rA(ctx->opcode)]);
5702 break;
5703 case 1:
5704 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5705 cpu_gpr[rA(ctx->opcode)]);
5706 break;
5707 default:
5708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5709 break;
5710 }
5711 #endif /* defined(CONFIG_USER_ONLY) */
5712 }
5713
5714 /* tlbsx - tlbsx. */
5715 static void gen_tlbsx_40x(DisasContext *ctx)
5716 {
5717 #if defined(CONFIG_USER_ONLY)
5718 GEN_PRIV;
5719 #else
5720 TCGv t0;
5721
5722 CHK_SV;
5723 t0 = tcg_temp_new();
5724 gen_addr_reg_index(ctx, t0);
5725 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5726 tcg_temp_free(t0);
5727 if (Rc(ctx->opcode)) {
5728 TCGLabel *l1 = gen_new_label();
5729 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5730 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5731 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5732 gen_set_label(l1);
5733 }
5734 #endif /* defined(CONFIG_USER_ONLY) */
5735 }
5736
5737 /* tlbwe */
5738 static void gen_tlbwe_40x(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 GEN_PRIV;
5742 #else
5743 CHK_SV;
5744
5745 switch (rB(ctx->opcode)) {
5746 case 0:
5747 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5748 cpu_gpr[rS(ctx->opcode)]);
5749 break;
5750 case 1:
5751 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5752 cpu_gpr[rS(ctx->opcode)]);
5753 break;
5754 default:
5755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5756 break;
5757 }
5758 #endif /* defined(CONFIG_USER_ONLY) */
5759 }
5760
5761 /* TLB management - PowerPC 440 implementation */
5762
5763 /* tlbre */
5764 static void gen_tlbre_440(DisasContext *ctx)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 GEN_PRIV;
5768 #else
5769 CHK_SV;
5770
5771 switch (rB(ctx->opcode)) {
5772 case 0:
5773 case 1:
5774 case 2:
5775 {
5776 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5777 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5778 t0, cpu_gpr[rA(ctx->opcode)]);
5779 tcg_temp_free_i32(t0);
5780 }
5781 break;
5782 default:
5783 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5784 break;
5785 }
5786 #endif /* defined(CONFIG_USER_ONLY) */
5787 }
5788
5789 /* tlbsx - tlbsx. */
5790 static void gen_tlbsx_440(DisasContext *ctx)
5791 {
5792 #if defined(CONFIG_USER_ONLY)
5793 GEN_PRIV;
5794 #else
5795 TCGv t0;
5796
5797 CHK_SV;
5798 t0 = tcg_temp_new();
5799 gen_addr_reg_index(ctx, t0);
5800 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5801 tcg_temp_free(t0);
5802 if (Rc(ctx->opcode)) {
5803 TCGLabel *l1 = gen_new_label();
5804 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5805 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5806 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5807 gen_set_label(l1);
5808 }
5809 #endif /* defined(CONFIG_USER_ONLY) */
5810 }
5811
5812 /* tlbwe */
5813 static void gen_tlbwe_440(DisasContext *ctx)
5814 {
5815 #if defined(CONFIG_USER_ONLY)
5816 GEN_PRIV;
5817 #else
5818 CHK_SV;
5819 switch (rB(ctx->opcode)) {
5820 case 0:
5821 case 1:
5822 case 2:
5823 {
5824 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5825 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5826 cpu_gpr[rS(ctx->opcode)]);
5827 tcg_temp_free_i32(t0);
5828 }
5829 break;
5830 default:
5831 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5832 break;
5833 }
5834 #endif /* defined(CONFIG_USER_ONLY) */
5835 }
5836
5837 /* TLB management - PowerPC BookE 2.06 implementation */
5838
5839 /* tlbre */
5840 static void gen_tlbre_booke206(DisasContext *ctx)
5841 {
5842 #if defined(CONFIG_USER_ONLY)
5843 GEN_PRIV;
5844 #else
5845 CHK_SV;
5846 gen_helper_booke206_tlbre(cpu_env);
5847 #endif /* defined(CONFIG_USER_ONLY) */
5848 }
5849
5850 /* tlbsx - tlbsx. */
5851 static void gen_tlbsx_booke206(DisasContext *ctx)
5852 {
5853 #if defined(CONFIG_USER_ONLY)
5854 GEN_PRIV;
5855 #else
5856 TCGv t0;
5857
5858 CHK_SV;
5859 if (rA(ctx->opcode)) {
5860 t0 = tcg_temp_new();
5861 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5862 } else {
5863 t0 = tcg_const_tl(0);
5864 }
5865
5866 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5867 gen_helper_booke206_tlbsx(cpu_env, t0);
5868 tcg_temp_free(t0);
5869 #endif /* defined(CONFIG_USER_ONLY) */
5870 }
5871
5872 /* tlbwe */
5873 static void gen_tlbwe_booke206(DisasContext *ctx)
5874 {
5875 #if defined(CONFIG_USER_ONLY)
5876 GEN_PRIV;
5877 #else
5878 CHK_SV;
5879 gen_helper_booke206_tlbwe(cpu_env);
5880 #endif /* defined(CONFIG_USER_ONLY) */
5881 }
5882
5883 static void gen_tlbivax_booke206(DisasContext *ctx)
5884 {
5885 #if defined(CONFIG_USER_ONLY)
5886 GEN_PRIV;
5887 #else
5888 TCGv t0;
5889
5890 CHK_SV;
5891 t0 = tcg_temp_new();
5892 gen_addr_reg_index(ctx, t0);
5893 gen_helper_booke206_tlbivax(cpu_env, t0);
5894 tcg_temp_free(t0);
5895 #endif /* defined(CONFIG_USER_ONLY) */
5896 }
5897
5898 static void gen_tlbilx_booke206(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 GEN_PRIV;
5902 #else
5903 TCGv t0;
5904
5905 CHK_SV;
5906 t0 = tcg_temp_new();
5907 gen_addr_reg_index(ctx, t0);
5908
5909 switch((ctx->opcode >> 21) & 0x3) {
5910 case 0:
5911 gen_helper_booke206_tlbilx0(cpu_env, t0);
5912 break;
5913 case 1:
5914 gen_helper_booke206_tlbilx1(cpu_env, t0);
5915 break;
5916 case 3:
5917 gen_helper_booke206_tlbilx3(cpu_env, t0);
5918 break;
5919 default:
5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5921 break;
5922 }
5923
5924 tcg_temp_free(t0);
5925 #endif /* defined(CONFIG_USER_ONLY) */
5926 }
5927
5928
5929 /* wrtee */
5930 static void gen_wrtee(DisasContext *ctx)
5931 {
5932 #if defined(CONFIG_USER_ONLY)
5933 GEN_PRIV;
5934 #else
5935 TCGv t0;
5936
5937 CHK_SV;
5938 t0 = tcg_temp_new();
5939 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5940 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5941 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5942 tcg_temp_free(t0);
5943 /* Stop translation to have a chance to raise an exception
5944 * if we just set msr_ee to 1
5945 */
5946 gen_stop_exception(ctx);
5947 #endif /* defined(CONFIG_USER_ONLY) */
5948 }
5949
5950 /* wrteei */
5951 static void gen_wrteei(DisasContext *ctx)
5952 {
5953 #if defined(CONFIG_USER_ONLY)
5954 GEN_PRIV;
5955 #else
5956 CHK_SV;
5957 if (ctx->opcode & 0x00008000) {
5958 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5959 /* Stop translation to have a chance to raise an exception */
5960 gen_stop_exception(ctx);
5961 } else {
5962 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5963 }
5964 #endif /* defined(CONFIG_USER_ONLY) */
5965 }
5966
5967 /* PowerPC 440 specific instructions */
5968
5969 /* dlmzb */
5970 static void gen_dlmzb(DisasContext *ctx)
5971 {
5972 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5973 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5974 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5975 tcg_temp_free_i32(t0);
5976 }
5977
5978 /* mbar replaces eieio on 440 */
5979 static void gen_mbar(DisasContext *ctx)
5980 {
5981 /* interpreted as no-op */
5982 }
5983
5984 /* msync replaces sync on 440 */
5985 static void gen_msync_4xx(DisasContext *ctx)
5986 {
5987 /* interpreted as no-op */
5988 }
5989
5990 /* icbt */
5991 static void gen_icbt_440(DisasContext *ctx)
5992 {
5993 /* interpreted as no-op */
5994 /* XXX: specification say this is treated as a load by the MMU
5995 * but does not generate any exception
5996 */
5997 }
5998
5999 /* Embedded.Processor Control */
6000
6001 static void gen_msgclr(DisasContext *ctx)
6002 {
6003 #if defined(CONFIG_USER_ONLY)
6004 GEN_PRIV;
6005 #else
6006 CHK_SV;
6007 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6008 #endif /* defined(CONFIG_USER_ONLY) */
6009 }
6010
6011 static void gen_msgsnd(DisasContext *ctx)
6012 {
6013 #if defined(CONFIG_USER_ONLY)
6014 GEN_PRIV;
6015 #else
6016 CHK_SV;
6017 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6018 #endif /* defined(CONFIG_USER_ONLY) */
6019 }
6020
6021
6022 #if defined(TARGET_PPC64)
6023 static void gen_maddld(DisasContext *ctx)
6024 {
6025 TCGv_i64 t1 = tcg_temp_new_i64();
6026
6027 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6028 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6029 tcg_temp_free_i64(t1);
6030 }
6031
6032 /* maddhd maddhdu */
6033 static void gen_maddhd_maddhdu(DisasContext *ctx)
6034 {
6035 TCGv_i64 lo = tcg_temp_new_i64();
6036 TCGv_i64 hi = tcg_temp_new_i64();
6037 TCGv_i64 t1 = tcg_temp_new_i64();
6038
6039 if (Rc(ctx->opcode)) {
6040 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6041 cpu_gpr[rB(ctx->opcode)]);
6042 tcg_gen_movi_i64(t1, 0);
6043 } else {
6044 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6045 cpu_gpr[rB(ctx->opcode)]);
6046 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6047 }
6048 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6049 cpu_gpr[rC(ctx->opcode)], t1);
6050 tcg_temp_free_i64(lo);
6051 tcg_temp_free_i64(hi);
6052 tcg_temp_free_i64(t1);
6053 }
6054 #endif /* defined(TARGET_PPC64) */
6055
6056 #include "translate/dfp-impl.c"
6057
6058 #include "translate/spe-impl.c"
6059
6060 static void gen_tbegin(DisasContext *ctx)
6061 {
6062 if (unlikely(!ctx->tm_enabled)) {
6063 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6064 return;
6065 }
6066 gen_helper_tbegin(cpu_env);
6067 }
6068
6069 #define GEN_TM_NOOP(name) \
6070 static inline void gen_##name(DisasContext *ctx) \
6071 { \
6072 if (unlikely(!ctx->tm_enabled)) { \
6073 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6074 return; \
6075 } \
6076 /* Because tbegin always fails in QEMU, these user \
6077 * space instructions all have a simple implementation: \
6078 * \
6079 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6080 * = 0b0 || 0b00 || 0b0 \
6081 */ \
6082 tcg_gen_movi_i32(cpu_crf[0], 0); \
6083 }
6084
6085 GEN_TM_NOOP(tend);
6086 GEN_TM_NOOP(tabort);
6087 GEN_TM_NOOP(tabortwc);
6088 GEN_TM_NOOP(tabortwci);
6089 GEN_TM_NOOP(tabortdc);
6090 GEN_TM_NOOP(tabortdci);
6091 GEN_TM_NOOP(tsr);
6092
6093 static void gen_tcheck(DisasContext *ctx)
6094 {
6095 if (unlikely(!ctx->tm_enabled)) {
6096 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6097 return;
6098 }
6099 /* Because tbegin always fails, the tcheck implementation
6100 * is simple:
6101 *
6102 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6103 * = 0b1 || 0b00 || 0b0
6104 */
6105 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6106 }
6107
6108 #if defined(CONFIG_USER_ONLY)
6109 #define GEN_TM_PRIV_NOOP(name) \
6110 static inline void gen_##name(DisasContext *ctx) \
6111 { \
6112 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6113 }
6114
6115 #else
6116
6117 #define GEN_TM_PRIV_NOOP(name) \
6118 static inline void gen_##name(DisasContext *ctx) \
6119 { \
6120 CHK_SV; \
6121 if (unlikely(!ctx->tm_enabled)) { \
6122 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6123 return; \
6124 } \
6125 /* Because tbegin always fails, the implementation is \
6126 * simple: \
6127 * \
6128 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6129 * = 0b0 || 0b00 | 0b0 \
6130 */ \
6131 tcg_gen_movi_i32(cpu_crf[0], 0); \
6132 }
6133
6134 #endif
6135
6136 GEN_TM_PRIV_NOOP(treclaim);
6137 GEN_TM_PRIV_NOOP(trechkpt);
6138
6139 static opcode_t opcodes[] = {
6140 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6141 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6142 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6143 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6144 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6145 #if defined(TARGET_PPC64)
6146 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6147 #endif
6148 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6149 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6150 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6151 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6152 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6153 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6154 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6155 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6156 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6157 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6158 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6159 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6160 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6161 #if defined(TARGET_PPC64)
6162 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6163 #endif
6164 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6165 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6166 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6167 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6168 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6169 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6170 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6171 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6172 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6173 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6174 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6175 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6176 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6177 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6178 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6179 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6180 #if defined(TARGET_PPC64)
6181 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6182 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6183 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6184 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6185 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6186 #endif
6187 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6188 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6189 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6190 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6191 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6192 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6193 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6194 #if defined(TARGET_PPC64)
6195 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6196 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6197 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6198 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6199 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6200 #endif
6201 #if defined(TARGET_PPC64)
6202 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6203 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6204 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6205 #endif
6206 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6207 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6208 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6209 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6210 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6211 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6212 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6213 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6214 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6215 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6216 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6217 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6218 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6219 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6220 #if defined(TARGET_PPC64)
6221 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6222 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6223 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6224 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6225 #endif
6226 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6227 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6228 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6229 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6230 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6231 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6232 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6233 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6234 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6235 #if defined(TARGET_PPC64)
6236 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6237 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6238 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6239 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6240 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6241 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6242 #endif
6243 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6244 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6245 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6246 #if defined(TARGET_PPC64)
6247 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6248 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6249 #endif
6250 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6251 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6252 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6253 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6254 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6255 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6256 #if defined(TARGET_PPC64)
6257 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6258 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6259 #endif
6260 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6261 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6262 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6263 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6264 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6265 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6266 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6267 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6268 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6269 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6270 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6271 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6272 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6273 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6274 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6275 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6276 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6277 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6278 #if defined(TARGET_PPC64)
6279 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6280 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6281 PPC_SEGMENT_64B),
6282 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6283 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6284 PPC_SEGMENT_64B),
6285 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6286 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6287 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6288 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6289 #endif
6290 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6291 /* XXX Those instructions will need to be handled differently for
6292 * different ISA versions */
6293 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6294 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6295 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6296 #if defined(TARGET_PPC64)
6297 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6298 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6299 #endif
6300 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6301 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6302 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6303 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6304 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6305 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6306 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6307 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6308 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6309 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6310 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6311 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6312 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6313 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6314 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6315 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6316 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6317 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6318 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6319 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6320 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6321 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6322 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6323 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6324 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6325 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6326 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6327 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6328 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6329 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6330 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6331 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6332 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6333 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6334 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6335 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6336 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6337 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6338 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6339 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6340 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6341 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6342 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6343 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6344 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6345 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6346 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6347 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6348 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6349 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6350 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6351 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6352 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6353 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6354 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6355 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6356 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6357 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6358 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6359 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6360 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6361 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6362 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6363 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6364 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6365 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6366 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6367 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6368 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6369 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6370 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6371 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6372 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6373 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6374 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6375 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6376 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6377 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6378 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6379 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6380 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6381 PPC_NONE, PPC2_BOOKE206),
6382 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6383 PPC_NONE, PPC2_BOOKE206),
6384 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6385 PPC_NONE, PPC2_BOOKE206),
6386 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6387 PPC_NONE, PPC2_BOOKE206),
6388 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6389 PPC_NONE, PPC2_BOOKE206),
6390 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6391 PPC_NONE, PPC2_PRCNTL),
6392 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6393 PPC_NONE, PPC2_PRCNTL),
6394 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6395 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6396 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6397 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6398 PPC_BOOKE, PPC2_BOOKE206),
6399 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6400 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6401 PPC_BOOKE, PPC2_BOOKE206),
6402 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6403 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6404 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6405 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6406 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6407 #if defined(TARGET_PPC64)
6408 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6409 PPC2_ISA300),
6410 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6411 #endif
6412
6413 #undef GEN_INT_ARITH_ADD
6414 #undef GEN_INT_ARITH_ADD_CONST
6415 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6416 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6417 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6418 add_ca, compute_ca, compute_ov) \
6419 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6420 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6421 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6422 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6423 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6424 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6425 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6426 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6427 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6428 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6429 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6430
6431 #undef GEN_INT_ARITH_DIVW
6432 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6433 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6434 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6435 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6436 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6437 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6438 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6439 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6440 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6441 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6442 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6443 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6444
6445 #if defined(TARGET_PPC64)
6446 #undef GEN_INT_ARITH_DIVD
6447 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6448 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6449 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6450 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6451 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6452 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6453
6454 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6455 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6456 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6457 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6458 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6459 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6460
6461 #undef GEN_INT_ARITH_MUL_HELPER
6462 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6463 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6464 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6465 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6466 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6467 #endif
6468
6469 #undef GEN_INT_ARITH_SUBF
6470 #undef GEN_INT_ARITH_SUBF_CONST
6471 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6472 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6473 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6474 add_ca, compute_ca, compute_ov) \
6475 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6476 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6477 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6478 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6479 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6480 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6481 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6482 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6483 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6484 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6485 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6486
6487 #undef GEN_LOGICAL1
6488 #undef GEN_LOGICAL2
6489 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6490 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6491 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6492 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6493 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6494 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6495 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6496 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6497 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6498 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6499 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6500 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6501 #if defined(TARGET_PPC64)
6502 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6503 #endif
6504
6505 #if defined(TARGET_PPC64)
6506 #undef GEN_PPC64_R2
6507 #undef GEN_PPC64_R4
6508 #define GEN_PPC64_R2(name, opc1, opc2) \
6509 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6510 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6511 PPC_64B)
6512 #define GEN_PPC64_R4(name, opc1, opc2) \
6513 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6514 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6515 PPC_64B), \
6516 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6517 PPC_64B), \
6518 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6519 PPC_64B)
6520 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6521 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6522 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6523 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6524 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6525 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6526 #endif
6527
6528 #undef GEN_LD
6529 #undef GEN_LDU
6530 #undef GEN_LDUX
6531 #undef GEN_LDX_E
6532 #undef GEN_LDS
6533 #define GEN_LD(name, ldop, opc, type) \
6534 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6535 #define GEN_LDU(name, ldop, opc, type) \
6536 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6537 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6538 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6539 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6540 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6541 #define GEN_LDS(name, ldop, op, type) \
6542 GEN_LD(name, ldop, op | 0x20, type) \
6543 GEN_LDU(name, ldop, op | 0x21, type) \
6544 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6545 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6546
6547 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6548 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6549 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6550 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6551 #if defined(TARGET_PPC64)
6552 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6553 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6554 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6555 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6556 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6557
6558 /* HV/P7 and later only */
6559 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6560 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6561 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6562 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6563 #endif
6564 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6565 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6566
6567 #undef GEN_ST
6568 #undef GEN_STU
6569 #undef GEN_STUX
6570 #undef GEN_STX_E
6571 #undef GEN_STS
6572 #define GEN_ST(name, stop, opc, type) \
6573 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6574 #define GEN_STU(name, stop, opc, type) \
6575 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6576 #define GEN_STUX(name, stop, opc2, opc3, type) \
6577 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6578 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6579 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6580 #define GEN_STS(name, stop, op, type) \
6581 GEN_ST(name, stop, op | 0x20, type) \
6582 GEN_STU(name, stop, op | 0x21, type) \
6583 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6584 GEN_STX(name, stop, 0x17, op | 0x00, type)
6585
6586 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6587 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6588 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6589 #if defined(TARGET_PPC64)
6590 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6591 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6592 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6593 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6594 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6595 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6596 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6597 #endif
6598 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6599 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6600
6601 #undef GEN_CRLOGIC
6602 #define GEN_CRLOGIC(name, tcg_op, opc) \
6603 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6604 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6605 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6606 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6607 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6608 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6609 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6610 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6611 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6612
6613 #undef GEN_MAC_HANDLER
6614 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6615 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6616 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6617 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6618 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6619 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6620 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6621 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6622 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6623 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6624 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6625 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6626 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6627 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6628 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6629 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6630 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6631 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6632 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6633 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6634 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6635 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6636 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6637 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6638 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6639 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6640 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6641 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6642 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6643 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6644 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6645 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6646 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6647 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6648 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6649 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6650 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6651 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6652 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6653 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6654 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6655 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6656 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6657 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6658
6659 #include "translate/fp-ops.c"
6660
6661 #include "translate/vmx-ops.c"
6662
6663 #include "translate/vsx-ops.c"
6664
6665 #include "translate/dfp-ops.c"
6666
6667 #include "translate/spe-ops.c"
6668
6669 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6670 PPC_NONE, PPC2_TM),
6671 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6672 PPC_NONE, PPC2_TM),
6673 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6674 PPC_NONE, PPC2_TM),
6675 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6676 PPC_NONE, PPC2_TM),
6677 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6678 PPC_NONE, PPC2_TM),
6679 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6680 PPC_NONE, PPC2_TM),
6681 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6682 PPC_NONE, PPC2_TM),
6683 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6684 PPC_NONE, PPC2_TM),
6685 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6686 PPC_NONE, PPC2_TM),
6687 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6688 PPC_NONE, PPC2_TM),
6689 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6690 PPC_NONE, PPC2_TM),
6691 };
6692
6693 #include "helper_regs.h"
6694 #include "translate_init.c"
6695
6696 /*****************************************************************************/
6697 /* Misc PowerPC helpers */
6698 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6699 int flags)
6700 {
6701 #define RGPL 4
6702 #define RFPL 4
6703
6704 PowerPCCPU *cpu = POWERPC_CPU(cs);
6705 CPUPPCState *env = &cpu->env;
6706 int i;
6707
6708 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6709 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6710 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6711 cs->cpu_index);
6712 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6713 TARGET_FMT_lx " iidx %d didx %d\n",
6714 env->msr, env->spr[SPR_HID0],
6715 env->hflags, env->immu_idx, env->dmmu_idx);
6716 #if !defined(NO_TIMER_DUMP)
6717 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6718 #if !defined(CONFIG_USER_ONLY)
6719 " DECR %08" PRIu32
6720 #endif
6721 "\n",
6722 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6723 #if !defined(CONFIG_USER_ONLY)
6724 , cpu_ppc_load_decr(env)
6725 #endif
6726 );
6727 #endif
6728 for (i = 0; i < 32; i++) {
6729 if ((i & (RGPL - 1)) == 0)
6730 cpu_fprintf(f, "GPR%02d", i);
6731 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6732 if ((i & (RGPL - 1)) == (RGPL - 1))
6733 cpu_fprintf(f, "\n");
6734 }
6735 cpu_fprintf(f, "CR ");
6736 for (i = 0; i < 8; i++)
6737 cpu_fprintf(f, "%01x", env->crf[i]);
6738 cpu_fprintf(f, " [");
6739 for (i = 0; i < 8; i++) {
6740 char a = '-';
6741 if (env->crf[i] & 0x08)
6742 a = 'L';
6743 else if (env->crf[i] & 0x04)
6744 a = 'G';
6745 else if (env->crf[i] & 0x02)
6746 a = 'E';
6747 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6748 }
6749 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6750 env->reserve_addr);
6751 for (i = 0; i < 32; i++) {
6752 if ((i & (RFPL - 1)) == 0)
6753 cpu_fprintf(f, "FPR%02d", i);
6754 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6755 if ((i & (RFPL - 1)) == (RFPL - 1))
6756 cpu_fprintf(f, "\n");
6757 }
6758 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6759 #if !defined(CONFIG_USER_ONLY)
6760 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6761 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6762 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6763 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6764
6765 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6766 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6767 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6768 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6769
6770 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6771 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6772 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6773 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6774
6775 #if defined(TARGET_PPC64)
6776 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6777 env->excp_model == POWERPC_EXCP_POWER8) {
6778 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6779 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6780 }
6781 #endif
6782 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6783 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6784 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6785 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6786 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6787
6788 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6789 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6790 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6791 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6792
6793 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6794 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6795 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6796 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6797
6798 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6799 " EPR " TARGET_FMT_lx "\n",
6800 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6801 env->spr[SPR_BOOKE_EPR]);
6802
6803 /* FSL-specific */
6804 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6805 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6806 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6807 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6808
6809 /*
6810 * IVORs are left out as they are large and do not change often --
6811 * they can be read with "p $ivor0", "p $ivor1", etc.
6812 */
6813 }
6814
6815 #if defined(TARGET_PPC64)
6816 if (env->flags & POWERPC_FLAG_CFAR) {
6817 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6818 }
6819 #endif
6820
6821 switch (env->mmu_model) {
6822 case POWERPC_MMU_32B:
6823 case POWERPC_MMU_601:
6824 case POWERPC_MMU_SOFT_6xx:
6825 case POWERPC_MMU_SOFT_74xx:
6826 #if defined(TARGET_PPC64)
6827 case POWERPC_MMU_64B:
6828 case POWERPC_MMU_2_03:
6829 case POWERPC_MMU_2_06:
6830 case POWERPC_MMU_2_06a:
6831 case POWERPC_MMU_2_07:
6832 case POWERPC_MMU_2_07a:
6833 #endif
6834 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6835 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6836 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6837 break;
6838 case POWERPC_MMU_BOOKE206:
6839 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6840 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6841 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6842 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6843
6844 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6845 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6846 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6847 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6848
6849 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6850 " TLB1CFG " TARGET_FMT_lx "\n",
6851 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6852 env->spr[SPR_BOOKE_TLB1CFG]);
6853 break;
6854 default:
6855 break;
6856 }
6857 #endif
6858
6859 #undef RGPL
6860 #undef RFPL
6861 }
6862
6863 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6864 fprintf_function cpu_fprintf, int flags)
6865 {
6866 #if defined(DO_PPC_STATISTICS)
6867 PowerPCCPU *cpu = POWERPC_CPU(cs);
6868 opc_handler_t **t1, **t2, **t3, *handler;
6869 int op1, op2, op3;
6870
6871 t1 = cpu->env.opcodes;
6872 for (op1 = 0; op1 < 64; op1++) {
6873 handler = t1[op1];
6874 if (is_indirect_opcode(handler)) {
6875 t2 = ind_table(handler);
6876 for (op2 = 0; op2 < 32; op2++) {
6877 handler = t2[op2];
6878 if (is_indirect_opcode(handler)) {
6879 t3 = ind_table(handler);
6880 for (op3 = 0; op3 < 32; op3++) {
6881 handler = t3[op3];
6882 if (handler->count == 0)
6883 continue;
6884 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6885 "%016" PRIx64 " %" PRId64 "\n",
6886 op1, op2, op3, op1, (op3 << 5) | op2,
6887 handler->oname,
6888 handler->count, handler->count);
6889 }
6890 } else {
6891 if (handler->count == 0)
6892 continue;
6893 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6894 "%016" PRIx64 " %" PRId64 "\n",
6895 op1, op2, op1, op2, handler->oname,
6896 handler->count, handler->count);
6897 }
6898 }
6899 } else {
6900 if (handler->count == 0)
6901 continue;
6902 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6903 " %" PRId64 "\n",
6904 op1, op1, handler->oname,
6905 handler->count, handler->count);
6906 }
6907 }
6908 #endif
6909 }
6910
6911 /*****************************************************************************/
6912 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6913 {
6914 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6915 CPUState *cs = CPU(cpu);
6916 DisasContext ctx, *ctxp = &ctx;
6917 opc_handler_t **table, *handler;
6918 target_ulong pc_start;
6919 int num_insns;
6920 int max_insns;
6921
6922 pc_start = tb->pc;
6923 ctx.nip = pc_start;
6924 ctx.tb = tb;
6925 ctx.exception = POWERPC_EXCP_NONE;
6926 ctx.spr_cb = env->spr_cb;
6927 ctx.pr = msr_pr;
6928 ctx.mem_idx = env->dmmu_idx;
6929 ctx.dr = msr_dr;
6930 #if !defined(CONFIG_USER_ONLY)
6931 ctx.hv = msr_hv || !env->has_hv_mode;
6932 #endif
6933 ctx.insns_flags = env->insns_flags;
6934 ctx.insns_flags2 = env->insns_flags2;
6935 ctx.access_type = -1;
6936 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6937 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6938 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6939 #if defined(TARGET_PPC64)
6940 ctx.sf_mode = msr_is_64bit(env, env->msr);
6941 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6942 #endif
6943 if (env->mmu_model == POWERPC_MMU_32B ||
6944 env->mmu_model == POWERPC_MMU_601 ||
6945 (env->mmu_model & POWERPC_MMU_64B))
6946 ctx.lazy_tlb_flush = true;
6947
6948 ctx.fpu_enabled = !!msr_fp;
6949 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6950 ctx.spe_enabled = !!msr_spe;
6951 else
6952 ctx.spe_enabled = false;
6953 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6954 ctx.altivec_enabled = !!msr_vr;
6955 else
6956 ctx.altivec_enabled = false;
6957 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6958 ctx.vsx_enabled = !!msr_vsx;
6959 } else {
6960 ctx.vsx_enabled = false;
6961 }
6962 #if defined(TARGET_PPC64)
6963 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6964 ctx.tm_enabled = !!msr_tm;
6965 } else {
6966 ctx.tm_enabled = false;
6967 }
6968 #endif
6969 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6970 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6971 else
6972 ctx.singlestep_enabled = 0;
6973 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6974 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6975 if (unlikely(cs->singlestep_enabled)) {
6976 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6977 }
6978 #if defined (DO_SINGLE_STEP) && 0
6979 /* Single step trace mode */
6980 msr_se = 1;
6981 #endif
6982 num_insns = 0;
6983 max_insns = tb->cflags & CF_COUNT_MASK;
6984 if (max_insns == 0) {
6985 max_insns = CF_COUNT_MASK;
6986 }
6987 if (max_insns > TCG_MAX_INSNS) {
6988 max_insns = TCG_MAX_INSNS;
6989 }
6990
6991 gen_tb_start(tb);
6992 tcg_clear_temp_count();
6993 /* Set env in case of segfault during code fetch */
6994 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
6995 tcg_gen_insn_start(ctx.nip);
6996 num_insns++;
6997
6998 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
6999 gen_debug_exception(ctxp);
7000 /* The address covered by the breakpoint must be included in
7001 [tb->pc, tb->pc + tb->size) in order to for it to be
7002 properly cleared -- thus we increment the PC here so that
7003 the logic setting tb->size below does the right thing. */
7004 ctx.nip += 4;
7005 break;
7006 }
7007
7008 LOG_DISAS("----------------\n");
7009 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7010 ctx.nip, ctx.mem_idx, (int)msr_ir);
7011 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7012 gen_io_start();
7013 if (unlikely(need_byteswap(&ctx))) {
7014 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7015 } else {
7016 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7017 }
7018 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7019 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7020 opc3(ctx.opcode), opc4(ctx.opcode),
7021 ctx.le_mode ? "little" : "big");
7022 ctx.nip += 4;
7023 table = env->opcodes;
7024 handler = table[opc1(ctx.opcode)];
7025 if (is_indirect_opcode(handler)) {
7026 table = ind_table(handler);
7027 handler = table[opc2(ctx.opcode)];
7028 if (is_indirect_opcode(handler)) {
7029 table = ind_table(handler);
7030 handler = table[opc3(ctx.opcode)];
7031 if (is_indirect_opcode(handler)) {
7032 table = ind_table(handler);
7033 handler = table[opc4(ctx.opcode)];
7034 }
7035 }
7036 }
7037 /* Is opcode *REALLY* valid ? */
7038 if (unlikely(handler->handler == &gen_invalid)) {
7039 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7040 "%02x - %02x - %02x - %02x (%08x) "
7041 TARGET_FMT_lx " %d\n",
7042 opc1(ctx.opcode), opc2(ctx.opcode),
7043 opc3(ctx.opcode), opc4(ctx.opcode),
7044 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7045 } else {
7046 uint32_t inval;
7047
7048 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7049 inval = handler->inval2;
7050 } else {
7051 inval = handler->inval1;
7052 }
7053
7054 if (unlikely((ctx.opcode & inval) != 0)) {
7055 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7056 "%02x - %02x - %02x - %02x (%08x) "
7057 TARGET_FMT_lx "\n", ctx.opcode & inval,
7058 opc1(ctx.opcode), opc2(ctx.opcode),
7059 opc3(ctx.opcode), opc4(ctx.opcode),
7060 ctx.opcode, ctx.nip - 4);
7061 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7062 break;
7063 }
7064 }
7065 (*(handler->handler))(&ctx);
7066 #if defined(DO_PPC_STATISTICS)
7067 handler->count++;
7068 #endif
7069 /* Check trace mode exceptions */
7070 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7071 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7072 ctx.exception != POWERPC_SYSCALL &&
7073 ctx.exception != POWERPC_EXCP_TRAP &&
7074 ctx.exception != POWERPC_EXCP_BRANCH)) {
7075 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7076 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7077 (cs->singlestep_enabled) ||
7078 singlestep ||
7079 num_insns >= max_insns)) {
7080 /* if we reach a page boundary or are single stepping, stop
7081 * generation
7082 */
7083 break;
7084 }
7085 if (tcg_check_temp_count()) {
7086 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7087 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7088 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7089 exit(1);
7090 }
7091 }
7092 if (tb->cflags & CF_LAST_IO)
7093 gen_io_end();
7094 if (ctx.exception == POWERPC_EXCP_NONE) {
7095 gen_goto_tb(&ctx, 0, ctx.nip);
7096 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7097 if (unlikely(cs->singlestep_enabled)) {
7098 gen_debug_exception(ctxp);
7099 }
7100 /* Generate the return instruction */
7101 tcg_gen_exit_tb(0);
7102 }
7103 gen_tb_end(tb, num_insns);
7104
7105 tb->size = ctx.nip - pc_start;
7106 tb->icount = num_insns;
7107
7108 #if defined(DEBUG_DISAS)
7109 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7110 && qemu_log_in_addr_range(pc_start)) {
7111 int flags;
7112 flags = env->bfd_mach;
7113 flags |= ctx.le_mode << 16;
7114 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7115 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7116 qemu_log("\n");
7117 }
7118 #endif
7119 }
7120
7121 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7122 target_ulong *data)
7123 {
7124 env->nip = data[0];
7125 }
Random patches