target/mips/internal.h

   1 /*
   2  * MIPS internal definitions and helpers
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #ifndef MIPS_INTERNAL_H
   9 #define MIPS_INTERNAL_H
  10
  11 #include "exec/memattrs.h"
  12 #ifdef CONFIG_TCG
  13 #include "tcg/tcg-internal.h"
  14 #endif
  15
  16 /*
  17  * MMU types, the first four entries have the same layout as the
  18  * CP0C0_MT field.
  19  */
  20 enum mips_mmu_types {
  21     MMU_TYPE_NONE       = 0,
  22     MMU_TYPE_R4000      = 1,    /* Standard TLB */
  23     MMU_TYPE_BAT        = 2,    /* Block Address Translation */
  24     MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
  25     MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
  26     MMU_TYPE_R3000,
  27     MMU_TYPE_R6000,
  28     MMU_TYPE_R8000
  29 };
  30
  31 struct mips_def_t {
  32     const char *name;
  33     int32_t CP0_PRid;
  34     int32_t CP0_Config0;
  35     int32_t CP0_Config1;
  36     int32_t CP0_Config2;
  37     int32_t CP0_Config3;
  38     int32_t CP0_Config4;
  39     int32_t CP0_Config4_rw_bitmask;
  40     int32_t CP0_Config5;
  41     int32_t CP0_Config5_rw_bitmask;
  42     int32_t CP0_Config6;
  43     int32_t CP0_Config6_rw_bitmask;
  44     int32_t CP0_Config7;
  45     int32_t CP0_Config7_rw_bitmask;
  46     target_ulong CP0_LLAddr_rw_bitmask;
  47     int CP0_LLAddr_shift;
  48     int32_t SYNCI_Step;
  49     int32_t CCRes;
  50     int32_t CP0_Status_rw_bitmask;
  51     int32_t CP0_TCStatus_rw_bitmask;
  52     int32_t CP0_SRSCtl;
  53     int32_t CP1_fcr0;
  54     int32_t CP1_fcr31_rw_bitmask;
  55     int32_t CP1_fcr31;
  56     int32_t MSAIR;
  57     int32_t SEGBITS;
  58     int32_t PABITS;
  59     int32_t CP0_SRSConf0_rw_bitmask;
  60     int32_t CP0_SRSConf0;
  61     int32_t CP0_SRSConf1_rw_bitmask;
  62     int32_t CP0_SRSConf1;
  63     int32_t CP0_SRSConf2_rw_bitmask;
  64     int32_t CP0_SRSConf2;
  65     int32_t CP0_SRSConf3_rw_bitmask;
  66     int32_t CP0_SRSConf3;
  67     int32_t CP0_SRSConf4_rw_bitmask;
  68     int32_t CP0_SRSConf4;
  69     int32_t CP0_PageGrain_rw_bitmask;
  70     int32_t CP0_PageGrain;
  71     target_ulong CP0_EBaseWG_rw_bitmask;
  72     uint64_t insn_flags;
  73     enum mips_mmu_types mmu_type;
  74     int32_t SAARP;
  75 };
  76
  77 extern const char regnames[32][4];
  78 extern const char fregnames[32][4];
  79
  80 extern const struct mips_def_t mips_defs[];
  81 extern const int mips_defs_number;
  82
  83 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  84 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  85 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  86 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  87                                   MMUAccessType access_type,
  88                                   int mmu_idx, uintptr_t retaddr);
  89
  90 #define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
  91 #define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
  92 #define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
  93 #define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
  94 #define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)
  95
  96 #define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
  97 #define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)
  98
  99 #if !defined(CONFIG_USER_ONLY)
 100
 101 enum {
 102     TLBRET_XI = -6,
 103     TLBRET_RI = -5,
 104     TLBRET_DIRTY = -4,
 105     TLBRET_INVALID = -3,
 106     TLBRET_NOMATCH = -2,
 107     TLBRET_BADADDR = -1,
 108     TLBRET_MATCH = 0
 109 };
 110
 111 int get_physical_address(CPUMIPSState *env, hwaddr *physical,
 112                          int *prot, target_ulong real_address,
 113                          MMUAccessType access_type, int mmu_idx);
 114 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 115
 116 typedef struct r4k_tlb_t r4k_tlb_t;
 117 struct r4k_tlb_t {
 118     target_ulong VPN;
 119     uint32_t PageMask;
 120     uint16_t ASID;
 121     uint32_t MMID;
 122     unsigned int G:1;
 123     unsigned int C0:3;
 124     unsigned int C1:3;
 125     unsigned int V0:1;
 126     unsigned int V1:1;
 127     unsigned int D0:1;
 128     unsigned int D1:1;
 129     unsigned int XI0:1;
 130     unsigned int XI1:1;
 131     unsigned int RI0:1;
 132     unsigned int RI1:1;
 133     unsigned int EHINV:1;
 134     uint64_t PFN[2];
 135 };
 136
 137 struct CPUMIPSTLBContext {
 138     uint32_t nb_tlb;
 139     uint32_t tlb_in_use;
 140     int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 141                        target_ulong address, MMUAccessType access_type);
 142     void (*helper_tlbwi)(struct CPUMIPSState *env);
 143     void (*helper_tlbwr)(struct CPUMIPSState *env);
 144     void (*helper_tlbp)(struct CPUMIPSState *env);
 145     void (*helper_tlbr)(struct CPUMIPSState *env);
 146     void (*helper_tlbinv)(struct CPUMIPSState *env);
 147     void (*helper_tlbinvf)(struct CPUMIPSState *env);
 148     union {
 149         struct {
 150             r4k_tlb_t tlb[MIPS_TLB_MAX];
 151         } r4k;
 152     } mmu;
 153 };
 154
 155 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 156                                     vaddr addr, unsigned size,
 157                                     MMUAccessType access_type,
 158                                     int mmu_idx, MemTxAttrs attrs,
 159                                     MemTxResult response, uintptr_t retaddr);
 160 extern const VMStateDescription vmstate_mips_cpu;
 161
 162 #endif /* !CONFIG_USER_ONLY */
 163
 164 #define cpu_signal_handler cpu_mips_signal_handler
 165
 166 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 167 {
 168     return (env->CP0_Status & (1 << CP0St_IE)) &&
 169         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 170         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 171         !(env->hflags & MIPS_HFLAG_DM) &&
 172         /*
 173          * Note that the TCStatus IXMT field is initialized to zero,
 174          * and only MT capable cores can set it to one. So we don't
 175          * need to check for MT capabilities here.
 176          */
 177         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 178 }
 179
 180 /* Check if there is pending and not masked out interrupt */
 181 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 182 {
 183     int32_t pending;
 184     int32_t status;
 185     bool r;
 186
 187     pending = env->CP0_Cause & CP0Ca_IP_mask;
 188     status = env->CP0_Status & CP0Ca_IP_mask;
 189
 190     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 191         /*
 192          * A MIPS configured with a vectorizing external interrupt controller
 193          * will feed a vector into the Cause pending lines. The core treats
 194          * the status lines as a vector level, not as individual masks.
 195          */
 196         r = pending > status;
 197     } else {
 198         /*
 199          * A MIPS configured with compatibility or VInt (Vectored Interrupts)
 200          * treats the pending lines as individual interrupt lines, the status
 201          * lines are individual masks.
 202          */
 203         r = (pending & status) != 0;
 204     }
 205     return r;
 206 }
 207
 208 void mips_tcg_init(void);
 209
 210 void msa_reset(CPUMIPSState *env);
 211
 212 /* cp0_timer.c */
 213 uint32_t cpu_mips_get_count(CPUMIPSState *env);
 214 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 215 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 216 void cpu_mips_start_count(CPUMIPSState *env);
 217 void cpu_mips_stop_count(CPUMIPSState *env);
 218
 219 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
 220 {
 221     env->active_tc.PC = value & ~(target_ulong)1;
 222     if (value & 1) {
 223         env->hflags |= MIPS_HFLAG_M16;
 224     } else {
 225         env->hflags &= ~(MIPS_HFLAG_M16);
 226     }
 227 }
 228
 229 static inline void restore_pamask(CPUMIPSState *env)
 230 {
 231     if (env->hflags & MIPS_HFLAG_ELPA) {
 232         env->PAMask = (1ULL << env->PABITS) - 1;
 233     } else {
 234         env->PAMask = PAMASK_BASE;
 235     }
 236 }
 237
 238 static inline int mips_vpe_active(CPUMIPSState *env)
 239 {
 240     int active = 1;
 241
 242     /* Check that the VPE is enabled.  */
 243     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 244         active = 0;
 245     }
 246     /* Check that the VPE is activated.  */
 247     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 248         active = 0;
 249     }
 250
 251     /*
 252      * Now verify that there are active thread contexts in the VPE.
 253      *
 254      * This assumes the CPU model will internally reschedule threads
 255      * if the active one goes to sleep. If there are no threads available
 256      * the active one will be in a sleeping state, and we can turn off
 257      * the entire VPE.
 258      */
 259     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 260         /* TC is not activated.  */
 261         active = 0;
 262     }
 263     if (env->active_tc.CP0_TCHalt & 1) {
 264         /* TC is in halt state.  */
 265         active = 0;
 266     }
 267
 268     return active;
 269 }
 270
 271 static inline int mips_vp_active(CPUMIPSState *env)
 272 {
 273     CPUState *other_cs = first_cpu;
 274
 275     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 276     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 277         return 1;
 278     }
 279
 280     /* Check if the virtual processor is disabled due to a DVP */
 281     CPU_FOREACH(other_cs) {
 282         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 283         if ((&other_cpu->env != env) &&
 284             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 285             return 0;
 286         }
 287     }
 288     return 1;
 289 }
 290
 291 static inline void compute_hflags(CPUMIPSState *env)
 292 {
 293     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 294                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 295                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 296                      MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
 297                      MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 298     if (env->CP0_Status & (1 << CP0St_ERL)) {
 299         env->hflags |= MIPS_HFLAG_ERL;
 300     }
 301     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 302         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 303         !(env->hflags & MIPS_HFLAG_DM)) {
 304         env->hflags |= (env->CP0_Status >> CP0St_KSU) &
 305                        MIPS_HFLAG_KSU;
 306     }
 307 #if defined(TARGET_MIPS64)
 308     if ((env->insn_flags & ISA_MIPS3) &&
 309         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 310          (env->CP0_Status & (1 << CP0St_PX)) ||
 311          (env->CP0_Status & (1 << CP0St_UX)))) {
 312         env->hflags |= MIPS_HFLAG_64;
 313     }
 314
 315     if (!(env->insn_flags & ISA_MIPS3)) {
 316         env->hflags |= MIPS_HFLAG_AWRAP;
 317     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 318                !(env->CP0_Status & (1 << CP0St_UX))) {
 319         env->hflags |= MIPS_HFLAG_AWRAP;
 320     } else if (env->insn_flags & ISA_MIPS_R6) {
 321         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 322         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 323              !(env->CP0_Status & (1 << CP0St_SX))) ||
 324             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 325              !(env->CP0_Status & (1 << CP0St_KX)))) {
 326             env->hflags |= MIPS_HFLAG_AWRAP;
 327         }
 328     }
 329 #endif
 330     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 331          !(env->insn_flags & ISA_MIPS_R6)) ||
 332         !(env->hflags & MIPS_HFLAG_KSU)) {
 333         env->hflags |= MIPS_HFLAG_CP0;
 334     }
 335     if (env->CP0_Status & (1 << CP0St_CU1)) {
 336         env->hflags |= MIPS_HFLAG_FPU;
 337     }
 338     if (env->CP0_Status & (1 << CP0St_FR)) {
 339         env->hflags |= MIPS_HFLAG_F64;
 340     }
 341     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 342         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 343         env->hflags |= MIPS_HFLAG_SBRI;
 344     }
 345     if (env->insn_flags & ASE_DSP_R3) {
 346         /*
 347          * Our cpu supports DSP R3 ASE, so enable
 348          * access to DSP R3 resources.
 349          */
 350         if (env->CP0_Status & (1 << CP0St_MX)) {
 351             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 352                            MIPS_HFLAG_DSP_R3;
 353         }
 354     } else if (env->insn_flags & ASE_DSP_R2) {
 355         /*
 356          * Our cpu supports DSP R2 ASE, so enable
 357          * access to DSP R2 resources.
 358          */
 359         if (env->CP0_Status & (1 << CP0St_MX)) {
 360             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
 361         }
 362
 363     } else if (env->insn_flags & ASE_DSP) {
 364         /*
 365          * Our cpu supports DSP ASE, so enable
 366          * access to DSP resources.
 367          */
 368         if (env->CP0_Status & (1 << CP0St_MX)) {
 369             env->hflags |= MIPS_HFLAG_DSP;
 370         }
 371
 372     }
 373     if (env->insn_flags & ISA_MIPS_R2) {
 374         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 375             env->hflags |= MIPS_HFLAG_COP1X;
 376         }
 377     } else if (env->insn_flags & ISA_MIPS_R1) {
 378         if (env->hflags & MIPS_HFLAG_64) {
 379             env->hflags |= MIPS_HFLAG_COP1X;
 380         }
 381     } else if (env->insn_flags & ISA_MIPS4) {
 382         /*
 383          * All supported MIPS IV CPUs use the XX (CU3) to enable
 384          * and disable the MIPS IV extensions to the MIPS III ISA.
 385          * Some other MIPS IV CPUs ignore the bit, so the check here
 386          * would be too restrictive for them.
 387          */
 388         if (env->CP0_Status & (1U << CP0St_CU3)) {
 389             env->hflags |= MIPS_HFLAG_COP1X;
 390         }
 391     }
 392     if (ase_msa_available(env)) {
 393         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 394             env->hflags |= MIPS_HFLAG_MSA;
 395         }
 396     }
 397     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 398         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 399             env->hflags |= MIPS_HFLAG_FRE;
 400         }
 401     }
 402     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 403         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 404             env->hflags |= MIPS_HFLAG_ELPA;
 405         }
 406     }
 407 }
 408
 409 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 410 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 411 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 412
 413 const char *mips_exception_name(int32_t exception);
 414
 415 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 416                                           int error_code, uintptr_t pc);
 417
 418 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 419                                                     uint32_t exception,
 420                                                     uintptr_t pc)
 421 {
 422     do_raise_exception_err(env, exception, 0, pc);
 423 }
 424
 425 #endif