hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/sysbus.h"
  13 #include "ui/console.h"
  14 #include "framebuffer.h"
  15 #include "ui/pixel_ops.h"
  16 #include "qemu/timer.h"
  17 #include "qemu/log.h"
  18 #include "qemu/module.h"
  19
  20 #define PL110_CR_EN   0x001
  21 #define PL110_CR_BGR  0x100
  22 #define PL110_CR_BEBO 0x200
  23 #define PL110_CR_BEPO 0x400
  24 #define PL110_CR_PWR  0x800
  25 #define PL110_IE_NB   0x004
  26 #define PL110_IE_VC   0x008
  27
  28 enum pl110_bppmode
  29 {
  30     BPP_1,
  31     BPP_2,
  32     BPP_4,
  33     BPP_8,
  34     BPP_16,
  35     BPP_32,
  36     BPP_16_565, /* PL111 only */
  37     BPP_12      /* PL111 only */
  38 };
  39
  40
  41 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  42 enum pl110_version
  43 {
  44     PL110,
  45     PL110_VERSATILE,
  46     PL111
  47 };
  48
  49 #define TYPE_PL110 "pl110"
  50 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  51
  52 typedef struct PL110State {
  53     SysBusDevice parent_obj;
  54
  55     MemoryRegion iomem;
  56     MemoryRegionSection fbsection;
  57     QemuConsole *con;
  58     QEMUTimer *vblank_timer;
  59
  60     int version;
  61     uint32_t timing[4];
  62     uint32_t cr;
  63     uint32_t upbase;
  64     uint32_t lpbase;
  65     uint32_t int_status;
  66     uint32_t int_mask;
  67     int cols;
  68     int rows;
  69     enum pl110_bppmode bpp;
  70     int invalidate;
  71     uint32_t mux_ctrl;
  72     uint32_t palette[256];
  73     uint32_t raw_palette[128];
  74     qemu_irq irq;
  75 } PL110State;
  76
  77 static int vmstate_pl110_post_load(void *opaque, int version_id);
  78
  79 static const VMStateDescription vmstate_pl110 = {
  80     .name = "pl110",
  81     .version_id = 2,
  82     .minimum_version_id = 1,
  83     .post_load = vmstate_pl110_post_load,
  84     .fields = (VMStateField[]) {
  85         VMSTATE_INT32(version, PL110State),
  86         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  87         VMSTATE_UINT32(cr, PL110State),
  88         VMSTATE_UINT32(upbase, PL110State),
  89         VMSTATE_UINT32(lpbase, PL110State),
  90         VMSTATE_UINT32(int_status, PL110State),
  91         VMSTATE_UINT32(int_mask, PL110State),
  92         VMSTATE_INT32(cols, PL110State),
  93         VMSTATE_INT32(rows, PL110State),
  94         VMSTATE_UINT32(bpp, PL110State),
  95         VMSTATE_INT32(invalidate, PL110State),
  96         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
  97         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
  98         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
  99         VMSTATE_END_OF_LIST()
 100     }
 101 };
 102
 103 static const unsigned char pl110_id[] =
 104 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
 105
 106 static const unsigned char pl111_id[] = {
 107     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 108 };
 109
 110
 111 /* Indexed by pl110_version */
 112 static const unsigned char *idregs[] = {
 113     pl110_id,
 114     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 115      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 116      * itself has the same ID values as a stock PL110, and guests (in
 117      * particular Linux) rely on this. We emulate what the hardware does,
 118      * rather than what the docs claim it ought to do.
 119      */
 120     pl110_id,
 121     pl111_id
 122 };
 123
 124 #define BITS 8
 125 #include "pl110_template.h"
 126 #define BITS 15
 127 #include "pl110_template.h"
 128 #define BITS 16
 129 #include "pl110_template.h"
 130 #define BITS 24
 131 #include "pl110_template.h"
 132 #define BITS 32
 133 #include "pl110_template.h"
 134
 135 static int pl110_enabled(PL110State *s)
 136 {
 137   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 138 }
 139
 140 static void pl110_update_display(void *opaque)
 141 {
 142     PL110State *s = (PL110State *)opaque;
 143     SysBusDevice *sbd;
 144     DisplaySurface *surface = qemu_console_surface(s->con);
 145     drawfn* fntable;
 146     drawfn fn;
 147     int dest_width;
 148     int src_width;
 149     int bpp_offset;
 150     int first;
 151     int last;
 152
 153     if (!pl110_enabled(s)) {
 154         return;
 155     }
 156
 157     sbd = SYS_BUS_DEVICE(s);
 158
 159     switch (surface_bits_per_pixel(surface)) {
 160     case 0:
 161         return;
 162     case 8:
 163         fntable = pl110_draw_fn_8;
 164         dest_width = 1;
 165         break;
 166     case 15:
 167         fntable = pl110_draw_fn_15;
 168         dest_width = 2;
 169         break;
 170     case 16:
 171         fntable = pl110_draw_fn_16;
 172         dest_width = 2;
 173         break;
 174     case 24:
 175         fntable = pl110_draw_fn_24;
 176         dest_width = 3;
 177         break;
 178     case 32:
 179         fntable = pl110_draw_fn_32;
 180         dest_width = 4;
 181         break;
 182     default:
 183         fprintf(stderr, "pl110: Bad color depth\n");
 184         exit(1);
 185     }
 186     if (s->cr & PL110_CR_BGR)
 187         bpp_offset = 0;
 188     else
 189         bpp_offset = 24;
 190
 191     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 192         /* The PL110's native 16 bit mode is 5551; however
 193          * most boards with a PL110 implement an external
 194          * mux which allows bits to be reshuffled to give
 195          * 565 format. The mux is typically controlled by
 196          * an external system register.
 197          * This is controlled by a GPIO input pin
 198          * so boards can wire it up to their register.
 199          *
 200          * The PL111 straightforwardly implements both
 201          * 5551 and 565 under control of the bpp field
 202          * in the LCDControl register.
 203          */
 204         switch (s->mux_ctrl) {
 205         case 3: /* 565 BGR */
 206             bpp_offset = (BPP_16_565 - BPP_16);
 207             break;
 208         case 1: /* 5551 */
 209             break;
 210         case 0: /* 888; also if we have loaded vmstate from an old version */
 211         case 2: /* 565 RGB */
 212         default:
 213             /* treat as 565 but honour BGR bit */
 214             bpp_offset += (BPP_16_565 - BPP_16);
 215             break;
 216         }
 217     }
 218
 219     if (s->cr & PL110_CR_BEBO)
 220         fn = fntable[s->bpp + 8 + bpp_offset];
 221     else if (s->cr & PL110_CR_BEPO)
 222         fn = fntable[s->bpp + 16 + bpp_offset];
 223     else
 224         fn = fntable[s->bpp + bpp_offset];
 225
 226     src_width = s->cols;
 227     switch (s->bpp) {
 228     case BPP_1:
 229         src_width >>= 3;
 230         break;
 231     case BPP_2:
 232         src_width >>= 2;
 233         break;
 234     case BPP_4:
 235         src_width >>= 1;
 236         break;
 237     case BPP_8:
 238         break;
 239     case BPP_16:
 240     case BPP_16_565:
 241     case BPP_12:
 242         src_width <<= 1;
 243         break;
 244     case BPP_32:
 245         src_width <<= 2;
 246         break;
 247     }
 248     dest_width *= s->cols;
 249     first = 0;
 250     if (s->invalidate) {
 251         framebuffer_update_memory_section(&s->fbsection,
 252                                           sysbus_address_space(sbd),
 253                                           s->upbase,
 254                                           s->rows, src_width);
 255     }
 256
 257     framebuffer_update_display(surface, &s->fbsection,
 258                                s->cols, s->rows,
 259                                src_width, dest_width, 0,
 260                                s->invalidate,
 261                                fn, s->palette,
 262                                &first, &last);
 263
 264     if (first >= 0) {
 265         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 266     }
 267     s->invalidate = 0;
 268 }
 269
 270 static void pl110_invalidate_display(void * opaque)
 271 {
 272     PL110State *s = (PL110State *)opaque;
 273     s->invalidate = 1;
 274     if (pl110_enabled(s)) {
 275         qemu_console_resize(s->con, s->cols, s->rows);
 276     }
 277 }
 278
 279 static void pl110_update_palette(PL110State *s, int n)
 280 {
 281     DisplaySurface *surface = qemu_console_surface(s->con);
 282     int i;
 283     uint32_t raw;
 284     unsigned int r, g, b;
 285
 286     raw = s->raw_palette[n];
 287     n <<= 1;
 288     for (i = 0; i < 2; i++) {
 289         r = (raw & 0x1f) << 3;
 290         raw >>= 5;
 291         g = (raw & 0x1f) << 3;
 292         raw >>= 5;
 293         b = (raw & 0x1f) << 3;
 294         /* The I bit is ignored.  */
 295         raw >>= 6;
 296         switch (surface_bits_per_pixel(surface)) {
 297         case 8:
 298             s->palette[n] = rgb_to_pixel8(r, g, b);
 299             break;
 300         case 15:
 301             s->palette[n] = rgb_to_pixel15(r, g, b);
 302             break;
 303         case 16:
 304             s->palette[n] = rgb_to_pixel16(r, g, b);
 305             break;
 306         case 24:
 307         case 32:
 308             s->palette[n] = rgb_to_pixel32(r, g, b);
 309             break;
 310         }
 311         n++;
 312     }
 313 }
 314
 315 static void pl110_resize(PL110State *s, int width, int height)
 316 {
 317     if (width != s->cols || height != s->rows) {
 318         if (pl110_enabled(s)) {
 319             qemu_console_resize(s->con, width, height);
 320         }
 321     }
 322     s->cols = width;
 323     s->rows = height;
 324 }
 325
 326 /* Update interrupts.  */
 327 static void pl110_update(PL110State *s)
 328 {
 329     /* Raise IRQ if enabled and any status bit is 1 */
 330     if (s->int_status & s->int_mask) {
 331         qemu_irq_raise(s->irq);
 332     } else {
 333         qemu_irq_lower(s->irq);
 334     }
 335 }
 336
 337 static void pl110_vblank_interrupt(void *opaque)
 338 {
 339     PL110State *s = opaque;
 340
 341     /* Fire the vertical compare and next base IRQs and re-arm */
 342     s->int_status |= (PL110_IE_NB | PL110_IE_VC);
 343     timer_mod(s->vblank_timer,
 344               qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 345                                 NANOSECONDS_PER_SECOND / 60);
 346     pl110_update(s);
 347 }
 348
 349 static uint64_t pl110_read(void *opaque, hwaddr offset,
 350                            unsigned size)
 351 {
 352     PL110State *s = (PL110State *)opaque;
 353
 354     if (offset >= 0xfe0 && offset < 0x1000) {
 355         return idregs[s->version][(offset - 0xfe0) >> 2];
 356     }
 357     if (offset >= 0x200 && offset < 0x400) {
 358         return s->raw_palette[(offset - 0x200) >> 2];
 359     }
 360     switch (offset >> 2) {
 361     case 0: /* LCDTiming0 */
 362         return s->timing[0];
 363     case 1: /* LCDTiming1 */
 364         return s->timing[1];
 365     case 2: /* LCDTiming2 */
 366         return s->timing[2];
 367     case 3: /* LCDTiming3 */
 368         return s->timing[3];
 369     case 4: /* LCDUPBASE */
 370         return s->upbase;
 371     case 5: /* LCDLPBASE */
 372         return s->lpbase;
 373     case 6: /* LCDIMSC */
 374         if (s->version != PL110) {
 375             return s->cr;
 376         }
 377         return s->int_mask;
 378     case 7: /* LCDControl */
 379         if (s->version != PL110) {
 380             return s->int_mask;
 381         }
 382         return s->cr;
 383     case 8: /* LCDRIS */
 384         return s->int_status;
 385     case 9: /* LCDMIS */
 386         return s->int_status & s->int_mask;
 387     case 11: /* LCDUPCURR */
 388         /* TODO: Implement vertical refresh.  */
 389         return s->upbase;
 390     case 12: /* LCDLPCURR */
 391         return s->lpbase;
 392     default:
 393         qemu_log_mask(LOG_GUEST_ERROR,
 394                       "pl110_read: Bad offset %x\n", (int)offset);
 395         return 0;
 396     }
 397 }
 398
 399 static void pl110_write(void *opaque, hwaddr offset,
 400                         uint64_t val, unsigned size)
 401 {
 402     PL110State *s = (PL110State *)opaque;
 403     int n;
 404
 405     /* For simplicity invalidate the display whenever a control register
 406        is written to.  */
 407     s->invalidate = 1;
 408     if (offset >= 0x200 && offset < 0x400) {
 409         /* Palette.  */
 410         n = (offset - 0x200) >> 2;
 411         s->raw_palette[(offset - 0x200) >> 2] = val;
 412         pl110_update_palette(s, n);
 413         return;
 414     }
 415     switch (offset >> 2) {
 416     case 0: /* LCDTiming0 */
 417         s->timing[0] = val;
 418         n = ((val & 0xfc) + 4) * 4;
 419         pl110_resize(s, n, s->rows);
 420         break;
 421     case 1: /* LCDTiming1 */
 422         s->timing[1] = val;
 423         n = (val & 0x3ff) + 1;
 424         pl110_resize(s, s->cols, n);
 425         break;
 426     case 2: /* LCDTiming2 */
 427         s->timing[2] = val;
 428         break;
 429     case 3: /* LCDTiming3 */
 430         s->timing[3] = val;
 431         break;
 432     case 4: /* LCDUPBASE */
 433         s->upbase = val;
 434         break;
 435     case 5: /* LCDLPBASE */
 436         s->lpbase = val;
 437         break;
 438     case 6: /* LCDIMSC */
 439         if (s->version != PL110) {
 440             goto control;
 441         }
 442     imsc:
 443         s->int_mask = val;
 444         pl110_update(s);
 445         break;
 446     case 7: /* LCDControl */
 447         if (s->version != PL110) {
 448             goto imsc;
 449         }
 450     control:
 451         s->cr = val;
 452         s->bpp = (val >> 1) & 7;
 453         if (pl110_enabled(s)) {
 454             qemu_console_resize(s->con, s->cols, s->rows);
 455             timer_mod(s->vblank_timer,
 456                       qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 457                                         NANOSECONDS_PER_SECOND / 60);
 458         } else {
 459             timer_del(s->vblank_timer);
 460         }
 461         break;
 462     case 10: /* LCDICR */
 463         s->int_status &= ~val;
 464         pl110_update(s);
 465         break;
 466     default:
 467         qemu_log_mask(LOG_GUEST_ERROR,
 468                       "pl110_write: Bad offset %x\n", (int)offset);
 469     }
 470 }
 471
 472 static const MemoryRegionOps pl110_ops = {
 473     .read = pl110_read,
 474     .write = pl110_write,
 475     .endianness = DEVICE_NATIVE_ENDIAN,
 476 };
 477
 478 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 479 {
 480     PL110State *s = (PL110State *)opaque;
 481     s->mux_ctrl = level;
 482 }
 483
 484 static int vmstate_pl110_post_load(void *opaque, int version_id)
 485 {
 486     PL110State *s = opaque;
 487     /* Make sure we redraw, and at the right size */
 488     pl110_invalidate_display(s);
 489     return 0;
 490 }
 491
 492 static const GraphicHwOps pl110_gfx_ops = {
 493     .invalidate  = pl110_invalidate_display,
 494     .gfx_update  = pl110_update_display,
 495 };
 496
 497 static void pl110_realize(DeviceState *dev, Error **errp)
 498 {
 499     PL110State *s = PL110(dev);
 500     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 501
 502     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 503     sysbus_init_mmio(sbd, &s->iomem);
 504     sysbus_init_irq(sbd, &s->irq);
 505     s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 506                                    pl110_vblank_interrupt, s);
 507     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 508     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 509 }
 510
 511 static void pl110_init(Object *obj)
 512 {
 513     PL110State *s = PL110(obj);
 514
 515     s->version = PL110;
 516 }
 517
 518 static void pl110_versatile_init(Object *obj)
 519 {
 520     PL110State *s = PL110(obj);
 521
 522     s->version = PL110_VERSATILE;
 523 }
 524
 525 static void pl111_init(Object *obj)
 526 {
 527     PL110State *s = PL110(obj);
 528
 529     s->version = PL111;
 530 }
 531
 532 static void pl110_class_init(ObjectClass *klass, void *data)
 533 {
 534     DeviceClass *dc = DEVICE_CLASS(klass);
 535
 536     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 537     dc->vmsd = &vmstate_pl110;
 538     dc->realize = pl110_realize;
 539 }
 540
 541 static const TypeInfo pl110_info = {
 542     .name          = TYPE_PL110,
 543     .parent        = TYPE_SYS_BUS_DEVICE,
 544     .instance_size = sizeof(PL110State),
 545     .instance_init = pl110_init,
 546     .class_init    = pl110_class_init,
 547 };
 548
 549 static const TypeInfo pl110_versatile_info = {
 550     .name          = "pl110_versatile",
 551     .parent        = TYPE_PL110,
 552     .instance_init = pl110_versatile_init,
 553 };
 554
 555 static const TypeInfo pl111_info = {
 556     .name          = "pl111",
 557     .parent        = TYPE_PL110,
 558     .instance_init = pl111_init,
 559 };
 560
 561 static void pl110_register_types(void)
 562 {
 563     type_register_static(&pl110_info);
 564     type_register_static(&pl110_versatile_info);
 565     type_register_static(&pl111_info);
 566 }
 567
 568 type_init(pl110_register_types)