don't dereference NULL after failed strdup
[qemu/kevin.git] / target-cris / helper.c
blobff4f2fe1da57c1aa06d7191f62a5cd9de69323bd
1 /*
2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include <stdio.h>
22 #include <string.h>
24 #include "config.h"
25 #include "cpu.h"
26 #include "mmu.h"
27 #include "exec-all.h"
28 #include "host-utils.h"
31 //#define CRIS_HELPER_DEBUG
34 #ifdef CRIS_HELPER_DEBUG
35 #define D(x) x
36 #define D_LOG(...) qemu_log(__VA__ARGS__)
37 #else
38 #define D(x)
39 #define D_LOG(...) do { } while (0)
40 #endif
42 #if defined(CONFIG_USER_ONLY)
44 void do_interrupt (CPUState *env)
46 env->exception_index = -1;
47 env->pregs[PR_ERP] = env->pc;
50 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
51 int mmu_idx, int is_softmmu)
53 env->exception_index = 0xaa;
54 env->pregs[PR_EDA] = address;
55 cpu_dump_state(env, stderr, fprintf, 0);
56 return 1;
59 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
61 return addr;
64 #else /* !CONFIG_USER_ONLY */
67 static void cris_shift_ccs(CPUState *env)
69 uint32_t ccs;
70 /* Apply the ccs shift. */
71 ccs = env->pregs[PR_CCS];
72 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
73 env->pregs[PR_CCS] = ccs;
76 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
77 int mmu_idx, int is_softmmu)
79 struct cris_mmu_result res;
80 int prot, miss;
81 int r = -1;
82 target_ulong phy;
84 D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
85 miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
86 rw, mmu_idx);
87 if (miss)
89 if (env->exception_index == EXCP_BUSFAULT)
90 cpu_abort(env,
91 "CRIS: Illegal recursive bus fault."
92 "addr=%x rw=%d\n",
93 address, rw);
95 env->pregs[PR_EDA] = address;
96 env->exception_index = EXCP_BUSFAULT;
97 env->fault_vector = res.bf_vec;
98 r = 1;
100 else
103 * Mask off the cache selection bit. The ETRAX busses do not
104 * see the top bit.
106 phy = res.phy & ~0x80000000;
107 prot = res.prot;
108 r = tlb_set_page(env, address & TARGET_PAGE_MASK,
109 phy, prot, mmu_idx, is_softmmu);
111 if (r > 0)
112 D_LOG("%s returns %d irqreq=%x addr=%x"
113 " phy=%x ismmu=%d vec=%x pc=%x\n",
114 __func__, r, env->interrupt_request,
115 address, res.phy, is_softmmu, res.bf_vec, env->pc);
116 return r;
119 void do_interrupt(CPUState *env)
121 int ex_vec = -1;
123 D_LOG( "exception index=%d interrupt_req=%d\n",
124 env->exception_index,
125 env->interrupt_request);
127 switch (env->exception_index)
129 case EXCP_BREAK:
130 /* These exceptions are genereated by the core itself.
131 ERP should point to the insn following the brk. */
132 ex_vec = env->trap_vector;
133 env->pregs[PR_ERP] = env->pc;
134 break;
136 case EXCP_NMI:
137 /* NMI is hardwired to vector zero. */
138 ex_vec = 0;
139 env->pregs[PR_CCS] &= ~M_FLAG;
140 env->pregs[PR_NRP] = env->pc;
141 break;
143 case EXCP_BUSFAULT:
144 ex_vec = env->fault_vector;
145 env->pregs[PR_ERP] = env->pc;
146 break;
148 default:
149 /* The interrupt controller gives us the vector. */
150 ex_vec = env->interrupt_vector;
151 /* Normal interrupts are taken between
152 TB's. env->pc is valid here. */
153 env->pregs[PR_ERP] = env->pc;
154 break;
157 /* Fill in the IDX field. */
158 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
160 if (env->dslot) {
161 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
162 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
163 ex_vec, env->pc, env->dslot,
164 env->regs[R_SP],
165 env->pregs[PR_ERP], env->pregs[PR_PID],
166 env->pregs[PR_CCS],
167 env->cc_op, env->cc_mask);
168 /* We loose the btarget, btaken state here so rexec the
169 branch. */
170 env->pregs[PR_ERP] -= env->dslot;
171 /* Exception starts with dslot cleared. */
172 env->dslot = 0;
175 if (env->pregs[PR_CCS] & U_FLAG) {
176 /* Swap stack pointers. */
177 env->pregs[PR_USP] = env->regs[R_SP];
178 env->regs[R_SP] = env->ksp;
181 /* Apply the CRIS CCS shift. Clears U if set. */
182 cris_shift_ccs(env);
184 /* Now that we are in kernel mode, load the handlers address. */
185 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
187 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
188 __func__, env->pc, ex_vec,
189 env->pregs[PR_CCS],
190 env->pregs[PR_PID],
191 env->pregs[PR_ERP]);
194 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
196 uint32_t phy = addr;
197 struct cris_mmu_result res;
198 int miss;
199 miss = cris_mmu_translate(&res, env, addr, 0, 0);
200 if (!miss)
201 phy = res.phy;
202 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
203 return phy;
205 #endif