target-arm/translate-a64.c

   1 /*
   2  *  AArch64 translation
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24
  25 #include "cpu.h"
  26 #include "tcg-op.h"
  27 #include "qemu/log.h"
  28 #include "translate.h"
  29 #include "qemu/host-utils.h"
  30
  31 #include "exec/gen-icount.h"
  32
  33 #include "helper.h"
  34 #define GEN_HELPER 1
  35 #include "helper.h"
  36
  37 static TCGv_i64 cpu_X[32];
  38 static TCGv_i64 cpu_pc;
  39 static TCGv_i32 pstate;
  40
  41 static const char *regnames[] = {
  42     "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
  43     "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
  44     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
  45     "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
  46 };
  47
  48 /* initialize TCG globals.  */
  49 void a64_translate_init(void)
  50 {
  51     int i;
  52
  53     cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
  54                                     offsetof(CPUARMState, pc),
  55                                     "pc");
  56     for (i = 0; i < 32; i++) {
  57         cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
  58                                           offsetof(CPUARMState, xregs[i]),
  59                                           regnames[i]);
  60     }
  61
  62     pstate = tcg_global_mem_new_i32(TCG_AREG0,
  63                                     offsetof(CPUARMState, pstate),
  64                                     "pstate");
  65 }
  66
  67 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  68                             fprintf_function cpu_fprintf, int flags)
  69 {
  70     ARMCPU *cpu = ARM_CPU(cs);
  71     CPUARMState *env = &cpu->env;
  72     uint32_t psr = pstate_read(env);
  73     int i;
  74
  75     cpu_fprintf(f, "PC=%016"PRIx64"  SP=%016"PRIx64"\n",
  76             env->pc, env->xregs[31]);
  77     for (i = 0; i < 31; i++) {
  78         cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
  79         if ((i % 4) == 3) {
  80             cpu_fprintf(f, "\n");
  81         } else {
  82             cpu_fprintf(f, " ");
  83         }
  84     }
  85     cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
  86                 psr,
  87                 psr & PSTATE_N ? 'N' : '-',
  88                 psr & PSTATE_Z ? 'Z' : '-',
  89                 psr & PSTATE_C ? 'C' : '-',
  90                 psr & PSTATE_V ? 'V' : '-');
  91     cpu_fprintf(f, "\n");
  92 }
  93
  94 void gen_a64_set_pc_im(uint64_t val)
  95 {
  96     tcg_gen_movi_i64(cpu_pc, val);
  97 }
  98
  99 static void gen_exception(int excp)
 100 {
 101     TCGv_i32 tmp = tcg_temp_new_i32();
 102     tcg_gen_movi_i32(tmp, excp);
 103     gen_helper_exception(cpu_env, tmp);
 104     tcg_temp_free_i32(tmp);
 105 }
 106
 107 static void gen_exception_insn(DisasContext *s, int offset, int excp)
 108 {
 109     gen_a64_set_pc_im(s->pc - offset);
 110     gen_exception(excp);
 111     s->is_jmp = DISAS_EXC;
 112 }
 113
 114 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
 115 {
 116     /* No direct tb linking with singlestep or deterministic io */
 117     if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
 118         return false;
 119     }
 120
 121     /* Only link tbs from inside the same guest page */
 122     if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
 123         return false;
 124     }
 125
 126     return true;
 127 }
 128
 129 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
 130 {
 131     TranslationBlock *tb;
 132
 133     tb = s->tb;
 134     if (use_goto_tb(s, n, dest)) {
 135         tcg_gen_goto_tb(n);
 136         gen_a64_set_pc_im(dest);
 137         tcg_gen_exit_tb((tcg_target_long)tb + n);
 138         s->is_jmp = DISAS_TB_JUMP;
 139     } else {
 140         gen_a64_set_pc_im(dest);
 141         if (s->singlestep_enabled) {
 142             gen_exception(EXCP_DEBUG);
 143         }
 144         tcg_gen_exit_tb(0);
 145         s->is_jmp = DISAS_JUMP;
 146     }
 147 }
 148
 149 static void unallocated_encoding(DisasContext *s)
 150 {
 151     gen_exception_insn(s, 4, EXCP_UDEF);
 152 }
 153
 154 #define unsupported_encoding(s, insn)                                    \
 155     do {                                                                 \
 156         qemu_log_mask(LOG_UNIMP,                                         \
 157                       "%s:%d: unsupported instruction encoding 0x%08x "  \
 158                       "at pc=%016" PRIx64 "\n",                          \
 159                       __FILE__, __LINE__, insn, s->pc - 4);              \
 160         unallocated_encoding(s);                                         \
 161     } while (0);
 162
 163 static void init_tmp_a64_array(DisasContext *s)
 164 {
 165 #ifdef CONFIG_DEBUG_TCG
 166     int i;
 167     for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
 168         TCGV_UNUSED_I64(s->tmp_a64[i]);
 169     }
 170 #endif
 171     s->tmp_a64_count = 0;
 172 }
 173
 174 static void free_tmp_a64(DisasContext *s)
 175 {
 176     int i;
 177     for (i = 0; i < s->tmp_a64_count; i++) {
 178         tcg_temp_free_i64(s->tmp_a64[i]);
 179     }
 180     init_tmp_a64_array(s);
 181 }
 182
 183 static TCGv_i64 new_tmp_a64(DisasContext *s)
 184 {
 185     assert(s->tmp_a64_count < TMP_A64_MAX);
 186     return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
 187 }
 188
 189 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
 190 {
 191     TCGv_i64 t = new_tmp_a64(s);
 192     tcg_gen_movi_i64(t, 0);
 193     return t;
 194 }
 195
 196 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
 197 {
 198     if (reg == 31) {
 199         return new_tmp_a64_zero(s);
 200     } else {
 201         return cpu_X[reg];
 202     }
 203 }
 204
 205 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
 206  * representing the register contents. This TCGv is an auto-freed
 207  * temporary so it need not be explicitly freed, and may be modified.
 208  */
 209 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
 210 {
 211     TCGv_i64 v = new_tmp_a64(s);
 212     if (reg != 31) {
 213         if (sf) {
 214             tcg_gen_mov_i64(v, cpu_X[reg]);
 215         } else {
 216             tcg_gen_ext32u_i64(v, cpu_X[reg]);
 217         }
 218     } else {
 219         tcg_gen_movi_i64(v, 0);
 220     }
 221     return v;
 222 }
 223
 224 /*
 225  * the instruction disassembly implemented here matches
 226  * the instruction encoding classifications in chapter 3 (C3)
 227  * of the ARM Architecture Reference Manual (DDI0487A_a)
 228  */
 229
 230 /* C3.2.7 Unconditional branch (immediate)
 231  *   31  30       26 25                                  0
 232  * +----+-----------+-------------------------------------+
 233  * | op | 0 0 1 0 1 |                 imm26               |
 234  * +----+-----------+-------------------------------------+
 235  */
 236 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 237 {
 238     uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
 239
 240     if (insn & (1 << 31)) {
 241         /* C5.6.26 BL Branch with link */
 242         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
 243     }
 244
 245     /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
 246     gen_goto_tb(s, 0, addr);
 247 }
 248
 249 /* C3.2.1 Compare & branch (immediate)
 250  *   31  30         25  24  23                  5 4      0
 251  * +----+-------------+----+---------------------+--------+
 252  * | sf | 0 1 1 0 1 0 | op |         imm19       |   Rt   |
 253  * +----+-------------+----+---------------------+--------+
 254  */
 255 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
 256 {
 257     unsigned int sf, op, rt;
 258     uint64_t addr;
 259     int label_match;
 260     TCGv_i64 tcg_cmp;
 261
 262     sf = extract32(insn, 31, 1);
 263     op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
 264     rt = extract32(insn, 0, 5);
 265     addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
 266
 267     tcg_cmp = read_cpu_reg(s, rt, sf);
 268     label_match = gen_new_label();
 269
 270     tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
 271                         tcg_cmp, 0, label_match);
 272
 273     gen_goto_tb(s, 0, s->pc);
 274     gen_set_label(label_match);
 275     gen_goto_tb(s, 1, addr);
 276 }
 277
 278 /* C3.2.5 Test & branch (immediate)
 279  *   31  30         25  24  23   19 18          5 4    0
 280  * +----+-------------+----+-------+-------------+------+
 281  * | b5 | 0 1 1 0 1 1 | op |  b40  |    imm14    |  Rt  |
 282  * +----+-------------+----+-------+-------------+------+
 283  */
 284 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 285 {
 286     unsigned int bit_pos, op, rt;
 287     uint64_t addr;
 288     int label_match;
 289     TCGv_i64 tcg_cmp;
 290
 291     bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
 292     op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
 293     addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
 294     rt = extract32(insn, 0, 5);
 295
 296     tcg_cmp = tcg_temp_new_i64();
 297     tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
 298     label_match = gen_new_label();
 299     tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
 300                         tcg_cmp, 0, label_match);
 301     tcg_temp_free_i64(tcg_cmp);
 302     gen_goto_tb(s, 0, s->pc);
 303     gen_set_label(label_match);
 304     gen_goto_tb(s, 1, addr);
 305 }
 306
 307 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
 308  *  31           25  24  23                  5   4  3    0
 309  * +---------------+----+---------------------+----+------+
 310  * | 0 1 0 1 0 1 0 | o1 |         imm19       | o0 | cond |
 311  * +---------------+----+---------------------+----+------+
 312  */
 313 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
 314 {
 315     unsigned int cond;
 316     uint64_t addr;
 317
 318     if ((insn & (1 << 4)) || (insn & (1 << 24))) {
 319         unallocated_encoding(s);
 320         return;
 321     }
 322     addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
 323     cond = extract32(insn, 0, 4);
 324
 325     if (cond < 0x0e) {
 326         /* genuinely conditional branches */
 327         int label_match = gen_new_label();
 328         arm_gen_test_cc(cond, label_match);
 329         gen_goto_tb(s, 0, s->pc);
 330         gen_set_label(label_match);
 331         gen_goto_tb(s, 1, addr);
 332     } else {
 333         /* 0xe and 0xf are both "always" conditions */
 334         gen_goto_tb(s, 0, addr);
 335     }
 336 }
 337
 338 /* C5.6.68 HINT */
 339 static void handle_hint(DisasContext *s, uint32_t insn,
 340                         unsigned int op1, unsigned int op2, unsigned int crm)
 341 {
 342     unsigned int selector = crm << 3 | op2;
 343
 344     if (op1 != 3) {
 345         unallocated_encoding(s);
 346         return;
 347     }
 348
 349     switch (selector) {
 350     case 0: /* NOP */
 351         return;
 352     case 1: /* YIELD */
 353     case 2: /* WFE */
 354     case 3: /* WFI */
 355     case 4: /* SEV */
 356     case 5: /* SEVL */
 357         /* we treat all as NOP at least for now */
 358         return;
 359     default:
 360         /* default specified as NOP equivalent */
 361         return;
 362     }
 363 }
 364
 365 /* CLREX, DSB, DMB, ISB */
 366 static void handle_sync(DisasContext *s, uint32_t insn,
 367                         unsigned int op1, unsigned int op2, unsigned int crm)
 368 {
 369     if (op1 != 3) {
 370         unallocated_encoding(s);
 371         return;
 372     }
 373
 374     switch (op2) {
 375     case 2: /* CLREX */
 376         unsupported_encoding(s, insn);
 377         return;
 378     case 4: /* DSB */
 379     case 5: /* DMB */
 380     case 6: /* ISB */
 381         /* We don't emulate caches so barriers are no-ops */
 382         return;
 383     default:
 384         unallocated_encoding(s);
 385         return;
 386     }
 387 }
 388
 389 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
 390 static void handle_msr_i(DisasContext *s, uint32_t insn,
 391                          unsigned int op1, unsigned int op2, unsigned int crm)
 392 {
 393     unsupported_encoding(s, insn);
 394 }
 395
 396 /* C5.6.204 SYS */
 397 static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,
 398                        unsigned int op1, unsigned int op2,
 399                        unsigned int crn, unsigned int crm, unsigned int rt)
 400 {
 401     unsupported_encoding(s, insn);
 402 }
 403
 404 /* C5.6.129 MRS - move from system register */
 405 static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,
 406                        unsigned int op1, unsigned int op2,
 407                        unsigned int crn, unsigned int crm, unsigned int rt)
 408 {
 409     unsupported_encoding(s, insn);
 410 }
 411
 412 /* C5.6.131 MSR (register) - move to system register */
 413 static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,
 414                        unsigned int op1, unsigned int op2,
 415                        unsigned int crn, unsigned int crm, unsigned int rt)
 416 {
 417     unsupported_encoding(s, insn);
 418 }
 419
 420 /* C3.2.4 System
 421  *  31                 22 21  20 19 18 16 15   12 11    8 7   5 4    0
 422  * +---------------------+---+-----+-----+-------+-------+-----+------+
 423  * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 |  CRn  |  CRm  | op2 |  Rt  |
 424  * +---------------------+---+-----+-----+-------+-------+-----+------+
 425  */
 426 static void disas_system(DisasContext *s, uint32_t insn)
 427 {
 428     unsigned int l, op0, op1, crn, crm, op2, rt;
 429     l = extract32(insn, 21, 1);
 430     op0 = extract32(insn, 19, 2);
 431     op1 = extract32(insn, 16, 3);
 432     crn = extract32(insn, 12, 4);
 433     crm = extract32(insn, 8, 4);
 434     op2 = extract32(insn, 5, 3);
 435     rt = extract32(insn, 0, 5);
 436
 437     if (op0 == 0) {
 438         if (l || rt != 31) {
 439             unallocated_encoding(s);
 440             return;
 441         }
 442         switch (crn) {
 443         case 2: /* C5.6.68 HINT */
 444             handle_hint(s, insn, op1, op2, crm);
 445             break;
 446         case 3: /* CLREX, DSB, DMB, ISB */
 447             handle_sync(s, insn, op1, op2, crm);
 448             break;
 449         case 4: /* C5.6.130 MSR (immediate) */
 450             handle_msr_i(s, insn, op1, op2, crm);
 451             break;
 452         default:
 453             unallocated_encoding(s);
 454             break;
 455         }
 456         return;
 457     }
 458
 459     if (op0 == 1) {
 460         /* C5.6.204 SYS */
 461         handle_sys(s, insn, l, op1, op2, crn, crm, rt);
 462     } else if (l) { /* op0 > 1 */
 463         /* C5.6.129 MRS - move from system register */
 464         handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);
 465     } else {
 466         /* C5.6.131 MSR (register) - move to system register */
 467         handle_msr(s, insn, op0, op1, op2, crn, crm, rt);
 468     }
 469 }
 470
 471 /* Exception generation */
 472 static void disas_exc(DisasContext *s, uint32_t insn)
 473 {
 474     unsupported_encoding(s, insn);
 475 }
 476
 477 /* C3.2.7 Unconditional branch (register)
 478  *  31           25 24   21 20   16 15   10 9    5 4     0
 479  * +---------------+-------+-------+-------+------+-------+
 480  * | 1 1 0 1 0 1 1 |  opc  |  op2  |  op3  |  Rn  |  op4  |
 481  * +---------------+-------+-------+-------+------+-------+
 482  */
 483 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
 484 {
 485     unsigned int opc, op2, op3, rn, op4;
 486
 487     opc = extract32(insn, 21, 4);
 488     op2 = extract32(insn, 16, 5);
 489     op3 = extract32(insn, 10, 6);
 490     rn = extract32(insn, 5, 5);
 491     op4 = extract32(insn, 0, 5);
 492
 493     if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
 494         unallocated_encoding(s);
 495         return;
 496     }
 497
 498     switch (opc) {
 499     case 0: /* BR */
 500     case 2: /* RET */
 501         break;
 502     case 1: /* BLR */
 503         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
 504         break;
 505     case 4: /* ERET */
 506     case 5: /* DRPS */
 507         if (rn != 0x1f) {
 508             unallocated_encoding(s);
 509         } else {
 510             unsupported_encoding(s, insn);
 511         }
 512         return;
 513     default:
 514         unallocated_encoding(s);
 515         return;
 516     }
 517
 518     tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
 519     s->is_jmp = DISAS_JUMP;
 520 }
 521
 522 /* C3.2 Branches, exception generating and system instructions */
 523 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
 524 {
 525     switch (extract32(insn, 25, 7)) {
 526     case 0x0a: case 0x0b:
 527     case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
 528         disas_uncond_b_imm(s, insn);
 529         break;
 530     case 0x1a: case 0x5a: /* Compare & branch (immediate) */
 531         disas_comp_b_imm(s, insn);
 532         break;
 533     case 0x1b: case 0x5b: /* Test & branch (immediate) */
 534         disas_test_b_imm(s, insn);
 535         break;
 536     case 0x2a: /* Conditional branch (immediate) */
 537         disas_cond_b_imm(s, insn);
 538         break;
 539     case 0x6a: /* Exception generation / System */
 540         if (insn & (1 << 24)) {
 541             disas_system(s, insn);
 542         } else {
 543             disas_exc(s, insn);
 544         }
 545         break;
 546     case 0x6b: /* Unconditional branch (register) */
 547         disas_uncond_b_reg(s, insn);
 548         break;
 549     default:
 550         unallocated_encoding(s);
 551         break;
 552     }
 553 }
 554
 555 /* Load/store exclusive */
 556 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
 557 {
 558     unsupported_encoding(s, insn);
 559 }
 560
 561 /* Load register (literal) */
 562 static void disas_ld_lit(DisasContext *s, uint32_t insn)
 563 {
 564     unsupported_encoding(s, insn);
 565 }
 566
 567 /* Load/store pair (all forms) */
 568 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
 569 {
 570     unsupported_encoding(s, insn);
 571 }
 572
 573 /* Load/store register (all forms) */
 574 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
 575 {
 576     unsupported_encoding(s, insn);
 577 }
 578
 579 /* AdvSIMD load/store multiple structures */
 580 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
 581 {
 582     unsupported_encoding(s, insn);
 583 }
 584
 585 /* AdvSIMD load/store single structure */
 586 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
 587 {
 588     unsupported_encoding(s, insn);
 589 }
 590
 591 /* C3.3 Loads and stores */
 592 static void disas_ldst(DisasContext *s, uint32_t insn)
 593 {
 594     switch (extract32(insn, 24, 6)) {
 595     case 0x08: /* Load/store exclusive */
 596         disas_ldst_excl(s, insn);
 597         break;
 598     case 0x18: case 0x1c: /* Load register (literal) */
 599         disas_ld_lit(s, insn);
 600         break;
 601     case 0x28: case 0x29:
 602     case 0x2c: case 0x2d: /* Load/store pair (all forms) */
 603         disas_ldst_pair(s, insn);
 604         break;
 605     case 0x38: case 0x39:
 606     case 0x3c: case 0x3d: /* Load/store register (all forms) */
 607         disas_ldst_reg(s, insn);
 608         break;
 609     case 0x0c: /* AdvSIMD load/store multiple structures */
 610         disas_ldst_multiple_struct(s, insn);
 611         break;
 612     case 0x0d: /* AdvSIMD load/store single structure */
 613         disas_ldst_single_struct(s, insn);
 614         break;
 615     default:
 616         unallocated_encoding(s);
 617         break;
 618     }
 619 }
 620
 621 /* PC-rel. addressing */
 622 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
 623 {
 624     unsupported_encoding(s, insn);
 625 }
 626
 627 /* Add/subtract (immediate) */
 628 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
 629 {
 630     unsupported_encoding(s, insn);
 631 }
 632
 633 /* Logical (immediate) */
 634 static void disas_logic_imm(DisasContext *s, uint32_t insn)
 635 {
 636     unsupported_encoding(s, insn);
 637 }
 638
 639 /* Move wide (immediate) */
 640 static void disas_movw_imm(DisasContext *s, uint32_t insn)
 641 {
 642     unsupported_encoding(s, insn);
 643 }
 644
 645 /* Bitfield */
 646 static void disas_bitfield(DisasContext *s, uint32_t insn)
 647 {
 648     unsupported_encoding(s, insn);
 649 }
 650
 651 /* Extract */
 652 static void disas_extract(DisasContext *s, uint32_t insn)
 653 {
 654     unsupported_encoding(s, insn);
 655 }
 656
 657 /* C3.4 Data processing - immediate */
 658 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
 659 {
 660     switch (extract32(insn, 23, 6)) {
 661     case 0x20: case 0x21: /* PC-rel. addressing */
 662         disas_pc_rel_adr(s, insn);
 663         break;
 664     case 0x22: case 0x23: /* Add/subtract (immediate) */
 665         disas_add_sub_imm(s, insn);
 666         break;
 667     case 0x24: /* Logical (immediate) */
 668         disas_logic_imm(s, insn);
 669         break;
 670     case 0x25: /* Move wide (immediate) */
 671         disas_movw_imm(s, insn);
 672         break;
 673     case 0x26: /* Bitfield */
 674         disas_bitfield(s, insn);
 675         break;
 676     case 0x27: /* Extract */
 677         disas_extract(s, insn);
 678         break;
 679     default:
 680         unallocated_encoding(s);
 681         break;
 682     }
 683 }
 684
 685 /* Logical (shifted register) */
 686 static void disas_logic_reg(DisasContext *s, uint32_t insn)
 687 {
 688     unsupported_encoding(s, insn);
 689 }
 690
 691 /* Add/subtract (extended register) */
 692 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
 693 {
 694     unsupported_encoding(s, insn);
 695 }
 696
 697 /* Add/subtract (shifted register) */
 698 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
 699 {
 700     unsupported_encoding(s, insn);
 701 }
 702
 703 /* Data-processing (3 source) */
 704 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
 705 {
 706     unsupported_encoding(s, insn);
 707 }
 708
 709 /* Add/subtract (with carry) */
 710 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
 711 {
 712     unsupported_encoding(s, insn);
 713 }
 714
 715 /* Conditional compare (immediate) */
 716 static void disas_cc_imm(DisasContext *s, uint32_t insn)
 717 {
 718     unsupported_encoding(s, insn);
 719 }
 720
 721 /* Conditional compare (register) */
 722 static void disas_cc_reg(DisasContext *s, uint32_t insn)
 723 {
 724     unsupported_encoding(s, insn);
 725 }
 726
 727 /* Conditional select */
 728 static void disas_cond_select(DisasContext *s, uint32_t insn)
 729 {
 730     unsupported_encoding(s, insn);
 731 }
 732
 733 /* Data-processing (1 source) */
 734 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
 735 {
 736     unsupported_encoding(s, insn);
 737 }
 738
 739 /* Data-processing (2 source) */
 740 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
 741 {
 742     unsupported_encoding(s, insn);
 743 }
 744
 745 /* C3.5 Data processing - register */
 746 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
 747 {
 748     switch (extract32(insn, 24, 5)) {
 749     case 0x0a: /* Logical (shifted register) */
 750         disas_logic_reg(s, insn);
 751         break;
 752     case 0x0b: /* Add/subtract */
 753         if (insn & (1 << 21)) { /* (extended register) */
 754             disas_add_sub_ext_reg(s, insn);
 755         } else {
 756             disas_add_sub_reg(s, insn);
 757         }
 758         break;
 759     case 0x1b: /* Data-processing (3 source) */
 760         disas_data_proc_3src(s, insn);
 761         break;
 762     case 0x1a:
 763         switch (extract32(insn, 21, 3)) {
 764         case 0x0: /* Add/subtract (with carry) */
 765             disas_adc_sbc(s, insn);
 766             break;
 767         case 0x2: /* Conditional compare */
 768             if (insn & (1 << 11)) { /* (immediate) */
 769                 disas_cc_imm(s, insn);
 770             } else {            /* (register) */
 771                 disas_cc_reg(s, insn);
 772             }
 773             break;
 774         case 0x4: /* Conditional select */
 775             disas_cond_select(s, insn);
 776             break;
 777         case 0x6: /* Data-processing */
 778             if (insn & (1 << 30)) { /* (1 source) */
 779                 disas_data_proc_1src(s, insn);
 780             } else {            /* (2 source) */
 781                 disas_data_proc_2src(s, insn);
 782             }
 783             break;
 784         default:
 785             unallocated_encoding(s);
 786             break;
 787         }
 788         break;
 789     default:
 790         unallocated_encoding(s);
 791         break;
 792     }
 793 }
 794
 795 /* C3.6 Data processing - SIMD and floating point */
 796 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
 797 {
 798     unsupported_encoding(s, insn);
 799 }
 800
 801 /* C3.1 A64 instruction index by encoding */
 802 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
 803 {
 804     uint32_t insn;
 805
 806     insn = arm_ldl_code(env, s->pc, s->bswap_code);
 807     s->insn = insn;
 808     s->pc += 4;
 809
 810     switch (extract32(insn, 25, 4)) {
 811     case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
 812         unallocated_encoding(s);
 813         break;
 814     case 0x8: case 0x9: /* Data processing - immediate */
 815         disas_data_proc_imm(s, insn);
 816         break;
 817     case 0xa: case 0xb: /* Branch, exception generation and system insns */
 818         disas_b_exc_sys(s, insn);
 819         break;
 820     case 0x4:
 821     case 0x6:
 822     case 0xc:
 823     case 0xe:      /* Loads and stores */
 824         disas_ldst(s, insn);
 825         break;
 826     case 0x5:
 827     case 0xd:      /* Data processing - register */
 828         disas_data_proc_reg(s, insn);
 829         break;
 830     case 0x7:
 831     case 0xf:      /* Data processing - SIMD and floating point */
 832         disas_data_proc_simd_fp(s, insn);
 833         break;
 834     default:
 835         assert(FALSE); /* all 15 cases should be handled above */
 836         break;
 837     }
 838
 839     /* if we allocated any temporaries, free them here */
 840     free_tmp_a64(s);
 841 }
 842
 843 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 844                                         TranslationBlock *tb,
 845                                         bool search_pc)
 846 {
 847     CPUState *cs = CPU(cpu);
 848     CPUARMState *env = &cpu->env;
 849     DisasContext dc1, *dc = &dc1;
 850     CPUBreakpoint *bp;
 851     uint16_t *gen_opc_end;
 852     int j, lj;
 853     target_ulong pc_start;
 854     target_ulong next_page_start;
 855     int num_insns;
 856     int max_insns;
 857
 858     pc_start = tb->pc;
 859
 860     dc->tb = tb;
 861
 862     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
 863
 864     dc->is_jmp = DISAS_NEXT;
 865     dc->pc = pc_start;
 866     dc->singlestep_enabled = cs->singlestep_enabled;
 867     dc->condjmp = 0;
 868
 869     dc->aarch64 = 1;
 870     dc->thumb = 0;
 871     dc->bswap_code = 0;
 872     dc->condexec_mask = 0;
 873     dc->condexec_cond = 0;
 874 #if !defined(CONFIG_USER_ONLY)
 875     dc->user = 0;
 876 #endif
 877     dc->vfp_enabled = 0;
 878     dc->vec_len = 0;
 879     dc->vec_stride = 0;
 880
 881     init_tmp_a64_array(dc);
 882
 883     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
 884     lj = -1;
 885     num_insns = 0;
 886     max_insns = tb->cflags & CF_COUNT_MASK;
 887     if (max_insns == 0) {
 888         max_insns = CF_COUNT_MASK;
 889     }
 890
 891     gen_tb_start();
 892
 893     tcg_clear_temp_count();
 894
 895     do {
 896         if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
 897             QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 898                 if (bp->pc == dc->pc) {
 899                     gen_exception_insn(dc, 0, EXCP_DEBUG);
 900                     /* Advance PC so that clearing the breakpoint will
 901                        invalidate this TB.  */
 902                     dc->pc += 2;
 903                     goto done_generating;
 904                 }
 905             }
 906         }
 907
 908         if (search_pc) {
 909             j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
 910             if (lj < j) {
 911                 lj++;
 912                 while (lj < j) {
 913                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
 914                 }
 915             }
 916             tcg_ctx.gen_opc_pc[lj] = dc->pc;
 917             tcg_ctx.gen_opc_instr_start[lj] = 1;
 918             tcg_ctx.gen_opc_icount[lj] = num_insns;
 919         }
 920
 921         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
 922             gen_io_start();
 923         }
 924
 925         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
 926             tcg_gen_debug_insn_start(dc->pc);
 927         }
 928
 929         disas_a64_insn(env, dc);
 930
 931         if (tcg_check_temp_count()) {
 932             fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
 933                     dc->pc);
 934         }
 935
 936         /* Translation stops when a conditional branch is encountered.
 937          * Otherwise the subsequent code could get translated several times.
 938          * Also stop translation when a page boundary is reached.  This
 939          * ensures prefetch aborts occur at the right place.
 940          */
 941         num_insns++;
 942     } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
 943              !cs->singlestep_enabled &&
 944              !singlestep &&
 945              dc->pc < next_page_start &&
 946              num_insns < max_insns);
 947
 948     if (tb->cflags & CF_LAST_IO) {
 949         gen_io_end();
 950     }
 951
 952     if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
 953         /* Note that this means single stepping WFI doesn't halt the CPU.
 954          * For conditional branch insns this is harmless unreachable code as
 955          * gen_goto_tb() has already handled emitting the debug exception
 956          * (and thus a tb-jump is not possible when singlestepping).
 957          */
 958         assert(dc->is_jmp != DISAS_TB_JUMP);
 959         if (dc->is_jmp != DISAS_JUMP) {
 960             gen_a64_set_pc_im(dc->pc);
 961         }
 962         gen_exception(EXCP_DEBUG);
 963     } else {
 964         switch (dc->is_jmp) {
 965         case DISAS_NEXT:
 966             gen_goto_tb(dc, 1, dc->pc);
 967             break;
 968         default:
 969         case DISAS_JUMP:
 970         case DISAS_UPDATE:
 971             /* indicate that the hash table must be used to find the next TB */
 972             tcg_gen_exit_tb(0);
 973             break;
 974         case DISAS_TB_JUMP:
 975         case DISAS_EXC:
 976         case DISAS_SWI:
 977             break;
 978         case DISAS_WFI:
 979             /* This is a special case because we don't want to just halt the CPU
 980              * if trying to debug across a WFI.
 981              */
 982             gen_helper_wfi(cpu_env);
 983             break;
 984         }
 985     }
 986
 987 done_generating:
 988     gen_tb_end(tb, num_insns);
 989     *tcg_ctx.gen_opc_ptr = INDEX_op_end;
 990
 991 #ifdef DEBUG_DISAS
 992     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
 993         qemu_log("----------------\n");
 994         qemu_log("IN: %s\n", lookup_symbol(pc_start));
 995         log_target_disas(env, pc_start, dc->pc - pc_start,
 996                          dc->thumb | (dc->bswap_code << 1));
 997         qemu_log("\n");
 998     }
 999 #endif
1000     if (search_pc) {
1001         j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1002         lj++;
1003         while (lj <= j) {
1004             tcg_ctx.gen_opc_instr_start[lj++] = 0;
1005         }
1006     } else {
1007         tb->size = dc->pc - pc_start;
1008         tb->icount = num_insns;
1009     }
1010 }