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PPC: Fix crash on spapr_tce_table_finalize()
[qemu/kevin.git] / target-i386 / kvm.c
blobf92edfe14a78830db1992e2daff6373a3341fe1f
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "qapi/qmp/qerror.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_bndcfgs;
77 static bool has_msr_kvm_steal_time;
78 static int lm_capable_kernel;
79 static bool has_msr_hv_hypercall;
80 static bool has_msr_hv_vapic;
81 static bool has_msr_hv_tsc;
82 static bool has_msr_mtrr;
83 static bool has_msr_xss;
84
85 static bool has_msr_architectural_pmu;
86 static uint32_t num_architectural_pmu_counters;
87
88 bool kvm_allows_irq0_override(void)
89 {
90 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
91 }
92
93 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
94 {
95 struct kvm_cpuid2 *cpuid;
96 int r, size;
97
98 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
99 cpuid = g_malloc0(size);
100 cpuid->nent = max;
101 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
102 if (r == 0 && cpuid->nent >= max) {
103 r = -E2BIG;
104 }
105 if (r < 0) {
106 if (r == -E2BIG) {
107 g_free(cpuid);
108 return NULL;
109 } else {
110 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
111 strerror(-r));
112 exit(1);
113 }
114 }
115 return cpuid;
116 }
117
118 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
119 * for all entries.
120 */
121 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
122 {
123 struct kvm_cpuid2 *cpuid;
124 int max = 1;
125 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
126 max *= 2;
127 }
128 return cpuid;
129 }
130
131 static const struct kvm_para_features {
132 int cap;
133 int feature;
134 } para_features[] = {
135 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
136 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
137 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
138 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
139 };
140
141 static int get_para_features(KVMState *s)
142 {
143 int i, features = 0;
144
145 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
146 if (kvm_check_extension(s, para_features[i].cap)) {
147 features |= (1 << para_features[i].feature);
148 }
149 }
150
151 return features;
152 }
153
154
155 /* Returns the value for a specific register on the cpuid entry
156 */
157 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
158 {
159 uint32_t ret = 0;
160 switch (reg) {
161 case R_EAX:
162 ret = entry->eax;
163 break;
164 case R_EBX:
165 ret = entry->ebx;
166 break;
167 case R_ECX:
168 ret = entry->ecx;
169 break;
170 case R_EDX:
171 ret = entry->edx;
172 break;
173 }
174 return ret;
175 }
176
177 /* Find matching entry for function/index on kvm_cpuid2 struct
178 */
179 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
180 uint32_t function,
181 uint32_t index)
182 {
183 int i;
184 for (i = 0; i < cpuid->nent; ++i) {
185 if (cpuid->entries[i].function == function &&
186 cpuid->entries[i].index == index) {
187 return &cpuid->entries[i];
188 }
189 }
190 /* not found: */
191 return NULL;
192 }
193
194 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
195 uint32_t index, int reg)
196 {
197 struct kvm_cpuid2 *cpuid;
198 uint32_t ret = 0;
199 uint32_t cpuid_1_edx;
200 bool found = false;
201
202 cpuid = get_supported_cpuid(s);
203
204 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
205 if (entry) {
206 found = true;
207 ret = cpuid_entry_get_reg(entry, reg);
208 }
209
210 /* Fixups for the data returned by KVM, below */
211
212 if (function == 1 && reg == R_EDX) {
213 /* KVM before 2.6.30 misreports the following features */
214 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
215 } else if (function == 1 && reg == R_ECX) {
216 /* We can set the hypervisor flag, even if KVM does not return it on
217 * GET_SUPPORTED_CPUID
218 */
219 ret |= CPUID_EXT_HYPERVISOR;
220 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
221 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
222 * and the irqchip is in the kernel.
223 */
224 if (kvm_irqchip_in_kernel() &&
225 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
226 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
227 }
228
229 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
230 * without the in-kernel irqchip
231 */
232 if (!kvm_irqchip_in_kernel()) {
233 ret &= ~CPUID_EXT_X2APIC;
234 }
235 } else if (function == 0x80000001 && reg == R_EDX) {
236 /* On Intel, kvm returns cpuid according to the Intel spec,
237 * so add missing bits according to the AMD spec:
238 */
239 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
240 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
241 }
242
243 g_free(cpuid);
244
245 /* fallback for older kernels */
246 if ((function == KVM_CPUID_FEATURES) && !found) {
247 ret = get_para_features(s);
248 }
249
250 return ret;
251 }
252
253 typedef struct HWPoisonPage {
254 ram_addr_t ram_addr;
255 QLIST_ENTRY(HWPoisonPage) list;
256 } HWPoisonPage;
257
258 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
259 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
260
261 static void kvm_unpoison_all(void *param)
262 {
263 HWPoisonPage *page, *next_page;
264
265 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
266 QLIST_REMOVE(page, list);
267 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
268 g_free(page);
269 }
270 }
271
272 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
273 {
274 HWPoisonPage *page;
275
276 QLIST_FOREACH(page, &hwpoison_page_list, list) {
277 if (page->ram_addr == ram_addr) {
278 return;
279 }
280 }
281 page = g_new(HWPoisonPage, 1);
282 page->ram_addr = ram_addr;
283 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
284 }
285
286 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
287 int *max_banks)
288 {
289 int r;
290
291 r = kvm_check_extension(s, KVM_CAP_MCE);
292 if (r > 0) {
293 *max_banks = r;
294 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
295 }
296 return -ENOSYS;
297 }
298
299 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
300 {
301 CPUX86State *env = &cpu->env;
302 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
303 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
304 uint64_t mcg_status = MCG_STATUS_MCIP;
305
306 if (code == BUS_MCEERR_AR) {
307 status |= MCI_STATUS_AR | 0x134;
308 mcg_status |= MCG_STATUS_EIPV;
309 } else {
310 status |= 0xc0;
311 mcg_status |= MCG_STATUS_RIPV;
312 }
313 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
314 (MCM_ADDR_PHYS << 6) | 0xc,
315 cpu_x86_support_mca_broadcast(env) ?
316 MCE_INJECT_BROADCAST : 0);
317 }
318
319 static void hardware_memory_error(void)
320 {
321 fprintf(stderr, "Hardware memory error!\n");
322 exit(1);
323 }
324
325 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
326 {
327 X86CPU *cpu = X86_CPU(c);
328 CPUX86State *env = &cpu->env;
329 ram_addr_t ram_addr;
330 hwaddr paddr;
331
332 if ((env->mcg_cap & MCG_SER_P) && addr
333 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
334 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
335 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
336 fprintf(stderr, "Hardware memory error for memory used by "
337 "QEMU itself instead of guest system!\n");
338 /* Hope we are lucky for AO MCE */
339 if (code == BUS_MCEERR_AO) {
340 return 0;
341 } else {
342 hardware_memory_error();
343 }
344 }
345 kvm_hwpoison_page_add(ram_addr);
346 kvm_mce_inject(cpu, paddr, code);
347 } else {
348 if (code == BUS_MCEERR_AO) {
349 return 0;
350 } else if (code == BUS_MCEERR_AR) {
351 hardware_memory_error();
352 } else {
353 return 1;
354 }
355 }
356 return 0;
357 }
358
359 int kvm_arch_on_sigbus(int code, void *addr)
360 {
361 X86CPU *cpu = X86_CPU(first_cpu);
362
363 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
364 ram_addr_t ram_addr;
365 hwaddr paddr;
366
367 /* Hope we are lucky for AO MCE */
368 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
369 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
370 addr, &paddr)) {
371 fprintf(stderr, "Hardware memory error for memory used by "
372 "QEMU itself instead of guest system!: %p\n", addr);
373 return 0;
374 }
375 kvm_hwpoison_page_add(ram_addr);
376 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
377 } else {
378 if (code == BUS_MCEERR_AO) {
379 return 0;
380 } else if (code == BUS_MCEERR_AR) {
381 hardware_memory_error();
382 } else {
383 return 1;
384 }
385 }
386 return 0;
387 }
388
389 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
390 {
391 CPUX86State *env = &cpu->env;
392
393 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
394 unsigned int bank, bank_num = env->mcg_cap & 0xff;
395 struct kvm_x86_mce mce;
396
397 env->exception_injected = -1;
398
399 /*
400 * There must be at least one bank in use if an MCE is pending.
401 * Find it and use its values for the event injection.
402 */
403 for (bank = 0; bank < bank_num; bank++) {
404 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
405 break;
406 }
407 }
408 assert(bank < bank_num);
409
410 mce.bank = bank;
411 mce.status = env->mce_banks[bank * 4 + 1];
412 mce.mcg_status = env->mcg_status;
413 mce.addr = env->mce_banks[bank * 4 + 2];
414 mce.misc = env->mce_banks[bank * 4 + 3];
415
416 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
417 }
418 return 0;
419 }
420
421 static void cpu_update_state(void *opaque, int running, RunState state)
422 {
423 CPUX86State *env = opaque;
424
425 if (running) {
426 env->tsc_valid = false;
427 }
428 }
429
430 unsigned long kvm_arch_vcpu_id(CPUState *cs)
431 {
432 X86CPU *cpu = X86_CPU(cs);
433 return cpu->env.cpuid_apic_id;
434 }
435
436 #ifndef KVM_CPUID_SIGNATURE_NEXT
437 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
438 #endif
439
440 static bool hyperv_hypercall_available(X86CPU *cpu)
441 {
442 return cpu->hyperv_vapic ||
443 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
444 }
445
446 static bool hyperv_enabled(X86CPU *cpu)
447 {
448 CPUState *cs = CPU(cpu);
449 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
450 (hyperv_hypercall_available(cpu) ||
451 cpu->hyperv_time ||
452 cpu->hyperv_relaxed_timing);
453 }
454
455 static Error *invtsc_mig_blocker;
456
457 #define KVM_MAX_CPUID_ENTRIES 100
458
459 int kvm_arch_init_vcpu(CPUState *cs)
460 {
461 struct {
462 struct kvm_cpuid2 cpuid;
463 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
464 } QEMU_PACKED cpuid_data;
465 X86CPU *cpu = X86_CPU(cs);
466 CPUX86State *env = &cpu->env;
467 uint32_t limit, i, j, cpuid_i;
468 uint32_t unused;
469 struct kvm_cpuid_entry2 *c;
470 uint32_t signature[3];
471 int kvm_base = KVM_CPUID_SIGNATURE;
472 int r;
473
474 memset(&cpuid_data, 0, sizeof(cpuid_data));
475
476 cpuid_i = 0;
477
478 /* Paravirtualization CPUIDs */
479 if (hyperv_enabled(cpu)) {
480 c = &cpuid_data.entries[cpuid_i++];
481 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
482 memcpy(signature, "Microsoft Hv", 12);
483 c->eax = HYPERV_CPUID_MIN;
484 c->ebx = signature[0];
485 c->ecx = signature[1];
486 c->edx = signature[2];
487
488 c = &cpuid_data.entries[cpuid_i++];
489 c->function = HYPERV_CPUID_INTERFACE;
490 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
491 c->eax = signature[0];
492 c->ebx = 0;
493 c->ecx = 0;
494 c->edx = 0;
495
496 c = &cpuid_data.entries[cpuid_i++];
497 c->function = HYPERV_CPUID_VERSION;
498 c->eax = 0x00001bbc;
499 c->ebx = 0x00060001;
500
501 c = &cpuid_data.entries[cpuid_i++];
502 c->function = HYPERV_CPUID_FEATURES;
503 if (cpu->hyperv_relaxed_timing) {
504 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
505 }
506 if (cpu->hyperv_vapic) {
507 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
508 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
509 has_msr_hv_vapic = true;
510 }
511 if (cpu->hyperv_time &&
512 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
513 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
514 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
515 c->eax |= 0x200;
516 has_msr_hv_tsc = true;
517 }
518 c = &cpuid_data.entries[cpuid_i++];
519 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
520 if (cpu->hyperv_relaxed_timing) {
521 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
522 }
523 if (has_msr_hv_vapic) {
524 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
525 }
526 c->ebx = cpu->hyperv_spinlock_attempts;
527
528 c = &cpuid_data.entries[cpuid_i++];
529 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
530 c->eax = 0x40;
531 c->ebx = 0x40;
532
533 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
534 has_msr_hv_hypercall = true;
535 }
536
537 if (cpu->expose_kvm) {
538 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
539 c = &cpuid_data.entries[cpuid_i++];
540 c->function = KVM_CPUID_SIGNATURE | kvm_base;
541 c->eax = KVM_CPUID_FEATURES | kvm_base;
542 c->ebx = signature[0];
543 c->ecx = signature[1];
544 c->edx = signature[2];
545
546 c = &cpuid_data.entries[cpuid_i++];
547 c->function = KVM_CPUID_FEATURES | kvm_base;
548 c->eax = env->features[FEAT_KVM];
549
550 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
551
552 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
553
554 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
555 }
556
557 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
558
559 for (i = 0; i <= limit; i++) {
560 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
561 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
562 abort();
563 }
564 c = &cpuid_data.entries[cpuid_i++];
565
566 switch (i) {
567 case 2: {
568 /* Keep reading function 2 till all the input is received */
569 int times;
570
571 c->function = i;
572 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
573 KVM_CPUID_FLAG_STATE_READ_NEXT;
574 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
575 times = c->eax & 0xff;
576
577 for (j = 1; j < times; ++j) {
578 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
579 fprintf(stderr, "cpuid_data is full, no space for "
580 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
581 abort();
582 }
583 c = &cpuid_data.entries[cpuid_i++];
584 c->function = i;
585 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
586 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
587 }
588 break;
589 }
590 case 4:
591 case 0xb:
592 case 0xd:
593 for (j = 0; ; j++) {
594 if (i == 0xd && j == 64) {
595 break;
596 }
597 c->function = i;
598 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
599 c->index = j;
600 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
601
602 if (i == 4 && c->eax == 0) {
603 break;
604 }
605 if (i == 0xb && !(c->ecx & 0xff00)) {
606 break;
607 }
608 if (i == 0xd && c->eax == 0) {
609 continue;
610 }
611 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
612 fprintf(stderr, "cpuid_data is full, no space for "
613 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
614 abort();
615 }
616 c = &cpuid_data.entries[cpuid_i++];
617 }
618 break;
619 default:
620 c->function = i;
621 c->flags = 0;
622 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
623 break;
624 }
625 }
626
627 if (limit >= 0x0a) {
628 uint32_t ver;
629
630 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
631 if ((ver & 0xff) > 0) {
632 has_msr_architectural_pmu = true;
633 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
634
635 /* Shouldn't be more than 32, since that's the number of bits
636 * available in EBX to tell us _which_ counters are available.
637 * Play it safe.
638 */
639 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
640 num_architectural_pmu_counters = MAX_GP_COUNTERS;
641 }
642 }
643 }
644
645 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
646
647 for (i = 0x80000000; i <= limit; i++) {
648 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
649 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
650 abort();
651 }
652 c = &cpuid_data.entries[cpuid_i++];
653
654 c->function = i;
655 c->flags = 0;
656 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
657 }
658
659 /* Call Centaur's CPUID instructions they are supported. */
660 if (env->cpuid_xlevel2 > 0) {
661 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
662
663 for (i = 0xC0000000; i <= limit; i++) {
664 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
665 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
666 abort();
667 }
668 c = &cpuid_data.entries[cpuid_i++];
669
670 c->function = i;
671 c->flags = 0;
672 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
673 }
674 }
675
676 cpuid_data.cpuid.nent = cpuid_i;
677
678 if (((env->cpuid_version >> 8)&0xF) >= 6
679 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
680 (CPUID_MCE | CPUID_MCA)
681 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
682 uint64_t mcg_cap;
683 int banks;
684 int ret;
685
686 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
687 if (ret < 0) {
688 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
689 return ret;
690 }
691
692 if (banks > MCE_BANKS_DEF) {
693 banks = MCE_BANKS_DEF;
694 }
695 mcg_cap &= MCE_CAP_DEF;
696 mcg_cap |= banks;
697 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
698 if (ret < 0) {
699 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
700 return ret;
701 }
702
703 env->mcg_cap = mcg_cap;
704 }
705
706 qemu_add_vm_change_state_handler(cpu_update_state, env);
707
708 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
709 if (c) {
710 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
711 !!(c->ecx & CPUID_EXT_SMX);
712 }
713
714 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
715 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
716 /* for migration */
717 error_setg(&invtsc_mig_blocker,
718 "State blocked by non-migratable CPU device"
719 " (invtsc flag)");
720 migrate_add_blocker(invtsc_mig_blocker);
721 /* for savevm */
722 vmstate_x86_cpu.unmigratable = 1;
723 }
724
725 cpuid_data.cpuid.padding = 0;
726 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
727 if (r) {
728 return r;
729 }
730
731 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
732 if (r && env->tsc_khz) {
733 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
734 if (r < 0) {
735 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
736 return r;
737 }
738 }
739
740 if (kvm_has_xsave()) {
741 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
742 }
743
744 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
745 has_msr_mtrr = true;
746 }
747
748 return 0;
749 }
750
751 void kvm_arch_reset_vcpu(X86CPU *cpu)
752 {
753 CPUX86State *env = &cpu->env;
754
755 env->exception_injected = -1;
756 env->interrupt_injected = -1;
757 env->xcr0 = 1;
758 if (kvm_irqchip_in_kernel()) {
759 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
760 KVM_MP_STATE_UNINITIALIZED;
761 } else {
762 env->mp_state = KVM_MP_STATE_RUNNABLE;
763 }
764 }
765
766 void kvm_arch_do_init_vcpu(X86CPU *cpu)
767 {
768 CPUX86State *env = &cpu->env;
769
770 /* APs get directly into wait-for-SIPI state. */
771 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
772 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
773 }
774 }
775
776 static int kvm_get_supported_msrs(KVMState *s)
777 {
778 static int kvm_supported_msrs;
779 int ret = 0;
780
781 /* first time */
782 if (kvm_supported_msrs == 0) {
783 struct kvm_msr_list msr_list, *kvm_msr_list;
784
785 kvm_supported_msrs = -1;
786
787 /* Obtain MSR list from KVM. These are the MSRs that we must
788 * save/restore */
789 msr_list.nmsrs = 0;
790 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
791 if (ret < 0 && ret != -E2BIG) {
792 return ret;
793 }
794 /* Old kernel modules had a bug and could write beyond the provided
795 memory. Allocate at least a safe amount of 1K. */
796 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
797 msr_list.nmsrs *
798 sizeof(msr_list.indices[0])));
799
800 kvm_msr_list->nmsrs = msr_list.nmsrs;
801 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
802 if (ret >= 0) {
803 int i;
804
805 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
806 if (kvm_msr_list->indices[i] == MSR_STAR) {
807 has_msr_star = true;
808 continue;
809 }
810 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
811 has_msr_hsave_pa = true;
812 continue;
813 }
814 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
815 has_msr_tsc_adjust = true;
816 continue;
817 }
818 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
819 has_msr_tsc_deadline = true;
820 continue;
821 }
822 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
823 has_msr_misc_enable = true;
824 continue;
825 }
826 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
827 has_msr_bndcfgs = true;
828 continue;
829 }
830 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
831 has_msr_xss = true;
832 continue;
833 }
834 }
835 }
836
837 g_free(kvm_msr_list);
838 }
839
840 return ret;
841 }
842
843 int kvm_arch_init(KVMState *s)
844 {
845 uint64_t identity_base = 0xfffbc000;
846 uint64_t shadow_mem;
847 int ret;
848 struct utsname utsname;
849
850 ret = kvm_get_supported_msrs(s);
851 if (ret < 0) {
852 return ret;
853 }
854
855 uname(&utsname);
856 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
857
858 /*
859 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
860 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
861 * Since these must be part of guest physical memory, we need to allocate
862 * them, both by setting their start addresses in the kernel and by
863 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
864 *
865 * Older KVM versions may not support setting the identity map base. In
866 * that case we need to stick with the default, i.e. a 256K maximum BIOS
867 * size.
868 */
869 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
870 /* Allows up to 16M BIOSes. */
871 identity_base = 0xfeffc000;
872
873 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
874 if (ret < 0) {
875 return ret;
876 }
877 }
878
879 /* Set TSS base one page after EPT identity map. */
880 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
881 if (ret < 0) {
882 return ret;
883 }
884
885 /* Tell fw_cfg to notify the BIOS to reserve the range. */
886 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
887 if (ret < 0) {
888 fprintf(stderr, "e820_add_entry() table is full\n");
889 return ret;
890 }
891 qemu_register_reset(kvm_unpoison_all, NULL);
892
893 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
894 "kvm_shadow_mem", -1);
895 if (shadow_mem != -1) {
896 shadow_mem /= 4096;
897 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
898 if (ret < 0) {
899 return ret;
900 }
901 }
902 return 0;
903 }
904
905 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
906 {
907 lhs->selector = rhs->selector;
908 lhs->base = rhs->base;
909 lhs->limit = rhs->limit;
910 lhs->type = 3;
911 lhs->present = 1;
912 lhs->dpl = 3;
913 lhs->db = 0;
914 lhs->s = 1;
915 lhs->l = 0;
916 lhs->g = 0;
917 lhs->avl = 0;
918 lhs->unusable = 0;
919 }
920
921 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
922 {
923 unsigned flags = rhs->flags;
924 lhs->selector = rhs->selector;
925 lhs->base = rhs->base;
926 lhs->limit = rhs->limit;
927 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
928 lhs->present = (flags & DESC_P_MASK) != 0;
929 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
930 lhs->db = (flags >> DESC_B_SHIFT) & 1;
931 lhs->s = (flags & DESC_S_MASK) != 0;
932 lhs->l = (flags >> DESC_L_SHIFT) & 1;
933 lhs->g = (flags & DESC_G_MASK) != 0;
934 lhs->avl = (flags & DESC_AVL_MASK) != 0;
935 lhs->unusable = 0;
936 lhs->padding = 0;
937 }
938
939 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
940 {
941 lhs->selector = rhs->selector;
942 lhs->base = rhs->base;
943 lhs->limit = rhs->limit;
944 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
945 (rhs->present * DESC_P_MASK) |
946 (rhs->dpl << DESC_DPL_SHIFT) |
947 (rhs->db << DESC_B_SHIFT) |
948 (rhs->s * DESC_S_MASK) |
949 (rhs->l << DESC_L_SHIFT) |
950 (rhs->g * DESC_G_MASK) |
951 (rhs->avl * DESC_AVL_MASK);
952 }
953
954 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
955 {
956 if (set) {
957 *kvm_reg = *qemu_reg;
958 } else {
959 *qemu_reg = *kvm_reg;
960 }
961 }
962
963 static int kvm_getput_regs(X86CPU *cpu, int set)
964 {
965 CPUX86State *env = &cpu->env;
966 struct kvm_regs regs;
967 int ret = 0;
968
969 if (!set) {
970 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
971 if (ret < 0) {
972 return ret;
973 }
974 }
975
976 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
977 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
978 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
979 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
980 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
981 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
982 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
983 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
984 #ifdef TARGET_X86_64
985 kvm_getput_reg(&regs.r8, &env->regs[8], set);
986 kvm_getput_reg(&regs.r9, &env->regs[9], set);
987 kvm_getput_reg(&regs.r10, &env->regs[10], set);
988 kvm_getput_reg(&regs.r11, &env->regs[11], set);
989 kvm_getput_reg(&regs.r12, &env->regs[12], set);
990 kvm_getput_reg(&regs.r13, &env->regs[13], set);
991 kvm_getput_reg(&regs.r14, &env->regs[14], set);
992 kvm_getput_reg(&regs.r15, &env->regs[15], set);
993 #endif
994
995 kvm_getput_reg(&regs.rflags, &env->eflags, set);
996 kvm_getput_reg(&regs.rip, &env->eip, set);
997
998 if (set) {
999 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1000 }
1001
1002 return ret;
1003 }
1004
1005 static int kvm_put_fpu(X86CPU *cpu)
1006 {
1007 CPUX86State *env = &cpu->env;
1008 struct kvm_fpu fpu;
1009 int i;
1010
1011 memset(&fpu, 0, sizeof fpu);
1012 fpu.fsw = env->fpus & ~(7 << 11);
1013 fpu.fsw |= (env->fpstt & 7) << 11;
1014 fpu.fcw = env->fpuc;
1015 fpu.last_opcode = env->fpop;
1016 fpu.last_ip = env->fpip;
1017 fpu.last_dp = env->fpdp;
1018 for (i = 0; i < 8; ++i) {
1019 fpu.ftwx |= (!env->fptags[i]) << i;
1020 }
1021 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1022 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
1023 fpu.mxcsr = env->mxcsr;
1024
1025 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1026 }
1027
1028 #define XSAVE_FCW_FSW 0
1029 #define XSAVE_FTW_FOP 1
1030 #define XSAVE_CWD_RIP 2
1031 #define XSAVE_CWD_RDP 4
1032 #define XSAVE_MXCSR 6
1033 #define XSAVE_ST_SPACE 8
1034 #define XSAVE_XMM_SPACE 40
1035 #define XSAVE_XSTATE_BV 128
1036 #define XSAVE_YMMH_SPACE 144
1037 #define XSAVE_BNDREGS 240
1038 #define XSAVE_BNDCSR 256
1039 #define XSAVE_OPMASK 272
1040 #define XSAVE_ZMM_Hi256 288
1041 #define XSAVE_Hi16_ZMM 416
1042
1043 static int kvm_put_xsave(X86CPU *cpu)
1044 {
1045 CPUX86State *env = &cpu->env;
1046 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1047 uint16_t cwd, swd, twd;
1048 int i, r;
1049
1050 if (!kvm_has_xsave()) {
1051 return kvm_put_fpu(cpu);
1052 }
1053
1054 memset(xsave, 0, sizeof(struct kvm_xsave));
1055 twd = 0;
1056 swd = env->fpus & ~(7 << 11);
1057 swd |= (env->fpstt & 7) << 11;
1058 cwd = env->fpuc;
1059 for (i = 0; i < 8; ++i) {
1060 twd |= (!env->fptags[i]) << i;
1061 }
1062 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1063 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1064 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1065 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1066 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1067 sizeof env->fpregs);
1068 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1069 sizeof env->xmm_regs);
1070 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1071 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1072 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1073 sizeof env->ymmh_regs);
1074 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1075 sizeof env->bnd_regs);
1076 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1077 sizeof(env->bndcs_regs));
1078 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1079 sizeof env->opmask_regs);
1080 memcpy(&xsave->region[XSAVE_ZMM_Hi256], env->zmmh_regs,
1081 sizeof env->zmmh_regs);
1082 #ifdef TARGET_X86_64
1083 memcpy(&xsave->region[XSAVE_Hi16_ZMM], env->hi16_zmm_regs,
1084 sizeof env->hi16_zmm_regs);
1085 #endif
1086 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1087 return r;
1088 }
1089
1090 static int kvm_put_xcrs(X86CPU *cpu)
1091 {
1092 CPUX86State *env = &cpu->env;
1093 struct kvm_xcrs xcrs = {};
1094
1095 if (!kvm_has_xcrs()) {
1096 return 0;
1097 }
1098
1099 xcrs.nr_xcrs = 1;
1100 xcrs.flags = 0;
1101 xcrs.xcrs[0].xcr = 0;
1102 xcrs.xcrs[0].value = env->xcr0;
1103 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1104 }
1105
1106 static int kvm_put_sregs(X86CPU *cpu)
1107 {
1108 CPUX86State *env = &cpu->env;
1109 struct kvm_sregs sregs;
1110
1111 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1112 if (env->interrupt_injected >= 0) {
1113 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1114 (uint64_t)1 << (env->interrupt_injected % 64);
1115 }
1116
1117 if ((env->eflags & VM_MASK)) {
1118 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1119 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1120 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1121 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1122 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1123 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1124 } else {
1125 set_seg(&sregs.cs, &env->segs[R_CS]);
1126 set_seg(&sregs.ds, &env->segs[R_DS]);
1127 set_seg(&sregs.es, &env->segs[R_ES]);
1128 set_seg(&sregs.fs, &env->segs[R_FS]);
1129 set_seg(&sregs.gs, &env->segs[R_GS]);
1130 set_seg(&sregs.ss, &env->segs[R_SS]);
1131 }
1132
1133 set_seg(&sregs.tr, &env->tr);
1134 set_seg(&sregs.ldt, &env->ldt);
1135
1136 sregs.idt.limit = env->idt.limit;
1137 sregs.idt.base = env->idt.base;
1138 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1139 sregs.gdt.limit = env->gdt.limit;
1140 sregs.gdt.base = env->gdt.base;
1141 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1142
1143 sregs.cr0 = env->cr[0];
1144 sregs.cr2 = env->cr[2];
1145 sregs.cr3 = env->cr[3];
1146 sregs.cr4 = env->cr[4];
1147
1148 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1149 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1150
1151 sregs.efer = env->efer;
1152
1153 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1154 }
1155
1156 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1157 uint32_t index, uint64_t value)
1158 {
1159 entry->index = index;
1160 entry->reserved = 0;
1161 entry->data = value;
1162 }
1163
1164 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1165 {
1166 CPUX86State *env = &cpu->env;
1167 struct {
1168 struct kvm_msrs info;
1169 struct kvm_msr_entry entries[1];
1170 } msr_data;
1171 struct kvm_msr_entry *msrs = msr_data.entries;
1172
1173 if (!has_msr_tsc_deadline) {
1174 return 0;
1175 }
1176
1177 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1178
1179 msr_data.info = (struct kvm_msrs) {
1180 .nmsrs = 1,
1181 };
1182
1183 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1184 }
1185
1186 /*
1187 * Provide a separate write service for the feature control MSR in order to
1188 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1189 * before writing any other state because forcibly leaving nested mode
1190 * invalidates the VCPU state.
1191 */
1192 static int kvm_put_msr_feature_control(X86CPU *cpu)
1193 {
1194 struct {
1195 struct kvm_msrs info;
1196 struct kvm_msr_entry entry;
1197 } msr_data;
1198
1199 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1200 cpu->env.msr_ia32_feature_control);
1201
1202 msr_data.info = (struct kvm_msrs) {
1203 .nmsrs = 1,
1204 };
1205
1206 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1207 }
1208
1209 static int kvm_put_msrs(X86CPU *cpu, int level)
1210 {
1211 CPUX86State *env = &cpu->env;
1212 struct {
1213 struct kvm_msrs info;
1214 struct kvm_msr_entry entries[150];
1215 } msr_data;
1216 struct kvm_msr_entry *msrs = msr_data.entries;
1217 int n = 0, i;
1218
1219 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1220 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1221 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1222 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1223 if (has_msr_star) {
1224 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1225 }
1226 if (has_msr_hsave_pa) {
1227 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1228 }
1229 if (has_msr_tsc_adjust) {
1230 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1231 }
1232 if (has_msr_misc_enable) {
1233 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1234 env->msr_ia32_misc_enable);
1235 }
1236 if (has_msr_bndcfgs) {
1237 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1238 }
1239 if (has_msr_xss) {
1240 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1241 }
1242 #ifdef TARGET_X86_64
1243 if (lm_capable_kernel) {
1244 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1245 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1246 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1247 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1248 }
1249 #endif
1250 /*
1251 * The following MSRs have side effects on the guest or are too heavy
1252 * for normal writeback. Limit them to reset or full state updates.
1253 */
1254 if (level >= KVM_PUT_RESET_STATE) {
1255 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1256 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1257 env->system_time_msr);
1258 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1259 if (has_msr_async_pf_en) {
1260 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1261 env->async_pf_en_msr);
1262 }
1263 if (has_msr_pv_eoi_en) {
1264 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1265 env->pv_eoi_en_msr);
1266 }
1267 if (has_msr_kvm_steal_time) {
1268 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1269 env->steal_time_msr);
1270 }
1271 if (has_msr_architectural_pmu) {
1272 /* Stop the counter. */
1273 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1274 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1275
1276 /* Set the counter values. */
1277 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1278 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1279 env->msr_fixed_counters[i]);
1280 }
1281 for (i = 0; i < num_architectural_pmu_counters; i++) {
1282 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1283 env->msr_gp_counters[i]);
1284 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1285 env->msr_gp_evtsel[i]);
1286 }
1287 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1288 env->msr_global_status);
1289 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1290 env->msr_global_ovf_ctrl);
1291
1292 /* Now start the PMU. */
1293 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1294 env->msr_fixed_ctr_ctrl);
1295 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1296 env->msr_global_ctrl);
1297 }
1298 if (has_msr_hv_hypercall) {
1299 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1300 env->msr_hv_guest_os_id);
1301 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1302 env->msr_hv_hypercall);
1303 }
1304 if (has_msr_hv_vapic) {
1305 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1306 env->msr_hv_vapic);
1307 }
1308 if (has_msr_hv_tsc) {
1309 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1310 env->msr_hv_tsc);
1311 }
1312 if (has_msr_mtrr) {
1313 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1314 kvm_msr_entry_set(&msrs[n++],
1315 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1316 kvm_msr_entry_set(&msrs[n++],
1317 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1318 kvm_msr_entry_set(&msrs[n++],
1319 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1320 kvm_msr_entry_set(&msrs[n++],
1321 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1322 kvm_msr_entry_set(&msrs[n++],
1323 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1324 kvm_msr_entry_set(&msrs[n++],
1325 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1326 kvm_msr_entry_set(&msrs[n++],
1327 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1328 kvm_msr_entry_set(&msrs[n++],
1329 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1330 kvm_msr_entry_set(&msrs[n++],
1331 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1332 kvm_msr_entry_set(&msrs[n++],
1333 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1334 kvm_msr_entry_set(&msrs[n++],
1335 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1336 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1337 kvm_msr_entry_set(&msrs[n++],
1338 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1339 kvm_msr_entry_set(&msrs[n++],
1340 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1341 }
1342 }
1343
1344 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1345 * kvm_put_msr_feature_control. */
1346 }
1347 if (env->mcg_cap) {
1348 int i;
1349
1350 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1351 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1352 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1353 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1354 }
1355 }
1356
1357 msr_data.info = (struct kvm_msrs) {
1358 .nmsrs = n,
1359 };
1360
1361 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1362
1363 }
1364
1365
1366 static int kvm_get_fpu(X86CPU *cpu)
1367 {
1368 CPUX86State *env = &cpu->env;
1369 struct kvm_fpu fpu;
1370 int i, ret;
1371
1372 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1373 if (ret < 0) {
1374 return ret;
1375 }
1376
1377 env->fpstt = (fpu.fsw >> 11) & 7;
1378 env->fpus = fpu.fsw;
1379 env->fpuc = fpu.fcw;
1380 env->fpop = fpu.last_opcode;
1381 env->fpip = fpu.last_ip;
1382 env->fpdp = fpu.last_dp;
1383 for (i = 0; i < 8; ++i) {
1384 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1385 }
1386 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1387 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1388 env->mxcsr = fpu.mxcsr;
1389
1390 return 0;
1391 }
1392
1393 static int kvm_get_xsave(X86CPU *cpu)
1394 {
1395 CPUX86State *env = &cpu->env;
1396 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1397 int ret, i;
1398 uint16_t cwd, swd, twd;
1399
1400 if (!kvm_has_xsave()) {
1401 return kvm_get_fpu(cpu);
1402 }
1403
1404 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1405 if (ret < 0) {
1406 return ret;
1407 }
1408
1409 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1410 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1411 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1412 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1413 env->fpstt = (swd >> 11) & 7;
1414 env->fpus = swd;
1415 env->fpuc = cwd;
1416 for (i = 0; i < 8; ++i) {
1417 env->fptags[i] = !((twd >> i) & 1);
1418 }
1419 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1420 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1421 env->mxcsr = xsave->region[XSAVE_MXCSR];
1422 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1423 sizeof env->fpregs);
1424 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1425 sizeof env->xmm_regs);
1426 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1427 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1428 sizeof env->ymmh_regs);
1429 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1430 sizeof env->bnd_regs);
1431 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1432 sizeof(env->bndcs_regs));
1433 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1434 sizeof env->opmask_regs);
1435 memcpy(env->zmmh_regs, &xsave->region[XSAVE_ZMM_Hi256],
1436 sizeof env->zmmh_regs);
1437 #ifdef TARGET_X86_64
1438 memcpy(env->hi16_zmm_regs, &xsave->region[XSAVE_Hi16_ZMM],
1439 sizeof env->hi16_zmm_regs);
1440 #endif
1441 return 0;
1442 }
1443
1444 static int kvm_get_xcrs(X86CPU *cpu)
1445 {
1446 CPUX86State *env = &cpu->env;
1447 int i, ret;
1448 struct kvm_xcrs xcrs;
1449
1450 if (!kvm_has_xcrs()) {
1451 return 0;
1452 }
1453
1454 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1455 if (ret < 0) {
1456 return ret;
1457 }
1458
1459 for (i = 0; i < xcrs.nr_xcrs; i++) {
1460 /* Only support xcr0 now */
1461 if (xcrs.xcrs[i].xcr == 0) {
1462 env->xcr0 = xcrs.xcrs[i].value;
1463 break;
1464 }
1465 }
1466 return 0;
1467 }
1468
1469 static int kvm_get_sregs(X86CPU *cpu)
1470 {
1471 CPUX86State *env = &cpu->env;
1472 struct kvm_sregs sregs;
1473 uint32_t hflags;
1474 int bit, i, ret;
1475
1476 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1477 if (ret < 0) {
1478 return ret;
1479 }
1480
1481 /* There can only be one pending IRQ set in the bitmap at a time, so try
1482 to find it and save its number instead (-1 for none). */
1483 env->interrupt_injected = -1;
1484 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1485 if (sregs.interrupt_bitmap[i]) {
1486 bit = ctz64(sregs.interrupt_bitmap[i]);
1487 env->interrupt_injected = i * 64 + bit;
1488 break;
1489 }
1490 }
1491
1492 get_seg(&env->segs[R_CS], &sregs.cs);
1493 get_seg(&env->segs[R_DS], &sregs.ds);
1494 get_seg(&env->segs[R_ES], &sregs.es);
1495 get_seg(&env->segs[R_FS], &sregs.fs);
1496 get_seg(&env->segs[R_GS], &sregs.gs);
1497 get_seg(&env->segs[R_SS], &sregs.ss);
1498
1499 get_seg(&env->tr, &sregs.tr);
1500 get_seg(&env->ldt, &sregs.ldt);
1501
1502 env->idt.limit = sregs.idt.limit;
1503 env->idt.base = sregs.idt.base;
1504 env->gdt.limit = sregs.gdt.limit;
1505 env->gdt.base = sregs.gdt.base;
1506
1507 env->cr[0] = sregs.cr0;
1508 env->cr[2] = sregs.cr2;
1509 env->cr[3] = sregs.cr3;
1510 env->cr[4] = sregs.cr4;
1511
1512 env->efer = sregs.efer;
1513
1514 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1515
1516 #define HFLAG_COPY_MASK \
1517 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1518 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1519 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1520 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1521
1522 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1523 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1524 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1525 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1526 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1527 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1528 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1529
1530 if (env->efer & MSR_EFER_LMA) {
1531 hflags |= HF_LMA_MASK;
1532 }
1533
1534 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1535 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1536 } else {
1537 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1538 (DESC_B_SHIFT - HF_CS32_SHIFT);
1539 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1540 (DESC_B_SHIFT - HF_SS32_SHIFT);
1541 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1542 !(hflags & HF_CS32_MASK)) {
1543 hflags |= HF_ADDSEG_MASK;
1544 } else {
1545 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1546 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1547 }
1548 }
1549 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1550
1551 return 0;
1552 }
1553
1554 static int kvm_get_msrs(X86CPU *cpu)
1555 {
1556 CPUX86State *env = &cpu->env;
1557 struct {
1558 struct kvm_msrs info;
1559 struct kvm_msr_entry entries[150];
1560 } msr_data;
1561 struct kvm_msr_entry *msrs = msr_data.entries;
1562 int ret, i, n;
1563
1564 n = 0;
1565 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1566 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1567 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1568 msrs[n++].index = MSR_PAT;
1569 if (has_msr_star) {
1570 msrs[n++].index = MSR_STAR;
1571 }
1572 if (has_msr_hsave_pa) {
1573 msrs[n++].index = MSR_VM_HSAVE_PA;
1574 }
1575 if (has_msr_tsc_adjust) {
1576 msrs[n++].index = MSR_TSC_ADJUST;
1577 }
1578 if (has_msr_tsc_deadline) {
1579 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1580 }
1581 if (has_msr_misc_enable) {
1582 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1583 }
1584 if (has_msr_feature_control) {
1585 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1586 }
1587 if (has_msr_bndcfgs) {
1588 msrs[n++].index = MSR_IA32_BNDCFGS;
1589 }
1590 if (has_msr_xss) {
1591 msrs[n++].index = MSR_IA32_XSS;
1592 }
1593
1594
1595 if (!env->tsc_valid) {
1596 msrs[n++].index = MSR_IA32_TSC;
1597 env->tsc_valid = !runstate_is_running();
1598 }
1599
1600 #ifdef TARGET_X86_64
1601 if (lm_capable_kernel) {
1602 msrs[n++].index = MSR_CSTAR;
1603 msrs[n++].index = MSR_KERNELGSBASE;
1604 msrs[n++].index = MSR_FMASK;
1605 msrs[n++].index = MSR_LSTAR;
1606 }
1607 #endif
1608 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1609 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1610 if (has_msr_async_pf_en) {
1611 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1612 }
1613 if (has_msr_pv_eoi_en) {
1614 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1615 }
1616 if (has_msr_kvm_steal_time) {
1617 msrs[n++].index = MSR_KVM_STEAL_TIME;
1618 }
1619 if (has_msr_architectural_pmu) {
1620 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1621 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1622 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1623 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1624 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1625 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1626 }
1627 for (i = 0; i < num_architectural_pmu_counters; i++) {
1628 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1629 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1630 }
1631 }
1632
1633 if (env->mcg_cap) {
1634 msrs[n++].index = MSR_MCG_STATUS;
1635 msrs[n++].index = MSR_MCG_CTL;
1636 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1637 msrs[n++].index = MSR_MC0_CTL + i;
1638 }
1639 }
1640
1641 if (has_msr_hv_hypercall) {
1642 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1643 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1644 }
1645 if (has_msr_hv_vapic) {
1646 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1647 }
1648 if (has_msr_hv_tsc) {
1649 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1650 }
1651 if (has_msr_mtrr) {
1652 msrs[n++].index = MSR_MTRRdefType;
1653 msrs[n++].index = MSR_MTRRfix64K_00000;
1654 msrs[n++].index = MSR_MTRRfix16K_80000;
1655 msrs[n++].index = MSR_MTRRfix16K_A0000;
1656 msrs[n++].index = MSR_MTRRfix4K_C0000;
1657 msrs[n++].index = MSR_MTRRfix4K_C8000;
1658 msrs[n++].index = MSR_MTRRfix4K_D0000;
1659 msrs[n++].index = MSR_MTRRfix4K_D8000;
1660 msrs[n++].index = MSR_MTRRfix4K_E0000;
1661 msrs[n++].index = MSR_MTRRfix4K_E8000;
1662 msrs[n++].index = MSR_MTRRfix4K_F0000;
1663 msrs[n++].index = MSR_MTRRfix4K_F8000;
1664 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1665 msrs[n++].index = MSR_MTRRphysBase(i);
1666 msrs[n++].index = MSR_MTRRphysMask(i);
1667 }
1668 }
1669
1670 msr_data.info = (struct kvm_msrs) {
1671 .nmsrs = n,
1672 };
1673
1674 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1675 if (ret < 0) {
1676 return ret;
1677 }
1678
1679 for (i = 0; i < ret; i++) {
1680 uint32_t index = msrs[i].index;
1681 switch (index) {
1682 case MSR_IA32_SYSENTER_CS:
1683 env->sysenter_cs = msrs[i].data;
1684 break;
1685 case MSR_IA32_SYSENTER_ESP:
1686 env->sysenter_esp = msrs[i].data;
1687 break;
1688 case MSR_IA32_SYSENTER_EIP:
1689 env->sysenter_eip = msrs[i].data;
1690 break;
1691 case MSR_PAT:
1692 env->pat = msrs[i].data;
1693 break;
1694 case MSR_STAR:
1695 env->star = msrs[i].data;
1696 break;
1697 #ifdef TARGET_X86_64
1698 case MSR_CSTAR:
1699 env->cstar = msrs[i].data;
1700 break;
1701 case MSR_KERNELGSBASE:
1702 env->kernelgsbase = msrs[i].data;
1703 break;
1704 case MSR_FMASK:
1705 env->fmask = msrs[i].data;
1706 break;
1707 case MSR_LSTAR:
1708 env->lstar = msrs[i].data;
1709 break;
1710 #endif
1711 case MSR_IA32_TSC:
1712 env->tsc = msrs[i].data;
1713 break;
1714 case MSR_TSC_ADJUST:
1715 env->tsc_adjust = msrs[i].data;
1716 break;
1717 case MSR_IA32_TSCDEADLINE:
1718 env->tsc_deadline = msrs[i].data;
1719 break;
1720 case MSR_VM_HSAVE_PA:
1721 env->vm_hsave = msrs[i].data;
1722 break;
1723 case MSR_KVM_SYSTEM_TIME:
1724 env->system_time_msr = msrs[i].data;
1725 break;
1726 case MSR_KVM_WALL_CLOCK:
1727 env->wall_clock_msr = msrs[i].data;
1728 break;
1729 case MSR_MCG_STATUS:
1730 env->mcg_status = msrs[i].data;
1731 break;
1732 case MSR_MCG_CTL:
1733 env->mcg_ctl = msrs[i].data;
1734 break;
1735 case MSR_IA32_MISC_ENABLE:
1736 env->msr_ia32_misc_enable = msrs[i].data;
1737 break;
1738 case MSR_IA32_FEATURE_CONTROL:
1739 env->msr_ia32_feature_control = msrs[i].data;
1740 break;
1741 case MSR_IA32_BNDCFGS:
1742 env->msr_bndcfgs = msrs[i].data;
1743 break;
1744 case MSR_IA32_XSS:
1745 env->xss = msrs[i].data;
1746 break;
1747 default:
1748 if (msrs[i].index >= MSR_MC0_CTL &&
1749 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1750 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1751 }
1752 break;
1753 case MSR_KVM_ASYNC_PF_EN:
1754 env->async_pf_en_msr = msrs[i].data;
1755 break;
1756 case MSR_KVM_PV_EOI_EN:
1757 env->pv_eoi_en_msr = msrs[i].data;
1758 break;
1759 case MSR_KVM_STEAL_TIME:
1760 env->steal_time_msr = msrs[i].data;
1761 break;
1762 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1763 env->msr_fixed_ctr_ctrl = msrs[i].data;
1764 break;
1765 case MSR_CORE_PERF_GLOBAL_CTRL:
1766 env->msr_global_ctrl = msrs[i].data;
1767 break;
1768 case MSR_CORE_PERF_GLOBAL_STATUS:
1769 env->msr_global_status = msrs[i].data;
1770 break;
1771 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1772 env->msr_global_ovf_ctrl = msrs[i].data;
1773 break;
1774 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1775 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1776 break;
1777 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1778 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1779 break;
1780 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1781 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1782 break;
1783 case HV_X64_MSR_HYPERCALL:
1784 env->msr_hv_hypercall = msrs[i].data;
1785 break;
1786 case HV_X64_MSR_GUEST_OS_ID:
1787 env->msr_hv_guest_os_id = msrs[i].data;
1788 break;
1789 case HV_X64_MSR_APIC_ASSIST_PAGE:
1790 env->msr_hv_vapic = msrs[i].data;
1791 break;
1792 case HV_X64_MSR_REFERENCE_TSC:
1793 env->msr_hv_tsc = msrs[i].data;
1794 break;
1795 case MSR_MTRRdefType:
1796 env->mtrr_deftype = msrs[i].data;
1797 break;
1798 case MSR_MTRRfix64K_00000:
1799 env->mtrr_fixed[0] = msrs[i].data;
1800 break;
1801 case MSR_MTRRfix16K_80000:
1802 env->mtrr_fixed[1] = msrs[i].data;
1803 break;
1804 case MSR_MTRRfix16K_A0000:
1805 env->mtrr_fixed[2] = msrs[i].data;
1806 break;
1807 case MSR_MTRRfix4K_C0000:
1808 env->mtrr_fixed[3] = msrs[i].data;
1809 break;
1810 case MSR_MTRRfix4K_C8000:
1811 env->mtrr_fixed[4] = msrs[i].data;
1812 break;
1813 case MSR_MTRRfix4K_D0000:
1814 env->mtrr_fixed[5] = msrs[i].data;
1815 break;
1816 case MSR_MTRRfix4K_D8000:
1817 env->mtrr_fixed[6] = msrs[i].data;
1818 break;
1819 case MSR_MTRRfix4K_E0000:
1820 env->mtrr_fixed[7] = msrs[i].data;
1821 break;
1822 case MSR_MTRRfix4K_E8000:
1823 env->mtrr_fixed[8] = msrs[i].data;
1824 break;
1825 case MSR_MTRRfix4K_F0000:
1826 env->mtrr_fixed[9] = msrs[i].data;
1827 break;
1828 case MSR_MTRRfix4K_F8000:
1829 env->mtrr_fixed[10] = msrs[i].data;
1830 break;
1831 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1832 if (index & 1) {
1833 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1834 } else {
1835 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1836 }
1837 break;
1838 }
1839 }
1840
1841 return 0;
1842 }
1843
1844 static int kvm_put_mp_state(X86CPU *cpu)
1845 {
1846 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1847
1848 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1849 }
1850
1851 static int kvm_get_mp_state(X86CPU *cpu)
1852 {
1853 CPUState *cs = CPU(cpu);
1854 CPUX86State *env = &cpu->env;
1855 struct kvm_mp_state mp_state;
1856 int ret;
1857
1858 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1859 if (ret < 0) {
1860 return ret;
1861 }
1862 env->mp_state = mp_state.mp_state;
1863 if (kvm_irqchip_in_kernel()) {
1864 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1865 }
1866 return 0;
1867 }
1868
1869 static int kvm_get_apic(X86CPU *cpu)
1870 {
1871 DeviceState *apic = cpu->apic_state;
1872 struct kvm_lapic_state kapic;
1873 int ret;
1874
1875 if (apic && kvm_irqchip_in_kernel()) {
1876 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1877 if (ret < 0) {
1878 return ret;
1879 }
1880
1881 kvm_get_apic_state(apic, &kapic);
1882 }
1883 return 0;
1884 }
1885
1886 static int kvm_put_apic(X86CPU *cpu)
1887 {
1888 DeviceState *apic = cpu->apic_state;
1889 struct kvm_lapic_state kapic;
1890
1891 if (apic && kvm_irqchip_in_kernel()) {
1892 kvm_put_apic_state(apic, &kapic);
1893
1894 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1895 }
1896 return 0;
1897 }
1898
1899 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1900 {
1901 CPUX86State *env = &cpu->env;
1902 struct kvm_vcpu_events events = {};
1903
1904 if (!kvm_has_vcpu_events()) {
1905 return 0;
1906 }
1907
1908 events.exception.injected = (env->exception_injected >= 0);
1909 events.exception.nr = env->exception_injected;
1910 events.exception.has_error_code = env->has_error_code;
1911 events.exception.error_code = env->error_code;
1912 events.exception.pad = 0;
1913
1914 events.interrupt.injected = (env->interrupt_injected >= 0);
1915 events.interrupt.nr = env->interrupt_injected;
1916 events.interrupt.soft = env->soft_interrupt;
1917
1918 events.nmi.injected = env->nmi_injected;
1919 events.nmi.pending = env->nmi_pending;
1920 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1921 events.nmi.pad = 0;
1922
1923 events.sipi_vector = env->sipi_vector;
1924
1925 events.flags = 0;
1926 if (level >= KVM_PUT_RESET_STATE) {
1927 events.flags |=
1928 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1929 }
1930
1931 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1932 }
1933
1934 static int kvm_get_vcpu_events(X86CPU *cpu)
1935 {
1936 CPUX86State *env = &cpu->env;
1937 struct kvm_vcpu_events events;
1938 int ret;
1939
1940 if (!kvm_has_vcpu_events()) {
1941 return 0;
1942 }
1943
1944 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1945 if (ret < 0) {
1946 return ret;
1947 }
1948 env->exception_injected =
1949 events.exception.injected ? events.exception.nr : -1;
1950 env->has_error_code = events.exception.has_error_code;
1951 env->error_code = events.exception.error_code;
1952
1953 env->interrupt_injected =
1954 events.interrupt.injected ? events.interrupt.nr : -1;
1955 env->soft_interrupt = events.interrupt.soft;
1956
1957 env->nmi_injected = events.nmi.injected;
1958 env->nmi_pending = events.nmi.pending;
1959 if (events.nmi.masked) {
1960 env->hflags2 |= HF2_NMI_MASK;
1961 } else {
1962 env->hflags2 &= ~HF2_NMI_MASK;
1963 }
1964
1965 env->sipi_vector = events.sipi_vector;
1966
1967 return 0;
1968 }
1969
1970 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1971 {
1972 CPUState *cs = CPU(cpu);
1973 CPUX86State *env = &cpu->env;
1974 int ret = 0;
1975 unsigned long reinject_trap = 0;
1976
1977 if (!kvm_has_vcpu_events()) {
1978 if (env->exception_injected == 1) {
1979 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1980 } else if (env->exception_injected == 3) {
1981 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1982 }
1983 env->exception_injected = -1;
1984 }
1985
1986 /*
1987 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1988 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1989 * by updating the debug state once again if single-stepping is on.
1990 * Another reason to call kvm_update_guest_debug here is a pending debug
1991 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1992 * reinject them via SET_GUEST_DEBUG.
1993 */
1994 if (reinject_trap ||
1995 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1996 ret = kvm_update_guest_debug(cs, reinject_trap);
1997 }
1998 return ret;
1999 }
2000
2001 static int kvm_put_debugregs(X86CPU *cpu)
2002 {
2003 CPUX86State *env = &cpu->env;
2004 struct kvm_debugregs dbgregs;
2005 int i;
2006
2007 if (!kvm_has_debugregs()) {
2008 return 0;
2009 }
2010
2011 for (i = 0; i < 4; i++) {
2012 dbgregs.db[i] = env->dr[i];
2013 }
2014 dbgregs.dr6 = env->dr[6];
2015 dbgregs.dr7 = env->dr[7];
2016 dbgregs.flags = 0;
2017
2018 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2019 }
2020
2021 static int kvm_get_debugregs(X86CPU *cpu)
2022 {
2023 CPUX86State *env = &cpu->env;
2024 struct kvm_debugregs dbgregs;
2025 int i, ret;
2026
2027 if (!kvm_has_debugregs()) {
2028 return 0;
2029 }
2030
2031 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2032 if (ret < 0) {
2033 return ret;
2034 }
2035 for (i = 0; i < 4; i++) {
2036 env->dr[i] = dbgregs.db[i];
2037 }
2038 env->dr[4] = env->dr[6] = dbgregs.dr6;
2039 env->dr[5] = env->dr[7] = dbgregs.dr7;
2040
2041 return 0;
2042 }
2043
2044 int kvm_arch_put_registers(CPUState *cpu, int level)
2045 {
2046 X86CPU *x86_cpu = X86_CPU(cpu);
2047 int ret;
2048
2049 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2050
2051 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2052 ret = kvm_put_msr_feature_control(x86_cpu);
2053 if (ret < 0) {
2054 return ret;
2055 }
2056 }
2057
2058 ret = kvm_getput_regs(x86_cpu, 1);
2059 if (ret < 0) {
2060 return ret;
2061 }
2062 ret = kvm_put_xsave(x86_cpu);
2063 if (ret < 0) {
2064 return ret;
2065 }
2066 ret = kvm_put_xcrs(x86_cpu);
2067 if (ret < 0) {
2068 return ret;
2069 }
2070 ret = kvm_put_sregs(x86_cpu);
2071 if (ret < 0) {
2072 return ret;
2073 }
2074 /* must be before kvm_put_msrs */
2075 ret = kvm_inject_mce_oldstyle(x86_cpu);
2076 if (ret < 0) {
2077 return ret;
2078 }
2079 ret = kvm_put_msrs(x86_cpu, level);
2080 if (ret < 0) {
2081 return ret;
2082 }
2083 if (level >= KVM_PUT_RESET_STATE) {
2084 ret = kvm_put_mp_state(x86_cpu);
2085 if (ret < 0) {
2086 return ret;
2087 }
2088 ret = kvm_put_apic(x86_cpu);
2089 if (ret < 0) {
2090 return ret;
2091 }
2092 }
2093
2094 ret = kvm_put_tscdeadline_msr(x86_cpu);
2095 if (ret < 0) {
2096 return ret;
2097 }
2098
2099 ret = kvm_put_vcpu_events(x86_cpu, level);
2100 if (ret < 0) {
2101 return ret;
2102 }
2103 ret = kvm_put_debugregs(x86_cpu);
2104 if (ret < 0) {
2105 return ret;
2106 }
2107 /* must be last */
2108 ret = kvm_guest_debug_workarounds(x86_cpu);
2109 if (ret < 0) {
2110 return ret;
2111 }
2112 return 0;
2113 }
2114
2115 int kvm_arch_get_registers(CPUState *cs)
2116 {
2117 X86CPU *cpu = X86_CPU(cs);
2118 int ret;
2119
2120 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2121
2122 ret = kvm_getput_regs(cpu, 0);
2123 if (ret < 0) {
2124 return ret;
2125 }
2126 ret = kvm_get_xsave(cpu);
2127 if (ret < 0) {
2128 return ret;
2129 }
2130 ret = kvm_get_xcrs(cpu);
2131 if (ret < 0) {
2132 return ret;
2133 }
2134 ret = kvm_get_sregs(cpu);
2135 if (ret < 0) {
2136 return ret;
2137 }
2138 ret = kvm_get_msrs(cpu);
2139 if (ret < 0) {
2140 return ret;
2141 }
2142 ret = kvm_get_mp_state(cpu);
2143 if (ret < 0) {
2144 return ret;
2145 }
2146 ret = kvm_get_apic(cpu);
2147 if (ret < 0) {
2148 return ret;
2149 }
2150 ret = kvm_get_vcpu_events(cpu);
2151 if (ret < 0) {
2152 return ret;
2153 }
2154 ret = kvm_get_debugregs(cpu);
2155 if (ret < 0) {
2156 return ret;
2157 }
2158 return 0;
2159 }
2160
2161 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2162 {
2163 X86CPU *x86_cpu = X86_CPU(cpu);
2164 CPUX86State *env = &x86_cpu->env;
2165 int ret;
2166
2167 /* Inject NMI */
2168 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2169 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2170 DPRINTF("injected NMI\n");
2171 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2172 if (ret < 0) {
2173 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2174 strerror(-ret));
2175 }
2176 }
2177
2178 /* Force the VCPU out of its inner loop to process any INIT requests
2179 * or (for userspace APIC, but it is cheap to combine the checks here)
2180 * pending TPR access reports.
2181 */
2182 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2183 cpu->exit_request = 1;
2184 }
2185
2186 if (!kvm_irqchip_in_kernel()) {
2187 /* Try to inject an interrupt if the guest can accept it */
2188 if (run->ready_for_interrupt_injection &&
2189 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2190 (env->eflags & IF_MASK)) {
2191 int irq;
2192
2193 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2194 irq = cpu_get_pic_interrupt(env);
2195 if (irq >= 0) {
2196 struct kvm_interrupt intr;
2197
2198 intr.irq = irq;
2199 DPRINTF("injected interrupt %d\n", irq);
2200 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2201 if (ret < 0) {
2202 fprintf(stderr,
2203 "KVM: injection failed, interrupt lost (%s)\n",
2204 strerror(-ret));
2205 }
2206 }
2207 }
2208
2209 /* If we have an interrupt but the guest is not ready to receive an
2210 * interrupt, request an interrupt window exit. This will
2211 * cause a return to userspace as soon as the guest is ready to
2212 * receive interrupts. */
2213 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2214 run->request_interrupt_window = 1;
2215 } else {
2216 run->request_interrupt_window = 0;
2217 }
2218
2219 DPRINTF("setting tpr\n");
2220 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2221 }
2222 }
2223
2224 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2225 {
2226 X86CPU *x86_cpu = X86_CPU(cpu);
2227 CPUX86State *env = &x86_cpu->env;
2228
2229 if (run->if_flag) {
2230 env->eflags |= IF_MASK;
2231 } else {
2232 env->eflags &= ~IF_MASK;
2233 }
2234 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2235 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2236 }
2237
2238 int kvm_arch_process_async_events(CPUState *cs)
2239 {
2240 X86CPU *cpu = X86_CPU(cs);
2241 CPUX86State *env = &cpu->env;
2242
2243 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2244 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2245 assert(env->mcg_cap);
2246
2247 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2248
2249 kvm_cpu_synchronize_state(cs);
2250
2251 if (env->exception_injected == EXCP08_DBLE) {
2252 /* this means triple fault */
2253 qemu_system_reset_request();
2254 cs->exit_request = 1;
2255 return 0;
2256 }
2257 env->exception_injected = EXCP12_MCHK;
2258 env->has_error_code = 0;
2259
2260 cs->halted = 0;
2261 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2262 env->mp_state = KVM_MP_STATE_RUNNABLE;
2263 }
2264 }
2265
2266 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2267 kvm_cpu_synchronize_state(cs);
2268 do_cpu_init(cpu);
2269 }
2270
2271 if (kvm_irqchip_in_kernel()) {
2272 return 0;
2273 }
2274
2275 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2276 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2277 apic_poll_irq(cpu->apic_state);
2278 }
2279 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2280 (env->eflags & IF_MASK)) ||
2281 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2282 cs->halted = 0;
2283 }
2284 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2285 kvm_cpu_synchronize_state(cs);
2286 do_cpu_sipi(cpu);
2287 }
2288 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2289 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2290 kvm_cpu_synchronize_state(cs);
2291 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2292 env->tpr_access_type);
2293 }
2294
2295 return cs->halted;
2296 }
2297
2298 static int kvm_handle_halt(X86CPU *cpu)
2299 {
2300 CPUState *cs = CPU(cpu);
2301 CPUX86State *env = &cpu->env;
2302
2303 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2304 (env->eflags & IF_MASK)) &&
2305 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2306 cs->halted = 1;
2307 return EXCP_HLT;
2308 }
2309
2310 return 0;
2311 }
2312
2313 static int kvm_handle_tpr_access(X86CPU *cpu)
2314 {
2315 CPUState *cs = CPU(cpu);
2316 struct kvm_run *run = cs->kvm_run;
2317
2318 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2319 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2320 : TPR_ACCESS_READ);
2321 return 1;
2322 }
2323
2324 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2325 {
2326 static const uint8_t int3 = 0xcc;
2327
2328 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2329 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2330 return -EINVAL;
2331 }
2332 return 0;
2333 }
2334
2335 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2336 {
2337 uint8_t int3;
2338
2339 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2340 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2341 return -EINVAL;
2342 }
2343 return 0;
2344 }
2345
2346 static struct {
2347 target_ulong addr;
2348 int len;
2349 int type;
2350 } hw_breakpoint[4];
2351
2352 static int nb_hw_breakpoint;
2353
2354 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2355 {
2356 int n;
2357
2358 for (n = 0; n < nb_hw_breakpoint; n++) {
2359 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2360 (hw_breakpoint[n].len == len || len == -1)) {
2361 return n;
2362 }
2363 }
2364 return -1;
2365 }
2366
2367 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2368 target_ulong len, int type)
2369 {
2370 switch (type) {
2371 case GDB_BREAKPOINT_HW:
2372 len = 1;
2373 break;
2374 case GDB_WATCHPOINT_WRITE:
2375 case GDB_WATCHPOINT_ACCESS:
2376 switch (len) {
2377 case 1:
2378 break;
2379 case 2:
2380 case 4:
2381 case 8:
2382 if (addr & (len - 1)) {
2383 return -EINVAL;
2384 }
2385 break;
2386 default:
2387 return -EINVAL;
2388 }
2389 break;
2390 default:
2391 return -ENOSYS;
2392 }
2393
2394 if (nb_hw_breakpoint == 4) {
2395 return -ENOBUFS;
2396 }
2397 if (find_hw_breakpoint(addr, len, type) >= 0) {
2398 return -EEXIST;
2399 }
2400 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2401 hw_breakpoint[nb_hw_breakpoint].len = len;
2402 hw_breakpoint[nb_hw_breakpoint].type = type;
2403 nb_hw_breakpoint++;
2404
2405 return 0;
2406 }
2407
2408 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2409 target_ulong len, int type)
2410 {
2411 int n;
2412
2413 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2414 if (n < 0) {
2415 return -ENOENT;
2416 }
2417 nb_hw_breakpoint--;
2418 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2419
2420 return 0;
2421 }
2422
2423 void kvm_arch_remove_all_hw_breakpoints(void)
2424 {
2425 nb_hw_breakpoint = 0;
2426 }
2427
2428 static CPUWatchpoint hw_watchpoint;
2429
2430 static int kvm_handle_debug(X86CPU *cpu,
2431 struct kvm_debug_exit_arch *arch_info)
2432 {
2433 CPUState *cs = CPU(cpu);
2434 CPUX86State *env = &cpu->env;
2435 int ret = 0;
2436 int n;
2437
2438 if (arch_info->exception == 1) {
2439 if (arch_info->dr6 & (1 << 14)) {
2440 if (cs->singlestep_enabled) {
2441 ret = EXCP_DEBUG;
2442 }
2443 } else {
2444 for (n = 0; n < 4; n++) {
2445 if (arch_info->dr6 & (1 << n)) {
2446 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2447 case 0x0:
2448 ret = EXCP_DEBUG;
2449 break;
2450 case 0x1:
2451 ret = EXCP_DEBUG;
2452 cs->watchpoint_hit = &hw_watchpoint;
2453 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2454 hw_watchpoint.flags = BP_MEM_WRITE;
2455 break;
2456 case 0x3:
2457 ret = EXCP_DEBUG;
2458 cs->watchpoint_hit = &hw_watchpoint;
2459 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2460 hw_watchpoint.flags = BP_MEM_ACCESS;
2461 break;
2462 }
2463 }
2464 }
2465 }
2466 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2467 ret = EXCP_DEBUG;
2468 }
2469 if (ret == 0) {
2470 cpu_synchronize_state(cs);
2471 assert(env->exception_injected == -1);
2472
2473 /* pass to guest */
2474 env->exception_injected = arch_info->exception;
2475 env->has_error_code = 0;
2476 }
2477
2478 return ret;
2479 }
2480
2481 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2482 {
2483 const uint8_t type_code[] = {
2484 [GDB_BREAKPOINT_HW] = 0x0,
2485 [GDB_WATCHPOINT_WRITE] = 0x1,
2486 [GDB_WATCHPOINT_ACCESS] = 0x3
2487 };
2488 const uint8_t len_code[] = {
2489 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2490 };
2491 int n;
2492
2493 if (kvm_sw_breakpoints_active(cpu)) {
2494 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2495 }
2496 if (nb_hw_breakpoint > 0) {
2497 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2498 dbg->arch.debugreg[7] = 0x0600;
2499 for (n = 0; n < nb_hw_breakpoint; n++) {
2500 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2501 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2502 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2503 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2504 }
2505 }
2506 }
2507
2508 static bool host_supports_vmx(void)
2509 {
2510 uint32_t ecx, unused;
2511
2512 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2513 return ecx & CPUID_EXT_VMX;
2514 }
2515
2516 #define VMX_INVALID_GUEST_STATE 0x80000021
2517
2518 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2519 {
2520 X86CPU *cpu = X86_CPU(cs);
2521 uint64_t code;
2522 int ret;
2523
2524 switch (run->exit_reason) {
2525 case KVM_EXIT_HLT:
2526 DPRINTF("handle_hlt\n");
2527 ret = kvm_handle_halt(cpu);
2528 break;
2529 case KVM_EXIT_SET_TPR:
2530 ret = 0;
2531 break;
2532 case KVM_EXIT_TPR_ACCESS:
2533 ret = kvm_handle_tpr_access(cpu);
2534 break;
2535 case KVM_EXIT_FAIL_ENTRY:
2536 code = run->fail_entry.hardware_entry_failure_reason;
2537 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2538 code);
2539 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2540 fprintf(stderr,
2541 "\nIf you're running a guest on an Intel machine without "
2542 "unrestricted mode\n"
2543 "support, the failure can be most likely due to the guest "
2544 "entering an invalid\n"
2545 "state for Intel VT. For example, the guest maybe running "
2546 "in big real mode\n"
2547 "which is not supported on less recent Intel processors."
2548 "\n\n");
2549 }
2550 ret = -1;
2551 break;
2552 case KVM_EXIT_EXCEPTION:
2553 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2554 run->ex.exception, run->ex.error_code);
2555 ret = -1;
2556 break;
2557 case KVM_EXIT_DEBUG:
2558 DPRINTF("kvm_exit_debug\n");
2559 ret = kvm_handle_debug(cpu, &run->debug.arch);
2560 break;
2561 default:
2562 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2563 ret = -1;
2564 break;
2565 }
2566
2567 return ret;
2568 }
2569
2570 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2571 {
2572 X86CPU *cpu = X86_CPU(cs);
2573 CPUX86State *env = &cpu->env;
2574
2575 kvm_cpu_synchronize_state(cs);
2576 return !(env->cr[0] & CR0_PE_MASK) ||
2577 ((env->segs[R_CS].selector & 3) != 3);
2578 }
2579
2580 void kvm_arch_init_irq_routing(KVMState *s)
2581 {
2582 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2583 /* If kernel can't do irq routing, interrupt source
2584 * override 0->2 cannot be set up as required by HPET.
2585 * So we have to disable it.
2586 */
2587 no_hpet = 1;
2588 }
2589 /* We know at this point that we're using the in-kernel
2590 * irqchip, so we can use irqfds, and on x86 we know
2591 * we can use msi via irqfd and GSI routing.
2592 */
2593 kvm_msi_via_irqfd_allowed = true;
2594 kvm_gsi_routing_allowed = true;
2595 }
2596
2597 /* Classic KVM device assignment interface. Will remain x86 only. */
2598 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2599 uint32_t flags, uint32_t *dev_id)
2600 {
2601 struct kvm_assigned_pci_dev dev_data = {
2602 .segnr = dev_addr->domain,
2603 .busnr = dev_addr->bus,
2604 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2605 .flags = flags,
2606 };
2607 int ret;
2608
2609 dev_data.assigned_dev_id =
2610 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2611
2612 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2613 if (ret < 0) {
2614 return ret;
2615 }
2616
2617 *dev_id = dev_data.assigned_dev_id;
2618
2619 return 0;
2620 }
2621
2622 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2623 {
2624 struct kvm_assigned_pci_dev dev_data = {
2625 .assigned_dev_id = dev_id,
2626 };
2627
2628 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2629 }
2630
2631 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2632 uint32_t irq_type, uint32_t guest_irq)
2633 {
2634 struct kvm_assigned_irq assigned_irq = {
2635 .assigned_dev_id = dev_id,
2636 .guest_irq = guest_irq,
2637 .flags = irq_type,
2638 };
2639
2640 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2641 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2642 } else {
2643 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2644 }
2645 }
2646
2647 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2648 uint32_t guest_irq)
2649 {
2650 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2651 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2652
2653 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2654 }
2655
2656 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2657 {
2658 struct kvm_assigned_pci_dev dev_data = {
2659 .assigned_dev_id = dev_id,
2660 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2661 };
2662
2663 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2664 }
2665
2666 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2667 uint32_t type)
2668 {
2669 struct kvm_assigned_irq assigned_irq = {
2670 .assigned_dev_id = dev_id,
2671 .flags = type,
2672 };
2673
2674 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2675 }
2676
2677 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2678 {
2679 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2680 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2681 }
2682
2683 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2684 {
2685 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2686 KVM_DEV_IRQ_GUEST_MSI, virq);
2687 }
2688
2689 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2690 {
2691 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2692 KVM_DEV_IRQ_HOST_MSI);
2693 }
2694
2695 bool kvm_device_msix_supported(KVMState *s)
2696 {
2697 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2698 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2699 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2700 }
2701
2702 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2703 uint32_t nr_vectors)
2704 {
2705 struct kvm_assigned_msix_nr msix_nr = {
2706 .assigned_dev_id = dev_id,
2707 .entry_nr = nr_vectors,
2708 };
2709
2710 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2711 }
2712
2713 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2714 int virq)
2715 {
2716 struct kvm_assigned_msix_entry msix_entry = {
2717 .assigned_dev_id = dev_id,
2718 .gsi = virq,
2719 .entry = vector,
2720 };
2721
2722 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2723 }
2724
2725 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2726 {
2727 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2728 KVM_DEV_IRQ_GUEST_MSIX, 0);
2729 }
2730
2731 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2732 {
2733 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2734 KVM_DEV_IRQ_HOST_MSIX);
2735 }
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