hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "scsi-disk.h"
  27 #include "scsi.h"
  28
  29 /* debug ESP card */
  30 //#define DEBUG_ESP
  31
  32 /*
  33  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  34  * also produced as NCR89C100. See
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  36  * and
  37  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  38  */
  39
  40 #ifdef DEBUG_ESP
  41 #define DPRINTF(fmt, ...)                                       \
  42     do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
  43 #else
  44 #define DPRINTF(fmt, ...) do {} while (0)
  45 #endif
  46
  47 #define ESP_ERROR(fmt, ...)                                             \
  48     do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  49
  50 #define ESP_REGS 16
  51 #define TI_BUFSZ 16
  52
  53 typedef struct ESPState ESPState;
  54
  55 struct ESPState {
  56     SysBusDevice busdev;
  57     uint32_t it_shift;
  58     qemu_irq irq;
  59     uint8_t rregs[ESP_REGS];
  60     uint8_t wregs[ESP_REGS];
  61     int32_t ti_size;
  62     uint32_t ti_rptr, ti_wptr;
  63     uint8_t ti_buf[TI_BUFSZ];
  64     uint32_t sense;
  65     uint32_t dma;
  66     SCSIDevice *scsi_dev[ESP_MAX_DEVS];
  67     SCSIDevice *current_dev;
  68     uint8_t cmdbuf[TI_BUFSZ];
  69     uint32_t cmdlen;
  70     uint32_t do_cmd;
  71
  72     /* The amount of data left in the current DMA transfer.  */
  73     uint32_t dma_left;
  74     /* The size of the current DMA transfer.  Zero if no transfer is in
  75        progress.  */
  76     uint32_t dma_counter;
  77     uint8_t *async_buf;
  78     uint32_t async_len;
  79
  80     espdma_memory_read_write dma_memory_read;
  81     espdma_memory_read_write dma_memory_write;
  82     void *dma_opaque;
  83 };
  84
  85 #define ESP_TCLO   0x0
  86 #define ESP_TCMID  0x1
  87 #define ESP_FIFO   0x2
  88 #define ESP_CMD    0x3
  89 #define ESP_RSTAT  0x4
  90 #define ESP_WBUSID 0x4
  91 #define ESP_RINTR  0x5
  92 #define ESP_WSEL   0x5
  93 #define ESP_RSEQ   0x6
  94 #define ESP_WSYNTP 0x6
  95 #define ESP_RFLAGS 0x7
  96 #define ESP_WSYNO  0x7
  97 #define ESP_CFG1   0x8
  98 #define ESP_RRES1  0x9
  99 #define ESP_WCCF   0x9
 100 #define ESP_RRES2  0xa
 101 #define ESP_WTEST  0xa
 102 #define ESP_CFG2   0xb
 103 #define ESP_CFG3   0xc
 104 #define ESP_RES3   0xd
 105 #define ESP_TCHI   0xe
 106 #define ESP_RES4   0xf
 107
 108 #define CMD_DMA 0x80
 109 #define CMD_CMD 0x7f
 110
 111 #define CMD_NOP      0x00
 112 #define CMD_FLUSH    0x01
 113 #define CMD_RESET    0x02
 114 #define CMD_BUSRESET 0x03
 115 #define CMD_TI       0x10
 116 #define CMD_ICCS     0x11
 117 #define CMD_MSGACC   0x12
 118 #define CMD_SATN     0x1a
 119 #define CMD_SEL      0x41
 120 #define CMD_SELATN   0x42
 121 #define CMD_SELATNS  0x43
 122 #define CMD_ENSEL    0x44
 123
 124 #define STAT_DO 0x00
 125 #define STAT_DI 0x01
 126 #define STAT_CD 0x02
 127 #define STAT_ST 0x03
 128 #define STAT_MO 0x06
 129 #define STAT_MI 0x07
 130 #define STAT_PIO_MASK 0x06
 131
 132 #define STAT_TC 0x10
 133 #define STAT_PE 0x20
 134 #define STAT_GE 0x40
 135 #define STAT_INT 0x80
 136
 137 #define BUSID_DID 0x07
 138
 139 #define INTR_FC 0x08
 140 #define INTR_BS 0x10
 141 #define INTR_DC 0x20
 142 #define INTR_RST 0x80
 143
 144 #define SEQ_0 0x0
 145 #define SEQ_CD 0x4
 146
 147 #define CFG1_RESREPT 0x40
 148
 149 #define TCHI_FAS100A 0x4
 150
 151 static void esp_raise_irq(ESPState *s)
 152 {
 153     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 154         s->rregs[ESP_RSTAT] |= STAT_INT;
 155         qemu_irq_raise(s->irq);
 156     }
 157 }
 158
 159 static void esp_lower_irq(ESPState *s)
 160 {
 161     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 162         s->rregs[ESP_RSTAT] &= ~STAT_INT;
 163         qemu_irq_lower(s->irq);
 164     }
 165 }
 166
 167 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 168 {
 169     uint32_t dmalen;
 170     int target;
 171
 172     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 173     if (s->dma) {
 174         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 175         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 176     } else {
 177         dmalen = s->ti_size;
 178         memcpy(buf, s->ti_buf, dmalen);
 179         buf[0] = 0;
 180     }
 181     DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
 182
 183     s->ti_size = 0;
 184     s->ti_rptr = 0;
 185     s->ti_wptr = 0;
 186
 187     if (s->current_dev) {
 188         /* Started a new command before the old one finished.  Cancel it.  */
 189         s->current_dev->cancel_io(s->current_dev, 0);
 190         s->async_len = 0;
 191     }
 192
 193     if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
 194         // No such drive
 195         s->rregs[ESP_RSTAT] = 0;
 196         s->rregs[ESP_RINTR] = INTR_DC;
 197         s->rregs[ESP_RSEQ] = SEQ_0;
 198         esp_raise_irq(s);
 199         return 0;
 200     }
 201     s->current_dev = s->scsi_dev[target];
 202     return dmalen;
 203 }
 204
 205 static void do_cmd(ESPState *s, uint8_t *buf)
 206 {
 207     int32_t datalen;
 208     int lun;
 209
 210     DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
 211     lun = buf[0] & 7;
 212     datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun);
 213     s->ti_size = datalen;
 214     if (datalen != 0) {
 215         s->rregs[ESP_RSTAT] = STAT_TC;
 216         s->dma_left = 0;
 217         s->dma_counter = 0;
 218         if (datalen > 0) {
 219             s->rregs[ESP_RSTAT] |= STAT_DI;
 220             s->current_dev->read_data(s->current_dev, 0);
 221         } else {
 222             s->rregs[ESP_RSTAT] |= STAT_DO;
 223             s->current_dev->write_data(s->current_dev, 0);
 224         }
 225     }
 226     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 227     s->rregs[ESP_RSEQ] = SEQ_CD;
 228     esp_raise_irq(s);
 229 }
 230
 231 static void handle_satn(ESPState *s)
 232 {
 233     uint8_t buf[32];
 234     int len;
 235
 236     len = get_cmd(s, buf);
 237     if (len)
 238         do_cmd(s, buf);
 239 }
 240
 241 static void handle_satn_stop(ESPState *s)
 242 {
 243     s->cmdlen = get_cmd(s, s->cmdbuf);
 244     if (s->cmdlen) {
 245         DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
 246         s->do_cmd = 1;
 247         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 248         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 249         s->rregs[ESP_RSEQ] = SEQ_CD;
 250         esp_raise_irq(s);
 251     }
 252 }
 253
 254 static void write_response(ESPState *s)
 255 {
 256     DPRINTF("Transfer status (sense=%d)\n", s->sense);
 257     s->ti_buf[0] = s->sense;
 258     s->ti_buf[1] = 0;
 259     if (s->dma) {
 260         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 261         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 262         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 263         s->rregs[ESP_RSEQ] = SEQ_CD;
 264     } else {
 265         s->ti_size = 2;
 266         s->ti_rptr = 0;
 267         s->ti_wptr = 0;
 268         s->rregs[ESP_RFLAGS] = 2;
 269     }
 270     esp_raise_irq(s);
 271 }
 272
 273 static void esp_dma_done(ESPState *s)
 274 {
 275     s->rregs[ESP_RSTAT] |= STAT_TC;
 276     s->rregs[ESP_RINTR] = INTR_BS;
 277     s->rregs[ESP_RSEQ] = 0;
 278     s->rregs[ESP_RFLAGS] = 0;
 279     s->rregs[ESP_TCLO] = 0;
 280     s->rregs[ESP_TCMID] = 0;
 281     esp_raise_irq(s);
 282 }
 283
 284 static void esp_do_dma(ESPState *s)
 285 {
 286     uint32_t len;
 287     int to_device;
 288
 289     to_device = (s->ti_size < 0);
 290     len = s->dma_left;
 291     if (s->do_cmd) {
 292         DPRINTF("command len %d + %d\n", s->cmdlen, len);
 293         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 294         s->ti_size = 0;
 295         s->cmdlen = 0;
 296         s->do_cmd = 0;
 297         do_cmd(s, s->cmdbuf);
 298         return;
 299     }
 300     if (s->async_len == 0) {
 301         /* Defer until data is available.  */
 302         return;
 303     }
 304     if (len > s->async_len) {
 305         len = s->async_len;
 306     }
 307     if (to_device) {
 308         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 309     } else {
 310         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 311     }
 312     s->dma_left -= len;
 313     s->async_buf += len;
 314     s->async_len -= len;
 315     if (to_device)
 316         s->ti_size += len;
 317     else
 318         s->ti_size -= len;
 319     if (s->async_len == 0) {
 320         if (to_device) {
 321             // ti_size is negative
 322             s->current_dev->write_data(s->current_dev, 0);
 323         } else {
 324             s->current_dev->read_data(s->current_dev, 0);
 325             /* If there is still data to be read from the device then
 326                complete the DMA operation immediately.  Otherwise defer
 327                until the scsi layer has completed.  */
 328             if (s->dma_left == 0 && s->ti_size > 0) {
 329                 esp_dma_done(s);
 330             }
 331         }
 332     } else {
 333         /* Partially filled a scsi buffer. Complete immediately.  */
 334         esp_dma_done(s);
 335     }
 336 }
 337
 338 static void esp_command_complete(void *opaque, int reason, uint32_t tag,
 339                                  uint32_t arg)
 340 {
 341     ESPState *s = (ESPState *)opaque;
 342
 343     if (reason == SCSI_REASON_DONE) {
 344         DPRINTF("SCSI Command complete\n");
 345         if (s->ti_size != 0)
 346             DPRINTF("SCSI command completed unexpectedly\n");
 347         s->ti_size = 0;
 348         s->dma_left = 0;
 349         s->async_len = 0;
 350         if (arg)
 351             DPRINTF("Command failed\n");
 352         s->sense = arg;
 353         s->rregs[ESP_RSTAT] = STAT_ST;
 354         esp_dma_done(s);
 355         s->current_dev = NULL;
 356     } else {
 357         DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
 358         s->async_len = arg;
 359         s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
 360         if (s->dma_left) {
 361             esp_do_dma(s);
 362         } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 363             /* If this was the last part of a DMA transfer then the
 364                completion interrupt is deferred to here.  */
 365             esp_dma_done(s);
 366         }
 367     }
 368 }
 369
 370 static void handle_ti(ESPState *s)
 371 {
 372     uint32_t dmalen, minlen;
 373
 374     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 375     if (dmalen==0) {
 376       dmalen=0x10000;
 377     }
 378     s->dma_counter = dmalen;
 379
 380     if (s->do_cmd)
 381         minlen = (dmalen < 32) ? dmalen : 32;
 382     else if (s->ti_size < 0)
 383         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 384     else
 385         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 386     DPRINTF("Transfer Information len %d\n", minlen);
 387     if (s->dma) {
 388         s->dma_left = minlen;
 389         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 390         esp_do_dma(s);
 391     } else if (s->do_cmd) {
 392         DPRINTF("command len %d\n", s->cmdlen);
 393         s->ti_size = 0;
 394         s->cmdlen = 0;
 395         s->do_cmd = 0;
 396         do_cmd(s, s->cmdbuf);
 397         return;
 398     }
 399 }
 400
 401 static void esp_reset(void *opaque)
 402 {
 403     ESPState *s = opaque;
 404
 405     memset(s->rregs, 0, ESP_REGS);
 406     memset(s->wregs, 0, ESP_REGS);
 407     s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
 408     s->ti_size = 0;
 409     s->ti_rptr = 0;
 410     s->ti_wptr = 0;
 411     s->dma = 0;
 412     s->do_cmd = 0;
 413
 414     s->rregs[ESP_CFG1] = 7;
 415 }
 416
 417 static void parent_esp_reset(void *opaque, int irq, int level)
 418 {
 419     if (level)
 420         esp_reset(opaque);
 421 }
 422
 423 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
 424 {
 425     ESPState *s = opaque;
 426     uint32_t saddr, old_val;
 427
 428     saddr = addr >> s->it_shift;
 429     DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
 430     switch (saddr) {
 431     case ESP_FIFO:
 432         if (s->ti_size > 0) {
 433             s->ti_size--;
 434             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 435                 /* Data out.  */
 436                 ESP_ERROR("PIO data read not implemented\n");
 437                 s->rregs[ESP_FIFO] = 0;
 438             } else {
 439                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 440             }
 441             esp_raise_irq(s);
 442         }
 443         if (s->ti_size == 0) {
 444             s->ti_rptr = 0;
 445             s->ti_wptr = 0;
 446         }
 447         break;
 448     case ESP_RINTR:
 449         /* Clear sequence step, interrupt register and all status bits
 450            except TC */
 451         old_val = s->rregs[ESP_RINTR];
 452         s->rregs[ESP_RINTR] = 0;
 453         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 454         s->rregs[ESP_RSEQ] = SEQ_CD;
 455         esp_lower_irq(s);
 456
 457         return old_val;
 458     default:
 459         break;
 460     }
 461     return s->rregs[saddr];
 462 }
 463
 464 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 465 {
 466     ESPState *s = opaque;
 467     uint32_t saddr;
 468
 469     saddr = addr >> s->it_shift;
 470     DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
 471             val);
 472     switch (saddr) {
 473     case ESP_TCLO:
 474     case ESP_TCMID:
 475         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 476         break;
 477     case ESP_FIFO:
 478         if (s->do_cmd) {
 479             s->cmdbuf[s->cmdlen++] = val & 0xff;
 480         } else if (s->ti_size == TI_BUFSZ - 1) {
 481             ESP_ERROR("fifo overrun\n");
 482         } else {
 483             s->ti_size++;
 484             s->ti_buf[s->ti_wptr++] = val & 0xff;
 485         }
 486         break;
 487     case ESP_CMD:
 488         s->rregs[saddr] = val;
 489         if (val & CMD_DMA) {
 490             s->dma = 1;
 491             /* Reload DMA counter.  */
 492             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 493             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 494         } else {
 495             s->dma = 0;
 496         }
 497         switch(val & CMD_CMD) {
 498         case CMD_NOP:
 499             DPRINTF("NOP (%2.2x)\n", val);
 500             break;
 501         case CMD_FLUSH:
 502             DPRINTF("Flush FIFO (%2.2x)\n", val);
 503             //s->ti_size = 0;
 504             s->rregs[ESP_RINTR] = INTR_FC;
 505             s->rregs[ESP_RSEQ] = 0;
 506             s->rregs[ESP_RFLAGS] = 0;
 507             break;
 508         case CMD_RESET:
 509             DPRINTF("Chip reset (%2.2x)\n", val);
 510             esp_reset(s);
 511             break;
 512         case CMD_BUSRESET:
 513             DPRINTF("Bus reset (%2.2x)\n", val);
 514             s->rregs[ESP_RINTR] = INTR_RST;
 515             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 516                 esp_raise_irq(s);
 517             }
 518             break;
 519         case CMD_TI:
 520             handle_ti(s);
 521             break;
 522         case CMD_ICCS:
 523             DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
 524             write_response(s);
 525             s->rregs[ESP_RINTR] = INTR_FC;
 526             s->rregs[ESP_RSTAT] |= STAT_MI;
 527             break;
 528         case CMD_MSGACC:
 529             DPRINTF("Message Accepted (%2.2x)\n", val);
 530             write_response(s);
 531             s->rregs[ESP_RINTR] = INTR_DC;
 532             s->rregs[ESP_RSEQ] = 0;
 533             break;
 534         case CMD_SATN:
 535             DPRINTF("Set ATN (%2.2x)\n", val);
 536             break;
 537         case CMD_SEL:
 538             DPRINTF("Select without ATN (%2.2x)\n", val);
 539             handle_satn(s);
 540             break;
 541         case CMD_SELATN:
 542             DPRINTF("Select with ATN (%2.2x)\n", val);
 543             handle_satn(s);
 544             break;
 545         case CMD_SELATNS:
 546             DPRINTF("Select with ATN & stop (%2.2x)\n", val);
 547             handle_satn_stop(s);
 548             break;
 549         case CMD_ENSEL:
 550             DPRINTF("Enable selection (%2.2x)\n", val);
 551             s->rregs[ESP_RINTR] = 0;
 552             break;
 553         default:
 554             ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
 555             break;
 556         }
 557         break;
 558     case ESP_WBUSID ... ESP_WSYNO:
 559         break;
 560     case ESP_CFG1:
 561         s->rregs[saddr] = val;
 562         break;
 563     case ESP_WCCF ... ESP_WTEST:
 564         break;
 565     case ESP_CFG2 ... ESP_RES4:
 566         s->rregs[saddr] = val;
 567         break;
 568     default:
 569         ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
 570         return;
 571     }
 572     s->wregs[saddr] = val;
 573 }
 574
 575 static CPUReadMemoryFunc *esp_mem_read[3] = {
 576     esp_mem_readb,
 577     NULL,
 578     NULL,
 579 };
 580
 581 static CPUWriteMemoryFunc *esp_mem_write[3] = {
 582     esp_mem_writeb,
 583     NULL,
 584     esp_mem_writeb,
 585 };
 586
 587 static void esp_save(QEMUFile *f, void *opaque)
 588 {
 589     ESPState *s = opaque;
 590
 591     qemu_put_buffer(f, s->rregs, ESP_REGS);
 592     qemu_put_buffer(f, s->wregs, ESP_REGS);
 593     qemu_put_sbe32s(f, &s->ti_size);
 594     qemu_put_be32s(f, &s->ti_rptr);
 595     qemu_put_be32s(f, &s->ti_wptr);
 596     qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
 597     qemu_put_be32s(f, &s->sense);
 598     qemu_put_be32s(f, &s->dma);
 599     qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ);
 600     qemu_put_be32s(f, &s->cmdlen);
 601     qemu_put_be32s(f, &s->do_cmd);
 602     qemu_put_be32s(f, &s->dma_left);
 603     // There should be no transfers in progress, so dma_counter is not saved
 604 }
 605
 606 static int esp_load(QEMUFile *f, void *opaque, int version_id)
 607 {
 608     ESPState *s = opaque;
 609
 610     if (version_id != 3)
 611         return -EINVAL; // Cannot emulate 2
 612
 613     qemu_get_buffer(f, s->rregs, ESP_REGS);
 614     qemu_get_buffer(f, s->wregs, ESP_REGS);
 615     qemu_get_sbe32s(f, &s->ti_size);
 616     qemu_get_be32s(f, &s->ti_rptr);
 617     qemu_get_be32s(f, &s->ti_wptr);
 618     qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
 619     qemu_get_be32s(f, &s->sense);
 620     qemu_get_be32s(f, &s->dma);
 621     qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ);
 622     qemu_get_be32s(f, &s->cmdlen);
 623     qemu_get_be32s(f, &s->do_cmd);
 624     qemu_get_be32s(f, &s->dma_left);
 625
 626     return 0;
 627 }
 628
 629 static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id)
 630 {
 631     ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host));
 632
 633     if (id < 0) {
 634         for (id = 0; id < ESP_MAX_DEVS; id++) {
 635             if (id == (s->rregs[ESP_CFG1] & 0x7))
 636                 continue;
 637             if (s->scsi_dev[id] == NULL)
 638                 break;
 639         }
 640     }
 641     if (id >= ESP_MAX_DEVS) {
 642         DPRINTF("Bad Device ID %d\n", id);
 643         return;
 644     }
 645     if (s->scsi_dev[id]) {
 646         DPRINTF("Destroying device %d\n", id);
 647         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
 648     }
 649     DPRINTF("Attaching block device %d\n", id);
 650     /* Command queueing is not implemented.  */
 651     s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
 652     if (s->scsi_dev[id] == NULL)
 653         s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
 654 }
 655
 656 void esp_init(target_phys_addr_t espaddr, int it_shift,
 657               espdma_memory_read_write dma_memory_read,
 658               espdma_memory_read_write dma_memory_write,
 659               void *dma_opaque, qemu_irq irq, qemu_irq *reset)
 660 {
 661     DeviceState *dev;
 662     SysBusDevice *s;
 663     ESPState *esp;
 664
 665     dev = qdev_create(NULL, "esp");
 666     esp = DO_UPCAST(ESPState, busdev.qdev, dev);
 667     esp->dma_memory_read = dma_memory_read;
 668     esp->dma_memory_write = dma_memory_write;
 669     esp->dma_opaque = dma_opaque;
 670     esp->it_shift = it_shift;
 671     qdev_init(dev);
 672     s = sysbus_from_qdev(dev);
 673     sysbus_connect_irq(s, 0, irq);
 674     sysbus_mmio_map(s, 0, espaddr);
 675     *reset = qdev_get_gpio_in(dev, 0);
 676 }
 677
 678 static void esp_init1(SysBusDevice *dev)
 679 {
 680     ESPState *s = FROM_SYSBUS(ESPState, dev);
 681     int esp_io_memory;
 682
 683     sysbus_init_irq(dev, &s->irq);
 684     assert(s->it_shift != -1);
 685
 686     esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
 687     sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
 688
 689     esp_reset(s);
 690
 691     register_savevm("esp", -1, 3, esp_save, esp_load, s);
 692     qemu_register_reset(esp_reset, s);
 693
 694     qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
 695
 696     scsi_bus_new(&dev->qdev, esp_scsi_attach);
 697 }
 698
 699 static void esp_register_devices(void)
 700 {
 701     sysbus_register_dev("esp", sizeof(ESPState), esp_init1);
 702 }
 703
 704 device_init(esp_register_devices)