target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "vs_external",
  92     "h_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 bool riscv_cpu_is_32bit(CPURISCVState *env)
 112 {
 113     if (env->misa & RV64) {
 114         return false;
 115     }
 116
 117     return true;
 118 }
 119
 120 static void set_misa(CPURISCVState *env, target_ulong misa)
 121 {
 122     env->misa_mask = env->misa = misa;
 123 }
 124
 125 static void set_priv_version(CPURISCVState *env, int priv_ver)
 126 {
 127     env->priv_ver = priv_ver;
 128 }
 129
 130 static void set_vext_version(CPURISCVState *env, int vext_ver)
 131 {
 132     env->vext_ver = vext_ver;
 133 }
 134
 135 static void set_feature(CPURISCVState *env, int feature)
 136 {
 137     env->features |= (1ULL << feature);
 138 }
 139
 140 static void set_resetvec(CPURISCVState *env, int resetvec)
 141 {
 142 #ifndef CONFIG_USER_ONLY
 143     env->resetvec = resetvec;
 144 #endif
 145 }
 146
 147 static void riscv_any_cpu_init(Object *obj)
 148 {
 149     CPURISCVState *env = &RISCV_CPU(obj)->env;
 150     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 151     set_priv_version(env, PRIV_VERSION_1_11_0);
 152 }
 153
 154 static void riscv_base_cpu_init(Object *obj)
 155 {
 156     CPURISCVState *env = &RISCV_CPU(obj)->env;
 157     /* We set this in the realise function */
 158     set_misa(env, 0);
 159 }
 160
 161 #ifdef TARGET_RISCV64
 162 static void rv64_sifive_u_cpu_init(Object *obj)
 163 {
 164     CPURISCVState *env = &RISCV_CPU(obj)->env;
 165     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 166     set_priv_version(env, PRIV_VERSION_1_10_0);
 167 }
 168
 169 static void rv64_sifive_e_cpu_init(Object *obj)
 170 {
 171     CPURISCVState *env = &RISCV_CPU(obj)->env;
 172     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 173     set_priv_version(env, PRIV_VERSION_1_10_0);
 174     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 175 }
 176 #else
 177 static void rv32_sifive_u_cpu_init(Object *obj)
 178 {
 179     CPURISCVState *env = &RISCV_CPU(obj)->env;
 180     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 181     set_priv_version(env, PRIV_VERSION_1_10_0);
 182 }
 183
 184 static void rv32_sifive_e_cpu_init(Object *obj)
 185 {
 186     CPURISCVState *env = &RISCV_CPU(obj)->env;
 187     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 188     set_priv_version(env, PRIV_VERSION_1_10_0);
 189     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 190 }
 191
 192 static void rv32_ibex_cpu_init(Object *obj)
 193 {
 194     CPURISCVState *env = &RISCV_CPU(obj)->env;
 195     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 196     set_priv_version(env, PRIV_VERSION_1_10_0);
 197     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 198 }
 199
 200 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 201 {
 202     CPURISCVState *env = &RISCV_CPU(obj)->env;
 203     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 204     set_priv_version(env, PRIV_VERSION_1_10_0);
 205     set_resetvec(env, DEFAULT_RSTVEC);
 206     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 207 }
 208 #endif
 209
 210 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 211 {
 212     ObjectClass *oc;
 213     char *typename;
 214     char **cpuname;
 215
 216     cpuname = g_strsplit(cpu_model, ",", 1);
 217     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 218     oc = object_class_by_name(typename);
 219     g_strfreev(cpuname);
 220     g_free(typename);
 221     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 222         object_class_is_abstract(oc)) {
 223         return NULL;
 224     }
 225     return oc;
 226 }
 227
 228 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 229 {
 230     RISCVCPU *cpu = RISCV_CPU(cs);
 231     CPURISCVState *env = &cpu->env;
 232     int i;
 233
 234 #if !defined(CONFIG_USER_ONLY)
 235     if (riscv_has_ext(env, RVH)) {
 236         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 237     }
 238 #endif
 239     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 240 #ifndef CONFIG_USER_ONLY
 241     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 242     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 243     if (riscv_cpu_is_32bit(env)) {
 244         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 245                      (target_ulong)(env->mstatus >> 32));
 246     }
 247     if (riscv_has_ext(env, RVH)) {
 248         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 249         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 250                      (target_ulong)env->vsstatus);
 251     }
 252     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 253     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 254     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 255     if (riscv_has_ext(env, RVH)) {
 256         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 257     }
 258     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 259     if (riscv_has_ext(env, RVH)) {
 260         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 261     }
 262     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 263     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 264     if (riscv_has_ext(env, RVH)) {
 265         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 266     }
 267     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 268     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 269     if (riscv_has_ext(env, RVH)) {
 270         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 271     }
 272     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 273     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 274     if (riscv_has_ext(env, RVH)) {
 275         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 276     }
 277     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 278     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 279     if (riscv_has_ext(env, RVH)) {
 280         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 281         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 282     }
 283 #endif
 284
 285     for (i = 0; i < 32; i++) {
 286         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 287                      riscv_int_regnames[i], env->gpr[i]);
 288         if ((i & 3) == 3) {
 289             qemu_fprintf(f, "\n");
 290         }
 291     }
 292     if (flags & CPU_DUMP_FPU) {
 293         for (i = 0; i < 32; i++) {
 294             qemu_fprintf(f, " %s %016" PRIx64,
 295                          riscv_fpr_regnames[i], env->fpr[i]);
 296             if ((i & 3) == 3) {
 297                 qemu_fprintf(f, "\n");
 298             }
 299         }
 300     }
 301 }
 302
 303 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 304 {
 305     RISCVCPU *cpu = RISCV_CPU(cs);
 306     CPURISCVState *env = &cpu->env;
 307     env->pc = value;
 308 }
 309
 310 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 311 {
 312     RISCVCPU *cpu = RISCV_CPU(cs);
 313     CPURISCVState *env = &cpu->env;
 314     env->pc = tb->pc;
 315 }
 316
 317 static bool riscv_cpu_has_work(CPUState *cs)
 318 {
 319 #ifndef CONFIG_USER_ONLY
 320     RISCVCPU *cpu = RISCV_CPU(cs);
 321     CPURISCVState *env = &cpu->env;
 322     /*
 323      * Definition of the WFI instruction requires it to ignore the privilege
 324      * mode and delegation registers, but respect individual enables
 325      */
 326     return (env->mip & env->mie) != 0;
 327 #else
 328     return true;
 329 #endif
 330 }
 331
 332 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 333                           target_ulong *data)
 334 {
 335     env->pc = data[0];
 336 }
 337
 338 static void riscv_cpu_reset(DeviceState *dev)
 339 {
 340     CPUState *cs = CPU(dev);
 341     RISCVCPU *cpu = RISCV_CPU(cs);
 342     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 343     CPURISCVState *env = &cpu->env;
 344
 345     mcc->parent_reset(dev);
 346 #ifndef CONFIG_USER_ONLY
 347     env->priv = PRV_M;
 348     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 349     env->mcause = 0;
 350     env->pc = env->resetvec;
 351 #endif
 352     cs->exception_index = EXCP_NONE;
 353     env->load_res = -1;
 354     set_default_nan_mode(1, &env->fp_status);
 355 }
 356
 357 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 358 {
 359     RISCVCPU *cpu = RISCV_CPU(s);
 360     if (riscv_cpu_is_32bit(&cpu->env)) {
 361         info->print_insn = print_insn_riscv32;
 362     } else {
 363         info->print_insn = print_insn_riscv64;
 364     }
 365 }
 366
 367 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 368 {
 369     CPUState *cs = CPU(dev);
 370     RISCVCPU *cpu = RISCV_CPU(dev);
 371     CPURISCVState *env = &cpu->env;
 372     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 373     int priv_version = PRIV_VERSION_1_11_0;
 374     int vext_version = VEXT_VERSION_0_07_1;
 375     target_ulong target_misa = 0;
 376     Error *local_err = NULL;
 377
 378     cpu_exec_realizefn(cs, &local_err);
 379     if (local_err != NULL) {
 380         error_propagate(errp, local_err);
 381         return;
 382     }
 383
 384     if (cpu->cfg.priv_spec) {
 385         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 386             priv_version = PRIV_VERSION_1_11_0;
 387         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 388             priv_version = PRIV_VERSION_1_10_0;
 389         } else {
 390             error_setg(errp,
 391                        "Unsupported privilege spec version '%s'",
 392                        cpu->cfg.priv_spec);
 393             return;
 394         }
 395     }
 396
 397     set_priv_version(env, priv_version);
 398     set_vext_version(env, vext_version);
 399
 400     if (cpu->cfg.mmu) {
 401         set_feature(env, RISCV_FEATURE_MMU);
 402     }
 403
 404     if (cpu->cfg.pmp) {
 405         set_feature(env, RISCV_FEATURE_PMP);
 406     }
 407
 408     set_resetvec(env, cpu->cfg.resetvec);
 409
 410     /* If misa isn't set (rv32 and rv64 machines) set it here */
 411     if (!env->misa) {
 412         /* Do some ISA extension error checking */
 413         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 414             error_setg(errp,
 415                        "I and E extensions are incompatible");
 416                        return;
 417        }
 418
 419         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 420             error_setg(errp,
 421                        "Either I or E extension must be set");
 422                        return;
 423        }
 424
 425        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 426                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 427                                cpu->cfg.ext_d)) {
 428             warn_report("Setting G will also set IMAFD");
 429             cpu->cfg.ext_i = true;
 430             cpu->cfg.ext_m = true;
 431             cpu->cfg.ext_a = true;
 432             cpu->cfg.ext_f = true;
 433             cpu->cfg.ext_d = true;
 434         }
 435
 436         /* Set the ISA extensions, checks should have happened above */
 437         if (cpu->cfg.ext_i) {
 438             target_misa |= RVI;
 439         }
 440         if (cpu->cfg.ext_e) {
 441             target_misa |= RVE;
 442         }
 443         if (cpu->cfg.ext_m) {
 444             target_misa |= RVM;
 445         }
 446         if (cpu->cfg.ext_a) {
 447             target_misa |= RVA;
 448         }
 449         if (cpu->cfg.ext_f) {
 450             target_misa |= RVF;
 451         }
 452         if (cpu->cfg.ext_d) {
 453             target_misa |= RVD;
 454         }
 455         if (cpu->cfg.ext_c) {
 456             target_misa |= RVC;
 457         }
 458         if (cpu->cfg.ext_s) {
 459             target_misa |= RVS;
 460         }
 461         if (cpu->cfg.ext_u) {
 462             target_misa |= RVU;
 463         }
 464         if (cpu->cfg.ext_h) {
 465             target_misa |= RVH;
 466         }
 467         if (cpu->cfg.ext_v) {
 468             target_misa |= RVV;
 469             if (!is_power_of_2(cpu->cfg.vlen)) {
 470                 error_setg(errp,
 471                         "Vector extension VLEN must be power of 2");
 472                 return;
 473             }
 474             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 475                 error_setg(errp,
 476                         "Vector extension implementation only supports VLEN "
 477                         "in the range [128, %d]", RV_VLEN_MAX);
 478                 return;
 479             }
 480             if (!is_power_of_2(cpu->cfg.elen)) {
 481                 error_setg(errp,
 482                         "Vector extension ELEN must be power of 2");
 483                 return;
 484             }
 485             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 486                 error_setg(errp,
 487                         "Vector extension implementation only supports ELEN "
 488                         "in the range [8, 64]");
 489                 return;
 490             }
 491             if (cpu->cfg.vext_spec) {
 492                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 493                     vext_version = VEXT_VERSION_0_07_1;
 494                 } else {
 495                     error_setg(errp,
 496                            "Unsupported vector spec version '%s'",
 497                            cpu->cfg.vext_spec);
 498                     return;
 499                 }
 500             } else {
 501                 qemu_log("vector verison is not specified, "
 502                         "use the default value v0.7.1\n");
 503             }
 504             set_vext_version(env, vext_version);
 505         }
 506
 507         set_misa(env, RVXLEN | target_misa);
 508     }
 509
 510     riscv_cpu_register_gdb_regs_for_features(cs);
 511
 512     qemu_init_vcpu(cs);
 513     cpu_reset(cs);
 514
 515     mcc->parent_realize(dev, errp);
 516 }
 517
 518 static void riscv_cpu_init(Object *obj)
 519 {
 520     RISCVCPU *cpu = RISCV_CPU(obj);
 521
 522     cpu_set_cpustate_pointers(cpu);
 523 }
 524
 525 static Property riscv_cpu_properties[] = {
 526     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 527     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 528     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 529     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 530     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 531     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 532     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 533     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 534     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 535     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 536     /* This is experimental so mark with 'x-' */
 537     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 538     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 539     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 540     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 541     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 542     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 543     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 544     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 545     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 546     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 547     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 548     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 549     DEFINE_PROP_END_OF_LIST(),
 550 };
 551
 552 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 553 {
 554     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 555     CPUClass *cc = CPU_CLASS(c);
 556     DeviceClass *dc = DEVICE_CLASS(c);
 557
 558     device_class_set_parent_realize(dc, riscv_cpu_realize,
 559                                     &mcc->parent_realize);
 560
 561     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 562
 563     cc->class_by_name = riscv_cpu_class_by_name;
 564     cc->has_work = riscv_cpu_has_work;
 565     cc->do_interrupt = riscv_cpu_do_interrupt;
 566     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 567     cc->dump_state = riscv_cpu_dump_state;
 568     cc->set_pc = riscv_cpu_set_pc;
 569     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 570     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 571     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 572     cc->gdb_num_core_regs = 33;
 573 #if defined(TARGET_RISCV32)
 574     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 575 #elif defined(TARGET_RISCV64)
 576     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 577 #endif
 578     cc->gdb_stop_before_watchpoint = true;
 579     cc->disas_set_info = riscv_cpu_disas_set_info;
 580 #ifndef CONFIG_USER_ONLY
 581     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 582     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 583     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 584     /* For now, mark unmigratable: */
 585     cc->vmsd = &vmstate_riscv_cpu;
 586 #endif
 587 #ifdef CONFIG_TCG
 588     cc->tcg_initialize = riscv_translate_init;
 589     cc->tlb_fill = riscv_cpu_tlb_fill;
 590 #endif
 591     device_class_set_props(dc, riscv_cpu_properties);
 592 }
 593
 594 char *riscv_isa_string(RISCVCPU *cpu)
 595 {
 596     int i;
 597     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 598     char *isa_str = g_new(char, maxlen);
 599     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 600     for (i = 0; i < sizeof(riscv_exts); i++) {
 601         if (cpu->env.misa & RV(riscv_exts[i])) {
 602             *p++ = qemu_tolower(riscv_exts[i]);
 603         }
 604     }
 605     *p = '\0';
 606     return isa_str;
 607 }
 608
 609 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 610 {
 611     ObjectClass *class_a = (ObjectClass *)a;
 612     ObjectClass *class_b = (ObjectClass *)b;
 613     const char *name_a, *name_b;
 614
 615     name_a = object_class_get_name(class_a);
 616     name_b = object_class_get_name(class_b);
 617     return strcmp(name_a, name_b);
 618 }
 619
 620 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 621 {
 622     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 623     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 624
 625     qemu_printf("%.*s\n", len, typename);
 626 }
 627
 628 void riscv_cpu_list(void)
 629 {
 630     GSList *list;
 631
 632     list = object_class_get_list(TYPE_RISCV_CPU, false);
 633     list = g_slist_sort(list, riscv_cpu_list_compare);
 634     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 635     g_slist_free(list);
 636 }
 637
 638 #define DEFINE_CPU(type_name, initfn)      \
 639     {                                      \
 640         .name = type_name,                 \
 641         .parent = TYPE_RISCV_CPU,          \
 642         .instance_init = initfn            \
 643     }
 644
 645 static const TypeInfo riscv_cpu_type_infos[] = {
 646     {
 647         .name = TYPE_RISCV_CPU,
 648         .parent = TYPE_CPU,
 649         .instance_size = sizeof(RISCVCPU),
 650         .instance_align = __alignof__(RISCVCPU),
 651         .instance_init = riscv_cpu_init,
 652         .abstract = true,
 653         .class_size = sizeof(RISCVCPUClass),
 654         .class_init = riscv_cpu_class_init,
 655     },
 656     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 657 #if defined(TARGET_RISCV32)
 658     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
 659     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 660     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 661     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 662     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 663 #elif defined(TARGET_RISCV64)
 664     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
 665     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 666     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 667 #endif
 668 };
 669
 670 DEFINE_TYPES(riscv_cpu_type_infos)