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ppc: Turn a bunch of booleans from int to bool
[qemu/kevin.git] / target-ppc / translate.c
blob55102bf2a32b9fd8c98fd82d2923c8160706ced6
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static inline void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
330 }
331
332 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
333 {
334 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
335 }
336
337 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
338 {
339 /* Will be converted to program check if needed */
340 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
341 }
342
343 /* Stop translation */
344 static inline void gen_stop_exception(DisasContext *ctx)
345 {
346 gen_update_nip(ctx, ctx->nip);
347 ctx->exception = POWERPC_EXCP_STOP;
348 }
349
350 #ifndef CONFIG_USER_ONLY
351 /* No need to update nip here, as execution flow will change */
352 static inline void gen_sync_exception(DisasContext *ctx)
353 {
354 ctx->exception = POWERPC_EXCP_SYNC;
355 }
356 #endif
357
358 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
360
361 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
362 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
363
364 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
369
370 typedef struct opcode_t {
371 unsigned char opc1, opc2, opc3;
372 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
373 unsigned char pad[5];
374 #else
375 unsigned char pad[1];
376 #endif
377 opc_handler_t handler;
378 const char *oname;
379 } opcode_t;
380
381 /* Helpers for priv. check */
382 #define GEN_PRIV \
383 do { \
384 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
385 } while (0)
386
387 #if defined(CONFIG_USER_ONLY)
388 #define CHK_HV GEN_PRIV
389 #define CHK_SV GEN_PRIV
390 #define CHK_HVRM GEN_PRIV
391 #else
392 #define CHK_HV \
393 do { \
394 if (unlikely(ctx->pr || !ctx->hv)) { \
395 GEN_PRIV; \
396 } \
397 } while (0)
398 #define CHK_SV \
399 do { \
400 if (unlikely(ctx->pr)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_HVRM \
405 do { \
406 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #endif
411
412 #define CHK_NONE
413
414
415 /*****************************************************************************/
416 /*** Instruction decoding ***/
417 #define EXTRACT_HELPER(name, shift, nb) \
418 static inline uint32_t name(uint32_t opcode) \
419 { \
420 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
421 }
422
423 #define EXTRACT_SHELPER(name, shift, nb) \
424 static inline int32_t name(uint32_t opcode) \
425 { \
426 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
427 }
428
429 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
430 static inline uint32_t name(uint32_t opcode) \
431 { \
432 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
433 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
434 }
435 /* Opcode part 1 */
436 EXTRACT_HELPER(opc1, 26, 6);
437 /* Opcode part 2 */
438 EXTRACT_HELPER(opc2, 1, 5);
439 /* Opcode part 3 */
440 EXTRACT_HELPER(opc3, 6, 5);
441 /* Update Cr0 flags */
442 EXTRACT_HELPER(Rc, 0, 1);
443 /* Update Cr6 flags (Altivec) */
444 EXTRACT_HELPER(Rc21, 10, 1);
445 /* Destination */
446 EXTRACT_HELPER(rD, 21, 5);
447 /* Source */
448 EXTRACT_HELPER(rS, 21, 5);
449 /* First operand */
450 EXTRACT_HELPER(rA, 16, 5);
451 /* Second operand */
452 EXTRACT_HELPER(rB, 11, 5);
453 /* Third operand */
454 EXTRACT_HELPER(rC, 6, 5);
455 /*** Get CRn ***/
456 EXTRACT_HELPER(crfD, 23, 3);
457 EXTRACT_HELPER(crfS, 18, 3);
458 EXTRACT_HELPER(crbD, 21, 5);
459 EXTRACT_HELPER(crbA, 16, 5);
460 EXTRACT_HELPER(crbB, 11, 5);
461 /* SPR / TBL */
462 EXTRACT_HELPER(_SPR, 11, 10);
463 static inline uint32_t SPR(uint32_t opcode)
464 {
465 uint32_t sprn = _SPR(opcode);
466
467 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
468 }
469 /*** Get constants ***/
470 /* 16 bits signed immediate value */
471 EXTRACT_SHELPER(SIMM, 0, 16);
472 /* 16 bits unsigned immediate value */
473 EXTRACT_HELPER(UIMM, 0, 16);
474 /* 5 bits signed immediate value */
475 EXTRACT_HELPER(SIMM5, 16, 5);
476 /* 5 bits signed immediate value */
477 EXTRACT_HELPER(UIMM5, 16, 5);
478 /* Bit count */
479 EXTRACT_HELPER(NB, 11, 5);
480 /* Shift count */
481 EXTRACT_HELPER(SH, 11, 5);
482 /* Vector shift count */
483 EXTRACT_HELPER(VSH, 6, 4);
484 /* Mask start */
485 EXTRACT_HELPER(MB, 6, 5);
486 /* Mask end */
487 EXTRACT_HELPER(ME, 1, 5);
488 /* Trap operand */
489 EXTRACT_HELPER(TO, 21, 5);
490
491 EXTRACT_HELPER(CRM, 12, 8);
492
493 #ifndef CONFIG_USER_ONLY
494 EXTRACT_HELPER(SR, 16, 4);
495 #endif
496
497 /* mtfsf/mtfsfi */
498 EXTRACT_HELPER(FPBF, 23, 3);
499 EXTRACT_HELPER(FPIMM, 12, 4);
500 EXTRACT_HELPER(FPL, 25, 1);
501 EXTRACT_HELPER(FPFLM, 17, 8);
502 EXTRACT_HELPER(FPW, 16, 1);
503
504 /*** Jump target decoding ***/
505 /* Immediate address */
506 static inline target_ulong LI(uint32_t opcode)
507 {
508 return (opcode >> 0) & 0x03FFFFFC;
509 }
510
511 static inline uint32_t BD(uint32_t opcode)
512 {
513 return (opcode >> 0) & 0xFFFC;
514 }
515
516 EXTRACT_HELPER(BO, 21, 5);
517 EXTRACT_HELPER(BI, 16, 5);
518 /* Absolute/relative address */
519 EXTRACT_HELPER(AA, 1, 1);
520 /* Link */
521 EXTRACT_HELPER(LK, 0, 1);
522
523 /* DFP Z22-form */
524 EXTRACT_HELPER(DCM, 10, 6)
525
526 /* DFP Z23-form */
527 EXTRACT_HELPER(RMC, 9, 2)
528
529 /* Create a mask between <start> and <end> bits */
530 static inline target_ulong MASK(uint32_t start, uint32_t end)
531 {
532 target_ulong ret;
533
534 #if defined(TARGET_PPC64)
535 if (likely(start == 0)) {
536 ret = UINT64_MAX << (63 - end);
537 } else if (likely(end == 63)) {
538 ret = UINT64_MAX >> start;
539 }
540 #else
541 if (likely(start == 0)) {
542 ret = UINT32_MAX << (31 - end);
543 } else if (likely(end == 31)) {
544 ret = UINT32_MAX >> start;
545 }
546 #endif
547 else {
548 ret = (((target_ulong)(-1ULL)) >> (start)) ^
549 (((target_ulong)(-1ULL) >> (end)) >> 1);
550 if (unlikely(start > end))
551 return ~ret;
552 }
553
554 return ret;
555 }
556
557 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
558 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
559 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
560 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
561 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
562 EXTRACT_HELPER(DM, 8, 2);
563 EXTRACT_HELPER(UIM, 16, 2);
564 EXTRACT_HELPER(SHW, 8, 2);
565 EXTRACT_HELPER(SP, 19, 2);
566 /*****************************************************************************/
567 /* PowerPC instructions table */
568
569 #if defined(DO_PPC_STATISTICS)
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 .oname = stringify(name), \
582 }, \
583 .oname = stringify(name), \
584 }
585 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586 { \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 .oname = stringify(name), \
598 }, \
599 .oname = stringify(name), \
600 }
601 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
602 { \
603 .opc1 = op1, \
604 .opc2 = op2, \
605 .opc3 = op3, \
606 .pad = { 0, }, \
607 .handler = { \
608 .inval1 = invl, \
609 .type = _typ, \
610 .type2 = _typ2, \
611 .handler = &gen_##name, \
612 .oname = onam, \
613 }, \
614 .oname = onam, \
615 }
616 #else
617 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
618 { \
619 .opc1 = op1, \
620 .opc2 = op2, \
621 .opc3 = op3, \
622 .pad = { 0, }, \
623 .handler = { \
624 .inval1 = invl, \
625 .type = _typ, \
626 .type2 = _typ2, \
627 .handler = &gen_##name, \
628 }, \
629 .oname = stringify(name), \
630 }
631 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
632 { \
633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
636 .pad = { 0, }, \
637 .handler = { \
638 .inval1 = invl1, \
639 .inval2 = invl2, \
640 .type = _typ, \
641 .type2 = _typ2, \
642 .handler = &gen_##name, \
643 }, \
644 .oname = stringify(name), \
645 }
646 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
647 { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .pad = { 0, }, \
652 .handler = { \
653 .inval1 = invl, \
654 .type = _typ, \
655 .type2 = _typ2, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = onam, \
659 }
660 #endif
661
662 /* SPR load/store helpers */
663 static inline void gen_load_spr(TCGv t, int reg)
664 {
665 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
666 }
667
668 static inline void gen_store_spr(int reg, TCGv t)
669 {
670 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
671 }
672
673 /* Invalid instruction */
674 static void gen_invalid(DisasContext *ctx)
675 {
676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
677 }
678
679 static opc_handler_t invalid_handler = {
680 .inval1 = 0xFFFFFFFF,
681 .inval2 = 0xFFFFFFFF,
682 .type = PPC_NONE,
683 .type2 = PPC_NONE,
684 .handler = gen_invalid,
685 };
686
687 /*** Integer comparison ***/
688
689 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
690 {
691 TCGv t0 = tcg_temp_new();
692 TCGv_i32 t1 = tcg_temp_new_i32();
693
694 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
695
696 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
697 tcg_gen_trunc_tl_i32(t1, t0);
698 tcg_gen_shli_i32(t1, t1, CRF_LT);
699 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
700
701 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
702 tcg_gen_trunc_tl_i32(t1, t0);
703 tcg_gen_shli_i32(t1, t1, CRF_GT);
704 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
705
706 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
707 tcg_gen_trunc_tl_i32(t1, t0);
708 tcg_gen_shli_i32(t1, t1, CRF_EQ);
709 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
710
711 tcg_temp_free(t0);
712 tcg_temp_free_i32(t1);
713 }
714
715 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
716 {
717 TCGv t0 = tcg_const_tl(arg1);
718 gen_op_cmp(arg0, t0, s, crf);
719 tcg_temp_free(t0);
720 }
721
722 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
723 {
724 TCGv t0, t1;
725 t0 = tcg_temp_new();
726 t1 = tcg_temp_new();
727 if (s) {
728 tcg_gen_ext32s_tl(t0, arg0);
729 tcg_gen_ext32s_tl(t1, arg1);
730 } else {
731 tcg_gen_ext32u_tl(t0, arg0);
732 tcg_gen_ext32u_tl(t1, arg1);
733 }
734 gen_op_cmp(t0, t1, s, crf);
735 tcg_temp_free(t1);
736 tcg_temp_free(t0);
737 }
738
739 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
740 {
741 TCGv t0 = tcg_const_tl(arg1);
742 gen_op_cmp32(arg0, t0, s, crf);
743 tcg_temp_free(t0);
744 }
745
746 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
747 {
748 if (NARROW_MODE(ctx)) {
749 gen_op_cmpi32(reg, 0, 1, 0);
750 } else {
751 gen_op_cmpi(reg, 0, 1, 0);
752 }
753 }
754
755 /* cmp */
756 static void gen_cmp(DisasContext *ctx)
757 {
758 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
759 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 1, crfD(ctx->opcode));
761 } else {
762 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
763 1, crfD(ctx->opcode));
764 }
765 }
766
767 /* cmpi */
768 static void gen_cmpi(DisasContext *ctx)
769 {
770 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
771 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
772 1, crfD(ctx->opcode));
773 } else {
774 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
775 1, crfD(ctx->opcode));
776 }
777 }
778
779 /* cmpl */
780 static void gen_cmpl(DisasContext *ctx)
781 {
782 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
783 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
784 0, crfD(ctx->opcode));
785 } else {
786 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 0, crfD(ctx->opcode));
788 }
789 }
790
791 /* cmpli */
792 static void gen_cmpli(DisasContext *ctx)
793 {
794 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
795 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
796 0, crfD(ctx->opcode));
797 } else {
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
799 0, crfD(ctx->opcode));
800 }
801 }
802
803 /* isel (PowerPC 2.03 specification) */
804 static void gen_isel(DisasContext *ctx)
805 {
806 uint32_t bi = rC(ctx->opcode);
807 uint32_t mask = 0x08 >> (bi & 0x03);
808 TCGv t0 = tcg_temp_new();
809 TCGv zr;
810
811 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
812 tcg_gen_andi_tl(t0, t0, mask);
813
814 zr = tcg_const_tl(0);
815 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
816 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
817 cpu_gpr[rB(ctx->opcode)]);
818 tcg_temp_free(zr);
819 tcg_temp_free(t0);
820 }
821
822 /* cmpb: PowerPC 2.05 specification */
823 static void gen_cmpb(DisasContext *ctx)
824 {
825 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
826 cpu_gpr[rB(ctx->opcode)]);
827 }
828
829 /*** Integer arithmetic ***/
830
831 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
832 TCGv arg1, TCGv arg2, int sub)
833 {
834 TCGv t0 = tcg_temp_new();
835
836 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
837 tcg_gen_xor_tl(t0, arg1, arg2);
838 if (sub) {
839 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
840 } else {
841 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
842 }
843 tcg_temp_free(t0);
844 if (NARROW_MODE(ctx)) {
845 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
846 }
847 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
848 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
849 }
850
851 /* Common add function */
852 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
853 TCGv arg2, bool add_ca, bool compute_ca,
854 bool compute_ov, bool compute_rc0)
855 {
856 TCGv t0 = ret;
857
858 if (compute_ca || compute_ov) {
859 t0 = tcg_temp_new();
860 }
861
862 if (compute_ca) {
863 if (NARROW_MODE(ctx)) {
864 /* Caution: a non-obvious corner case of the spec is that we
865 must produce the *entire* 64-bit addition, but produce the
866 carry into bit 32. */
867 TCGv t1 = tcg_temp_new();
868 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
869 tcg_gen_add_tl(t0, arg1, arg2);
870 if (add_ca) {
871 tcg_gen_add_tl(t0, t0, cpu_ca);
872 }
873 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
874 tcg_temp_free(t1);
875 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
876 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
877 } else {
878 TCGv zero = tcg_const_tl(0);
879 if (add_ca) {
880 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
881 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
882 } else {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
884 }
885 tcg_temp_free(zero);
886 }
887 } else {
888 tcg_gen_add_tl(t0, arg1, arg2);
889 if (add_ca) {
890 tcg_gen_add_tl(t0, t0, cpu_ca);
891 }
892 }
893
894 if (compute_ov) {
895 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
896 }
897 if (unlikely(compute_rc0)) {
898 gen_set_Rc0(ctx, t0);
899 }
900
901 if (!TCGV_EQUAL(t0, ret)) {
902 tcg_gen_mov_tl(ret, t0);
903 tcg_temp_free(t0);
904 }
905 }
906 /* Add functions with two operands */
907 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
908 static void glue(gen_, name)(DisasContext *ctx) \
909 { \
910 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
911 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
912 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
913 }
914 /* Add functions with one operand and one immediate */
915 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
916 add_ca, compute_ca, compute_ov) \
917 static void glue(gen_, name)(DisasContext *ctx) \
918 { \
919 TCGv t0 = tcg_const_tl(const_val); \
920 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
921 cpu_gpr[rA(ctx->opcode)], t0, \
922 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
923 tcg_temp_free(t0); \
924 }
925
926 /* add add. addo addo. */
927 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
928 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
929 /* addc addc. addco addco. */
930 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
931 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
932 /* adde adde. addeo addeo. */
933 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
934 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
935 /* addme addme. addmeo addmeo. */
936 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
937 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
938 /* addze addze. addzeo addzeo.*/
939 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
940 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
941 /* addi */
942 static void gen_addi(DisasContext *ctx)
943 {
944 target_long simm = SIMM(ctx->opcode);
945
946 if (rA(ctx->opcode) == 0) {
947 /* li case */
948 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
949 } else {
950 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
951 cpu_gpr[rA(ctx->opcode)], simm);
952 }
953 }
954 /* addic addic.*/
955 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
956 {
957 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
958 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
959 c, 0, 1, 0, compute_rc0);
960 tcg_temp_free(c);
961 }
962
963 static void gen_addic(DisasContext *ctx)
964 {
965 gen_op_addic(ctx, 0);
966 }
967
968 static void gen_addic_(DisasContext *ctx)
969 {
970 gen_op_addic(ctx, 1);
971 }
972
973 /* addis */
974 static void gen_addis(DisasContext *ctx)
975 {
976 target_long simm = SIMM(ctx->opcode);
977
978 if (rA(ctx->opcode) == 0) {
979 /* lis case */
980 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
981 } else {
982 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
983 cpu_gpr[rA(ctx->opcode)], simm << 16);
984 }
985 }
986
987 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
988 TCGv arg2, int sign, int compute_ov)
989 {
990 TCGLabel *l1 = gen_new_label();
991 TCGLabel *l2 = gen_new_label();
992 TCGv_i32 t0 = tcg_temp_local_new_i32();
993 TCGv_i32 t1 = tcg_temp_local_new_i32();
994
995 tcg_gen_trunc_tl_i32(t0, arg1);
996 tcg_gen_trunc_tl_i32(t1, arg2);
997 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
998 if (sign) {
999 TCGLabel *l3 = gen_new_label();
1000 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1001 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1002 gen_set_label(l3);
1003 tcg_gen_div_i32(t0, t0, t1);
1004 } else {
1005 tcg_gen_divu_i32(t0, t0, t1);
1006 }
1007 if (compute_ov) {
1008 tcg_gen_movi_tl(cpu_ov, 0);
1009 }
1010 tcg_gen_br(l2);
1011 gen_set_label(l1);
1012 if (sign) {
1013 tcg_gen_sari_i32(t0, t0, 31);
1014 } else {
1015 tcg_gen_movi_i32(t0, 0);
1016 }
1017 if (compute_ov) {
1018 tcg_gen_movi_tl(cpu_ov, 1);
1019 tcg_gen_movi_tl(cpu_so, 1);
1020 }
1021 gen_set_label(l2);
1022 tcg_gen_extu_i32_tl(ret, t0);
1023 tcg_temp_free_i32(t0);
1024 tcg_temp_free_i32(t1);
1025 if (unlikely(Rc(ctx->opcode) != 0))
1026 gen_set_Rc0(ctx, ret);
1027 }
1028 /* Div functions */
1029 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1030 static void glue(gen_, name)(DisasContext *ctx) \
1031 { \
1032 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1033 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1034 sign, compute_ov); \
1035 }
1036 /* divwu divwu. divwuo divwuo. */
1037 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1038 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1039 /* divw divw. divwo divwo. */
1040 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1041 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1042
1043 /* div[wd]eu[o][.] */
1044 #define GEN_DIVE(name, hlpr, compute_ov) \
1045 static void gen_##name(DisasContext *ctx) \
1046 { \
1047 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1048 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1049 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1050 tcg_temp_free_i32(t0); \
1051 if (unlikely(Rc(ctx->opcode) != 0)) { \
1052 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1053 } \
1054 }
1055
1056 GEN_DIVE(divweu, divweu, 0);
1057 GEN_DIVE(divweuo, divweu, 1);
1058 GEN_DIVE(divwe, divwe, 0);
1059 GEN_DIVE(divweo, divwe, 1);
1060
1061 #if defined(TARGET_PPC64)
1062 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1063 TCGv arg2, int sign, int compute_ov)
1064 {
1065 TCGLabel *l1 = gen_new_label();
1066 TCGLabel *l2 = gen_new_label();
1067
1068 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1069 if (sign) {
1070 TCGLabel *l3 = gen_new_label();
1071 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1072 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1073 gen_set_label(l3);
1074 tcg_gen_div_i64(ret, arg1, arg2);
1075 } else {
1076 tcg_gen_divu_i64(ret, arg1, arg2);
1077 }
1078 if (compute_ov) {
1079 tcg_gen_movi_tl(cpu_ov, 0);
1080 }
1081 tcg_gen_br(l2);
1082 gen_set_label(l1);
1083 if (sign) {
1084 tcg_gen_sari_i64(ret, arg1, 63);
1085 } else {
1086 tcg_gen_movi_i64(ret, 0);
1087 }
1088 if (compute_ov) {
1089 tcg_gen_movi_tl(cpu_ov, 1);
1090 tcg_gen_movi_tl(cpu_so, 1);
1091 }
1092 gen_set_label(l2);
1093 if (unlikely(Rc(ctx->opcode) != 0))
1094 gen_set_Rc0(ctx, ret);
1095 }
1096 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1097 static void glue(gen_, name)(DisasContext *ctx) \
1098 { \
1099 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1100 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1101 sign, compute_ov); \
1102 }
1103 /* divwu divwu. divwuo divwuo. */
1104 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1105 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1106 /* divw divw. divwo divwo. */
1107 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1108 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1109
1110 GEN_DIVE(divdeu, divdeu, 0);
1111 GEN_DIVE(divdeuo, divdeu, 1);
1112 GEN_DIVE(divde, divde, 0);
1113 GEN_DIVE(divdeo, divde, 1);
1114 #endif
1115
1116 /* mulhw mulhw. */
1117 static void gen_mulhw(DisasContext *ctx)
1118 {
1119 TCGv_i32 t0 = tcg_temp_new_i32();
1120 TCGv_i32 t1 = tcg_temp_new_i32();
1121
1122 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1123 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1124 tcg_gen_muls2_i32(t0, t1, t0, t1);
1125 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1126 tcg_temp_free_i32(t0);
1127 tcg_temp_free_i32(t1);
1128 if (unlikely(Rc(ctx->opcode) != 0))
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131
1132 /* mulhwu mulhwu. */
1133 static void gen_mulhwu(DisasContext *ctx)
1134 {
1135 TCGv_i32 t0 = tcg_temp_new_i32();
1136 TCGv_i32 t1 = tcg_temp_new_i32();
1137
1138 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1139 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1140 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1141 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1146 }
1147
1148 /* mullw mullw. */
1149 static void gen_mullw(DisasContext *ctx)
1150 {
1151 #if defined(TARGET_PPC64)
1152 TCGv_i64 t0, t1;
1153 t0 = tcg_temp_new_i64();
1154 t1 = tcg_temp_new_i64();
1155 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1156 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1157 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1158 tcg_temp_free(t0);
1159 tcg_temp_free(t1);
1160 #else
1161 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1162 cpu_gpr[rB(ctx->opcode)]);
1163 #endif
1164 if (unlikely(Rc(ctx->opcode) != 0))
1165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1166 }
1167
1168 /* mullwo mullwo. */
1169 static void gen_mullwo(DisasContext *ctx)
1170 {
1171 TCGv_i32 t0 = tcg_temp_new_i32();
1172 TCGv_i32 t1 = tcg_temp_new_i32();
1173
1174 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_muls2_i32(t0, t1, t0, t1);
1177 #if defined(TARGET_PPC64)
1178 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1179 #else
1180 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1181 #endif
1182
1183 tcg_gen_sari_i32(t0, t0, 31);
1184 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1185 tcg_gen_extu_i32_tl(cpu_ov, t0);
1186 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1187
1188 tcg_temp_free_i32(t0);
1189 tcg_temp_free_i32(t1);
1190 if (unlikely(Rc(ctx->opcode) != 0))
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193
1194 /* mulli */
1195 static void gen_mulli(DisasContext *ctx)
1196 {
1197 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1198 SIMM(ctx->opcode));
1199 }
1200
1201 #if defined(TARGET_PPC64)
1202 /* mulhd mulhd. */
1203 static void gen_mulhd(DisasContext *ctx)
1204 {
1205 TCGv lo = tcg_temp_new();
1206 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1207 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1208 tcg_temp_free(lo);
1209 if (unlikely(Rc(ctx->opcode) != 0)) {
1210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211 }
1212 }
1213
1214 /* mulhdu mulhdu. */
1215 static void gen_mulhdu(DisasContext *ctx)
1216 {
1217 TCGv lo = tcg_temp_new();
1218 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1219 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1220 tcg_temp_free(lo);
1221 if (unlikely(Rc(ctx->opcode) != 0)) {
1222 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1223 }
1224 }
1225
1226 /* mulld mulld. */
1227 static void gen_mulld(DisasContext *ctx)
1228 {
1229 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1230 cpu_gpr[rB(ctx->opcode)]);
1231 if (unlikely(Rc(ctx->opcode) != 0))
1232 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1233 }
1234
1235 /* mulldo mulldo. */
1236 static void gen_mulldo(DisasContext *ctx)
1237 {
1238 TCGv_i64 t0 = tcg_temp_new_i64();
1239 TCGv_i64 t1 = tcg_temp_new_i64();
1240
1241 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1242 cpu_gpr[rB(ctx->opcode)]);
1243 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244
1245 tcg_gen_sari_i64(t0, t0, 63);
1246 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1247 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1248
1249 tcg_temp_free_i64(t0);
1250 tcg_temp_free_i64(t1);
1251
1252 if (unlikely(Rc(ctx->opcode) != 0)) {
1253 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1254 }
1255 }
1256 #endif
1257
1258 /* Common subf function */
1259 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1260 TCGv arg2, bool add_ca, bool compute_ca,
1261 bool compute_ov, bool compute_rc0)
1262 {
1263 TCGv t0 = ret;
1264
1265 if (compute_ca || compute_ov) {
1266 t0 = tcg_temp_new();
1267 }
1268
1269 if (compute_ca) {
1270 /* dest = ~arg1 + arg2 [+ ca]. */
1271 if (NARROW_MODE(ctx)) {
1272 /* Caution: a non-obvious corner case of the spec is that we
1273 must produce the *entire* 64-bit addition, but produce the
1274 carry into bit 32. */
1275 TCGv inv1 = tcg_temp_new();
1276 TCGv t1 = tcg_temp_new();
1277 tcg_gen_not_tl(inv1, arg1);
1278 if (add_ca) {
1279 tcg_gen_add_tl(t0, arg2, cpu_ca);
1280 } else {
1281 tcg_gen_addi_tl(t0, arg2, 1);
1282 }
1283 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1284 tcg_gen_add_tl(t0, t0, inv1);
1285 tcg_temp_free(inv1);
1286 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1287 tcg_temp_free(t1);
1288 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1289 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1290 } else if (add_ca) {
1291 TCGv zero, inv1 = tcg_temp_new();
1292 tcg_gen_not_tl(inv1, arg1);
1293 zero = tcg_const_tl(0);
1294 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1295 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1296 tcg_temp_free(zero);
1297 tcg_temp_free(inv1);
1298 } else {
1299 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1300 tcg_gen_sub_tl(t0, arg2, arg1);
1301 }
1302 } else if (add_ca) {
1303 /* Since we're ignoring carry-out, we can simplify the
1304 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1305 tcg_gen_sub_tl(t0, arg2, arg1);
1306 tcg_gen_add_tl(t0, t0, cpu_ca);
1307 tcg_gen_subi_tl(t0, t0, 1);
1308 } else {
1309 tcg_gen_sub_tl(t0, arg2, arg1);
1310 }
1311
1312 if (compute_ov) {
1313 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1314 }
1315 if (unlikely(compute_rc0)) {
1316 gen_set_Rc0(ctx, t0);
1317 }
1318
1319 if (!TCGV_EQUAL(t0, ret)) {
1320 tcg_gen_mov_tl(ret, t0);
1321 tcg_temp_free(t0);
1322 }
1323 }
1324 /* Sub functions with Two operands functions */
1325 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1326 static void glue(gen_, name)(DisasContext *ctx) \
1327 { \
1328 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1329 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1330 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1331 }
1332 /* Sub functions with one operand and one immediate */
1333 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1334 add_ca, compute_ca, compute_ov) \
1335 static void glue(gen_, name)(DisasContext *ctx) \
1336 { \
1337 TCGv t0 = tcg_const_tl(const_val); \
1338 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1339 cpu_gpr[rA(ctx->opcode)], t0, \
1340 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1341 tcg_temp_free(t0); \
1342 }
1343 /* subf subf. subfo subfo. */
1344 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1345 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1346 /* subfc subfc. subfco subfco. */
1347 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1348 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1349 /* subfe subfe. subfeo subfo. */
1350 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1351 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1352 /* subfme subfme. subfmeo subfmeo. */
1353 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1354 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1355 /* subfze subfze. subfzeo subfzeo.*/
1356 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1357 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1358
1359 /* subfic */
1360 static void gen_subfic(DisasContext *ctx)
1361 {
1362 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1363 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 c, 0, 1, 0, 0);
1365 tcg_temp_free(c);
1366 }
1367
1368 /* neg neg. nego nego. */
1369 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1370 {
1371 TCGv zero = tcg_const_tl(0);
1372 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1373 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1374 tcg_temp_free(zero);
1375 }
1376
1377 static void gen_neg(DisasContext *ctx)
1378 {
1379 gen_op_arith_neg(ctx, 0);
1380 }
1381
1382 static void gen_nego(DisasContext *ctx)
1383 {
1384 gen_op_arith_neg(ctx, 1);
1385 }
1386
1387 /*** Integer logical ***/
1388 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1389 static void glue(gen_, name)(DisasContext *ctx) \
1390 { \
1391 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1392 cpu_gpr[rB(ctx->opcode)]); \
1393 if (unlikely(Rc(ctx->opcode) != 0)) \
1394 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1395 }
1396
1397 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1398 static void glue(gen_, name)(DisasContext *ctx) \
1399 { \
1400 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1401 if (unlikely(Rc(ctx->opcode) != 0)) \
1402 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1403 }
1404
1405 /* and & and. */
1406 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1407 /* andc & andc. */
1408 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1409
1410 /* andi. */
1411 static void gen_andi_(DisasContext *ctx)
1412 {
1413 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1414 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1415 }
1416
1417 /* andis. */
1418 static void gen_andis_(DisasContext *ctx)
1419 {
1420 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1422 }
1423
1424 /* cntlzw */
1425 static void gen_cntlzw(DisasContext *ctx)
1426 {
1427 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1428 if (unlikely(Rc(ctx->opcode) != 0))
1429 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1430 }
1431 /* eqv & eqv. */
1432 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1433 /* extsb & extsb. */
1434 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1435 /* extsh & extsh. */
1436 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1437 /* nand & nand. */
1438 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1439 /* nor & nor. */
1440 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1441
1442 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1443 static void gen_pause(DisasContext *ctx)
1444 {
1445 TCGv_i32 t0 = tcg_const_i32(0);
1446 tcg_gen_st_i32(t0, cpu_env,
1447 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1448 tcg_temp_free_i32(t0);
1449
1450 /* Stop translation, this gives other CPUs a chance to run */
1451 gen_exception_err(ctx, EXCP_HLT, 1);
1452 }
1453 #endif /* defined(TARGET_PPC64) */
1454
1455 /* or & or. */
1456 static void gen_or(DisasContext *ctx)
1457 {
1458 int rs, ra, rb;
1459
1460 rs = rS(ctx->opcode);
1461 ra = rA(ctx->opcode);
1462 rb = rB(ctx->opcode);
1463 /* Optimisation for mr. ri case */
1464 if (rs != ra || rs != rb) {
1465 if (rs != rb)
1466 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1467 else
1468 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1469 if (unlikely(Rc(ctx->opcode) != 0))
1470 gen_set_Rc0(ctx, cpu_gpr[ra]);
1471 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1472 gen_set_Rc0(ctx, cpu_gpr[rs]);
1473 #if defined(TARGET_PPC64)
1474 } else {
1475 int prio = 0;
1476
1477 switch (rs) {
1478 case 1:
1479 /* Set process priority to low */
1480 prio = 2;
1481 break;
1482 case 6:
1483 /* Set process priority to medium-low */
1484 prio = 3;
1485 break;
1486 case 2:
1487 /* Set process priority to normal */
1488 prio = 4;
1489 break;
1490 #if !defined(CONFIG_USER_ONLY)
1491 case 31:
1492 if (!ctx->pr) {
1493 /* Set process priority to very low */
1494 prio = 1;
1495 }
1496 break;
1497 case 5:
1498 if (!ctx->pr) {
1499 /* Set process priority to medium-hight */
1500 prio = 5;
1501 }
1502 break;
1503 case 3:
1504 if (!ctx->pr) {
1505 /* Set process priority to high */
1506 prio = 6;
1507 }
1508 break;
1509 case 7:
1510 if (ctx->hv && !ctx->pr) {
1511 /* Set process priority to very high */
1512 prio = 7;
1513 }
1514 break;
1515 #endif
1516 default:
1517 /* nop */
1518 break;
1519 }
1520 if (prio) {
1521 TCGv t0 = tcg_temp_new();
1522 gen_load_spr(t0, SPR_PPR);
1523 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1524 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1525 gen_store_spr(SPR_PPR, t0);
1526 tcg_temp_free(t0);
1527 /* Pause us out of TCG otherwise spin loops with smt_low
1528 * eat too much CPU and the kernel hangs
1529 */
1530 #if !defined(CONFIG_USER_ONLY)
1531 gen_pause(ctx);
1532 #endif
1533 }
1534 #endif
1535 }
1536 }
1537 /* orc & orc. */
1538 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1539
1540 /* xor & xor. */
1541 static void gen_xor(DisasContext *ctx)
1542 {
1543 /* Optimisation for "set to zero" case */
1544 if (rS(ctx->opcode) != rB(ctx->opcode))
1545 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1546 else
1547 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1548 if (unlikely(Rc(ctx->opcode) != 0))
1549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1550 }
1551
1552 /* ori */
1553 static void gen_ori(DisasContext *ctx)
1554 {
1555 target_ulong uimm = UIMM(ctx->opcode);
1556
1557 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1558 return;
1559 }
1560 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1561 }
1562
1563 /* oris */
1564 static void gen_oris(DisasContext *ctx)
1565 {
1566 target_ulong uimm = UIMM(ctx->opcode);
1567
1568 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1569 /* NOP */
1570 return;
1571 }
1572 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1573 }
1574
1575 /* xori */
1576 static void gen_xori(DisasContext *ctx)
1577 {
1578 target_ulong uimm = UIMM(ctx->opcode);
1579
1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
1582 return;
1583 }
1584 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1585 }
1586
1587 /* xoris */
1588 static void gen_xoris(DisasContext *ctx)
1589 {
1590 target_ulong uimm = UIMM(ctx->opcode);
1591
1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
1595 }
1596 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1597 }
1598
1599 /* popcntb : PowerPC 2.03 specification */
1600 static void gen_popcntb(DisasContext *ctx)
1601 {
1602 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1603 }
1604
1605 static void gen_popcntw(DisasContext *ctx)
1606 {
1607 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1608 }
1609
1610 #if defined(TARGET_PPC64)
1611 /* popcntd: PowerPC 2.06 specification */
1612 static void gen_popcntd(DisasContext *ctx)
1613 {
1614 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1615 }
1616 #endif
1617
1618 /* prtyw: PowerPC 2.05 specification */
1619 static void gen_prtyw(DisasContext *ctx)
1620 {
1621 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1622 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1623 TCGv t0 = tcg_temp_new();
1624 tcg_gen_shri_tl(t0, rs, 16);
1625 tcg_gen_xor_tl(ra, rs, t0);
1626 tcg_gen_shri_tl(t0, ra, 8);
1627 tcg_gen_xor_tl(ra, ra, t0);
1628 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1629 tcg_temp_free(t0);
1630 }
1631
1632 #if defined(TARGET_PPC64)
1633 /* prtyd: PowerPC 2.05 specification */
1634 static void gen_prtyd(DisasContext *ctx)
1635 {
1636 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1637 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1638 TCGv t0 = tcg_temp_new();
1639 tcg_gen_shri_tl(t0, rs, 32);
1640 tcg_gen_xor_tl(ra, rs, t0);
1641 tcg_gen_shri_tl(t0, ra, 16);
1642 tcg_gen_xor_tl(ra, ra, t0);
1643 tcg_gen_shri_tl(t0, ra, 8);
1644 tcg_gen_xor_tl(ra, ra, t0);
1645 tcg_gen_andi_tl(ra, ra, 1);
1646 tcg_temp_free(t0);
1647 }
1648 #endif
1649
1650 #if defined(TARGET_PPC64)
1651 /* bpermd */
1652 static void gen_bpermd(DisasContext *ctx)
1653 {
1654 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1655 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1656 }
1657 #endif
1658
1659 #if defined(TARGET_PPC64)
1660 /* extsw & extsw. */
1661 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1662
1663 /* cntlzd */
1664 static void gen_cntlzd(DisasContext *ctx)
1665 {
1666 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1667 if (unlikely(Rc(ctx->opcode) != 0))
1668 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1669 }
1670 #endif
1671
1672 /*** Integer rotate ***/
1673
1674 /* rlwimi & rlwimi. */
1675 static void gen_rlwimi(DisasContext *ctx)
1676 {
1677 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1678 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1679 uint32_t sh = SH(ctx->opcode);
1680 uint32_t mb = MB(ctx->opcode);
1681 uint32_t me = ME(ctx->opcode);
1682
1683 if (sh == (31-me) && mb <= me) {
1684 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1685 } else {
1686 target_ulong mask;
1687 TCGv t1;
1688
1689 #if defined(TARGET_PPC64)
1690 mb += 32;
1691 me += 32;
1692 #endif
1693 mask = MASK(mb, me);
1694
1695 t1 = tcg_temp_new();
1696 if (mask <= 0xffffffffu) {
1697 TCGv_i32 t0 = tcg_temp_new_i32();
1698 tcg_gen_trunc_tl_i32(t0, t_rs);
1699 tcg_gen_rotli_i32(t0, t0, sh);
1700 tcg_gen_extu_i32_tl(t1, t0);
1701 tcg_temp_free_i32(t0);
1702 } else {
1703 #if defined(TARGET_PPC64)
1704 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1705 tcg_gen_rotli_i64(t1, t1, sh);
1706 #else
1707 g_assert_not_reached();
1708 #endif
1709 }
1710
1711 tcg_gen_andi_tl(t1, t1, mask);
1712 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1713 tcg_gen_or_tl(t_ra, t_ra, t1);
1714 tcg_temp_free(t1);
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0)) {
1717 gen_set_Rc0(ctx, t_ra);
1718 }
1719 }
1720
1721 /* rlwinm & rlwinm. */
1722 static void gen_rlwinm(DisasContext *ctx)
1723 {
1724 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1725 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1726 uint32_t sh = SH(ctx->opcode);
1727 uint32_t mb = MB(ctx->opcode);
1728 uint32_t me = ME(ctx->opcode);
1729
1730 if (mb == 0 && me == (31 - sh)) {
1731 tcg_gen_shli_tl(t_ra, t_rs, sh);
1732 tcg_gen_ext32u_tl(t_ra, t_ra);
1733 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1734 tcg_gen_ext32u_tl(t_ra, t_rs);
1735 tcg_gen_shri_tl(t_ra, t_ra, mb);
1736 } else {
1737 target_ulong mask;
1738 #if defined(TARGET_PPC64)
1739 mb += 32;
1740 me += 32;
1741 #endif
1742 mask = MASK(mb, me);
1743
1744 if (mask <= 0xffffffffu) {
1745 TCGv_i32 t0 = tcg_temp_new_i32();
1746 tcg_gen_trunc_tl_i32(t0, t_rs);
1747 tcg_gen_rotli_i32(t0, t0, sh);
1748 tcg_gen_andi_i32(t0, t0, mask);
1749 tcg_gen_extu_i32_tl(t_ra, t0);
1750 tcg_temp_free_i32(t0);
1751 } else {
1752 #if defined(TARGET_PPC64)
1753 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1754 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1755 tcg_gen_andi_i64(t_ra, t_ra, mask);
1756 #else
1757 g_assert_not_reached();
1758 #endif
1759 }
1760 }
1761 if (unlikely(Rc(ctx->opcode) != 0)) {
1762 gen_set_Rc0(ctx, t_ra);
1763 }
1764 }
1765
1766 /* rlwnm & rlwnm. */
1767 static void gen_rlwnm(DisasContext *ctx)
1768 {
1769 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1770 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1771 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1772 uint32_t mb = MB(ctx->opcode);
1773 uint32_t me = ME(ctx->opcode);
1774 target_ulong mask;
1775
1776 #if defined(TARGET_PPC64)
1777 mb += 32;
1778 me += 32;
1779 #endif
1780 mask = MASK(mb, me);
1781
1782 if (mask <= 0xffffffffu) {
1783 TCGv_i32 t0 = tcg_temp_new_i32();
1784 TCGv_i32 t1 = tcg_temp_new_i32();
1785 tcg_gen_trunc_tl_i32(t0, t_rb);
1786 tcg_gen_trunc_tl_i32(t1, t_rs);
1787 tcg_gen_andi_i32(t0, t0, 0x1f);
1788 tcg_gen_rotl_i32(t1, t1, t0);
1789 tcg_gen_extu_i32_tl(t_ra, t1);
1790 tcg_temp_free_i32(t0);
1791 tcg_temp_free_i32(t1);
1792 } else {
1793 #if defined(TARGET_PPC64)
1794 TCGv_i64 t0 = tcg_temp_new_i64();
1795 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1796 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1797 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1798 tcg_temp_free_i64(t0);
1799 #else
1800 g_assert_not_reached();
1801 #endif
1802 }
1803
1804 tcg_gen_andi_tl(t_ra, t_ra, mask);
1805
1806 if (unlikely(Rc(ctx->opcode) != 0)) {
1807 gen_set_Rc0(ctx, t_ra);
1808 }
1809 }
1810
1811 #if defined(TARGET_PPC64)
1812 #define GEN_PPC64_R2(name, opc1, opc2) \
1813 static void glue(gen_, name##0)(DisasContext *ctx) \
1814 { \
1815 gen_##name(ctx, 0); \
1816 } \
1817 \
1818 static void glue(gen_, name##1)(DisasContext *ctx) \
1819 { \
1820 gen_##name(ctx, 1); \
1821 }
1822 #define GEN_PPC64_R4(name, opc1, opc2) \
1823 static void glue(gen_, name##0)(DisasContext *ctx) \
1824 { \
1825 gen_##name(ctx, 0, 0); \
1826 } \
1827 \
1828 static void glue(gen_, name##1)(DisasContext *ctx) \
1829 { \
1830 gen_##name(ctx, 0, 1); \
1831 } \
1832 \
1833 static void glue(gen_, name##2)(DisasContext *ctx) \
1834 { \
1835 gen_##name(ctx, 1, 0); \
1836 } \
1837 \
1838 static void glue(gen_, name##3)(DisasContext *ctx) \
1839 { \
1840 gen_##name(ctx, 1, 1); \
1841 }
1842
1843 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1844 {
1845 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1846 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1847
1848 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1849 tcg_gen_shli_tl(t_ra, t_rs, sh);
1850 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1851 tcg_gen_shri_tl(t_ra, t_rs, mb);
1852 } else {
1853 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1854 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0)) {
1857 gen_set_Rc0(ctx, t_ra);
1858 }
1859 }
1860
1861 /* rldicl - rldicl. */
1862 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1863 {
1864 uint32_t sh, mb;
1865
1866 sh = SH(ctx->opcode) | (shn << 5);
1867 mb = MB(ctx->opcode) | (mbn << 5);
1868 gen_rldinm(ctx, mb, 63, sh);
1869 }
1870 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1871
1872 /* rldicr - rldicr. */
1873 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1874 {
1875 uint32_t sh, me;
1876
1877 sh = SH(ctx->opcode) | (shn << 5);
1878 me = MB(ctx->opcode) | (men << 5);
1879 gen_rldinm(ctx, 0, me, sh);
1880 }
1881 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1882
1883 /* rldic - rldic. */
1884 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1885 {
1886 uint32_t sh, mb;
1887
1888 sh = SH(ctx->opcode) | (shn << 5);
1889 mb = MB(ctx->opcode) | (mbn << 5);
1890 gen_rldinm(ctx, mb, 63 - sh, sh);
1891 }
1892 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1893
1894 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1895 {
1896 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1897 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1898 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1899 TCGv t0;
1900
1901 t0 = tcg_temp_new();
1902 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1903 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1904 tcg_temp_free(t0);
1905
1906 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1907 if (unlikely(Rc(ctx->opcode) != 0)) {
1908 gen_set_Rc0(ctx, t_ra);
1909 }
1910 }
1911
1912 /* rldcl - rldcl. */
1913 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1914 {
1915 uint32_t mb;
1916
1917 mb = MB(ctx->opcode) | (mbn << 5);
1918 gen_rldnm(ctx, mb, 63);
1919 }
1920 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1921
1922 /* rldcr - rldcr. */
1923 static inline void gen_rldcr(DisasContext *ctx, int men)
1924 {
1925 uint32_t me;
1926
1927 me = MB(ctx->opcode) | (men << 5);
1928 gen_rldnm(ctx, 0, me);
1929 }
1930 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1931
1932 /* rldimi - rldimi. */
1933 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1934 {
1935 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1936 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1937 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1938 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1939 uint32_t me = 63 - sh;
1940
1941 if (mb <= me) {
1942 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1943 } else {
1944 target_ulong mask = MASK(mb, me);
1945 TCGv t1 = tcg_temp_new();
1946
1947 tcg_gen_rotli_tl(t1, t_rs, sh);
1948 tcg_gen_andi_tl(t1, t1, mask);
1949 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1950 tcg_gen_or_tl(t_ra, t_ra, t1);
1951 tcg_temp_free(t1);
1952 }
1953 if (unlikely(Rc(ctx->opcode) != 0)) {
1954 gen_set_Rc0(ctx, t_ra);
1955 }
1956 }
1957 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1958 #endif
1959
1960 /*** Integer shift ***/
1961
1962 /* slw & slw. */
1963 static void gen_slw(DisasContext *ctx)
1964 {
1965 TCGv t0, t1;
1966
1967 t0 = tcg_temp_new();
1968 /* AND rS with a mask that is 0 when rB >= 0x20 */
1969 #if defined(TARGET_PPC64)
1970 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1971 tcg_gen_sari_tl(t0, t0, 0x3f);
1972 #else
1973 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1974 tcg_gen_sari_tl(t0, t0, 0x1f);
1975 #endif
1976 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1977 t1 = tcg_temp_new();
1978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1979 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1980 tcg_temp_free(t1);
1981 tcg_temp_free(t0);
1982 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1983 if (unlikely(Rc(ctx->opcode) != 0))
1984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1985 }
1986
1987 /* sraw & sraw. */
1988 static void gen_sraw(DisasContext *ctx)
1989 {
1990 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1991 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994 }
1995
1996 /* srawi & srawi. */
1997 static void gen_srawi(DisasContext *ctx)
1998 {
1999 int sh = SH(ctx->opcode);
2000 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2001 TCGv src = cpu_gpr[rS(ctx->opcode)];
2002 if (sh == 0) {
2003 tcg_gen_ext32s_tl(dst, src);
2004 tcg_gen_movi_tl(cpu_ca, 0);
2005 } else {
2006 TCGv t0;
2007 tcg_gen_ext32s_tl(dst, src);
2008 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, dst, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
2018 }
2019 }
2020
2021 /* srw & srw. */
2022 static void gen_srw(DisasContext *ctx)
2023 {
2024 TCGv t0, t1;
2025
2026 t0 = tcg_temp_new();
2027 /* AND rS with a mask that is 0 when rB >= 0x20 */
2028 #if defined(TARGET_PPC64)
2029 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2030 tcg_gen_sari_tl(t0, t0, 0x3f);
2031 #else
2032 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2033 tcg_gen_sari_tl(t0, t0, 0x1f);
2034 #endif
2035 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2036 tcg_gen_ext32u_tl(t0, t0);
2037 t1 = tcg_temp_new();
2038 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2039 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2040 tcg_temp_free(t1);
2041 tcg_temp_free(t0);
2042 if (unlikely(Rc(ctx->opcode) != 0))
2043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2044 }
2045
2046 #if defined(TARGET_PPC64)
2047 /* sld & sld. */
2048 static void gen_sld(DisasContext *ctx)
2049 {
2050 TCGv t0, t1;
2051
2052 t0 = tcg_temp_new();
2053 /* AND rS with a mask that is 0 when rB >= 0x40 */
2054 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2055 tcg_gen_sari_tl(t0, t0, 0x3f);
2056 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2057 t1 = tcg_temp_new();
2058 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2059 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2060 tcg_temp_free(t1);
2061 tcg_temp_free(t0);
2062 if (unlikely(Rc(ctx->opcode) != 0))
2063 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2064 }
2065
2066 /* srad & srad. */
2067 static void gen_srad(DisasContext *ctx)
2068 {
2069 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2070 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2071 if (unlikely(Rc(ctx->opcode) != 0))
2072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2073 }
2074 /* sradi & sradi. */
2075 static inline void gen_sradi(DisasContext *ctx, int n)
2076 {
2077 int sh = SH(ctx->opcode) + (n << 5);
2078 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2079 TCGv src = cpu_gpr[rS(ctx->opcode)];
2080 if (sh == 0) {
2081 tcg_gen_mov_tl(dst, src);
2082 tcg_gen_movi_tl(cpu_ca, 0);
2083 } else {
2084 TCGv t0;
2085 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2086 t0 = tcg_temp_new();
2087 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2088 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2089 tcg_temp_free(t0);
2090 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2091 tcg_gen_sari_tl(dst, src, sh);
2092 }
2093 if (unlikely(Rc(ctx->opcode) != 0)) {
2094 gen_set_Rc0(ctx, dst);
2095 }
2096 }
2097
2098 static void gen_sradi0(DisasContext *ctx)
2099 {
2100 gen_sradi(ctx, 0);
2101 }
2102
2103 static void gen_sradi1(DisasContext *ctx)
2104 {
2105 gen_sradi(ctx, 1);
2106 }
2107
2108 /* srd & srd. */
2109 static void gen_srd(DisasContext *ctx)
2110 {
2111 TCGv t0, t1;
2112
2113 t0 = tcg_temp_new();
2114 /* AND rS with a mask that is 0 when rB >= 0x40 */
2115 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2116 tcg_gen_sari_tl(t0, t0, 0x3f);
2117 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2118 t1 = tcg_temp_new();
2119 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2120 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2121 tcg_temp_free(t1);
2122 tcg_temp_free(t0);
2123 if (unlikely(Rc(ctx->opcode) != 0))
2124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2125 }
2126 #endif
2127
2128 #if defined(TARGET_PPC64)
2129 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2130 {
2131 TCGv_i32 tmp = tcg_temp_new_i32();
2132 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2133 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2134 tcg_temp_free_i32(tmp);
2135 }
2136 #else
2137 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2138 {
2139 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2140 }
2141 #endif
2142
2143 /*** Floating-Point arithmetic ***/
2144 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2145 static void gen_f##name(DisasContext *ctx) \
2146 { \
2147 if (unlikely(!ctx->fpu_enabled)) { \
2148 gen_exception(ctx, POWERPC_EXCP_FPU); \
2149 return; \
2150 } \
2151 /* NIP cannot be restored if the memory exception comes from an helper */ \
2152 gen_update_nip(ctx, ctx->nip - 4); \
2153 gen_reset_fpstatus(); \
2154 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2155 cpu_fpr[rA(ctx->opcode)], \
2156 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2157 if (isfloat) { \
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2159 cpu_fpr[rD(ctx->opcode)]); \
2160 } \
2161 if (set_fprf) { \
2162 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2163 } \
2164 if (unlikely(Rc(ctx->opcode) != 0)) { \
2165 gen_set_cr1_from_fpscr(ctx); \
2166 } \
2167 }
2168
2169 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2170 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2171 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2172
2173 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2174 static void gen_f##name(DisasContext *ctx) \
2175 { \
2176 if (unlikely(!ctx->fpu_enabled)) { \
2177 gen_exception(ctx, POWERPC_EXCP_FPU); \
2178 return; \
2179 } \
2180 /* NIP cannot be restored if the memory exception comes from an helper */ \
2181 gen_update_nip(ctx, ctx->nip - 4); \
2182 gen_reset_fpstatus(); \
2183 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2184 cpu_fpr[rA(ctx->opcode)], \
2185 cpu_fpr[rB(ctx->opcode)]); \
2186 if (isfloat) { \
2187 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2188 cpu_fpr[rD(ctx->opcode)]); \
2189 } \
2190 if (set_fprf) { \
2191 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2192 } \
2193 if (unlikely(Rc(ctx->opcode) != 0)) { \
2194 gen_set_cr1_from_fpscr(ctx); \
2195 } \
2196 }
2197 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2198 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2199 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2200
2201 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2202 static void gen_f##name(DisasContext *ctx) \
2203 { \
2204 if (unlikely(!ctx->fpu_enabled)) { \
2205 gen_exception(ctx, POWERPC_EXCP_FPU); \
2206 return; \
2207 } \
2208 /* NIP cannot be restored if the memory exception comes from an helper */ \
2209 gen_update_nip(ctx, ctx->nip - 4); \
2210 gen_reset_fpstatus(); \
2211 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2212 cpu_fpr[rA(ctx->opcode)], \
2213 cpu_fpr[rC(ctx->opcode)]); \
2214 if (isfloat) { \
2215 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2216 cpu_fpr[rD(ctx->opcode)]); \
2217 } \
2218 if (set_fprf) { \
2219 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2220 } \
2221 if (unlikely(Rc(ctx->opcode) != 0)) { \
2222 gen_set_cr1_from_fpscr(ctx); \
2223 } \
2224 }
2225 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2226 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2227 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2228
2229 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2230 static void gen_f##name(DisasContext *ctx) \
2231 { \
2232 if (unlikely(!ctx->fpu_enabled)) { \
2233 gen_exception(ctx, POWERPC_EXCP_FPU); \
2234 return; \
2235 } \
2236 /* NIP cannot be restored if the memory exception comes from an helper */ \
2237 gen_update_nip(ctx, ctx->nip - 4); \
2238 gen_reset_fpstatus(); \
2239 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2240 cpu_fpr[rB(ctx->opcode)]); \
2241 if (set_fprf) { \
2242 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2243 } \
2244 if (unlikely(Rc(ctx->opcode) != 0)) { \
2245 gen_set_cr1_from_fpscr(ctx); \
2246 } \
2247 }
2248
2249 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2250 static void gen_f##name(DisasContext *ctx) \
2251 { \
2252 if (unlikely(!ctx->fpu_enabled)) { \
2253 gen_exception(ctx, POWERPC_EXCP_FPU); \
2254 return; \
2255 } \
2256 /* NIP cannot be restored if the memory exception comes from an helper */ \
2257 gen_update_nip(ctx, ctx->nip - 4); \
2258 gen_reset_fpstatus(); \
2259 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2260 cpu_fpr[rB(ctx->opcode)]); \
2261 if (set_fprf) { \
2262 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2263 } \
2264 if (unlikely(Rc(ctx->opcode) != 0)) { \
2265 gen_set_cr1_from_fpscr(ctx); \
2266 } \
2267 }
2268
2269 /* fadd - fadds */
2270 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2271 /* fdiv - fdivs */
2272 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2273 /* fmul - fmuls */
2274 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2275
2276 /* fre */
2277 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2278
2279 /* fres */
2280 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2281
2282 /* frsqrte */
2283 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2284
2285 /* frsqrtes */
2286 static void gen_frsqrtes(DisasContext *ctx)
2287 {
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
2294 gen_reset_fpstatus();
2295 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2296 cpu_fpr[rB(ctx->opcode)]);
2297 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2298 cpu_fpr[rD(ctx->opcode)]);
2299 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2300 if (unlikely(Rc(ctx->opcode) != 0)) {
2301 gen_set_cr1_from_fpscr(ctx);
2302 }
2303 }
2304
2305 /* fsel */
2306 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2307 /* fsub - fsubs */
2308 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2309 /* Optional: */
2310
2311 /* fsqrt */
2312 static void gen_fsqrt(DisasContext *ctx)
2313 {
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 gen_exception(ctx, POWERPC_EXCP_FPU);
2316 return;
2317 }
2318 /* NIP cannot be restored if the memory exception comes from an helper */
2319 gen_update_nip(ctx, ctx->nip - 4);
2320 gen_reset_fpstatus();
2321 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2322 cpu_fpr[rB(ctx->opcode)]);
2323 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2324 if (unlikely(Rc(ctx->opcode) != 0)) {
2325 gen_set_cr1_from_fpscr(ctx);
2326 }
2327 }
2328
2329 static void gen_fsqrts(DisasContext *ctx)
2330 {
2331 if (unlikely(!ctx->fpu_enabled)) {
2332 gen_exception(ctx, POWERPC_EXCP_FPU);
2333 return;
2334 }
2335 /* NIP cannot be restored if the memory exception comes from an helper */
2336 gen_update_nip(ctx, ctx->nip - 4);
2337 gen_reset_fpstatus();
2338 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2339 cpu_fpr[rB(ctx->opcode)]);
2340 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2341 cpu_fpr[rD(ctx->opcode)]);
2342 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2343 if (unlikely(Rc(ctx->opcode) != 0)) {
2344 gen_set_cr1_from_fpscr(ctx);
2345 }
2346 }
2347
2348 /*** Floating-Point multiply-and-add ***/
2349 /* fmadd - fmadds */
2350 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2351 /* fmsub - fmsubs */
2352 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2353 /* fnmadd - fnmadds */
2354 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2355 /* fnmsub - fnmsubs */
2356 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2357
2358 /*** Floating-Point round & convert ***/
2359 /* fctiw */
2360 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2361 /* fctiwu */
2362 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2363 /* fctiwz */
2364 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2365 /* fctiwuz */
2366 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2367 /* frsp */
2368 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2369 /* fcfid */
2370 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2371 /* fcfids */
2372 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2373 /* fcfidu */
2374 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2375 /* fcfidus */
2376 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2377 /* fctid */
2378 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2379 /* fctidu */
2380 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2381 /* fctidz */
2382 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2383 /* fctidu */
2384 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2385
2386 /* frin */
2387 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2388 /* friz */
2389 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2390 /* frip */
2391 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2392 /* frim */
2393 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2394
2395 static void gen_ftdiv(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2402 cpu_fpr[rB(ctx->opcode)]);
2403 }
2404
2405 static void gen_ftsqrt(DisasContext *ctx)
2406 {
2407 if (unlikely(!ctx->fpu_enabled)) {
2408 gen_exception(ctx, POWERPC_EXCP_FPU);
2409 return;
2410 }
2411 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2412 }
2413
2414
2415
2416 /*** Floating-Point compare ***/
2417
2418 /* fcmpo */
2419 static void gen_fcmpo(DisasContext *ctx)
2420 {
2421 TCGv_i32 crf;
2422 if (unlikely(!ctx->fpu_enabled)) {
2423 gen_exception(ctx, POWERPC_EXCP_FPU);
2424 return;
2425 }
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx, ctx->nip - 4);
2428 gen_reset_fpstatus();
2429 crf = tcg_const_i32(crfD(ctx->opcode));
2430 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2431 cpu_fpr[rB(ctx->opcode)], crf);
2432 tcg_temp_free_i32(crf);
2433 gen_helper_float_check_status(cpu_env);
2434 }
2435
2436 /* fcmpu */
2437 static void gen_fcmpu(DisasContext *ctx)
2438 {
2439 TCGv_i32 crf;
2440 if (unlikely(!ctx->fpu_enabled)) {
2441 gen_exception(ctx, POWERPC_EXCP_FPU);
2442 return;
2443 }
2444 /* NIP cannot be restored if the memory exception comes from an helper */
2445 gen_update_nip(ctx, ctx->nip - 4);
2446 gen_reset_fpstatus();
2447 crf = tcg_const_i32(crfD(ctx->opcode));
2448 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2449 cpu_fpr[rB(ctx->opcode)], crf);
2450 tcg_temp_free_i32(crf);
2451 gen_helper_float_check_status(cpu_env);
2452 }
2453
2454 /*** Floating-point move ***/
2455 /* fabs */
2456 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2457 static void gen_fabs(DisasContext *ctx)
2458 {
2459 if (unlikely(!ctx->fpu_enabled)) {
2460 gen_exception(ctx, POWERPC_EXCP_FPU);
2461 return;
2462 }
2463 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2464 ~(1ULL << 63));
2465 if (unlikely(Rc(ctx->opcode))) {
2466 gen_set_cr1_from_fpscr(ctx);
2467 }
2468 }
2469
2470 /* fmr - fmr. */
2471 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2472 static void gen_fmr(DisasContext *ctx)
2473 {
2474 if (unlikely(!ctx->fpu_enabled)) {
2475 gen_exception(ctx, POWERPC_EXCP_FPU);
2476 return;
2477 }
2478 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2479 if (unlikely(Rc(ctx->opcode))) {
2480 gen_set_cr1_from_fpscr(ctx);
2481 }
2482 }
2483
2484 /* fnabs */
2485 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2486 static void gen_fnabs(DisasContext *ctx)
2487 {
2488 if (unlikely(!ctx->fpu_enabled)) {
2489 gen_exception(ctx, POWERPC_EXCP_FPU);
2490 return;
2491 }
2492 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2493 1ULL << 63);
2494 if (unlikely(Rc(ctx->opcode))) {
2495 gen_set_cr1_from_fpscr(ctx);
2496 }
2497 }
2498
2499 /* fneg */
2500 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2501 static void gen_fneg(DisasContext *ctx)
2502 {
2503 if (unlikely(!ctx->fpu_enabled)) {
2504 gen_exception(ctx, POWERPC_EXCP_FPU);
2505 return;
2506 }
2507 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2508 1ULL << 63);
2509 if (unlikely(Rc(ctx->opcode))) {
2510 gen_set_cr1_from_fpscr(ctx);
2511 }
2512 }
2513
2514 /* fcpsgn: PowerPC 2.05 specification */
2515 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2516 static void gen_fcpsgn(DisasContext *ctx)
2517 {
2518 if (unlikely(!ctx->fpu_enabled)) {
2519 gen_exception(ctx, POWERPC_EXCP_FPU);
2520 return;
2521 }
2522 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2523 cpu_fpr[rB(ctx->opcode)], 0, 63);
2524 if (unlikely(Rc(ctx->opcode))) {
2525 gen_set_cr1_from_fpscr(ctx);
2526 }
2527 }
2528
2529 static void gen_fmrgew(DisasContext *ctx)
2530 {
2531 TCGv_i64 b0;
2532 if (unlikely(!ctx->fpu_enabled)) {
2533 gen_exception(ctx, POWERPC_EXCP_FPU);
2534 return;
2535 }
2536 b0 = tcg_temp_new_i64();
2537 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2538 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2539 b0, 0, 32);
2540 tcg_temp_free_i64(b0);
2541 }
2542
2543 static void gen_fmrgow(DisasContext *ctx)
2544 {
2545 if (unlikely(!ctx->fpu_enabled)) {
2546 gen_exception(ctx, POWERPC_EXCP_FPU);
2547 return;
2548 }
2549 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2550 cpu_fpr[rB(ctx->opcode)],
2551 cpu_fpr[rA(ctx->opcode)],
2552 32, 32);
2553 }
2554
2555 /*** Floating-Point status & ctrl register ***/
2556
2557 /* mcrfs */
2558 static void gen_mcrfs(DisasContext *ctx)
2559 {
2560 TCGv tmp = tcg_temp_new();
2561 TCGv_i32 tmask;
2562 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2563 int bfa;
2564 int nibble;
2565 int shift;
2566
2567 if (unlikely(!ctx->fpu_enabled)) {
2568 gen_exception(ctx, POWERPC_EXCP_FPU);
2569 return;
2570 }
2571 bfa = crfS(ctx->opcode);
2572 nibble = 7 - bfa;
2573 shift = 4 * nibble;
2574 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2575 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2576 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2577 tcg_temp_free(tmp);
2578 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2579 /* Only the exception bits (including FX) should be cleared if read */
2580 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2581 /* FEX and VX need to be updated, so don't set fpscr directly */
2582 tmask = tcg_const_i32(1 << nibble);
2583 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2584 tcg_temp_free_i32(tmask);
2585 tcg_temp_free_i64(tnew_fpscr);
2586 }
2587
2588 /* mffs */
2589 static void gen_mffs(DisasContext *ctx)
2590 {
2591 if (unlikely(!ctx->fpu_enabled)) {
2592 gen_exception(ctx, POWERPC_EXCP_FPU);
2593 return;
2594 }
2595 gen_reset_fpstatus();
2596 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2597 if (unlikely(Rc(ctx->opcode))) {
2598 gen_set_cr1_from_fpscr(ctx);
2599 }
2600 }
2601
2602 /* mtfsb0 */
2603 static void gen_mtfsb0(DisasContext *ctx)
2604 {
2605 uint8_t crb;
2606
2607 if (unlikely(!ctx->fpu_enabled)) {
2608 gen_exception(ctx, POWERPC_EXCP_FPU);
2609 return;
2610 }
2611 crb = 31 - crbD(ctx->opcode);
2612 gen_reset_fpstatus();
2613 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2614 TCGv_i32 t0;
2615 /* NIP cannot be restored if the memory exception comes from an helper */
2616 gen_update_nip(ctx, ctx->nip - 4);
2617 t0 = tcg_const_i32(crb);
2618 gen_helper_fpscr_clrbit(cpu_env, t0);
2619 tcg_temp_free_i32(t0);
2620 }
2621 if (unlikely(Rc(ctx->opcode) != 0)) {
2622 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2623 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2624 }
2625 }
2626
2627 /* mtfsb1 */
2628 static void gen_mtfsb1(DisasContext *ctx)
2629 {
2630 uint8_t crb;
2631
2632 if (unlikely(!ctx->fpu_enabled)) {
2633 gen_exception(ctx, POWERPC_EXCP_FPU);
2634 return;
2635 }
2636 crb = 31 - crbD(ctx->opcode);
2637 gen_reset_fpstatus();
2638 /* XXX: we pretend we can only do IEEE floating-point computations */
2639 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2640 TCGv_i32 t0;
2641 /* NIP cannot be restored if the memory exception comes from an helper */
2642 gen_update_nip(ctx, ctx->nip - 4);
2643 t0 = tcg_const_i32(crb);
2644 gen_helper_fpscr_setbit(cpu_env, t0);
2645 tcg_temp_free_i32(t0);
2646 }
2647 if (unlikely(Rc(ctx->opcode) != 0)) {
2648 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2649 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2650 }
2651 /* We can raise a differed exception */
2652 gen_helper_float_check_status(cpu_env);
2653 }
2654
2655 /* mtfsf */
2656 static void gen_mtfsf(DisasContext *ctx)
2657 {
2658 TCGv_i32 t0;
2659 int flm, l, w;
2660
2661 if (unlikely(!ctx->fpu_enabled)) {
2662 gen_exception(ctx, POWERPC_EXCP_FPU);
2663 return;
2664 }
2665 flm = FPFLM(ctx->opcode);
2666 l = FPL(ctx->opcode);
2667 w = FPW(ctx->opcode);
2668 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2669 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2670 return;
2671 }
2672 /* NIP cannot be restored if the memory exception comes from an helper */
2673 gen_update_nip(ctx, ctx->nip - 4);
2674 gen_reset_fpstatus();
2675 if (l) {
2676 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2677 } else {
2678 t0 = tcg_const_i32(flm << (w * 8));
2679 }
2680 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2681 tcg_temp_free_i32(t0);
2682 if (unlikely(Rc(ctx->opcode) != 0)) {
2683 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2684 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2685 }
2686 /* We can raise a differed exception */
2687 gen_helper_float_check_status(cpu_env);
2688 }
2689
2690 /* mtfsfi */
2691 static void gen_mtfsfi(DisasContext *ctx)
2692 {
2693 int bf, sh, w;
2694 TCGv_i64 t0;
2695 TCGv_i32 t1;
2696
2697 if (unlikely(!ctx->fpu_enabled)) {
2698 gen_exception(ctx, POWERPC_EXCP_FPU);
2699 return;
2700 }
2701 w = FPW(ctx->opcode);
2702 bf = FPBF(ctx->opcode);
2703 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2705 return;
2706 }
2707 sh = (8 * w) + 7 - bf;
2708 /* NIP cannot be restored if the memory exception comes from an helper */
2709 gen_update_nip(ctx, ctx->nip - 4);
2710 gen_reset_fpstatus();
2711 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2712 t1 = tcg_const_i32(1 << sh);
2713 gen_helper_store_fpscr(cpu_env, t0, t1);
2714 tcg_temp_free_i64(t0);
2715 tcg_temp_free_i32(t1);
2716 if (unlikely(Rc(ctx->opcode) != 0)) {
2717 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2718 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2719 }
2720 /* We can raise a differed exception */
2721 gen_helper_float_check_status(cpu_env);
2722 }
2723
2724 /*** Addressing modes ***/
2725 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2726 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2727 target_long maskl)
2728 {
2729 target_long simm = SIMM(ctx->opcode);
2730
2731 simm &= ~maskl;
2732 if (rA(ctx->opcode) == 0) {
2733 if (NARROW_MODE(ctx)) {
2734 simm = (uint32_t)simm;
2735 }
2736 tcg_gen_movi_tl(EA, simm);
2737 } else if (likely(simm != 0)) {
2738 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2739 if (NARROW_MODE(ctx)) {
2740 tcg_gen_ext32u_tl(EA, EA);
2741 }
2742 } else {
2743 if (NARROW_MODE(ctx)) {
2744 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2745 } else {
2746 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2747 }
2748 }
2749 }
2750
2751 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2752 {
2753 if (rA(ctx->opcode) == 0) {
2754 if (NARROW_MODE(ctx)) {
2755 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2756 } else {
2757 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2758 }
2759 } else {
2760 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2761 if (NARROW_MODE(ctx)) {
2762 tcg_gen_ext32u_tl(EA, EA);
2763 }
2764 }
2765 }
2766
2767 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2768 {
2769 if (rA(ctx->opcode) == 0) {
2770 tcg_gen_movi_tl(EA, 0);
2771 } else if (NARROW_MODE(ctx)) {
2772 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2773 } else {
2774 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2775 }
2776 }
2777
2778 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2779 target_long val)
2780 {
2781 tcg_gen_addi_tl(ret, arg1, val);
2782 if (NARROW_MODE(ctx)) {
2783 tcg_gen_ext32u_tl(ret, ret);
2784 }
2785 }
2786
2787 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2788 {
2789 TCGLabel *l1 = gen_new_label();
2790 TCGv t0 = tcg_temp_new();
2791 TCGv_i32 t1, t2;
2792 /* NIP cannot be restored if the memory exception comes from an helper */
2793 gen_update_nip(ctx, ctx->nip - 4);
2794 tcg_gen_andi_tl(t0, EA, mask);
2795 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2796 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2797 t2 = tcg_const_i32(0);
2798 gen_helper_raise_exception_err(cpu_env, t1, t2);
2799 tcg_temp_free_i32(t1);
2800 tcg_temp_free_i32(t2);
2801 gen_set_label(l1);
2802 tcg_temp_free(t0);
2803 }
2804
2805 /*** Integer load ***/
2806 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2807 {
2808 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2809 }
2810
2811 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2812 {
2813 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2814 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2815 }
2816
2817 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2818 {
2819 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2820 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2821 }
2822
2823 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2824 {
2825 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2826 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2827 }
2828
2829 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2830 {
2831 TCGv tmp = tcg_temp_new();
2832 gen_qemu_ld32u(ctx, tmp, addr);
2833 tcg_gen_extu_tl_i64(val, tmp);
2834 tcg_temp_free(tmp);
2835 }
2836
2837 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838 {
2839 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2840 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2841 }
2842
2843 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2844 {
2845 TCGv tmp = tcg_temp_new();
2846 gen_qemu_ld32s(ctx, tmp, addr);
2847 tcg_gen_ext_tl_i64(val, tmp);
2848 tcg_temp_free(tmp);
2849 }
2850
2851 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2852 {
2853 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2854 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2855 }
2856
2857 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2858 {
2859 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2860 }
2861
2862 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2863 {
2864 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2865 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2866 }
2867
2868 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2869 {
2870 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2871 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2872 }
2873
2874 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2875 {
2876 TCGv tmp = tcg_temp_new();
2877 tcg_gen_trunc_i64_tl(tmp, val);
2878 gen_qemu_st32(ctx, tmp, addr);
2879 tcg_temp_free(tmp);
2880 }
2881
2882 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2883 {
2884 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2885 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2886 }
2887
2888 #define GEN_LD(name, ldop, opc, type) \
2889 static void glue(gen_, name)(DisasContext *ctx) \
2890 { \
2891 TCGv EA; \
2892 gen_set_access_type(ctx, ACCESS_INT); \
2893 EA = tcg_temp_new(); \
2894 gen_addr_imm_index(ctx, EA, 0); \
2895 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2896 tcg_temp_free(EA); \
2897 }
2898
2899 #define GEN_LDU(name, ldop, opc, type) \
2900 static void glue(gen_, name##u)(DisasContext *ctx) \
2901 { \
2902 TCGv EA; \
2903 if (unlikely(rA(ctx->opcode) == 0 || \
2904 rA(ctx->opcode) == rD(ctx->opcode))) { \
2905 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2906 return; \
2907 } \
2908 gen_set_access_type(ctx, ACCESS_INT); \
2909 EA = tcg_temp_new(); \
2910 if (type == PPC_64B) \
2911 gen_addr_imm_index(ctx, EA, 0x03); \
2912 else \
2913 gen_addr_imm_index(ctx, EA, 0); \
2914 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2915 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2916 tcg_temp_free(EA); \
2917 }
2918
2919 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2920 static void glue(gen_, name##ux)(DisasContext *ctx) \
2921 { \
2922 TCGv EA; \
2923 if (unlikely(rA(ctx->opcode) == 0 || \
2924 rA(ctx->opcode) == rD(ctx->opcode))) { \
2925 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2926 return; \
2927 } \
2928 gen_set_access_type(ctx, ACCESS_INT); \
2929 EA = tcg_temp_new(); \
2930 gen_addr_reg_index(ctx, EA); \
2931 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2932 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2933 tcg_temp_free(EA); \
2934 }
2935
2936 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2937 static void glue(gen_, name##x)(DisasContext *ctx) \
2938 { \
2939 TCGv EA; \
2940 chk; \
2941 gen_set_access_type(ctx, ACCESS_INT); \
2942 EA = tcg_temp_new(); \
2943 gen_addr_reg_index(ctx, EA); \
2944 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2945 tcg_temp_free(EA); \
2946 }
2947
2948 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2949 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2950
2951 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2952 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2953
2954 #define GEN_LDS(name, ldop, op, type) \
2955 GEN_LD(name, ldop, op | 0x20, type); \
2956 GEN_LDU(name, ldop, op | 0x21, type); \
2957 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2958 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2959
2960 /* lbz lbzu lbzux lbzx */
2961 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2962 /* lha lhau lhaux lhax */
2963 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2964 /* lhz lhzu lhzux lhzx */
2965 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2966 /* lwz lwzu lwzux lwzx */
2967 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2968 #if defined(TARGET_PPC64)
2969 /* lwaux */
2970 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2971 /* lwax */
2972 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2973 /* ldux */
2974 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2975 /* ldx */
2976 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2977
2978 /* CI load/store variants */
2979 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2980 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2981 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2982 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2983
2984 static void gen_ld(DisasContext *ctx)
2985 {
2986 TCGv EA;
2987 if (Rc(ctx->opcode)) {
2988 if (unlikely(rA(ctx->opcode) == 0 ||
2989 rA(ctx->opcode) == rD(ctx->opcode))) {
2990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2991 return;
2992 }
2993 }
2994 gen_set_access_type(ctx, ACCESS_INT);
2995 EA = tcg_temp_new();
2996 gen_addr_imm_index(ctx, EA, 0x03);
2997 if (ctx->opcode & 0x02) {
2998 /* lwa (lwau is undefined) */
2999 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3000 } else {
3001 /* ld - ldu */
3002 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3003 }
3004 if (Rc(ctx->opcode))
3005 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3006 tcg_temp_free(EA);
3007 }
3008
3009 /* lq */
3010 static void gen_lq(DisasContext *ctx)
3011 {
3012 int ra, rd;
3013 TCGv EA;
3014
3015 /* lq is a legal user mode instruction starting in ISA 2.07 */
3016 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3017 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3018
3019 if (!legal_in_user_mode && ctx->pr) {
3020 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3021 return;
3022 }
3023
3024 if (!le_is_supported && ctx->le_mode) {
3025 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3026 return;
3027 }
3028
3029 ra = rA(ctx->opcode);
3030 rd = rD(ctx->opcode);
3031 if (unlikely((rd & 1) || rd == ra)) {
3032 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3033 return;
3034 }
3035
3036 gen_set_access_type(ctx, ACCESS_INT);
3037 EA = tcg_temp_new();
3038 gen_addr_imm_index(ctx, EA, 0x0F);
3039
3040 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3041 64-bit byteswap already. */
3042 if (unlikely(ctx->le_mode)) {
3043 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3044 gen_addr_add(ctx, EA, EA, 8);
3045 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3046 } else {
3047 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3048 gen_addr_add(ctx, EA, EA, 8);
3049 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3050 }
3051 tcg_temp_free(EA);
3052 }
3053 #endif
3054
3055 /*** Integer store ***/
3056 #define GEN_ST(name, stop, opc, type) \
3057 static void glue(gen_, name)(DisasContext *ctx) \
3058 { \
3059 TCGv EA; \
3060 gen_set_access_type(ctx, ACCESS_INT); \
3061 EA = tcg_temp_new(); \
3062 gen_addr_imm_index(ctx, EA, 0); \
3063 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3064 tcg_temp_free(EA); \
3065 }
3066
3067 #define GEN_STU(name, stop, opc, type) \
3068 static void glue(gen_, stop##u)(DisasContext *ctx) \
3069 { \
3070 TCGv EA; \
3071 if (unlikely(rA(ctx->opcode) == 0)) { \
3072 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3073 return; \
3074 } \
3075 gen_set_access_type(ctx, ACCESS_INT); \
3076 EA = tcg_temp_new(); \
3077 if (type == PPC_64B) \
3078 gen_addr_imm_index(ctx, EA, 0x03); \
3079 else \
3080 gen_addr_imm_index(ctx, EA, 0); \
3081 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3082 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3083 tcg_temp_free(EA); \
3084 }
3085
3086 #define GEN_STUX(name, stop, opc2, opc3, type) \
3087 static void glue(gen_, name##ux)(DisasContext *ctx) \
3088 { \
3089 TCGv EA; \
3090 if (unlikely(rA(ctx->opcode) == 0)) { \
3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3092 return; \
3093 } \
3094 gen_set_access_type(ctx, ACCESS_INT); \
3095 EA = tcg_temp_new(); \
3096 gen_addr_reg_index(ctx, EA); \
3097 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3098 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3099 tcg_temp_free(EA); \
3100 }
3101
3102 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3103 static void glue(gen_, name##x)(DisasContext *ctx) \
3104 { \
3105 TCGv EA; \
3106 chk; \
3107 gen_set_access_type(ctx, ACCESS_INT); \
3108 EA = tcg_temp_new(); \
3109 gen_addr_reg_index(ctx, EA); \
3110 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3111 tcg_temp_free(EA); \
3112 }
3113 #define GEN_STX(name, stop, opc2, opc3, type) \
3114 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3115
3116 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3117 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3118
3119 #define GEN_STS(name, stop, op, type) \
3120 GEN_ST(name, stop, op | 0x20, type); \
3121 GEN_STU(name, stop, op | 0x21, type); \
3122 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3123 GEN_STX(name, stop, 0x17, op | 0x00, type)
3124
3125 /* stb stbu stbux stbx */
3126 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3127 /* sth sthu sthux sthx */
3128 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3129 /* stw stwu stwux stwx */
3130 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3131 #if defined(TARGET_PPC64)
3132 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3133 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3134 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
3135 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3136 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3137 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3138
3139 static void gen_std(DisasContext *ctx)
3140 {
3141 int rs;
3142 TCGv EA;
3143
3144 rs = rS(ctx->opcode);
3145 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3146 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3147 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3148
3149 if (!(ctx->insns_flags & PPC_64BX)) {
3150 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3151 }
3152
3153 if (!legal_in_user_mode && ctx->pr) {
3154 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3155 return;
3156 }
3157
3158 if (!le_is_supported && ctx->le_mode) {
3159 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3160 return;
3161 }
3162
3163 if (unlikely(rs & 1)) {
3164 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3165 return;
3166 }
3167 gen_set_access_type(ctx, ACCESS_INT);
3168 EA = tcg_temp_new();
3169 gen_addr_imm_index(ctx, EA, 0x03);
3170
3171 /* We only need to swap high and low halves. gen_qemu_st64 does
3172 necessary 64-bit byteswap already. */
3173 if (unlikely(ctx->le_mode)) {
3174 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3175 gen_addr_add(ctx, EA, EA, 8);
3176 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3177 } else {
3178 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3179 gen_addr_add(ctx, EA, EA, 8);
3180 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3181 }
3182 tcg_temp_free(EA);
3183 } else {
3184 /* std / stdu*/
3185 if (Rc(ctx->opcode)) {
3186 if (unlikely(rA(ctx->opcode) == 0)) {
3187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3188 return;
3189 }
3190 }
3191 gen_set_access_type(ctx, ACCESS_INT);
3192 EA = tcg_temp_new();
3193 gen_addr_imm_index(ctx, EA, 0x03);
3194 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3195 if (Rc(ctx->opcode))
3196 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3197 tcg_temp_free(EA);
3198 }
3199 }
3200 #endif
3201 /*** Integer load and store with byte reverse ***/
3202
3203 /* lhbrx */
3204 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3205 {
3206 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3207 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3208 }
3209 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3210
3211 /* lwbrx */
3212 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3213 {
3214 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3215 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3216 }
3217 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3218
3219 #if defined(TARGET_PPC64)
3220 /* ldbrx */
3221 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3222 {
3223 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3224 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3225 }
3226 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3227 #endif /* TARGET_PPC64 */
3228
3229 /* sthbrx */
3230 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3231 {
3232 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3233 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3234 }
3235 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3236
3237 /* stwbrx */
3238 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3239 {
3240 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3241 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3242 }
3243 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3244
3245 #if defined(TARGET_PPC64)
3246 /* stdbrx */
3247 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3248 {
3249 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3250 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3251 }
3252 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3253 #endif /* TARGET_PPC64 */
3254
3255 /*** Integer load and store multiple ***/
3256
3257 /* lmw */
3258 static void gen_lmw(DisasContext *ctx)
3259 {
3260 TCGv t0;
3261 TCGv_i32 t1;
3262 gen_set_access_type(ctx, ACCESS_INT);
3263 /* NIP cannot be restored if the memory exception comes from an helper */
3264 gen_update_nip(ctx, ctx->nip - 4);
3265 t0 = tcg_temp_new();
3266 t1 = tcg_const_i32(rD(ctx->opcode));
3267 gen_addr_imm_index(ctx, t0, 0);
3268 gen_helper_lmw(cpu_env, t0, t1);
3269 tcg_temp_free(t0);
3270 tcg_temp_free_i32(t1);
3271 }
3272
3273 /* stmw */
3274 static void gen_stmw(DisasContext *ctx)
3275 {
3276 TCGv t0;
3277 TCGv_i32 t1;
3278 gen_set_access_type(ctx, ACCESS_INT);
3279 /* NIP cannot be restored if the memory exception comes from an helper */
3280 gen_update_nip(ctx, ctx->nip - 4);
3281 t0 = tcg_temp_new();
3282 t1 = tcg_const_i32(rS(ctx->opcode));
3283 gen_addr_imm_index(ctx, t0, 0);
3284 gen_helper_stmw(cpu_env, t0, t1);
3285 tcg_temp_free(t0);
3286 tcg_temp_free_i32(t1);
3287 }
3288
3289 /*** Integer load and store strings ***/
3290
3291 /* lswi */
3292 /* PowerPC32 specification says we must generate an exception if
3293 * rA is in the range of registers to be loaded.
3294 * In an other hand, IBM says this is valid, but rA won't be loaded.
3295 * For now, I'll follow the spec...
3296 */
3297 static void gen_lswi(DisasContext *ctx)
3298 {
3299 TCGv t0;
3300 TCGv_i32 t1, t2;
3301 int nb = NB(ctx->opcode);
3302 int start = rD(ctx->opcode);
3303 int ra = rA(ctx->opcode);
3304 int nr;
3305
3306 if (nb == 0)
3307 nb = 32;
3308 nr = (nb + 3) / 4;
3309 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3310 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3311 return;
3312 }
3313 gen_set_access_type(ctx, ACCESS_INT);
3314 /* NIP cannot be restored if the memory exception comes from an helper */
3315 gen_update_nip(ctx, ctx->nip - 4);
3316 t0 = tcg_temp_new();
3317 gen_addr_register(ctx, t0);
3318 t1 = tcg_const_i32(nb);
3319 t2 = tcg_const_i32(start);
3320 gen_helper_lsw(cpu_env, t0, t1, t2);
3321 tcg_temp_free(t0);
3322 tcg_temp_free_i32(t1);
3323 tcg_temp_free_i32(t2);
3324 }
3325
3326 /* lswx */
3327 static void gen_lswx(DisasContext *ctx)
3328 {
3329 TCGv t0;
3330 TCGv_i32 t1, t2, t3;
3331 gen_set_access_type(ctx, ACCESS_INT);
3332 /* NIP cannot be restored if the memory exception comes from an helper */
3333 gen_update_nip(ctx, ctx->nip - 4);
3334 t0 = tcg_temp_new();
3335 gen_addr_reg_index(ctx, t0);
3336 t1 = tcg_const_i32(rD(ctx->opcode));
3337 t2 = tcg_const_i32(rA(ctx->opcode));
3338 t3 = tcg_const_i32(rB(ctx->opcode));
3339 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3340 tcg_temp_free(t0);
3341 tcg_temp_free_i32(t1);
3342 tcg_temp_free_i32(t2);
3343 tcg_temp_free_i32(t3);
3344 }
3345
3346 /* stswi */
3347 static void gen_stswi(DisasContext *ctx)
3348 {
3349 TCGv t0;
3350 TCGv_i32 t1, t2;
3351 int nb = NB(ctx->opcode);
3352 gen_set_access_type(ctx, ACCESS_INT);
3353 /* NIP cannot be restored if the memory exception comes from an helper */
3354 gen_update_nip(ctx, ctx->nip - 4);
3355 t0 = tcg_temp_new();
3356 gen_addr_register(ctx, t0);
3357 if (nb == 0)
3358 nb = 32;
3359 t1 = tcg_const_i32(nb);
3360 t2 = tcg_const_i32(rS(ctx->opcode));
3361 gen_helper_stsw(cpu_env, t0, t1, t2);
3362 tcg_temp_free(t0);
3363 tcg_temp_free_i32(t1);
3364 tcg_temp_free_i32(t2);
3365 }
3366
3367 /* stswx */
3368 static void gen_stswx(DisasContext *ctx)
3369 {
3370 TCGv t0;
3371 TCGv_i32 t1, t2;
3372 gen_set_access_type(ctx, ACCESS_INT);
3373 /* NIP cannot be restored if the memory exception comes from an helper */
3374 gen_update_nip(ctx, ctx->nip - 4);
3375 t0 = tcg_temp_new();
3376 gen_addr_reg_index(ctx, t0);
3377 t1 = tcg_temp_new_i32();
3378 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3379 tcg_gen_andi_i32(t1, t1, 0x7F);
3380 t2 = tcg_const_i32(rS(ctx->opcode));
3381 gen_helper_stsw(cpu_env, t0, t1, t2);
3382 tcg_temp_free(t0);
3383 tcg_temp_free_i32(t1);
3384 tcg_temp_free_i32(t2);
3385 }
3386
3387 /*** Memory synchronisation ***/
3388 /* eieio */
3389 static void gen_eieio(DisasContext *ctx)
3390 {
3391 }
3392
3393 #if !defined(CONFIG_USER_ONLY)
3394 static inline void gen_check_tlb_flush(DisasContext *ctx)
3395 {
3396 TCGv_i32 t;
3397 TCGLabel *l;
3398
3399 if (!ctx->lazy_tlb_flush) {
3400 return;
3401 }
3402 l = gen_new_label();
3403 t = tcg_temp_new_i32();
3404 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3405 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3406 gen_helper_check_tlb_flush(cpu_env);
3407 gen_set_label(l);
3408 tcg_temp_free_i32(t);
3409 }
3410 #else
3411 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3412 #endif
3413
3414 /* isync */
3415 static void gen_isync(DisasContext *ctx)
3416 {
3417 /*
3418 * We need to check for a pending TLB flush. This can only happen in
3419 * kernel mode however so check MSR_PR
3420 */
3421 if (!ctx->pr) {
3422 gen_check_tlb_flush(ctx);
3423 }
3424 gen_stop_exception(ctx);
3425 }
3426
3427 #define LARX(name, len, loadop) \
3428 static void gen_##name(DisasContext *ctx) \
3429 { \
3430 TCGv t0; \
3431 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3432 gen_set_access_type(ctx, ACCESS_RES); \
3433 t0 = tcg_temp_local_new(); \
3434 gen_addr_reg_index(ctx, t0); \
3435 if ((len) > 1) { \
3436 gen_check_align(ctx, t0, (len)-1); \
3437 } \
3438 gen_qemu_##loadop(ctx, gpr, t0); \
3439 tcg_gen_mov_tl(cpu_reserve, t0); \
3440 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3441 tcg_temp_free(t0); \
3442 }
3443
3444 /* lwarx */
3445 LARX(lbarx, 1, ld8u);
3446 LARX(lharx, 2, ld16u);
3447 LARX(lwarx, 4, ld32u);
3448
3449
3450 #if defined(CONFIG_USER_ONLY)
3451 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3452 int reg, int size)
3453 {
3454 TCGv t0 = tcg_temp_new();
3455 uint32_t save_exception = ctx->exception;
3456
3457 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3458 tcg_gen_movi_tl(t0, (size << 5) | reg);
3459 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3460 tcg_temp_free(t0);
3461 gen_update_nip(ctx, ctx->nip-4);
3462 ctx->exception = POWERPC_EXCP_BRANCH;
3463 gen_exception(ctx, POWERPC_EXCP_STCX);
3464 ctx->exception = save_exception;
3465 }
3466 #else
3467 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3468 int reg, int size)
3469 {
3470 TCGLabel *l1;
3471
3472 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3473 l1 = gen_new_label();
3474 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3475 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3476 #if defined(TARGET_PPC64)
3477 if (size == 8) {
3478 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3479 } else
3480 #endif
3481 if (size == 4) {
3482 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3483 } else if (size == 2) {
3484 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3485 #if defined(TARGET_PPC64)
3486 } else if (size == 16) {
3487 TCGv gpr1, gpr2 , EA8;
3488 if (unlikely(ctx->le_mode)) {
3489 gpr1 = cpu_gpr[reg+1];
3490 gpr2 = cpu_gpr[reg];
3491 } else {
3492 gpr1 = cpu_gpr[reg];
3493 gpr2 = cpu_gpr[reg+1];
3494 }
3495 gen_qemu_st64(ctx, gpr1, EA);
3496 EA8 = tcg_temp_local_new();
3497 gen_addr_add(ctx, EA8, EA, 8);
3498 gen_qemu_st64(ctx, gpr2, EA8);
3499 tcg_temp_free(EA8);
3500 #endif
3501 } else {
3502 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3503 }
3504 gen_set_label(l1);
3505 tcg_gen_movi_tl(cpu_reserve, -1);
3506 }
3507 #endif
3508
3509 #define STCX(name, len) \
3510 static void gen_##name(DisasContext *ctx) \
3511 { \
3512 TCGv t0; \
3513 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3514 gen_inval_exception(ctx, \
3515 POWERPC_EXCP_INVAL_INVAL); \
3516 return; \
3517 } \
3518 gen_set_access_type(ctx, ACCESS_RES); \
3519 t0 = tcg_temp_local_new(); \
3520 gen_addr_reg_index(ctx, t0); \
3521 if (len > 1) { \
3522 gen_check_align(ctx, t0, (len)-1); \
3523 } \
3524 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3525 tcg_temp_free(t0); \
3526 }
3527
3528 STCX(stbcx_, 1);
3529 STCX(sthcx_, 2);
3530 STCX(stwcx_, 4);
3531
3532 #if defined(TARGET_PPC64)
3533 /* ldarx */
3534 LARX(ldarx, 8, ld64);
3535
3536 /* lqarx */
3537 static void gen_lqarx(DisasContext *ctx)
3538 {
3539 TCGv EA;
3540 int rd = rD(ctx->opcode);
3541 TCGv gpr1, gpr2;
3542
3543 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3544 (rd == rB(ctx->opcode)))) {
3545 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3546 return;
3547 }
3548
3549 gen_set_access_type(ctx, ACCESS_RES);
3550 EA = tcg_temp_local_new();
3551 gen_addr_reg_index(ctx, EA);
3552 gen_check_align(ctx, EA, 15);
3553 if (unlikely(ctx->le_mode)) {
3554 gpr1 = cpu_gpr[rd+1];
3555 gpr2 = cpu_gpr[rd];
3556 } else {
3557 gpr1 = cpu_gpr[rd];
3558 gpr2 = cpu_gpr[rd+1];
3559 }
3560 gen_qemu_ld64(ctx, gpr1, EA);
3561 tcg_gen_mov_tl(cpu_reserve, EA);
3562
3563 gen_addr_add(ctx, EA, EA, 8);
3564 gen_qemu_ld64(ctx, gpr2, EA);
3565
3566 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3567 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3568
3569 tcg_temp_free(EA);
3570 }
3571
3572 /* stdcx. */
3573 STCX(stdcx_, 8);
3574 STCX(stqcx_, 16);
3575 #endif /* defined(TARGET_PPC64) */
3576
3577 /* sync */
3578 static void gen_sync(DisasContext *ctx)
3579 {
3580 uint32_t l = (ctx->opcode >> 21) & 3;
3581
3582 /*
3583 * We may need to check for a pending TLB flush.
3584 *
3585 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3586 *
3587 * Additionally, this can only happen in kernel mode however so
3588 * check MSR_PR as well.
3589 */
3590 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3591 gen_check_tlb_flush(ctx);
3592 }
3593 }
3594
3595 /* wait */
3596 static void gen_wait(DisasContext *ctx)
3597 {
3598 TCGv_i32 t0 = tcg_const_i32(1);
3599 tcg_gen_st_i32(t0, cpu_env,
3600 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3601 tcg_temp_free_i32(t0);
3602 /* Stop translation, as the CPU is supposed to sleep from now */
3603 gen_exception_err(ctx, EXCP_HLT, 1);
3604 }
3605
3606 /*** Floating-point load ***/
3607 #define GEN_LDF(name, ldop, opc, type) \
3608 static void glue(gen_, name)(DisasContext *ctx) \
3609 { \
3610 TCGv EA; \
3611 if (unlikely(!ctx->fpu_enabled)) { \
3612 gen_exception(ctx, POWERPC_EXCP_FPU); \
3613 return; \
3614 } \
3615 gen_set_access_type(ctx, ACCESS_FLOAT); \
3616 EA = tcg_temp_new(); \
3617 gen_addr_imm_index(ctx, EA, 0); \
3618 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3619 tcg_temp_free(EA); \
3620 }
3621
3622 #define GEN_LDUF(name, ldop, opc, type) \
3623 static void glue(gen_, name##u)(DisasContext *ctx) \
3624 { \
3625 TCGv EA; \
3626 if (unlikely(!ctx->fpu_enabled)) { \
3627 gen_exception(ctx, POWERPC_EXCP_FPU); \
3628 return; \
3629 } \
3630 if (unlikely(rA(ctx->opcode) == 0)) { \
3631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3632 return; \
3633 } \
3634 gen_set_access_type(ctx, ACCESS_FLOAT); \
3635 EA = tcg_temp_new(); \
3636 gen_addr_imm_index(ctx, EA, 0); \
3637 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3639 tcg_temp_free(EA); \
3640 }
3641
3642 #define GEN_LDUXF(name, ldop, opc, type) \
3643 static void glue(gen_, name##ux)(DisasContext *ctx) \
3644 { \
3645 TCGv EA; \
3646 if (unlikely(!ctx->fpu_enabled)) { \
3647 gen_exception(ctx, POWERPC_EXCP_FPU); \
3648 return; \
3649 } \
3650 if (unlikely(rA(ctx->opcode) == 0)) { \
3651 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3652 return; \
3653 } \
3654 gen_set_access_type(ctx, ACCESS_FLOAT); \
3655 EA = tcg_temp_new(); \
3656 gen_addr_reg_index(ctx, EA); \
3657 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3658 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3659 tcg_temp_free(EA); \
3660 }
3661
3662 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3663 static void glue(gen_, name##x)(DisasContext *ctx) \
3664 { \
3665 TCGv EA; \
3666 if (unlikely(!ctx->fpu_enabled)) { \
3667 gen_exception(ctx, POWERPC_EXCP_FPU); \
3668 return; \
3669 } \
3670 gen_set_access_type(ctx, ACCESS_FLOAT); \
3671 EA = tcg_temp_new(); \
3672 gen_addr_reg_index(ctx, EA); \
3673 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3674 tcg_temp_free(EA); \
3675 }
3676
3677 #define GEN_LDFS(name, ldop, op, type) \
3678 GEN_LDF(name, ldop, op | 0x20, type); \
3679 GEN_LDUF(name, ldop, op | 0x21, type); \
3680 GEN_LDUXF(name, ldop, op | 0x01, type); \
3681 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3682
3683 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3684 {
3685 TCGv t0 = tcg_temp_new();
3686 TCGv_i32 t1 = tcg_temp_new_i32();
3687 gen_qemu_ld32u(ctx, t0, arg2);
3688 tcg_gen_trunc_tl_i32(t1, t0);
3689 tcg_temp_free(t0);
3690 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3691 tcg_temp_free_i32(t1);
3692 }
3693
3694 /* lfd lfdu lfdux lfdx */
3695 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3696 /* lfs lfsu lfsux lfsx */
3697 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3698
3699 /* lfdp */
3700 static void gen_lfdp(DisasContext *ctx)
3701 {
3702 TCGv EA;
3703 if (unlikely(!ctx->fpu_enabled)) {
3704 gen_exception(ctx, POWERPC_EXCP_FPU);
3705 return;
3706 }
3707 gen_set_access_type(ctx, ACCESS_FLOAT);
3708 EA = tcg_temp_new();
3709 gen_addr_imm_index(ctx, EA, 0);
3710 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3711 64-bit byteswap already. */
3712 if (unlikely(ctx->le_mode)) {
3713 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3714 tcg_gen_addi_tl(EA, EA, 8);
3715 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3716 } else {
3717 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3718 tcg_gen_addi_tl(EA, EA, 8);
3719 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3720 }
3721 tcg_temp_free(EA);
3722 }
3723
3724 /* lfdpx */
3725 static void gen_lfdpx(DisasContext *ctx)
3726 {
3727 TCGv EA;
3728 if (unlikely(!ctx->fpu_enabled)) {
3729 gen_exception(ctx, POWERPC_EXCP_FPU);
3730 return;
3731 }
3732 gen_set_access_type(ctx, ACCESS_FLOAT);
3733 EA = tcg_temp_new();
3734 gen_addr_reg_index(ctx, EA);
3735 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3736 64-bit byteswap already. */
3737 if (unlikely(ctx->le_mode)) {
3738 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3739 tcg_gen_addi_tl(EA, EA, 8);
3740 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3741 } else {
3742 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3743 tcg_gen_addi_tl(EA, EA, 8);
3744 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3745 }
3746 tcg_temp_free(EA);
3747 }
3748
3749 /* lfiwax */
3750 static void gen_lfiwax(DisasContext *ctx)
3751 {
3752 TCGv EA;
3753 TCGv t0;
3754 if (unlikely(!ctx->fpu_enabled)) {
3755 gen_exception(ctx, POWERPC_EXCP_FPU);
3756 return;
3757 }
3758 gen_set_access_type(ctx, ACCESS_FLOAT);
3759 EA = tcg_temp_new();
3760 t0 = tcg_temp_new();
3761 gen_addr_reg_index(ctx, EA);
3762 gen_qemu_ld32s(ctx, t0, EA);
3763 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3764 tcg_temp_free(EA);
3765 tcg_temp_free(t0);
3766 }
3767
3768 /* lfiwzx */
3769 static void gen_lfiwzx(DisasContext *ctx)
3770 {
3771 TCGv EA;
3772 if (unlikely(!ctx->fpu_enabled)) {
3773 gen_exception(ctx, POWERPC_EXCP_FPU);
3774 return;
3775 }
3776 gen_set_access_type(ctx, ACCESS_FLOAT);
3777 EA = tcg_temp_new();
3778 gen_addr_reg_index(ctx, EA);
3779 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3780 tcg_temp_free(EA);
3781 }
3782 /*** Floating-point store ***/
3783 #define GEN_STF(name, stop, opc, type) \
3784 static void glue(gen_, name)(DisasContext *ctx) \
3785 { \
3786 TCGv EA; \
3787 if (unlikely(!ctx->fpu_enabled)) { \
3788 gen_exception(ctx, POWERPC_EXCP_FPU); \
3789 return; \
3790 } \
3791 gen_set_access_type(ctx, ACCESS_FLOAT); \
3792 EA = tcg_temp_new(); \
3793 gen_addr_imm_index(ctx, EA, 0); \
3794 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3795 tcg_temp_free(EA); \
3796 }
3797
3798 #define GEN_STUF(name, stop, opc, type) \
3799 static void glue(gen_, name##u)(DisasContext *ctx) \
3800 { \
3801 TCGv EA; \
3802 if (unlikely(!ctx->fpu_enabled)) { \
3803 gen_exception(ctx, POWERPC_EXCP_FPU); \
3804 return; \
3805 } \
3806 if (unlikely(rA(ctx->opcode) == 0)) { \
3807 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3808 return; \
3809 } \
3810 gen_set_access_type(ctx, ACCESS_FLOAT); \
3811 EA = tcg_temp_new(); \
3812 gen_addr_imm_index(ctx, EA, 0); \
3813 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3814 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3815 tcg_temp_free(EA); \
3816 }
3817
3818 #define GEN_STUXF(name, stop, opc, type) \
3819 static void glue(gen_, name##ux)(DisasContext *ctx) \
3820 { \
3821 TCGv EA; \
3822 if (unlikely(!ctx->fpu_enabled)) { \
3823 gen_exception(ctx, POWERPC_EXCP_FPU); \
3824 return; \
3825 } \
3826 if (unlikely(rA(ctx->opcode) == 0)) { \
3827 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3828 return; \
3829 } \
3830 gen_set_access_type(ctx, ACCESS_FLOAT); \
3831 EA = tcg_temp_new(); \
3832 gen_addr_reg_index(ctx, EA); \
3833 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3835 tcg_temp_free(EA); \
3836 }
3837
3838 #define GEN_STXF(name, stop, opc2, opc3, type) \
3839 static void glue(gen_, name##x)(DisasContext *ctx) \
3840 { \
3841 TCGv EA; \
3842 if (unlikely(!ctx->fpu_enabled)) { \
3843 gen_exception(ctx, POWERPC_EXCP_FPU); \
3844 return; \
3845 } \
3846 gen_set_access_type(ctx, ACCESS_FLOAT); \
3847 EA = tcg_temp_new(); \
3848 gen_addr_reg_index(ctx, EA); \
3849 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3850 tcg_temp_free(EA); \
3851 }
3852
3853 #define GEN_STFS(name, stop, op, type) \
3854 GEN_STF(name, stop, op | 0x20, type); \
3855 GEN_STUF(name, stop, op | 0x21, type); \
3856 GEN_STUXF(name, stop, op | 0x01, type); \
3857 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3858
3859 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3860 {
3861 TCGv_i32 t0 = tcg_temp_new_i32();
3862 TCGv t1 = tcg_temp_new();
3863 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3864 tcg_gen_extu_i32_tl(t1, t0);
3865 tcg_temp_free_i32(t0);
3866 gen_qemu_st32(ctx, t1, arg2);
3867 tcg_temp_free(t1);
3868 }
3869
3870 /* stfd stfdu stfdux stfdx */
3871 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3872 /* stfs stfsu stfsux stfsx */
3873 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3874
3875 /* stfdp */
3876 static void gen_stfdp(DisasContext *ctx)
3877 {
3878 TCGv EA;
3879 if (unlikely(!ctx->fpu_enabled)) {
3880 gen_exception(ctx, POWERPC_EXCP_FPU);
3881 return;
3882 }
3883 gen_set_access_type(ctx, ACCESS_FLOAT);
3884 EA = tcg_temp_new();
3885 gen_addr_imm_index(ctx, EA, 0);
3886 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3887 64-bit byteswap already. */
3888 if (unlikely(ctx->le_mode)) {
3889 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3890 tcg_gen_addi_tl(EA, EA, 8);
3891 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3892 } else {
3893 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3894 tcg_gen_addi_tl(EA, EA, 8);
3895 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3896 }
3897 tcg_temp_free(EA);
3898 }
3899
3900 /* stfdpx */
3901 static void gen_stfdpx(DisasContext *ctx)
3902 {
3903 TCGv EA;
3904 if (unlikely(!ctx->fpu_enabled)) {
3905 gen_exception(ctx, POWERPC_EXCP_FPU);
3906 return;
3907 }
3908 gen_set_access_type(ctx, ACCESS_FLOAT);
3909 EA = tcg_temp_new();
3910 gen_addr_reg_index(ctx, EA);
3911 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3912 64-bit byteswap already. */
3913 if (unlikely(ctx->le_mode)) {
3914 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3915 tcg_gen_addi_tl(EA, EA, 8);
3916 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3917 } else {
3918 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3919 tcg_gen_addi_tl(EA, EA, 8);
3920 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3921 }
3922 tcg_temp_free(EA);
3923 }
3924
3925 /* Optional: */
3926 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3927 {
3928 TCGv t0 = tcg_temp_new();
3929 tcg_gen_trunc_i64_tl(t0, arg1),
3930 gen_qemu_st32(ctx, t0, arg2);
3931 tcg_temp_free(t0);
3932 }
3933 /* stfiwx */
3934 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3935
3936 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3937 {
3938 #if defined(TARGET_PPC64)
3939 if (ctx->has_cfar)
3940 tcg_gen_movi_tl(cpu_cfar, nip);
3941 #endif
3942 }
3943
3944 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3945 {
3946 if (unlikely(ctx->singlestep_enabled)) {
3947 return false;
3948 }
3949
3950 #ifndef CONFIG_USER_ONLY
3951 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3952 #else
3953 return true;
3954 #endif
3955 }
3956
3957 /*** Branch ***/
3958 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3959 {
3960 if (NARROW_MODE(ctx)) {
3961 dest = (uint32_t) dest;
3962 }
3963 if (use_goto_tb(ctx, dest)) {
3964 tcg_gen_goto_tb(n);
3965 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3966 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3967 } else {
3968 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3969 if (unlikely(ctx->singlestep_enabled)) {
3970 if ((ctx->singlestep_enabled &
3971 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3972 (ctx->exception == POWERPC_EXCP_BRANCH ||
3973 ctx->exception == POWERPC_EXCP_TRACE)) {
3974 target_ulong tmp = ctx->nip;
3975 ctx->nip = dest;
3976 gen_exception(ctx, POWERPC_EXCP_TRACE);
3977 ctx->nip = tmp;
3978 }
3979 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3980 gen_debug_exception(ctx);
3981 }
3982 }
3983 tcg_gen_exit_tb(0);
3984 }
3985 }
3986
3987 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3988 {
3989 if (NARROW_MODE(ctx)) {
3990 nip = (uint32_t)nip;
3991 }
3992 tcg_gen_movi_tl(cpu_lr, nip);
3993 }
3994
3995 /* b ba bl bla */
3996 static void gen_b(DisasContext *ctx)
3997 {
3998 target_ulong li, target;
3999
4000 ctx->exception = POWERPC_EXCP_BRANCH;
4001 /* sign extend LI */
4002 li = LI(ctx->opcode);
4003 li = (li ^ 0x02000000) - 0x02000000;
4004 if (likely(AA(ctx->opcode) == 0)) {
4005 target = ctx->nip + li - 4;
4006 } else {
4007 target = li;
4008 }
4009 if (LK(ctx->opcode)) {
4010 gen_setlr(ctx, ctx->nip);
4011 }
4012 gen_update_cfar(ctx, ctx->nip);
4013 gen_goto_tb(ctx, 0, target);
4014 }
4015
4016 #define BCOND_IM 0
4017 #define BCOND_LR 1
4018 #define BCOND_CTR 2
4019 #define BCOND_TAR 3
4020
4021 static inline void gen_bcond(DisasContext *ctx, int type)
4022 {
4023 uint32_t bo = BO(ctx->opcode);
4024 TCGLabel *l1;
4025 TCGv target;
4026
4027 ctx->exception = POWERPC_EXCP_BRANCH;
4028 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4029 target = tcg_temp_local_new();
4030 if (type == BCOND_CTR)
4031 tcg_gen_mov_tl(target, cpu_ctr);
4032 else if (type == BCOND_TAR)
4033 gen_load_spr(target, SPR_TAR);
4034 else
4035 tcg_gen_mov_tl(target, cpu_lr);
4036 } else {
4037 TCGV_UNUSED(target);
4038 }
4039 if (LK(ctx->opcode))
4040 gen_setlr(ctx, ctx->nip);
4041 l1 = gen_new_label();
4042 if ((bo & 0x4) == 0) {
4043 /* Decrement and test CTR */
4044 TCGv temp = tcg_temp_new();
4045 if (unlikely(type == BCOND_CTR)) {
4046 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4047 return;
4048 }
4049 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4050 if (NARROW_MODE(ctx)) {
4051 tcg_gen_ext32u_tl(temp, cpu_ctr);
4052 } else {
4053 tcg_gen_mov_tl(temp, cpu_ctr);
4054 }
4055 if (bo & 0x2) {
4056 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4057 } else {
4058 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4059 }
4060 tcg_temp_free(temp);
4061 }
4062 if ((bo & 0x10) == 0) {
4063 /* Test CR */
4064 uint32_t bi = BI(ctx->opcode);
4065 uint32_t mask = 0x08 >> (bi & 0x03);
4066 TCGv_i32 temp = tcg_temp_new_i32();
4067
4068 if (bo & 0x8) {
4069 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4070 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4071 } else {
4072 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4073 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4074 }
4075 tcg_temp_free_i32(temp);
4076 }
4077 gen_update_cfar(ctx, ctx->nip);
4078 if (type == BCOND_IM) {
4079 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4080 if (likely(AA(ctx->opcode) == 0)) {
4081 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4082 } else {
4083 gen_goto_tb(ctx, 0, li);
4084 }
4085 gen_set_label(l1);
4086 gen_goto_tb(ctx, 1, ctx->nip);
4087 } else {
4088 if (NARROW_MODE(ctx)) {
4089 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4090 } else {
4091 tcg_gen_andi_tl(cpu_nip, target, ~3);
4092 }
4093 tcg_gen_exit_tb(0);
4094 gen_set_label(l1);
4095 gen_update_nip(ctx, ctx->nip);
4096 tcg_gen_exit_tb(0);
4097 }
4098 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4099 tcg_temp_free(target);
4100 }
4101 }
4102
4103 static void gen_bc(DisasContext *ctx)
4104 {
4105 gen_bcond(ctx, BCOND_IM);
4106 }
4107
4108 static void gen_bcctr(DisasContext *ctx)
4109 {
4110 gen_bcond(ctx, BCOND_CTR);
4111 }
4112
4113 static void gen_bclr(DisasContext *ctx)
4114 {
4115 gen_bcond(ctx, BCOND_LR);
4116 }
4117
4118 static void gen_bctar(DisasContext *ctx)
4119 {
4120 gen_bcond(ctx, BCOND_TAR);
4121 }
4122
4123 /*** Condition register logical ***/
4124 #define GEN_CRLOGIC(name, tcg_op, opc) \
4125 static void glue(gen_, name)(DisasContext *ctx) \
4126 { \
4127 uint8_t bitmask; \
4128 int sh; \
4129 TCGv_i32 t0, t1; \
4130 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4131 t0 = tcg_temp_new_i32(); \
4132 if (sh > 0) \
4133 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4134 else if (sh < 0) \
4135 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4136 else \
4137 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4138 t1 = tcg_temp_new_i32(); \
4139 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4140 if (sh > 0) \
4141 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4142 else if (sh < 0) \
4143 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4144 else \
4145 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4146 tcg_op(t0, t0, t1); \
4147 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4148 tcg_gen_andi_i32(t0, t0, bitmask); \
4149 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4150 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4151 tcg_temp_free_i32(t0); \
4152 tcg_temp_free_i32(t1); \
4153 }
4154
4155 /* crand */
4156 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4157 /* crandc */
4158 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4159 /* creqv */
4160 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4161 /* crnand */
4162 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4163 /* crnor */
4164 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4165 /* cror */
4166 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4167 /* crorc */
4168 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4169 /* crxor */
4170 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4171
4172 /* mcrf */
4173 static void gen_mcrf(DisasContext *ctx)
4174 {
4175 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4176 }
4177
4178 /*** System linkage ***/
4179
4180 /* rfi (supervisor only) */
4181 static void gen_rfi(DisasContext *ctx)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 GEN_PRIV;
4185 #else
4186 /* FIXME: This instruction doesn't exist anymore on 64-bit server
4187 * processors compliant with arch 2.x, we should remove it there,
4188 * but we need to fix OpenBIOS not to use it on 970 first
4189 */
4190 /* Restore CPU state */
4191 CHK_SV;
4192 gen_update_cfar(ctx, ctx->nip);
4193 gen_helper_rfi(cpu_env);
4194 gen_sync_exception(ctx);
4195 #endif
4196 }
4197
4198 #if defined(TARGET_PPC64)
4199 static void gen_rfid(DisasContext *ctx)
4200 {
4201 #if defined(CONFIG_USER_ONLY)
4202 GEN_PRIV;
4203 #else
4204 /* Restore CPU state */
4205 CHK_SV;
4206 gen_update_cfar(ctx, ctx->nip);
4207 gen_helper_rfid(cpu_env);
4208 gen_sync_exception(ctx);
4209 #endif
4210 }
4211
4212 static void gen_hrfid(DisasContext *ctx)
4213 {
4214 #if defined(CONFIG_USER_ONLY)
4215 GEN_PRIV;
4216 #else
4217 /* Restore CPU state */
4218 CHK_HV;
4219 gen_helper_hrfid(cpu_env);
4220 gen_sync_exception(ctx);
4221 #endif
4222 }
4223 #endif
4224
4225 /* sc */
4226 #if defined(CONFIG_USER_ONLY)
4227 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4228 #else
4229 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4230 #endif
4231 static void gen_sc(DisasContext *ctx)
4232 {
4233 uint32_t lev;
4234
4235 lev = (ctx->opcode >> 5) & 0x7F;
4236 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4237 }
4238
4239 /*** Trap ***/
4240
4241 /* tw */
4242 static void gen_tw(DisasContext *ctx)
4243 {
4244 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4245 /* Update the nip since this might generate a trap exception */
4246 gen_update_nip(ctx, ctx->nip);
4247 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4248 t0);
4249 tcg_temp_free_i32(t0);
4250 }
4251
4252 /* twi */
4253 static void gen_twi(DisasContext *ctx)
4254 {
4255 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4256 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4257 /* Update the nip since this might generate a trap exception */
4258 gen_update_nip(ctx, ctx->nip);
4259 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4260 tcg_temp_free(t0);
4261 tcg_temp_free_i32(t1);
4262 }
4263
4264 #if defined(TARGET_PPC64)
4265 /* td */
4266 static void gen_td(DisasContext *ctx)
4267 {
4268 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4269 /* Update the nip since this might generate a trap exception */
4270 gen_update_nip(ctx, ctx->nip);
4271 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4272 t0);
4273 tcg_temp_free_i32(t0);
4274 }
4275
4276 /* tdi */
4277 static void gen_tdi(DisasContext *ctx)
4278 {
4279 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4280 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4281 /* Update the nip since this might generate a trap exception */
4282 gen_update_nip(ctx, ctx->nip);
4283 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4284 tcg_temp_free(t0);
4285 tcg_temp_free_i32(t1);
4286 }
4287 #endif
4288
4289 /*** Processor control ***/
4290
4291 static void gen_read_xer(TCGv dst)
4292 {
4293 TCGv t0 = tcg_temp_new();
4294 TCGv t1 = tcg_temp_new();
4295 TCGv t2 = tcg_temp_new();
4296 tcg_gen_mov_tl(dst, cpu_xer);
4297 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4298 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4299 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4300 tcg_gen_or_tl(t0, t0, t1);
4301 tcg_gen_or_tl(dst, dst, t2);
4302 tcg_gen_or_tl(dst, dst, t0);
4303 tcg_temp_free(t0);
4304 tcg_temp_free(t1);
4305 tcg_temp_free(t2);
4306 }
4307
4308 static void gen_write_xer(TCGv src)
4309 {
4310 tcg_gen_andi_tl(cpu_xer, src,
4311 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4312 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4313 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4314 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4315 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4316 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4317 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4318 }
4319
4320 /* mcrxr */
4321 static void gen_mcrxr(DisasContext *ctx)
4322 {
4323 TCGv_i32 t0 = tcg_temp_new_i32();
4324 TCGv_i32 t1 = tcg_temp_new_i32();
4325 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4326
4327 tcg_gen_trunc_tl_i32(t0, cpu_so);
4328 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4329 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4330 tcg_gen_shli_i32(t0, t0, 3);
4331 tcg_gen_shli_i32(t1, t1, 2);
4332 tcg_gen_shli_i32(dst, dst, 1);
4333 tcg_gen_or_i32(dst, dst, t0);
4334 tcg_gen_or_i32(dst, dst, t1);
4335 tcg_temp_free_i32(t0);
4336 tcg_temp_free_i32(t1);
4337
4338 tcg_gen_movi_tl(cpu_so, 0);
4339 tcg_gen_movi_tl(cpu_ov, 0);
4340 tcg_gen_movi_tl(cpu_ca, 0);
4341 }
4342
4343 /* mfcr mfocrf */
4344 static void gen_mfcr(DisasContext *ctx)
4345 {
4346 uint32_t crm, crn;
4347
4348 if (likely(ctx->opcode & 0x00100000)) {
4349 crm = CRM(ctx->opcode);
4350 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4351 crn = ctz32 (crm);
4352 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4353 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4354 cpu_gpr[rD(ctx->opcode)], crn * 4);
4355 }
4356 } else {
4357 TCGv_i32 t0 = tcg_temp_new_i32();
4358 tcg_gen_mov_i32(t0, cpu_crf[0]);
4359 tcg_gen_shli_i32(t0, t0, 4);
4360 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4361 tcg_gen_shli_i32(t0, t0, 4);
4362 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4363 tcg_gen_shli_i32(t0, t0, 4);
4364 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4365 tcg_gen_shli_i32(t0, t0, 4);
4366 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4367 tcg_gen_shli_i32(t0, t0, 4);
4368 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4369 tcg_gen_shli_i32(t0, t0, 4);
4370 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4371 tcg_gen_shli_i32(t0, t0, 4);
4372 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4373 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4374 tcg_temp_free_i32(t0);
4375 }
4376 }
4377
4378 /* mfmsr */
4379 static void gen_mfmsr(DisasContext *ctx)
4380 {
4381 CHK_SV;
4382 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4383 }
4384
4385 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4386 {
4387 #if 0
4388 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4389 printf("ERROR: try to access SPR %d !\n", sprn);
4390 #endif
4391 }
4392 #define SPR_NOACCESS (&spr_noaccess)
4393
4394 /* mfspr */
4395 static inline void gen_op_mfspr(DisasContext *ctx)
4396 {
4397 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4398 uint32_t sprn = SPR(ctx->opcode);
4399
4400 #if defined(CONFIG_USER_ONLY)
4401 read_cb = ctx->spr_cb[sprn].uea_read;
4402 #else
4403 if (ctx->pr) {
4404 read_cb = ctx->spr_cb[sprn].uea_read;
4405 } else if (ctx->hv) {
4406 read_cb = ctx->spr_cb[sprn].hea_read;
4407 } else {
4408 read_cb = ctx->spr_cb[sprn].oea_read;
4409 }
4410 #endif
4411 if (likely(read_cb != NULL)) {
4412 if (likely(read_cb != SPR_NOACCESS)) {
4413 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4414 } else {
4415 /* Privilege exception */
4416 /* This is a hack to avoid warnings when running Linux:
4417 * this OS breaks the PowerPC virtualisation model,
4418 * allowing userland application to read the PVR
4419 */
4420 if (sprn != SPR_PVR) {
4421 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4422 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4423 if (qemu_log_separate()) {
4424 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4425 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4426 }
4427 }
4428 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4429 }
4430 } else {
4431 /* ISA 2.07 defines these as no-ops */
4432 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4433 (sprn >= 808 && sprn <= 811)) {
4434 /* This is a nop */
4435 return;
4436 }
4437 /* Not defined */
4438 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4439 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4440 if (qemu_log_separate()) {
4441 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4442 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4443 }
4444
4445 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4446 * it can generate a priv, a hv emu or a no-op
4447 */
4448 if (sprn & 0x10) {
4449 if (ctx->pr) {
4450 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4451 }
4452 } else {
4453 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4454 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4455 }
4456 }
4457 }
4458 }
4459
4460 static void gen_mfspr(DisasContext *ctx)
4461 {
4462 gen_op_mfspr(ctx);
4463 }
4464
4465 /* mftb */
4466 static void gen_mftb(DisasContext *ctx)
4467 {
4468 gen_op_mfspr(ctx);
4469 }
4470
4471 /* mtcrf mtocrf*/
4472 static void gen_mtcrf(DisasContext *ctx)
4473 {
4474 uint32_t crm, crn;
4475
4476 crm = CRM(ctx->opcode);
4477 if (likely((ctx->opcode & 0x00100000))) {
4478 if (crm && ((crm & (crm - 1)) == 0)) {
4479 TCGv_i32 temp = tcg_temp_new_i32();
4480 crn = ctz32 (crm);
4481 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4482 tcg_gen_shri_i32(temp, temp, crn * 4);
4483 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4484 tcg_temp_free_i32(temp);
4485 }
4486 } else {
4487 TCGv_i32 temp = tcg_temp_new_i32();
4488 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4489 for (crn = 0 ; crn < 8 ; crn++) {
4490 if (crm & (1 << crn)) {
4491 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4492 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4493 }
4494 }
4495 tcg_temp_free_i32(temp);
4496 }
4497 }
4498
4499 /* mtmsr */
4500 #if defined(TARGET_PPC64)
4501 static void gen_mtmsrd(DisasContext *ctx)
4502 {
4503 CHK_SV;
4504
4505 #if !defined(CONFIG_USER_ONLY)
4506 if (ctx->opcode & 0x00010000) {
4507 /* Special form that does not need any synchronisation */
4508 TCGv t0 = tcg_temp_new();
4509 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4510 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4511 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4512 tcg_temp_free(t0);
4513 } else {
4514 /* XXX: we need to update nip before the store
4515 * if we enter power saving mode, we will exit the loop
4516 * directly from ppc_store_msr
4517 */
4518 gen_update_nip(ctx, ctx->nip);
4519 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4520 /* Must stop the translation as machine state (may have) changed */
4521 /* Note that mtmsr is not always defined as context-synchronizing */
4522 gen_stop_exception(ctx);
4523 }
4524 #endif /* !defined(CONFIG_USER_ONLY) */
4525 }
4526 #endif /* defined(TARGET_PPC64) */
4527
4528 static void gen_mtmsr(DisasContext *ctx)
4529 {
4530 CHK_SV;
4531
4532 #if !defined(CONFIG_USER_ONLY)
4533 if (ctx->opcode & 0x00010000) {
4534 /* Special form that does not need any synchronisation */
4535 TCGv t0 = tcg_temp_new();
4536 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4537 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4538 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4539 tcg_temp_free(t0);
4540 } else {
4541 TCGv msr = tcg_temp_new();
4542
4543 /* XXX: we need to update nip before the store
4544 * if we enter power saving mode, we will exit the loop
4545 * directly from ppc_store_msr
4546 */
4547 gen_update_nip(ctx, ctx->nip);
4548 #if defined(TARGET_PPC64)
4549 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4550 #else
4551 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4552 #endif
4553 gen_helper_store_msr(cpu_env, msr);
4554 tcg_temp_free(msr);
4555 /* Must stop the translation as machine state (may have) changed */
4556 /* Note that mtmsr is not always defined as context-synchronizing */
4557 gen_stop_exception(ctx);
4558 }
4559 #endif
4560 }
4561
4562 /* mtspr */
4563 static void gen_mtspr(DisasContext *ctx)
4564 {
4565 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4566 uint32_t sprn = SPR(ctx->opcode);
4567
4568 #if defined(CONFIG_USER_ONLY)
4569 write_cb = ctx->spr_cb[sprn].uea_write;
4570 #else
4571 if (ctx->pr) {
4572 write_cb = ctx->spr_cb[sprn].uea_write;
4573 } else if (ctx->hv) {
4574 write_cb = ctx->spr_cb[sprn].hea_write;
4575 } else {
4576 write_cb = ctx->spr_cb[sprn].oea_write;
4577 }
4578 #endif
4579 if (likely(write_cb != NULL)) {
4580 if (likely(write_cb != SPR_NOACCESS)) {
4581 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4582 } else {
4583 /* Privilege exception */
4584 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4585 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4586 if (qemu_log_separate()) {
4587 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4588 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4589 }
4590 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4591 }
4592 } else {
4593 /* ISA 2.07 defines these as no-ops */
4594 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4595 (sprn >= 808 && sprn <= 811)) {
4596 /* This is a nop */
4597 return;
4598 }
4599
4600 /* Not defined */
4601 if (qemu_log_separate()) {
4602 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4603 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4604 }
4605 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4606 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4607
4608
4609 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4610 * it can generate a priv, a hv emu or a no-op
4611 */
4612 if (sprn & 0x10) {
4613 if (ctx->pr) {
4614 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4615 }
4616 } else {
4617 if (ctx->pr || sprn == 0) {
4618 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4619 }
4620 }
4621 }
4622 }
4623
4624 /*** Cache management ***/
4625
4626 /* dcbf */
4627 static void gen_dcbf(DisasContext *ctx)
4628 {
4629 /* XXX: specification says this is treated as a load by the MMU */
4630 TCGv t0;
4631 gen_set_access_type(ctx, ACCESS_CACHE);
4632 t0 = tcg_temp_new();
4633 gen_addr_reg_index(ctx, t0);
4634 gen_qemu_ld8u(ctx, t0, t0);
4635 tcg_temp_free(t0);
4636 }
4637
4638 /* dcbi (Supervisor only) */
4639 static void gen_dcbi(DisasContext *ctx)
4640 {
4641 #if defined(CONFIG_USER_ONLY)
4642 GEN_PRIV;
4643 #else
4644 TCGv EA, val;
4645
4646 CHK_SV;
4647 EA = tcg_temp_new();
4648 gen_set_access_type(ctx, ACCESS_CACHE);
4649 gen_addr_reg_index(ctx, EA);
4650 val = tcg_temp_new();
4651 /* XXX: specification says this should be treated as a store by the MMU */
4652 gen_qemu_ld8u(ctx, val, EA);
4653 gen_qemu_st8(ctx, val, EA);
4654 tcg_temp_free(val);
4655 tcg_temp_free(EA);
4656 #endif /* defined(CONFIG_USER_ONLY) */
4657 }
4658
4659 /* dcdst */
4660 static void gen_dcbst(DisasContext *ctx)
4661 {
4662 /* XXX: specification say this is treated as a load by the MMU */
4663 TCGv t0;
4664 gen_set_access_type(ctx, ACCESS_CACHE);
4665 t0 = tcg_temp_new();
4666 gen_addr_reg_index(ctx, t0);
4667 gen_qemu_ld8u(ctx, t0, t0);
4668 tcg_temp_free(t0);
4669 }
4670
4671 /* dcbt */
4672 static void gen_dcbt(DisasContext *ctx)
4673 {
4674 /* interpreted as no-op */
4675 /* XXX: specification say this is treated as a load by the MMU
4676 * but does not generate any exception
4677 */
4678 }
4679
4680 /* dcbtst */
4681 static void gen_dcbtst(DisasContext *ctx)
4682 {
4683 /* interpreted as no-op */
4684 /* XXX: specification say this is treated as a load by the MMU
4685 * but does not generate any exception
4686 */
4687 }
4688
4689 /* dcbtls */
4690 static void gen_dcbtls(DisasContext *ctx)
4691 {
4692 /* Always fails locking the cache */
4693 TCGv t0 = tcg_temp_new();
4694 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4695 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4696 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4697 tcg_temp_free(t0);
4698 }
4699
4700 /* dcbz */
4701 static void gen_dcbz(DisasContext *ctx)
4702 {
4703 TCGv tcgv_addr;
4704 TCGv_i32 tcgv_is_dcbzl;
4705 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4706
4707 gen_set_access_type(ctx, ACCESS_CACHE);
4708 /* NIP cannot be restored if the memory exception comes from an helper */
4709 gen_update_nip(ctx, ctx->nip - 4);
4710 tcgv_addr = tcg_temp_new();
4711 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4712
4713 gen_addr_reg_index(ctx, tcgv_addr);
4714 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4715
4716 tcg_temp_free(tcgv_addr);
4717 tcg_temp_free_i32(tcgv_is_dcbzl);
4718 }
4719
4720 /* dst / dstt */
4721 static void gen_dst(DisasContext *ctx)
4722 {
4723 if (rA(ctx->opcode) == 0) {
4724 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4725 } else {
4726 /* interpreted as no-op */
4727 }
4728 }
4729
4730 /* dstst /dststt */
4731 static void gen_dstst(DisasContext *ctx)
4732 {
4733 if (rA(ctx->opcode) == 0) {
4734 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4735 } else {
4736 /* interpreted as no-op */
4737 }
4738
4739 }
4740
4741 /* dss / dssall */
4742 static void gen_dss(DisasContext *ctx)
4743 {
4744 /* interpreted as no-op */
4745 }
4746
4747 /* icbi */
4748 static void gen_icbi(DisasContext *ctx)
4749 {
4750 TCGv t0;
4751 gen_set_access_type(ctx, ACCESS_CACHE);
4752 /* NIP cannot be restored if the memory exception comes from an helper */
4753 gen_update_nip(ctx, ctx->nip - 4);
4754 t0 = tcg_temp_new();
4755 gen_addr_reg_index(ctx, t0);
4756 gen_helper_icbi(cpu_env, t0);
4757 tcg_temp_free(t0);
4758 }
4759
4760 /* Optional: */
4761 /* dcba */
4762 static void gen_dcba(DisasContext *ctx)
4763 {
4764 /* interpreted as no-op */
4765 /* XXX: specification say this is treated as a store by the MMU
4766 * but does not generate any exception
4767 */
4768 }
4769
4770 /*** Segment register manipulation ***/
4771 /* Supervisor only: */
4772
4773 /* mfsr */
4774 static void gen_mfsr(DisasContext *ctx)
4775 {
4776 #if defined(CONFIG_USER_ONLY)
4777 GEN_PRIV;
4778 #else
4779 TCGv t0;
4780
4781 CHK_SV;
4782 t0 = tcg_const_tl(SR(ctx->opcode));
4783 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4784 tcg_temp_free(t0);
4785 #endif /* defined(CONFIG_USER_ONLY) */
4786 }
4787
4788 /* mfsrin */
4789 static void gen_mfsrin(DisasContext *ctx)
4790 {
4791 #if defined(CONFIG_USER_ONLY)
4792 GEN_PRIV;
4793 #else
4794 TCGv t0;
4795
4796 CHK_SV;
4797 t0 = tcg_temp_new();
4798 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4799 tcg_gen_andi_tl(t0, t0, 0xF);
4800 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4801 tcg_temp_free(t0);
4802 #endif /* defined(CONFIG_USER_ONLY) */
4803 }
4804
4805 /* mtsr */
4806 static void gen_mtsr(DisasContext *ctx)
4807 {
4808 #if defined(CONFIG_USER_ONLY)
4809 GEN_PRIV;
4810 #else
4811 TCGv t0;
4812
4813 CHK_SV;
4814 t0 = tcg_const_tl(SR(ctx->opcode));
4815 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4816 tcg_temp_free(t0);
4817 #endif /* defined(CONFIG_USER_ONLY) */
4818 }
4819
4820 /* mtsrin */
4821 static void gen_mtsrin(DisasContext *ctx)
4822 {
4823 #if defined(CONFIG_USER_ONLY)
4824 GEN_PRIV;
4825 #else
4826 TCGv t0;
4827 CHK_SV;
4828
4829 t0 = tcg_temp_new();
4830 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4831 tcg_gen_andi_tl(t0, t0, 0xF);
4832 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4833 tcg_temp_free(t0);
4834 #endif /* defined(CONFIG_USER_ONLY) */
4835 }
4836
4837 #if defined(TARGET_PPC64)
4838 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4839
4840 /* mfsr */
4841 static void gen_mfsr_64b(DisasContext *ctx)
4842 {
4843 #if defined(CONFIG_USER_ONLY)
4844 GEN_PRIV;
4845 #else
4846 TCGv t0;
4847
4848 CHK_SV;
4849 t0 = tcg_const_tl(SR(ctx->opcode));
4850 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4851 tcg_temp_free(t0);
4852 #endif /* defined(CONFIG_USER_ONLY) */
4853 }
4854
4855 /* mfsrin */
4856 static void gen_mfsrin_64b(DisasContext *ctx)
4857 {
4858 #if defined(CONFIG_USER_ONLY)
4859 GEN_PRIV;
4860 #else
4861 TCGv t0;
4862
4863 CHK_SV;
4864 t0 = tcg_temp_new();
4865 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4866 tcg_gen_andi_tl(t0, t0, 0xF);
4867 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4868 tcg_temp_free(t0);
4869 #endif /* defined(CONFIG_USER_ONLY) */
4870 }
4871
4872 /* mtsr */
4873 static void gen_mtsr_64b(DisasContext *ctx)
4874 {
4875 #if defined(CONFIG_USER_ONLY)
4876 GEN_PRIV;
4877 #else
4878 TCGv t0;
4879
4880 CHK_SV;
4881 t0 = tcg_const_tl(SR(ctx->opcode));
4882 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4883 tcg_temp_free(t0);
4884 #endif /* defined(CONFIG_USER_ONLY) */
4885 }
4886
4887 /* mtsrin */
4888 static void gen_mtsrin_64b(DisasContext *ctx)
4889 {
4890 #if defined(CONFIG_USER_ONLY)
4891 GEN_PRIV;
4892 #else
4893 TCGv t0;
4894
4895 CHK_SV;
4896 t0 = tcg_temp_new();
4897 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4898 tcg_gen_andi_tl(t0, t0, 0xF);
4899 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4900 tcg_temp_free(t0);
4901 #endif /* defined(CONFIG_USER_ONLY) */
4902 }
4903
4904 /* slbmte */
4905 static void gen_slbmte(DisasContext *ctx)
4906 {
4907 #if defined(CONFIG_USER_ONLY)
4908 GEN_PRIV;
4909 #else
4910 CHK_SV;
4911
4912 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4913 cpu_gpr[rS(ctx->opcode)]);
4914 #endif /* defined(CONFIG_USER_ONLY) */
4915 }
4916
4917 static void gen_slbmfee(DisasContext *ctx)
4918 {
4919 #if defined(CONFIG_USER_ONLY)
4920 GEN_PRIV;
4921 #else
4922 CHK_SV;
4923
4924 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4925 cpu_gpr[rB(ctx->opcode)]);
4926 #endif /* defined(CONFIG_USER_ONLY) */
4927 }
4928
4929 static void gen_slbmfev(DisasContext *ctx)
4930 {
4931 #if defined(CONFIG_USER_ONLY)
4932 GEN_PRIV;
4933 #else
4934 CHK_SV;
4935
4936 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4937 cpu_gpr[rB(ctx->opcode)]);
4938 #endif /* defined(CONFIG_USER_ONLY) */
4939 }
4940
4941 static void gen_slbfee_(DisasContext *ctx)
4942 {
4943 #if defined(CONFIG_USER_ONLY)
4944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4945 #else
4946 TCGLabel *l1, *l2;
4947
4948 if (unlikely(ctx->pr)) {
4949 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4950 return;
4951 }
4952 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4953 cpu_gpr[rB(ctx->opcode)]);
4954 l1 = gen_new_label();
4955 l2 = gen_new_label();
4956 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4957 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4958 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4959 tcg_gen_br(l2);
4960 gen_set_label(l1);
4961 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4962 gen_set_label(l2);
4963 #endif
4964 }
4965 #endif /* defined(TARGET_PPC64) */
4966
4967 /*** Lookaside buffer management ***/
4968 /* Optional & supervisor only: */
4969
4970 /* tlbia */
4971 static void gen_tlbia(DisasContext *ctx)
4972 {
4973 #if defined(CONFIG_USER_ONLY)
4974 GEN_PRIV;
4975 #else
4976 CHK_HV;
4977
4978 gen_helper_tlbia(cpu_env);
4979 #endif /* defined(CONFIG_USER_ONLY) */
4980 }
4981
4982 /* tlbiel */
4983 static void gen_tlbiel(DisasContext *ctx)
4984 {
4985 #if defined(CONFIG_USER_ONLY)
4986 GEN_PRIV;
4987 #else
4988 CHK_SV;
4989
4990 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4991 #endif /* defined(CONFIG_USER_ONLY) */
4992 }
4993
4994 /* tlbie */
4995 static void gen_tlbie(DisasContext *ctx)
4996 {
4997 #if defined(CONFIG_USER_ONLY)
4998 GEN_PRIV;
4999 #else
5000 CHK_HV;
5001
5002 if (NARROW_MODE(ctx)) {
5003 TCGv t0 = tcg_temp_new();
5004 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
5005 gen_helper_tlbie(cpu_env, t0);
5006 tcg_temp_free(t0);
5007 } else {
5008 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5009 }
5010 #endif /* defined(CONFIG_USER_ONLY) */
5011 }
5012
5013 /* tlbsync */
5014 static void gen_tlbsync(DisasContext *ctx)
5015 {
5016 #if defined(CONFIG_USER_ONLY)
5017 GEN_PRIV;
5018 #else
5019 CHK_HV;
5020
5021 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
5022 * embedded however needs to deal with tlbsync. We don't try to be
5023 * fancy and swallow the overhead of checking for both.
5024 */
5025 gen_check_tlb_flush(ctx);
5026 #endif /* defined(CONFIG_USER_ONLY) */
5027 }
5028
5029 #if defined(TARGET_PPC64)
5030 /* slbia */
5031 static void gen_slbia(DisasContext *ctx)
5032 {
5033 #if defined(CONFIG_USER_ONLY)
5034 GEN_PRIV;
5035 #else
5036 CHK_SV;
5037
5038 gen_helper_slbia(cpu_env);
5039 #endif /* defined(CONFIG_USER_ONLY) */
5040 }
5041
5042 /* slbie */
5043 static void gen_slbie(DisasContext *ctx)
5044 {
5045 #if defined(CONFIG_USER_ONLY)
5046 GEN_PRIV;
5047 #else
5048 CHK_SV;
5049
5050 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5051 #endif /* defined(CONFIG_USER_ONLY) */
5052 }
5053 #endif /* defined(TARGET_PPC64) */
5054
5055 /*** External control ***/
5056 /* Optional: */
5057
5058 /* eciwx */
5059 static void gen_eciwx(DisasContext *ctx)
5060 {
5061 TCGv t0;
5062 /* Should check EAR[E] ! */
5063 gen_set_access_type(ctx, ACCESS_EXT);
5064 t0 = tcg_temp_new();
5065 gen_addr_reg_index(ctx, t0);
5066 gen_check_align(ctx, t0, 0x03);
5067 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5068 tcg_temp_free(t0);
5069 }
5070
5071 /* ecowx */
5072 static void gen_ecowx(DisasContext *ctx)
5073 {
5074 TCGv t0;
5075 /* Should check EAR[E] ! */
5076 gen_set_access_type(ctx, ACCESS_EXT);
5077 t0 = tcg_temp_new();
5078 gen_addr_reg_index(ctx, t0);
5079 gen_check_align(ctx, t0, 0x03);
5080 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5081 tcg_temp_free(t0);
5082 }
5083
5084 /* PowerPC 601 specific instructions */
5085
5086 /* abs - abs. */
5087 static void gen_abs(DisasContext *ctx)
5088 {
5089 TCGLabel *l1 = gen_new_label();
5090 TCGLabel *l2 = gen_new_label();
5091 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5092 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5093 tcg_gen_br(l2);
5094 gen_set_label(l1);
5095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5096 gen_set_label(l2);
5097 if (unlikely(Rc(ctx->opcode) != 0))
5098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5099 }
5100
5101 /* abso - abso. */
5102 static void gen_abso(DisasContext *ctx)
5103 {
5104 TCGLabel *l1 = gen_new_label();
5105 TCGLabel *l2 = gen_new_label();
5106 TCGLabel *l3 = gen_new_label();
5107 /* Start with XER OV disabled, the most likely case */
5108 tcg_gen_movi_tl(cpu_ov, 0);
5109 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5110 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5111 tcg_gen_movi_tl(cpu_ov, 1);
5112 tcg_gen_movi_tl(cpu_so, 1);
5113 tcg_gen_br(l2);
5114 gen_set_label(l1);
5115 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5116 tcg_gen_br(l3);
5117 gen_set_label(l2);
5118 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5119 gen_set_label(l3);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5122 }
5123
5124 /* clcs */
5125 static void gen_clcs(DisasContext *ctx)
5126 {
5127 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5128 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5129 tcg_temp_free_i32(t0);
5130 /* Rc=1 sets CR0 to an undefined state */
5131 }
5132
5133 /* div - div. */
5134 static void gen_div(DisasContext *ctx)
5135 {
5136 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5137 cpu_gpr[rB(ctx->opcode)]);
5138 if (unlikely(Rc(ctx->opcode) != 0))
5139 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5140 }
5141
5142 /* divo - divo. */
5143 static void gen_divo(DisasContext *ctx)
5144 {
5145 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5146 cpu_gpr[rB(ctx->opcode)]);
5147 if (unlikely(Rc(ctx->opcode) != 0))
5148 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5149 }
5150
5151 /* divs - divs. */
5152 static void gen_divs(DisasContext *ctx)
5153 {
5154 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5155 cpu_gpr[rB(ctx->opcode)]);
5156 if (unlikely(Rc(ctx->opcode) != 0))
5157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5158 }
5159
5160 /* divso - divso. */
5161 static void gen_divso(DisasContext *ctx)
5162 {
5163 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5165 if (unlikely(Rc(ctx->opcode) != 0))
5166 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5167 }
5168
5169 /* doz - doz. */
5170 static void gen_doz(DisasContext *ctx)
5171 {
5172 TCGLabel *l1 = gen_new_label();
5173 TCGLabel *l2 = gen_new_label();
5174 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5175 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5176 tcg_gen_br(l2);
5177 gen_set_label(l1);
5178 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5179 gen_set_label(l2);
5180 if (unlikely(Rc(ctx->opcode) != 0))
5181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5182 }
5183
5184 /* dozo - dozo. */
5185 static void gen_dozo(DisasContext *ctx)
5186 {
5187 TCGLabel *l1 = gen_new_label();
5188 TCGLabel *l2 = gen_new_label();
5189 TCGv t0 = tcg_temp_new();
5190 TCGv t1 = tcg_temp_new();
5191 TCGv t2 = tcg_temp_new();
5192 /* Start with XER OV disabled, the most likely case */
5193 tcg_gen_movi_tl(cpu_ov, 0);
5194 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5195 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5196 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5197 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5198 tcg_gen_andc_tl(t1, t1, t2);
5199 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5200 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5201 tcg_gen_movi_tl(cpu_ov, 1);
5202 tcg_gen_movi_tl(cpu_so, 1);
5203 tcg_gen_br(l2);
5204 gen_set_label(l1);
5205 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5206 gen_set_label(l2);
5207 tcg_temp_free(t0);
5208 tcg_temp_free(t1);
5209 tcg_temp_free(t2);
5210 if (unlikely(Rc(ctx->opcode) != 0))
5211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5212 }
5213
5214 /* dozi */
5215 static void gen_dozi(DisasContext *ctx)
5216 {
5217 target_long simm = SIMM(ctx->opcode);
5218 TCGLabel *l1 = gen_new_label();
5219 TCGLabel *l2 = gen_new_label();
5220 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5221 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5222 tcg_gen_br(l2);
5223 gen_set_label(l1);
5224 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5225 gen_set_label(l2);
5226 if (unlikely(Rc(ctx->opcode) != 0))
5227 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5228 }
5229
5230 /* lscbx - lscbx. */
5231 static void gen_lscbx(DisasContext *ctx)
5232 {
5233 TCGv t0 = tcg_temp_new();
5234 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5235 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5236 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5237
5238 gen_addr_reg_index(ctx, t0);
5239 /* NIP cannot be restored if the memory exception comes from an helper */
5240 gen_update_nip(ctx, ctx->nip - 4);
5241 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5242 tcg_temp_free_i32(t1);
5243 tcg_temp_free_i32(t2);
5244 tcg_temp_free_i32(t3);
5245 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5246 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5247 if (unlikely(Rc(ctx->opcode) != 0))
5248 gen_set_Rc0(ctx, t0);
5249 tcg_temp_free(t0);
5250 }
5251
5252 /* maskg - maskg. */
5253 static void gen_maskg(DisasContext *ctx)
5254 {
5255 TCGLabel *l1 = gen_new_label();
5256 TCGv t0 = tcg_temp_new();
5257 TCGv t1 = tcg_temp_new();
5258 TCGv t2 = tcg_temp_new();
5259 TCGv t3 = tcg_temp_new();
5260 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5261 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5262 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5263 tcg_gen_addi_tl(t2, t0, 1);
5264 tcg_gen_shr_tl(t2, t3, t2);
5265 tcg_gen_shr_tl(t3, t3, t1);
5266 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5267 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5268 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5269 gen_set_label(l1);
5270 tcg_temp_free(t0);
5271 tcg_temp_free(t1);
5272 tcg_temp_free(t2);
5273 tcg_temp_free(t3);
5274 if (unlikely(Rc(ctx->opcode) != 0))
5275 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5276 }
5277
5278 /* maskir - maskir. */
5279 static void gen_maskir(DisasContext *ctx)
5280 {
5281 TCGv t0 = tcg_temp_new();
5282 TCGv t1 = tcg_temp_new();
5283 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5284 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5285 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5286 tcg_temp_free(t0);
5287 tcg_temp_free(t1);
5288 if (unlikely(Rc(ctx->opcode) != 0))
5289 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5290 }
5291
5292 /* mul - mul. */
5293 static void gen_mul(DisasContext *ctx)
5294 {
5295 TCGv_i64 t0 = tcg_temp_new_i64();
5296 TCGv_i64 t1 = tcg_temp_new_i64();
5297 TCGv t2 = tcg_temp_new();
5298 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5299 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5300 tcg_gen_mul_i64(t0, t0, t1);
5301 tcg_gen_trunc_i64_tl(t2, t0);
5302 gen_store_spr(SPR_MQ, t2);
5303 tcg_gen_shri_i64(t1, t0, 32);
5304 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5305 tcg_temp_free_i64(t0);
5306 tcg_temp_free_i64(t1);
5307 tcg_temp_free(t2);
5308 if (unlikely(Rc(ctx->opcode) != 0))
5309 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5310 }
5311
5312 /* mulo - mulo. */
5313 static void gen_mulo(DisasContext *ctx)
5314 {
5315 TCGLabel *l1 = gen_new_label();
5316 TCGv_i64 t0 = tcg_temp_new_i64();
5317 TCGv_i64 t1 = tcg_temp_new_i64();
5318 TCGv t2 = tcg_temp_new();
5319 /* Start with XER OV disabled, the most likely case */
5320 tcg_gen_movi_tl(cpu_ov, 0);
5321 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5322 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5323 tcg_gen_mul_i64(t0, t0, t1);
5324 tcg_gen_trunc_i64_tl(t2, t0);
5325 gen_store_spr(SPR_MQ, t2);
5326 tcg_gen_shri_i64(t1, t0, 32);
5327 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5328 tcg_gen_ext32s_i64(t1, t0);
5329 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5330 tcg_gen_movi_tl(cpu_ov, 1);
5331 tcg_gen_movi_tl(cpu_so, 1);
5332 gen_set_label(l1);
5333 tcg_temp_free_i64(t0);
5334 tcg_temp_free_i64(t1);
5335 tcg_temp_free(t2);
5336 if (unlikely(Rc(ctx->opcode) != 0))
5337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5338 }
5339
5340 /* nabs - nabs. */
5341 static void gen_nabs(DisasContext *ctx)
5342 {
5343 TCGLabel *l1 = gen_new_label();
5344 TCGLabel *l2 = gen_new_label();
5345 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5346 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5347 tcg_gen_br(l2);
5348 gen_set_label(l1);
5349 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5350 gen_set_label(l2);
5351 if (unlikely(Rc(ctx->opcode) != 0))
5352 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5353 }
5354
5355 /* nabso - nabso. */
5356 static void gen_nabso(DisasContext *ctx)
5357 {
5358 TCGLabel *l1 = gen_new_label();
5359 TCGLabel *l2 = gen_new_label();
5360 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5361 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5362 tcg_gen_br(l2);
5363 gen_set_label(l1);
5364 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5365 gen_set_label(l2);
5366 /* nabs never overflows */
5367 tcg_gen_movi_tl(cpu_ov, 0);
5368 if (unlikely(Rc(ctx->opcode) != 0))
5369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5370 }
5371
5372 /* rlmi - rlmi. */
5373 static void gen_rlmi(DisasContext *ctx)
5374 {
5375 uint32_t mb = MB(ctx->opcode);
5376 uint32_t me = ME(ctx->opcode);
5377 TCGv t0 = tcg_temp_new();
5378 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5379 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5380 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5381 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5382 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5383 tcg_temp_free(t0);
5384 if (unlikely(Rc(ctx->opcode) != 0))
5385 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5386 }
5387
5388 /* rrib - rrib. */
5389 static void gen_rrib(DisasContext *ctx)
5390 {
5391 TCGv t0 = tcg_temp_new();
5392 TCGv t1 = tcg_temp_new();
5393 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5394 tcg_gen_movi_tl(t1, 0x80000000);
5395 tcg_gen_shr_tl(t1, t1, t0);
5396 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5397 tcg_gen_and_tl(t0, t0, t1);
5398 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5399 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5400 tcg_temp_free(t0);
5401 tcg_temp_free(t1);
5402 if (unlikely(Rc(ctx->opcode) != 0))
5403 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5404 }
5405
5406 /* sle - sle. */
5407 static void gen_sle(DisasContext *ctx)
5408 {
5409 TCGv t0 = tcg_temp_new();
5410 TCGv t1 = tcg_temp_new();
5411 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5412 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5413 tcg_gen_subfi_tl(t1, 32, t1);
5414 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5415 tcg_gen_or_tl(t1, t0, t1);
5416 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5417 gen_store_spr(SPR_MQ, t1);
5418 tcg_temp_free(t0);
5419 tcg_temp_free(t1);
5420 if (unlikely(Rc(ctx->opcode) != 0))
5421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5422 }
5423
5424 /* sleq - sleq. */
5425 static void gen_sleq(DisasContext *ctx)
5426 {
5427 TCGv t0 = tcg_temp_new();
5428 TCGv t1 = tcg_temp_new();
5429 TCGv t2 = tcg_temp_new();
5430 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5431 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5432 tcg_gen_shl_tl(t2, t2, t0);
5433 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5434 gen_load_spr(t1, SPR_MQ);
5435 gen_store_spr(SPR_MQ, t0);
5436 tcg_gen_and_tl(t0, t0, t2);
5437 tcg_gen_andc_tl(t1, t1, t2);
5438 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5439 tcg_temp_free(t0);
5440 tcg_temp_free(t1);
5441 tcg_temp_free(t2);
5442 if (unlikely(Rc(ctx->opcode) != 0))
5443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5444 }
5445
5446 /* sliq - sliq. */
5447 static void gen_sliq(DisasContext *ctx)
5448 {
5449 int sh = SH(ctx->opcode);
5450 TCGv t0 = tcg_temp_new();
5451 TCGv t1 = tcg_temp_new();
5452 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5453 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5454 tcg_gen_or_tl(t1, t0, t1);
5455 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5456 gen_store_spr(SPR_MQ, t1);
5457 tcg_temp_free(t0);
5458 tcg_temp_free(t1);
5459 if (unlikely(Rc(ctx->opcode) != 0))
5460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5461 }
5462
5463 /* slliq - slliq. */
5464 static void gen_slliq(DisasContext *ctx)
5465 {
5466 int sh = SH(ctx->opcode);
5467 TCGv t0 = tcg_temp_new();
5468 TCGv t1 = tcg_temp_new();
5469 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5470 gen_load_spr(t1, SPR_MQ);
5471 gen_store_spr(SPR_MQ, t0);
5472 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5473 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5474 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5475 tcg_temp_free(t0);
5476 tcg_temp_free(t1);
5477 if (unlikely(Rc(ctx->opcode) != 0))
5478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5479 }
5480
5481 /* sllq - sllq. */
5482 static void gen_sllq(DisasContext *ctx)
5483 {
5484 TCGLabel *l1 = gen_new_label();
5485 TCGLabel *l2 = gen_new_label();
5486 TCGv t0 = tcg_temp_local_new();
5487 TCGv t1 = tcg_temp_local_new();
5488 TCGv t2 = tcg_temp_local_new();
5489 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5490 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5491 tcg_gen_shl_tl(t1, t1, t2);
5492 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5493 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5494 gen_load_spr(t0, SPR_MQ);
5495 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5496 tcg_gen_br(l2);
5497 gen_set_label(l1);
5498 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5499 gen_load_spr(t2, SPR_MQ);
5500 tcg_gen_andc_tl(t1, t2, t1);
5501 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5502 gen_set_label(l2);
5503 tcg_temp_free(t0);
5504 tcg_temp_free(t1);
5505 tcg_temp_free(t2);
5506 if (unlikely(Rc(ctx->opcode) != 0))
5507 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5508 }
5509
5510 /* slq - slq. */
5511 static void gen_slq(DisasContext *ctx)
5512 {
5513 TCGLabel *l1 = gen_new_label();
5514 TCGv t0 = tcg_temp_new();
5515 TCGv t1 = tcg_temp_new();
5516 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5517 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5518 tcg_gen_subfi_tl(t1, 32, t1);
5519 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5520 tcg_gen_or_tl(t1, t0, t1);
5521 gen_store_spr(SPR_MQ, t1);
5522 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5523 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5524 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5525 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5526 gen_set_label(l1);
5527 tcg_temp_free(t0);
5528 tcg_temp_free(t1);
5529 if (unlikely(Rc(ctx->opcode) != 0))
5530 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5531 }
5532
5533 /* sraiq - sraiq. */
5534 static void gen_sraiq(DisasContext *ctx)
5535 {
5536 int sh = SH(ctx->opcode);
5537 TCGLabel *l1 = gen_new_label();
5538 TCGv t0 = tcg_temp_new();
5539 TCGv t1 = tcg_temp_new();
5540 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5541 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5542 tcg_gen_or_tl(t0, t0, t1);
5543 gen_store_spr(SPR_MQ, t0);
5544 tcg_gen_movi_tl(cpu_ca, 0);
5545 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5546 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5547 tcg_gen_movi_tl(cpu_ca, 1);
5548 gen_set_label(l1);
5549 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5550 tcg_temp_free(t0);
5551 tcg_temp_free(t1);
5552 if (unlikely(Rc(ctx->opcode) != 0))
5553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5554 }
5555
5556 /* sraq - sraq. */
5557 static void gen_sraq(DisasContext *ctx)
5558 {
5559 TCGLabel *l1 = gen_new_label();
5560 TCGLabel *l2 = gen_new_label();
5561 TCGv t0 = tcg_temp_new();
5562 TCGv t1 = tcg_temp_local_new();
5563 TCGv t2 = tcg_temp_local_new();
5564 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5565 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5566 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5567 tcg_gen_subfi_tl(t2, 32, t2);
5568 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5569 tcg_gen_or_tl(t0, t0, t2);
5570 gen_store_spr(SPR_MQ, t0);
5571 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5572 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5573 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5574 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5575 gen_set_label(l1);
5576 tcg_temp_free(t0);
5577 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5578 tcg_gen_movi_tl(cpu_ca, 0);
5579 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5580 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5581 tcg_gen_movi_tl(cpu_ca, 1);
5582 gen_set_label(l2);
5583 tcg_temp_free(t1);
5584 tcg_temp_free(t2);
5585 if (unlikely(Rc(ctx->opcode) != 0))
5586 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5587 }
5588
5589 /* sre - sre. */
5590 static void gen_sre(DisasContext *ctx)
5591 {
5592 TCGv t0 = tcg_temp_new();
5593 TCGv t1 = tcg_temp_new();
5594 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5595 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5596 tcg_gen_subfi_tl(t1, 32, t1);
5597 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5598 tcg_gen_or_tl(t1, t0, t1);
5599 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5600 gen_store_spr(SPR_MQ, t1);
5601 tcg_temp_free(t0);
5602 tcg_temp_free(t1);
5603 if (unlikely(Rc(ctx->opcode) != 0))
5604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5605 }
5606
5607 /* srea - srea. */
5608 static void gen_srea(DisasContext *ctx)
5609 {
5610 TCGv t0 = tcg_temp_new();
5611 TCGv t1 = tcg_temp_new();
5612 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5613 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5614 gen_store_spr(SPR_MQ, t0);
5615 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5616 tcg_temp_free(t0);
5617 tcg_temp_free(t1);
5618 if (unlikely(Rc(ctx->opcode) != 0))
5619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5620 }
5621
5622 /* sreq */
5623 static void gen_sreq(DisasContext *ctx)
5624 {
5625 TCGv t0 = tcg_temp_new();
5626 TCGv t1 = tcg_temp_new();
5627 TCGv t2 = tcg_temp_new();
5628 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5629 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5630 tcg_gen_shr_tl(t1, t1, t0);
5631 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5632 gen_load_spr(t2, SPR_MQ);
5633 gen_store_spr(SPR_MQ, t0);
5634 tcg_gen_and_tl(t0, t0, t1);
5635 tcg_gen_andc_tl(t2, t2, t1);
5636 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5637 tcg_temp_free(t0);
5638 tcg_temp_free(t1);
5639 tcg_temp_free(t2);
5640 if (unlikely(Rc(ctx->opcode) != 0))
5641 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5642 }
5643
5644 /* sriq */
5645 static void gen_sriq(DisasContext *ctx)
5646 {
5647 int sh = SH(ctx->opcode);
5648 TCGv t0 = tcg_temp_new();
5649 TCGv t1 = tcg_temp_new();
5650 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5651 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5652 tcg_gen_or_tl(t1, t0, t1);
5653 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5654 gen_store_spr(SPR_MQ, t1);
5655 tcg_temp_free(t0);
5656 tcg_temp_free(t1);
5657 if (unlikely(Rc(ctx->opcode) != 0))
5658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5659 }
5660
5661 /* srliq */
5662 static void gen_srliq(DisasContext *ctx)
5663 {
5664 int sh = SH(ctx->opcode);
5665 TCGv t0 = tcg_temp_new();
5666 TCGv t1 = tcg_temp_new();
5667 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5668 gen_load_spr(t1, SPR_MQ);
5669 gen_store_spr(SPR_MQ, t0);
5670 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5671 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5672 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5673 tcg_temp_free(t0);
5674 tcg_temp_free(t1);
5675 if (unlikely(Rc(ctx->opcode) != 0))
5676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5677 }
5678
5679 /* srlq */
5680 static void gen_srlq(DisasContext *ctx)
5681 {
5682 TCGLabel *l1 = gen_new_label();
5683 TCGLabel *l2 = gen_new_label();
5684 TCGv t0 = tcg_temp_local_new();
5685 TCGv t1 = tcg_temp_local_new();
5686 TCGv t2 = tcg_temp_local_new();
5687 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5688 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5689 tcg_gen_shr_tl(t2, t1, t2);
5690 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5691 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5692 gen_load_spr(t0, SPR_MQ);
5693 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5694 tcg_gen_br(l2);
5695 gen_set_label(l1);
5696 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5697 tcg_gen_and_tl(t0, t0, t2);
5698 gen_load_spr(t1, SPR_MQ);
5699 tcg_gen_andc_tl(t1, t1, t2);
5700 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5701 gen_set_label(l2);
5702 tcg_temp_free(t0);
5703 tcg_temp_free(t1);
5704 tcg_temp_free(t2);
5705 if (unlikely(Rc(ctx->opcode) != 0))
5706 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5707 }
5708
5709 /* srq */
5710 static void gen_srq(DisasContext *ctx)
5711 {
5712 TCGLabel *l1 = gen_new_label();
5713 TCGv t0 = tcg_temp_new();
5714 TCGv t1 = tcg_temp_new();
5715 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5716 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5717 tcg_gen_subfi_tl(t1, 32, t1);
5718 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5719 tcg_gen_or_tl(t1, t0, t1);
5720 gen_store_spr(SPR_MQ, t1);
5721 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5722 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5723 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5724 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5725 gen_set_label(l1);
5726 tcg_temp_free(t0);
5727 tcg_temp_free(t1);
5728 if (unlikely(Rc(ctx->opcode) != 0))
5729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5730 }
5731
5732 /* PowerPC 602 specific instructions */
5733
5734 /* dsa */
5735 static void gen_dsa(DisasContext *ctx)
5736 {
5737 /* XXX: TODO */
5738 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5739 }
5740
5741 /* esa */
5742 static void gen_esa(DisasContext *ctx)
5743 {
5744 /* XXX: TODO */
5745 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5746 }
5747
5748 /* mfrom */
5749 static void gen_mfrom(DisasContext *ctx)
5750 {
5751 #if defined(CONFIG_USER_ONLY)
5752 GEN_PRIV;
5753 #else
5754 CHK_SV;
5755 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5756 #endif /* defined(CONFIG_USER_ONLY) */
5757 }
5758
5759 /* 602 - 603 - G2 TLB management */
5760
5761 /* tlbld */
5762 static void gen_tlbld_6xx(DisasContext *ctx)
5763 {
5764 #if defined(CONFIG_USER_ONLY)
5765 GEN_PRIV;
5766 #else
5767 CHK_SV;
5768 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5769 #endif /* defined(CONFIG_USER_ONLY) */
5770 }
5771
5772 /* tlbli */
5773 static void gen_tlbli_6xx(DisasContext *ctx)
5774 {
5775 #if defined(CONFIG_USER_ONLY)
5776 GEN_PRIV;
5777 #else
5778 CHK_SV;
5779 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5780 #endif /* defined(CONFIG_USER_ONLY) */
5781 }
5782
5783 /* 74xx TLB management */
5784
5785 /* tlbld */
5786 static void gen_tlbld_74xx(DisasContext *ctx)
5787 {
5788 #if defined(CONFIG_USER_ONLY)
5789 GEN_PRIV;
5790 #else
5791 CHK_SV;
5792 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5793 #endif /* defined(CONFIG_USER_ONLY) */
5794 }
5795
5796 /* tlbli */
5797 static void gen_tlbli_74xx(DisasContext *ctx)
5798 {
5799 #if defined(CONFIG_USER_ONLY)
5800 GEN_PRIV;
5801 #else
5802 CHK_SV;
5803 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5804 #endif /* defined(CONFIG_USER_ONLY) */
5805 }
5806
5807 /* POWER instructions not in PowerPC 601 */
5808
5809 /* clf */
5810 static void gen_clf(DisasContext *ctx)
5811 {
5812 /* Cache line flush: implemented as no-op */
5813 }
5814
5815 /* cli */
5816 static void gen_cli(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 GEN_PRIV;
5820 #else
5821 /* Cache line invalidate: privileged and treated as no-op */
5822 CHK_SV;
5823 #endif /* defined(CONFIG_USER_ONLY) */
5824 }
5825
5826 /* dclst */
5827 static void gen_dclst(DisasContext *ctx)
5828 {
5829 /* Data cache line store: treated as no-op */
5830 }
5831
5832 static void gen_mfsri(DisasContext *ctx)
5833 {
5834 #if defined(CONFIG_USER_ONLY)
5835 GEN_PRIV;
5836 #else
5837 int ra = rA(ctx->opcode);
5838 int rd = rD(ctx->opcode);
5839 TCGv t0;
5840
5841 CHK_SV;
5842 t0 = tcg_temp_new();
5843 gen_addr_reg_index(ctx, t0);
5844 tcg_gen_shri_tl(t0, t0, 28);
5845 tcg_gen_andi_tl(t0, t0, 0xF);
5846 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5847 tcg_temp_free(t0);
5848 if (ra != 0 && ra != rd)
5849 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5850 #endif /* defined(CONFIG_USER_ONLY) */
5851 }
5852
5853 static void gen_rac(DisasContext *ctx)
5854 {
5855 #if defined(CONFIG_USER_ONLY)
5856 GEN_PRIV;
5857 #else
5858 TCGv t0;
5859
5860 CHK_SV;
5861 t0 = tcg_temp_new();
5862 gen_addr_reg_index(ctx, t0);
5863 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5864 tcg_temp_free(t0);
5865 #endif /* defined(CONFIG_USER_ONLY) */
5866 }
5867
5868 static void gen_rfsvc(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 GEN_PRIV;
5872 #else
5873 CHK_SV;
5874
5875 gen_helper_rfsvc(cpu_env);
5876 gen_sync_exception(ctx);
5877 #endif /* defined(CONFIG_USER_ONLY) */
5878 }
5879
5880 /* svc is not implemented for now */
5881
5882 /* POWER2 specific instructions */
5883 /* Quad manipulation (load/store two floats at a time) */
5884
5885 /* lfq */
5886 static void gen_lfq(DisasContext *ctx)
5887 {
5888 int rd = rD(ctx->opcode);
5889 TCGv t0;
5890 gen_set_access_type(ctx, ACCESS_FLOAT);
5891 t0 = tcg_temp_new();
5892 gen_addr_imm_index(ctx, t0, 0);
5893 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5894 gen_addr_add(ctx, t0, t0, 8);
5895 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5896 tcg_temp_free(t0);
5897 }
5898
5899 /* lfqu */
5900 static void gen_lfqu(DisasContext *ctx)
5901 {
5902 int ra = rA(ctx->opcode);
5903 int rd = rD(ctx->opcode);
5904 TCGv t0, t1;
5905 gen_set_access_type(ctx, ACCESS_FLOAT);
5906 t0 = tcg_temp_new();
5907 t1 = tcg_temp_new();
5908 gen_addr_imm_index(ctx, t0, 0);
5909 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5910 gen_addr_add(ctx, t1, t0, 8);
5911 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5912 if (ra != 0)
5913 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5914 tcg_temp_free(t0);
5915 tcg_temp_free(t1);
5916 }
5917
5918 /* lfqux */
5919 static void gen_lfqux(DisasContext *ctx)
5920 {
5921 int ra = rA(ctx->opcode);
5922 int rd = rD(ctx->opcode);
5923 gen_set_access_type(ctx, ACCESS_FLOAT);
5924 TCGv t0, t1;
5925 t0 = tcg_temp_new();
5926 gen_addr_reg_index(ctx, t0);
5927 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5928 t1 = tcg_temp_new();
5929 gen_addr_add(ctx, t1, t0, 8);
5930 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5931 tcg_temp_free(t1);
5932 if (ra != 0)
5933 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5934 tcg_temp_free(t0);
5935 }
5936
5937 /* lfqx */
5938 static void gen_lfqx(DisasContext *ctx)
5939 {
5940 int rd = rD(ctx->opcode);
5941 TCGv t0;
5942 gen_set_access_type(ctx, ACCESS_FLOAT);
5943 t0 = tcg_temp_new();
5944 gen_addr_reg_index(ctx, t0);
5945 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5946 gen_addr_add(ctx, t0, t0, 8);
5947 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5948 tcg_temp_free(t0);
5949 }
5950
5951 /* stfq */
5952 static void gen_stfq(DisasContext *ctx)
5953 {
5954 int rd = rD(ctx->opcode);
5955 TCGv t0;
5956 gen_set_access_type(ctx, ACCESS_FLOAT);
5957 t0 = tcg_temp_new();
5958 gen_addr_imm_index(ctx, t0, 0);
5959 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5960 gen_addr_add(ctx, t0, t0, 8);
5961 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5962 tcg_temp_free(t0);
5963 }
5964
5965 /* stfqu */
5966 static void gen_stfqu(DisasContext *ctx)
5967 {
5968 int ra = rA(ctx->opcode);
5969 int rd = rD(ctx->opcode);
5970 TCGv t0, t1;
5971 gen_set_access_type(ctx, ACCESS_FLOAT);
5972 t0 = tcg_temp_new();
5973 gen_addr_imm_index(ctx, t0, 0);
5974 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5975 t1 = tcg_temp_new();
5976 gen_addr_add(ctx, t1, t0, 8);
5977 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5978 tcg_temp_free(t1);
5979 if (ra != 0)
5980 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5981 tcg_temp_free(t0);
5982 }
5983
5984 /* stfqux */
5985 static void gen_stfqux(DisasContext *ctx)
5986 {
5987 int ra = rA(ctx->opcode);
5988 int rd = rD(ctx->opcode);
5989 TCGv t0, t1;
5990 gen_set_access_type(ctx, ACCESS_FLOAT);
5991 t0 = tcg_temp_new();
5992 gen_addr_reg_index(ctx, t0);
5993 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5994 t1 = tcg_temp_new();
5995 gen_addr_add(ctx, t1, t0, 8);
5996 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5997 tcg_temp_free(t1);
5998 if (ra != 0)
5999 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6000 tcg_temp_free(t0);
6001 }
6002
6003 /* stfqx */
6004 static void gen_stfqx(DisasContext *ctx)
6005 {
6006 int rd = rD(ctx->opcode);
6007 TCGv t0;
6008 gen_set_access_type(ctx, ACCESS_FLOAT);
6009 t0 = tcg_temp_new();
6010 gen_addr_reg_index(ctx, t0);
6011 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6012 gen_addr_add(ctx, t0, t0, 8);
6013 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6014 tcg_temp_free(t0);
6015 }
6016
6017 /* BookE specific instructions */
6018
6019 /* XXX: not implemented on 440 ? */
6020 static void gen_mfapidi(DisasContext *ctx)
6021 {
6022 /* XXX: TODO */
6023 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6024 }
6025
6026 /* XXX: not implemented on 440 ? */
6027 static void gen_tlbiva(DisasContext *ctx)
6028 {
6029 #if defined(CONFIG_USER_ONLY)
6030 GEN_PRIV;
6031 #else
6032 TCGv t0;
6033
6034 CHK_SV;
6035 t0 = tcg_temp_new();
6036 gen_addr_reg_index(ctx, t0);
6037 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6038 tcg_temp_free(t0);
6039 #endif /* defined(CONFIG_USER_ONLY) */
6040 }
6041
6042 /* All 405 MAC instructions are translated here */
6043 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6044 int ra, int rb, int rt, int Rc)
6045 {
6046 TCGv t0, t1;
6047
6048 t0 = tcg_temp_local_new();
6049 t1 = tcg_temp_local_new();
6050
6051 switch (opc3 & 0x0D) {
6052 case 0x05:
6053 /* macchw - macchw. - macchwo - macchwo. */
6054 /* macchws - macchws. - macchwso - macchwso. */
6055 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6056 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6057 /* mulchw - mulchw. */
6058 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6059 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6060 tcg_gen_ext16s_tl(t1, t1);
6061 break;
6062 case 0x04:
6063 /* macchwu - macchwu. - macchwuo - macchwuo. */
6064 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6065 /* mulchwu - mulchwu. */
6066 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6067 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6068 tcg_gen_ext16u_tl(t1, t1);
6069 break;
6070 case 0x01:
6071 /* machhw - machhw. - machhwo - machhwo. */
6072 /* machhws - machhws. - machhwso - machhwso. */
6073 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6074 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6075 /* mulhhw - mulhhw. */
6076 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6077 tcg_gen_ext16s_tl(t0, t0);
6078 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6079 tcg_gen_ext16s_tl(t1, t1);
6080 break;
6081 case 0x00:
6082 /* machhwu - machhwu. - machhwuo - machhwuo. */
6083 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6084 /* mulhhwu - mulhhwu. */
6085 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6086 tcg_gen_ext16u_tl(t0, t0);
6087 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6088 tcg_gen_ext16u_tl(t1, t1);
6089 break;
6090 case 0x0D:
6091 /* maclhw - maclhw. - maclhwo - maclhwo. */
6092 /* maclhws - maclhws. - maclhwso - maclhwso. */
6093 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6094 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6095 /* mullhw - mullhw. */
6096 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6097 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6098 break;
6099 case 0x0C:
6100 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6101 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6102 /* mullhwu - mullhwu. */
6103 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6104 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6105 break;
6106 }
6107 if (opc2 & 0x04) {
6108 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6109 tcg_gen_mul_tl(t1, t0, t1);
6110 if (opc2 & 0x02) {
6111 /* nmultiply-and-accumulate (0x0E) */
6112 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6113 } else {
6114 /* multiply-and-accumulate (0x0C) */
6115 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6116 }
6117
6118 if (opc3 & 0x12) {
6119 /* Check overflow and/or saturate */
6120 TCGLabel *l1 = gen_new_label();
6121
6122 if (opc3 & 0x10) {
6123 /* Start with XER OV disabled, the most likely case */
6124 tcg_gen_movi_tl(cpu_ov, 0);
6125 }
6126 if (opc3 & 0x01) {
6127 /* Signed */
6128 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6129 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6130 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6131 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6132 if (opc3 & 0x02) {
6133 /* Saturate */
6134 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6135 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6136 }
6137 } else {
6138 /* Unsigned */
6139 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6140 if (opc3 & 0x02) {
6141 /* Saturate */
6142 tcg_gen_movi_tl(t0, UINT32_MAX);
6143 }
6144 }
6145 if (opc3 & 0x10) {
6146 /* Check overflow */
6147 tcg_gen_movi_tl(cpu_ov, 1);
6148 tcg_gen_movi_tl(cpu_so, 1);
6149 }
6150 gen_set_label(l1);
6151 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6152 }
6153 } else {
6154 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6155 }
6156 tcg_temp_free(t0);
6157 tcg_temp_free(t1);
6158 if (unlikely(Rc) != 0) {
6159 /* Update Rc0 */
6160 gen_set_Rc0(ctx, cpu_gpr[rt]);
6161 }
6162 }
6163
6164 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6165 static void glue(gen_, name)(DisasContext *ctx) \
6166 { \
6167 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6168 rD(ctx->opcode), Rc(ctx->opcode)); \
6169 }
6170
6171 /* macchw - macchw. */
6172 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6173 /* macchwo - macchwo. */
6174 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6175 /* macchws - macchws. */
6176 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6177 /* macchwso - macchwso. */
6178 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6179 /* macchwsu - macchwsu. */
6180 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6181 /* macchwsuo - macchwsuo. */
6182 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6183 /* macchwu - macchwu. */
6184 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6185 /* macchwuo - macchwuo. */
6186 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6187 /* machhw - machhw. */
6188 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6189 /* machhwo - machhwo. */
6190 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6191 /* machhws - machhws. */
6192 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6193 /* machhwso - machhwso. */
6194 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6195 /* machhwsu - machhwsu. */
6196 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6197 /* machhwsuo - machhwsuo. */
6198 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6199 /* machhwu - machhwu. */
6200 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6201 /* machhwuo - machhwuo. */
6202 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6203 /* maclhw - maclhw. */
6204 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6205 /* maclhwo - maclhwo. */
6206 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6207 /* maclhws - maclhws. */
6208 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6209 /* maclhwso - maclhwso. */
6210 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6211 /* maclhwu - maclhwu. */
6212 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6213 /* maclhwuo - maclhwuo. */
6214 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6215 /* maclhwsu - maclhwsu. */
6216 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6217 /* maclhwsuo - maclhwsuo. */
6218 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6219 /* nmacchw - nmacchw. */
6220 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6221 /* nmacchwo - nmacchwo. */
6222 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6223 /* nmacchws - nmacchws. */
6224 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6225 /* nmacchwso - nmacchwso. */
6226 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6227 /* nmachhw - nmachhw. */
6228 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6229 /* nmachhwo - nmachhwo. */
6230 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6231 /* nmachhws - nmachhws. */
6232 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6233 /* nmachhwso - nmachhwso. */
6234 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6235 /* nmaclhw - nmaclhw. */
6236 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6237 /* nmaclhwo - nmaclhwo. */
6238 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6239 /* nmaclhws - nmaclhws. */
6240 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6241 /* nmaclhwso - nmaclhwso. */
6242 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6243
6244 /* mulchw - mulchw. */
6245 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6246 /* mulchwu - mulchwu. */
6247 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6248 /* mulhhw - mulhhw. */
6249 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6250 /* mulhhwu - mulhhwu. */
6251 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6252 /* mullhw - mullhw. */
6253 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6254 /* mullhwu - mullhwu. */
6255 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6256
6257 /* mfdcr */
6258 static void gen_mfdcr(DisasContext *ctx)
6259 {
6260 #if defined(CONFIG_USER_ONLY)
6261 GEN_PRIV;
6262 #else
6263 TCGv dcrn;
6264
6265 CHK_SV;
6266 /* NIP cannot be restored if the memory exception comes from an helper */
6267 gen_update_nip(ctx, ctx->nip - 4);
6268 dcrn = tcg_const_tl(SPR(ctx->opcode));
6269 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6270 tcg_temp_free(dcrn);
6271 #endif /* defined(CONFIG_USER_ONLY) */
6272 }
6273
6274 /* mtdcr */
6275 static void gen_mtdcr(DisasContext *ctx)
6276 {
6277 #if defined(CONFIG_USER_ONLY)
6278 GEN_PRIV;
6279 #else
6280 TCGv dcrn;
6281
6282 CHK_SV;
6283 /* NIP cannot be restored if the memory exception comes from an helper */
6284 gen_update_nip(ctx, ctx->nip - 4);
6285 dcrn = tcg_const_tl(SPR(ctx->opcode));
6286 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6287 tcg_temp_free(dcrn);
6288 #endif /* defined(CONFIG_USER_ONLY) */
6289 }
6290
6291 /* mfdcrx */
6292 /* XXX: not implemented on 440 ? */
6293 static void gen_mfdcrx(DisasContext *ctx)
6294 {
6295 #if defined(CONFIG_USER_ONLY)
6296 GEN_PRIV;
6297 #else
6298 CHK_SV;
6299 /* NIP cannot be restored if the memory exception comes from an helper */
6300 gen_update_nip(ctx, ctx->nip - 4);
6301 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6302 cpu_gpr[rA(ctx->opcode)]);
6303 /* Note: Rc update flag set leads to undefined state of Rc0 */
6304 #endif /* defined(CONFIG_USER_ONLY) */
6305 }
6306
6307 /* mtdcrx */
6308 /* XXX: not implemented on 440 ? */
6309 static void gen_mtdcrx(DisasContext *ctx)
6310 {
6311 #if defined(CONFIG_USER_ONLY)
6312 GEN_PRIV;
6313 #else
6314 CHK_SV;
6315 /* NIP cannot be restored if the memory exception comes from an helper */
6316 gen_update_nip(ctx, ctx->nip - 4);
6317 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6318 cpu_gpr[rS(ctx->opcode)]);
6319 /* Note: Rc update flag set leads to undefined state of Rc0 */
6320 #endif /* defined(CONFIG_USER_ONLY) */
6321 }
6322
6323 /* mfdcrux (PPC 460) : user-mode access to DCR */
6324 static void gen_mfdcrux(DisasContext *ctx)
6325 {
6326 /* NIP cannot be restored if the memory exception comes from an helper */
6327 gen_update_nip(ctx, ctx->nip - 4);
6328 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6329 cpu_gpr[rA(ctx->opcode)]);
6330 /* Note: Rc update flag set leads to undefined state of Rc0 */
6331 }
6332
6333 /* mtdcrux (PPC 460) : user-mode access to DCR */
6334 static void gen_mtdcrux(DisasContext *ctx)
6335 {
6336 /* NIP cannot be restored if the memory exception comes from an helper */
6337 gen_update_nip(ctx, ctx->nip - 4);
6338 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6339 cpu_gpr[rS(ctx->opcode)]);
6340 /* Note: Rc update flag set leads to undefined state of Rc0 */
6341 }
6342
6343 /* dccci */
6344 static void gen_dccci(DisasContext *ctx)
6345 {
6346 CHK_SV;
6347 /* interpreted as no-op */
6348 }
6349
6350 /* dcread */
6351 static void gen_dcread(DisasContext *ctx)
6352 {
6353 #if defined(CONFIG_USER_ONLY)
6354 GEN_PRIV;
6355 #else
6356 TCGv EA, val;
6357
6358 CHK_SV;
6359 gen_set_access_type(ctx, ACCESS_CACHE);
6360 EA = tcg_temp_new();
6361 gen_addr_reg_index(ctx, EA);
6362 val = tcg_temp_new();
6363 gen_qemu_ld32u(ctx, val, EA);
6364 tcg_temp_free(val);
6365 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6366 tcg_temp_free(EA);
6367 #endif /* defined(CONFIG_USER_ONLY) */
6368 }
6369
6370 /* icbt */
6371 static void gen_icbt_40x(DisasContext *ctx)
6372 {
6373 /* interpreted as no-op */
6374 /* XXX: specification say this is treated as a load by the MMU
6375 * but does not generate any exception
6376 */
6377 }
6378
6379 /* iccci */
6380 static void gen_iccci(DisasContext *ctx)
6381 {
6382 CHK_SV;
6383 /* interpreted as no-op */
6384 }
6385
6386 /* icread */
6387 static void gen_icread(DisasContext *ctx)
6388 {
6389 CHK_SV;
6390 /* interpreted as no-op */
6391 }
6392
6393 /* rfci (supervisor only) */
6394 static void gen_rfci_40x(DisasContext *ctx)
6395 {
6396 #if defined(CONFIG_USER_ONLY)
6397 GEN_PRIV;
6398 #else
6399 CHK_SV;
6400 /* Restore CPU state */
6401 gen_helper_40x_rfci(cpu_env);
6402 gen_sync_exception(ctx);
6403 #endif /* defined(CONFIG_USER_ONLY) */
6404 }
6405
6406 static void gen_rfci(DisasContext *ctx)
6407 {
6408 #if defined(CONFIG_USER_ONLY)
6409 GEN_PRIV;
6410 #else
6411 CHK_SV;
6412 /* Restore CPU state */
6413 gen_helper_rfci(cpu_env);
6414 gen_sync_exception(ctx);
6415 #endif /* defined(CONFIG_USER_ONLY) */
6416 }
6417
6418 /* BookE specific */
6419
6420 /* XXX: not implemented on 440 ? */
6421 static void gen_rfdi(DisasContext *ctx)
6422 {
6423 #if defined(CONFIG_USER_ONLY)
6424 GEN_PRIV;
6425 #else
6426 CHK_SV;
6427 /* Restore CPU state */
6428 gen_helper_rfdi(cpu_env);
6429 gen_sync_exception(ctx);
6430 #endif /* defined(CONFIG_USER_ONLY) */
6431 }
6432
6433 /* XXX: not implemented on 440 ? */
6434 static void gen_rfmci(DisasContext *ctx)
6435 {
6436 #if defined(CONFIG_USER_ONLY)
6437 GEN_PRIV;
6438 #else
6439 CHK_SV;
6440 /* Restore CPU state */
6441 gen_helper_rfmci(cpu_env);
6442 gen_sync_exception(ctx);
6443 #endif /* defined(CONFIG_USER_ONLY) */
6444 }
6445
6446 /* TLB management - PowerPC 405 implementation */
6447
6448 /* tlbre */
6449 static void gen_tlbre_40x(DisasContext *ctx)
6450 {
6451 #if defined(CONFIG_USER_ONLY)
6452 GEN_PRIV;
6453 #else
6454 CHK_SV;
6455 switch (rB(ctx->opcode)) {
6456 case 0:
6457 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6458 cpu_gpr[rA(ctx->opcode)]);
6459 break;
6460 case 1:
6461 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6462 cpu_gpr[rA(ctx->opcode)]);
6463 break;
6464 default:
6465 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6466 break;
6467 }
6468 #endif /* defined(CONFIG_USER_ONLY) */
6469 }
6470
6471 /* tlbsx - tlbsx. */
6472 static void gen_tlbsx_40x(DisasContext *ctx)
6473 {
6474 #if defined(CONFIG_USER_ONLY)
6475 GEN_PRIV;
6476 #else
6477 TCGv t0;
6478
6479 CHK_SV;
6480 t0 = tcg_temp_new();
6481 gen_addr_reg_index(ctx, t0);
6482 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6483 tcg_temp_free(t0);
6484 if (Rc(ctx->opcode)) {
6485 TCGLabel *l1 = gen_new_label();
6486 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6487 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6488 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6489 gen_set_label(l1);
6490 }
6491 #endif /* defined(CONFIG_USER_ONLY) */
6492 }
6493
6494 /* tlbwe */
6495 static void gen_tlbwe_40x(DisasContext *ctx)
6496 {
6497 #if defined(CONFIG_USER_ONLY)
6498 GEN_PRIV;
6499 #else
6500 CHK_SV;
6501
6502 switch (rB(ctx->opcode)) {
6503 case 0:
6504 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6505 cpu_gpr[rS(ctx->opcode)]);
6506 break;
6507 case 1:
6508 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6509 cpu_gpr[rS(ctx->opcode)]);
6510 break;
6511 default:
6512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6513 break;
6514 }
6515 #endif /* defined(CONFIG_USER_ONLY) */
6516 }
6517
6518 /* TLB management - PowerPC 440 implementation */
6519
6520 /* tlbre */
6521 static void gen_tlbre_440(DisasContext *ctx)
6522 {
6523 #if defined(CONFIG_USER_ONLY)
6524 GEN_PRIV;
6525 #else
6526 CHK_SV;
6527
6528 switch (rB(ctx->opcode)) {
6529 case 0:
6530 case 1:
6531 case 2:
6532 {
6533 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6534 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6535 t0, cpu_gpr[rA(ctx->opcode)]);
6536 tcg_temp_free_i32(t0);
6537 }
6538 break;
6539 default:
6540 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6541 break;
6542 }
6543 #endif /* defined(CONFIG_USER_ONLY) */
6544 }
6545
6546 /* tlbsx - tlbsx. */
6547 static void gen_tlbsx_440(DisasContext *ctx)
6548 {
6549 #if defined(CONFIG_USER_ONLY)
6550 GEN_PRIV;
6551 #else
6552 TCGv t0;
6553
6554 CHK_SV;
6555 t0 = tcg_temp_new();
6556 gen_addr_reg_index(ctx, t0);
6557 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6558 tcg_temp_free(t0);
6559 if (Rc(ctx->opcode)) {
6560 TCGLabel *l1 = gen_new_label();
6561 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6562 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6563 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6564 gen_set_label(l1);
6565 }
6566 #endif /* defined(CONFIG_USER_ONLY) */
6567 }
6568
6569 /* tlbwe */
6570 static void gen_tlbwe_440(DisasContext *ctx)
6571 {
6572 #if defined(CONFIG_USER_ONLY)
6573 GEN_PRIV;
6574 #else
6575 CHK_SV;
6576 switch (rB(ctx->opcode)) {
6577 case 0:
6578 case 1:
6579 case 2:
6580 {
6581 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6582 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6583 cpu_gpr[rS(ctx->opcode)]);
6584 tcg_temp_free_i32(t0);
6585 }
6586 break;
6587 default:
6588 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6589 break;
6590 }
6591 #endif /* defined(CONFIG_USER_ONLY) */
6592 }
6593
6594 /* TLB management - PowerPC BookE 2.06 implementation */
6595
6596 /* tlbre */
6597 static void gen_tlbre_booke206(DisasContext *ctx)
6598 {
6599 #if defined(CONFIG_USER_ONLY)
6600 GEN_PRIV;
6601 #else
6602 CHK_SV;
6603 gen_helper_booke206_tlbre(cpu_env);
6604 #endif /* defined(CONFIG_USER_ONLY) */
6605 }
6606
6607 /* tlbsx - tlbsx. */
6608 static void gen_tlbsx_booke206(DisasContext *ctx)
6609 {
6610 #if defined(CONFIG_USER_ONLY)
6611 GEN_PRIV;
6612 #else
6613 TCGv t0;
6614
6615 CHK_SV;
6616 if (rA(ctx->opcode)) {
6617 t0 = tcg_temp_new();
6618 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6619 } else {
6620 t0 = tcg_const_tl(0);
6621 }
6622
6623 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6624 gen_helper_booke206_tlbsx(cpu_env, t0);
6625 tcg_temp_free(t0);
6626 #endif /* defined(CONFIG_USER_ONLY) */
6627 }
6628
6629 /* tlbwe */
6630 static void gen_tlbwe_booke206(DisasContext *ctx)
6631 {
6632 #if defined(CONFIG_USER_ONLY)
6633 GEN_PRIV;
6634 #else
6635 CHK_SV;
6636 gen_update_nip(ctx, ctx->nip - 4);
6637 gen_helper_booke206_tlbwe(cpu_env);
6638 #endif /* defined(CONFIG_USER_ONLY) */
6639 }
6640
6641 static void gen_tlbivax_booke206(DisasContext *ctx)
6642 {
6643 #if defined(CONFIG_USER_ONLY)
6644 GEN_PRIV;
6645 #else
6646 TCGv t0;
6647
6648 CHK_SV;
6649 t0 = tcg_temp_new();
6650 gen_addr_reg_index(ctx, t0);
6651 gen_helper_booke206_tlbivax(cpu_env, t0);
6652 tcg_temp_free(t0);
6653 #endif /* defined(CONFIG_USER_ONLY) */
6654 }
6655
6656 static void gen_tlbilx_booke206(DisasContext *ctx)
6657 {
6658 #if defined(CONFIG_USER_ONLY)
6659 GEN_PRIV;
6660 #else
6661 TCGv t0;
6662
6663 CHK_SV;
6664 t0 = tcg_temp_new();
6665 gen_addr_reg_index(ctx, t0);
6666
6667 switch((ctx->opcode >> 21) & 0x3) {
6668 case 0:
6669 gen_helper_booke206_tlbilx0(cpu_env, t0);
6670 break;
6671 case 1:
6672 gen_helper_booke206_tlbilx1(cpu_env, t0);
6673 break;
6674 case 3:
6675 gen_helper_booke206_tlbilx3(cpu_env, t0);
6676 break;
6677 default:
6678 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6679 break;
6680 }
6681
6682 tcg_temp_free(t0);
6683 #endif /* defined(CONFIG_USER_ONLY) */
6684 }
6685
6686
6687 /* wrtee */
6688 static void gen_wrtee(DisasContext *ctx)
6689 {
6690 #if defined(CONFIG_USER_ONLY)
6691 GEN_PRIV;
6692 #else
6693 TCGv t0;
6694
6695 CHK_SV;
6696 t0 = tcg_temp_new();
6697 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6698 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6699 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6700 tcg_temp_free(t0);
6701 /* Stop translation to have a chance to raise an exception
6702 * if we just set msr_ee to 1
6703 */
6704 gen_stop_exception(ctx);
6705 #endif /* defined(CONFIG_USER_ONLY) */
6706 }
6707
6708 /* wrteei */
6709 static void gen_wrteei(DisasContext *ctx)
6710 {
6711 #if defined(CONFIG_USER_ONLY)
6712 GEN_PRIV;
6713 #else
6714 CHK_SV;
6715 if (ctx->opcode & 0x00008000) {
6716 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6717 /* Stop translation to have a chance to raise an exception */
6718 gen_stop_exception(ctx);
6719 } else {
6720 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6721 }
6722 #endif /* defined(CONFIG_USER_ONLY) */
6723 }
6724
6725 /* PowerPC 440 specific instructions */
6726
6727 /* dlmzb */
6728 static void gen_dlmzb(DisasContext *ctx)
6729 {
6730 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6731 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6732 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6733 tcg_temp_free_i32(t0);
6734 }
6735
6736 /* mbar replaces eieio on 440 */
6737 static void gen_mbar(DisasContext *ctx)
6738 {
6739 /* interpreted as no-op */
6740 }
6741
6742 /* msync replaces sync on 440 */
6743 static void gen_msync_4xx(DisasContext *ctx)
6744 {
6745 /* interpreted as no-op */
6746 }
6747
6748 /* icbt */
6749 static void gen_icbt_440(DisasContext *ctx)
6750 {
6751 /* interpreted as no-op */
6752 /* XXX: specification say this is treated as a load by the MMU
6753 * but does not generate any exception
6754 */
6755 }
6756
6757 /* Embedded.Processor Control */
6758
6759 static void gen_msgclr(DisasContext *ctx)
6760 {
6761 #if defined(CONFIG_USER_ONLY)
6762 GEN_PRIV;
6763 #else
6764 CHK_SV;
6765 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6766 #endif /* defined(CONFIG_USER_ONLY) */
6767 }
6768
6769 static void gen_msgsnd(DisasContext *ctx)
6770 {
6771 #if defined(CONFIG_USER_ONLY)
6772 GEN_PRIV;
6773 #else
6774 CHK_SV;
6775 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6776 #endif /* defined(CONFIG_USER_ONLY) */
6777 }
6778
6779 /*** Altivec vector extension ***/
6780 /* Altivec registers moves */
6781
6782 static inline TCGv_ptr gen_avr_ptr(int reg)
6783 {
6784 TCGv_ptr r = tcg_temp_new_ptr();
6785 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6786 return r;
6787 }
6788
6789 #define GEN_VR_LDX(name, opc2, opc3) \
6790 static void glue(gen_, name)(DisasContext *ctx) \
6791 { \
6792 TCGv EA; \
6793 if (unlikely(!ctx->altivec_enabled)) { \
6794 gen_exception(ctx, POWERPC_EXCP_VPU); \
6795 return; \
6796 } \
6797 gen_set_access_type(ctx, ACCESS_INT); \
6798 EA = tcg_temp_new(); \
6799 gen_addr_reg_index(ctx, EA); \
6800 tcg_gen_andi_tl(EA, EA, ~0xf); \
6801 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6802 64-bit byteswap already. */ \
6803 if (ctx->le_mode) { \
6804 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6805 tcg_gen_addi_tl(EA, EA, 8); \
6806 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6807 } else { \
6808 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6809 tcg_gen_addi_tl(EA, EA, 8); \
6810 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6811 } \
6812 tcg_temp_free(EA); \
6813 }
6814
6815 #define GEN_VR_STX(name, opc2, opc3) \
6816 static void gen_st##name(DisasContext *ctx) \
6817 { \
6818 TCGv EA; \
6819 if (unlikely(!ctx->altivec_enabled)) { \
6820 gen_exception(ctx, POWERPC_EXCP_VPU); \
6821 return; \
6822 } \
6823 gen_set_access_type(ctx, ACCESS_INT); \
6824 EA = tcg_temp_new(); \
6825 gen_addr_reg_index(ctx, EA); \
6826 tcg_gen_andi_tl(EA, EA, ~0xf); \
6827 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6828 64-bit byteswap already. */ \
6829 if (ctx->le_mode) { \
6830 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6831 tcg_gen_addi_tl(EA, EA, 8); \
6832 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6833 } else { \
6834 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6835 tcg_gen_addi_tl(EA, EA, 8); \
6836 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6837 } \
6838 tcg_temp_free(EA); \
6839 }
6840
6841 #define GEN_VR_LVE(name, opc2, opc3, size) \
6842 static void gen_lve##name(DisasContext *ctx) \
6843 { \
6844 TCGv EA; \
6845 TCGv_ptr rs; \
6846 if (unlikely(!ctx->altivec_enabled)) { \
6847 gen_exception(ctx, POWERPC_EXCP_VPU); \
6848 return; \
6849 } \
6850 gen_set_access_type(ctx, ACCESS_INT); \
6851 EA = tcg_temp_new(); \
6852 gen_addr_reg_index(ctx, EA); \
6853 if (size > 1) { \
6854 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6855 } \
6856 rs = gen_avr_ptr(rS(ctx->opcode)); \
6857 gen_helper_lve##name(cpu_env, rs, EA); \
6858 tcg_temp_free(EA); \
6859 tcg_temp_free_ptr(rs); \
6860 }
6861
6862 #define GEN_VR_STVE(name, opc2, opc3, size) \
6863 static void gen_stve##name(DisasContext *ctx) \
6864 { \
6865 TCGv EA; \
6866 TCGv_ptr rs; \
6867 if (unlikely(!ctx->altivec_enabled)) { \
6868 gen_exception(ctx, POWERPC_EXCP_VPU); \
6869 return; \
6870 } \
6871 gen_set_access_type(ctx, ACCESS_INT); \
6872 EA = tcg_temp_new(); \
6873 gen_addr_reg_index(ctx, EA); \
6874 if (size > 1) { \
6875 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6876 } \
6877 rs = gen_avr_ptr(rS(ctx->opcode)); \
6878 gen_helper_stve##name(cpu_env, rs, EA); \
6879 tcg_temp_free(EA); \
6880 tcg_temp_free_ptr(rs); \
6881 }
6882
6883 GEN_VR_LDX(lvx, 0x07, 0x03);
6884 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6885 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6886
6887 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6888 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6889 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6890
6891 GEN_VR_STX(svx, 0x07, 0x07);
6892 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6893 GEN_VR_STX(svxl, 0x07, 0x0F);
6894
6895 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6896 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6897 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6898
6899 static void gen_lvsl(DisasContext *ctx)
6900 {
6901 TCGv_ptr rd;
6902 TCGv EA;
6903 if (unlikely(!ctx->altivec_enabled)) {
6904 gen_exception(ctx, POWERPC_EXCP_VPU);
6905 return;
6906 }
6907 EA = tcg_temp_new();
6908 gen_addr_reg_index(ctx, EA);
6909 rd = gen_avr_ptr(rD(ctx->opcode));
6910 gen_helper_lvsl(rd, EA);
6911 tcg_temp_free(EA);
6912 tcg_temp_free_ptr(rd);
6913 }
6914
6915 static void gen_lvsr(DisasContext *ctx)
6916 {
6917 TCGv_ptr rd;
6918 TCGv EA;
6919 if (unlikely(!ctx->altivec_enabled)) {
6920 gen_exception(ctx, POWERPC_EXCP_VPU);
6921 return;
6922 }
6923 EA = tcg_temp_new();
6924 gen_addr_reg_index(ctx, EA);
6925 rd = gen_avr_ptr(rD(ctx->opcode));
6926 gen_helper_lvsr(rd, EA);
6927 tcg_temp_free(EA);
6928 tcg_temp_free_ptr(rd);
6929 }
6930
6931 static void gen_mfvscr(DisasContext *ctx)
6932 {
6933 TCGv_i32 t;
6934 if (unlikely(!ctx->altivec_enabled)) {
6935 gen_exception(ctx, POWERPC_EXCP_VPU);
6936 return;
6937 }
6938 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6939 t = tcg_temp_new_i32();
6940 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6941 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6942 tcg_temp_free_i32(t);
6943 }
6944
6945 static void gen_mtvscr(DisasContext *ctx)
6946 {
6947 TCGv_ptr p;
6948 if (unlikely(!ctx->altivec_enabled)) {
6949 gen_exception(ctx, POWERPC_EXCP_VPU);
6950 return;
6951 }
6952 p = gen_avr_ptr(rB(ctx->opcode));
6953 gen_helper_mtvscr(cpu_env, p);
6954 tcg_temp_free_ptr(p);
6955 }
6956
6957 /* Logical operations */
6958 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6959 static void glue(gen_, name)(DisasContext *ctx) \
6960 { \
6961 if (unlikely(!ctx->altivec_enabled)) { \
6962 gen_exception(ctx, POWERPC_EXCP_VPU); \
6963 return; \
6964 } \
6965 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6966 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6967 }
6968
6969 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6970 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6971 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6972 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6973 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6974 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6975 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6976 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6977
6978 #define GEN_VXFORM(name, opc2, opc3) \
6979 static void glue(gen_, name)(DisasContext *ctx) \
6980 { \
6981 TCGv_ptr ra, rb, rd; \
6982 if (unlikely(!ctx->altivec_enabled)) { \
6983 gen_exception(ctx, POWERPC_EXCP_VPU); \
6984 return; \
6985 } \
6986 ra = gen_avr_ptr(rA(ctx->opcode)); \
6987 rb = gen_avr_ptr(rB(ctx->opcode)); \
6988 rd = gen_avr_ptr(rD(ctx->opcode)); \
6989 gen_helper_##name (rd, ra, rb); \
6990 tcg_temp_free_ptr(ra); \
6991 tcg_temp_free_ptr(rb); \
6992 tcg_temp_free_ptr(rd); \
6993 }
6994
6995 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6996 static void glue(gen_, name)(DisasContext *ctx) \
6997 { \
6998 TCGv_ptr ra, rb, rd; \
6999 if (unlikely(!ctx->altivec_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_VPU); \
7001 return; \
7002 } \
7003 ra = gen_avr_ptr(rA(ctx->opcode)); \
7004 rb = gen_avr_ptr(rB(ctx->opcode)); \
7005 rd = gen_avr_ptr(rD(ctx->opcode)); \
7006 gen_helper_##name(cpu_env, rd, ra, rb); \
7007 tcg_temp_free_ptr(ra); \
7008 tcg_temp_free_ptr(rb); \
7009 tcg_temp_free_ptr(rd); \
7010 }
7011
7012 #define GEN_VXFORM3(name, opc2, opc3) \
7013 static void glue(gen_, name)(DisasContext *ctx) \
7014 { \
7015 TCGv_ptr ra, rb, rc, rd; \
7016 if (unlikely(!ctx->altivec_enabled)) { \
7017 gen_exception(ctx, POWERPC_EXCP_VPU); \
7018 return; \
7019 } \
7020 ra = gen_avr_ptr(rA(ctx->opcode)); \
7021 rb = gen_avr_ptr(rB(ctx->opcode)); \
7022 rc = gen_avr_ptr(rC(ctx->opcode)); \
7023 rd = gen_avr_ptr(rD(ctx->opcode)); \
7024 gen_helper_##name(rd, ra, rb, rc); \
7025 tcg_temp_free_ptr(ra); \
7026 tcg_temp_free_ptr(rb); \
7027 tcg_temp_free_ptr(rc); \
7028 tcg_temp_free_ptr(rd); \
7029 }
7030
7031 /*
7032 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7033 * an opcode bit. In general, these pairs come from different
7034 * versions of the ISA, so we must also support a pair of flags for
7035 * each instruction.
7036 */
7037 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7038 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7039 { \
7040 if ((Rc(ctx->opcode) == 0) && \
7041 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7042 gen_##name0(ctx); \
7043 } else if ((Rc(ctx->opcode) == 1) && \
7044 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7045 gen_##name1(ctx); \
7046 } else { \
7047 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7048 } \
7049 }
7050
7051 GEN_VXFORM(vaddubm, 0, 0);
7052 GEN_VXFORM(vadduhm, 0, 1);
7053 GEN_VXFORM(vadduwm, 0, 2);
7054 GEN_VXFORM(vaddudm, 0, 3);
7055 GEN_VXFORM(vsububm, 0, 16);
7056 GEN_VXFORM(vsubuhm, 0, 17);
7057 GEN_VXFORM(vsubuwm, 0, 18);
7058 GEN_VXFORM(vsubudm, 0, 19);
7059 GEN_VXFORM(vmaxub, 1, 0);
7060 GEN_VXFORM(vmaxuh, 1, 1);
7061 GEN_VXFORM(vmaxuw, 1, 2);
7062 GEN_VXFORM(vmaxud, 1, 3);
7063 GEN_VXFORM(vmaxsb, 1, 4);
7064 GEN_VXFORM(vmaxsh, 1, 5);
7065 GEN_VXFORM(vmaxsw, 1, 6);
7066 GEN_VXFORM(vmaxsd, 1, 7);
7067 GEN_VXFORM(vminub, 1, 8);
7068 GEN_VXFORM(vminuh, 1, 9);
7069 GEN_VXFORM(vminuw, 1, 10);
7070 GEN_VXFORM(vminud, 1, 11);
7071 GEN_VXFORM(vminsb, 1, 12);
7072 GEN_VXFORM(vminsh, 1, 13);
7073 GEN_VXFORM(vminsw, 1, 14);
7074 GEN_VXFORM(vminsd, 1, 15);
7075 GEN_VXFORM(vavgub, 1, 16);
7076 GEN_VXFORM(vavguh, 1, 17);
7077 GEN_VXFORM(vavguw, 1, 18);
7078 GEN_VXFORM(vavgsb, 1, 20);
7079 GEN_VXFORM(vavgsh, 1, 21);
7080 GEN_VXFORM(vavgsw, 1, 22);
7081 GEN_VXFORM(vmrghb, 6, 0);
7082 GEN_VXFORM(vmrghh, 6, 1);
7083 GEN_VXFORM(vmrghw, 6, 2);
7084 GEN_VXFORM(vmrglb, 6, 4);
7085 GEN_VXFORM(vmrglh, 6, 5);
7086 GEN_VXFORM(vmrglw, 6, 6);
7087
7088 static void gen_vmrgew(DisasContext *ctx)
7089 {
7090 TCGv_i64 tmp;
7091 int VT, VA, VB;
7092 if (unlikely(!ctx->altivec_enabled)) {
7093 gen_exception(ctx, POWERPC_EXCP_VPU);
7094 return;
7095 }
7096 VT = rD(ctx->opcode);
7097 VA = rA(ctx->opcode);
7098 VB = rB(ctx->opcode);
7099 tmp = tcg_temp_new_i64();
7100 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7101 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7102 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7103 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7104 tcg_temp_free_i64(tmp);
7105 }
7106
7107 static void gen_vmrgow(DisasContext *ctx)
7108 {
7109 int VT, VA, VB;
7110 if (unlikely(!ctx->altivec_enabled)) {
7111 gen_exception(ctx, POWERPC_EXCP_VPU);
7112 return;
7113 }
7114 VT = rD(ctx->opcode);
7115 VA = rA(ctx->opcode);
7116 VB = rB(ctx->opcode);
7117
7118 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7119 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7120 }
7121
7122 GEN_VXFORM(vmuloub, 4, 0);
7123 GEN_VXFORM(vmulouh, 4, 1);
7124 GEN_VXFORM(vmulouw, 4, 2);
7125 GEN_VXFORM(vmuluwm, 4, 2);
7126 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7127 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7128 GEN_VXFORM(vmulosb, 4, 4);
7129 GEN_VXFORM(vmulosh, 4, 5);
7130 GEN_VXFORM(vmulosw, 4, 6);
7131 GEN_VXFORM(vmuleub, 4, 8);
7132 GEN_VXFORM(vmuleuh, 4, 9);
7133 GEN_VXFORM(vmuleuw, 4, 10);
7134 GEN_VXFORM(vmulesb, 4, 12);
7135 GEN_VXFORM(vmulesh, 4, 13);
7136 GEN_VXFORM(vmulesw, 4, 14);
7137 GEN_VXFORM(vslb, 2, 4);
7138 GEN_VXFORM(vslh, 2, 5);
7139 GEN_VXFORM(vslw, 2, 6);
7140 GEN_VXFORM(vsld, 2, 23);
7141 GEN_VXFORM(vsrb, 2, 8);
7142 GEN_VXFORM(vsrh, 2, 9);
7143 GEN_VXFORM(vsrw, 2, 10);
7144 GEN_VXFORM(vsrd, 2, 27);
7145 GEN_VXFORM(vsrab, 2, 12);
7146 GEN_VXFORM(vsrah, 2, 13);
7147 GEN_VXFORM(vsraw, 2, 14);
7148 GEN_VXFORM(vsrad, 2, 15);
7149 GEN_VXFORM(vslo, 6, 16);
7150 GEN_VXFORM(vsro, 6, 17);
7151 GEN_VXFORM(vaddcuw, 0, 6);
7152 GEN_VXFORM(vsubcuw, 0, 22);
7153 GEN_VXFORM_ENV(vaddubs, 0, 8);
7154 GEN_VXFORM_ENV(vadduhs, 0, 9);
7155 GEN_VXFORM_ENV(vadduws, 0, 10);
7156 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7157 GEN_VXFORM_ENV(vaddshs, 0, 13);
7158 GEN_VXFORM_ENV(vaddsws, 0, 14);
7159 GEN_VXFORM_ENV(vsububs, 0, 24);
7160 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7161 GEN_VXFORM_ENV(vsubuws, 0, 26);
7162 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7163 GEN_VXFORM_ENV(vsubshs, 0, 29);
7164 GEN_VXFORM_ENV(vsubsws, 0, 30);
7165 GEN_VXFORM(vadduqm, 0, 4);
7166 GEN_VXFORM(vaddcuq, 0, 5);
7167 GEN_VXFORM3(vaddeuqm, 30, 0);
7168 GEN_VXFORM3(vaddecuq, 30, 0);
7169 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7170 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7171 GEN_VXFORM(vsubuqm, 0, 20);
7172 GEN_VXFORM(vsubcuq, 0, 21);
7173 GEN_VXFORM3(vsubeuqm, 31, 0);
7174 GEN_VXFORM3(vsubecuq, 31, 0);
7175 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7176 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7177 GEN_VXFORM(vrlb, 2, 0);
7178 GEN_VXFORM(vrlh, 2, 1);
7179 GEN_VXFORM(vrlw, 2, 2);
7180 GEN_VXFORM(vrld, 2, 3);
7181 GEN_VXFORM(vsl, 2, 7);
7182 GEN_VXFORM(vsr, 2, 11);
7183 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7184 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7185 GEN_VXFORM_ENV(vpkudum, 7, 17);
7186 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7187 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7188 GEN_VXFORM_ENV(vpkudus, 7, 19);
7189 GEN_VXFORM_ENV(vpkshus, 7, 4);
7190 GEN_VXFORM_ENV(vpkswus, 7, 5);
7191 GEN_VXFORM_ENV(vpksdus, 7, 21);
7192 GEN_VXFORM_ENV(vpkshss, 7, 6);
7193 GEN_VXFORM_ENV(vpkswss, 7, 7);
7194 GEN_VXFORM_ENV(vpksdss, 7, 23);
7195 GEN_VXFORM(vpkpx, 7, 12);
7196 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7197 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7198 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7199 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7200 GEN_VXFORM_ENV(vsumsws, 4, 30);
7201 GEN_VXFORM_ENV(vaddfp, 5, 0);
7202 GEN_VXFORM_ENV(vsubfp, 5, 1);
7203 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7204 GEN_VXFORM_ENV(vminfp, 5, 17);
7205
7206 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7207 static void glue(gen_, name)(DisasContext *ctx) \
7208 { \
7209 TCGv_ptr ra, rb, rd; \
7210 if (unlikely(!ctx->altivec_enabled)) { \
7211 gen_exception(ctx, POWERPC_EXCP_VPU); \
7212 return; \
7213 } \
7214 ra = gen_avr_ptr(rA(ctx->opcode)); \
7215 rb = gen_avr_ptr(rB(ctx->opcode)); \
7216 rd = gen_avr_ptr(rD(ctx->opcode)); \
7217 gen_helper_##opname(cpu_env, rd, ra, rb); \
7218 tcg_temp_free_ptr(ra); \
7219 tcg_temp_free_ptr(rb); \
7220 tcg_temp_free_ptr(rd); \
7221 }
7222
7223 #define GEN_VXRFORM(name, opc2, opc3) \
7224 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7225 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7226
7227 /*
7228 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7229 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7230 * come from different versions of the ISA, so we must also support a
7231 * pair of flags for each instruction.
7232 */
7233 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7234 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7235 { \
7236 if ((Rc(ctx->opcode) == 0) && \
7237 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7238 if (Rc21(ctx->opcode) == 0) { \
7239 gen_##name0(ctx); \
7240 } else { \
7241 gen_##name0##_(ctx); \
7242 } \
7243 } else if ((Rc(ctx->opcode) == 1) && \
7244 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7245 if (Rc21(ctx->opcode) == 0) { \
7246 gen_##name1(ctx); \
7247 } else { \
7248 gen_##name1##_(ctx); \
7249 } \
7250 } else { \
7251 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7252 } \
7253 }
7254
7255 GEN_VXRFORM(vcmpequb, 3, 0)
7256 GEN_VXRFORM(vcmpequh, 3, 1)
7257 GEN_VXRFORM(vcmpequw, 3, 2)
7258 GEN_VXRFORM(vcmpequd, 3, 3)
7259 GEN_VXRFORM(vcmpgtsb, 3, 12)
7260 GEN_VXRFORM(vcmpgtsh, 3, 13)
7261 GEN_VXRFORM(vcmpgtsw, 3, 14)
7262 GEN_VXRFORM(vcmpgtsd, 3, 15)
7263 GEN_VXRFORM(vcmpgtub, 3, 8)
7264 GEN_VXRFORM(vcmpgtuh, 3, 9)
7265 GEN_VXRFORM(vcmpgtuw, 3, 10)
7266 GEN_VXRFORM(vcmpgtud, 3, 11)
7267 GEN_VXRFORM(vcmpeqfp, 3, 3)
7268 GEN_VXRFORM(vcmpgefp, 3, 7)
7269 GEN_VXRFORM(vcmpgtfp, 3, 11)
7270 GEN_VXRFORM(vcmpbfp, 3, 15)
7271
7272 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7273 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7274 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7275 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7276 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7277 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7278
7279 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7280 static void glue(gen_, name)(DisasContext *ctx) \
7281 { \
7282 TCGv_ptr rd; \
7283 TCGv_i32 simm; \
7284 if (unlikely(!ctx->altivec_enabled)) { \
7285 gen_exception(ctx, POWERPC_EXCP_VPU); \
7286 return; \
7287 } \
7288 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7289 rd = gen_avr_ptr(rD(ctx->opcode)); \
7290 gen_helper_##name (rd, simm); \
7291 tcg_temp_free_i32(simm); \
7292 tcg_temp_free_ptr(rd); \
7293 }
7294
7295 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7296 GEN_VXFORM_SIMM(vspltish, 6, 13);
7297 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7298
7299 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7300 static void glue(gen_, name)(DisasContext *ctx) \
7301 { \
7302 TCGv_ptr rb, rd; \
7303 if (unlikely(!ctx->altivec_enabled)) { \
7304 gen_exception(ctx, POWERPC_EXCP_VPU); \
7305 return; \
7306 } \
7307 rb = gen_avr_ptr(rB(ctx->opcode)); \
7308 rd = gen_avr_ptr(rD(ctx->opcode)); \
7309 gen_helper_##name (rd, rb); \
7310 tcg_temp_free_ptr(rb); \
7311 tcg_temp_free_ptr(rd); \
7312 }
7313
7314 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7315 static void glue(gen_, name)(DisasContext *ctx) \
7316 { \
7317 TCGv_ptr rb, rd; \
7318 \
7319 if (unlikely(!ctx->altivec_enabled)) { \
7320 gen_exception(ctx, POWERPC_EXCP_VPU); \
7321 return; \
7322 } \
7323 rb = gen_avr_ptr(rB(ctx->opcode)); \
7324 rd = gen_avr_ptr(rD(ctx->opcode)); \
7325 gen_helper_##name(cpu_env, rd, rb); \
7326 tcg_temp_free_ptr(rb); \
7327 tcg_temp_free_ptr(rd); \
7328 }
7329
7330 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7331 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7332 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7333 GEN_VXFORM_NOA(vupklsb, 7, 10);
7334 GEN_VXFORM_NOA(vupklsh, 7, 11);
7335 GEN_VXFORM_NOA(vupklsw, 7, 27);
7336 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7337 GEN_VXFORM_NOA(vupklpx, 7, 15);
7338 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7339 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7340 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7341 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7342 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7343 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7344 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7345 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7346
7347 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7348 static void glue(gen_, name)(DisasContext *ctx) \
7349 { \
7350 TCGv_ptr rd; \
7351 TCGv_i32 simm; \
7352 if (unlikely(!ctx->altivec_enabled)) { \
7353 gen_exception(ctx, POWERPC_EXCP_VPU); \
7354 return; \
7355 } \
7356 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7357 rd = gen_avr_ptr(rD(ctx->opcode)); \
7358 gen_helper_##name (rd, simm); \
7359 tcg_temp_free_i32(simm); \
7360 tcg_temp_free_ptr(rd); \
7361 }
7362
7363 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7364 static void glue(gen_, name)(DisasContext *ctx) \
7365 { \
7366 TCGv_ptr rb, rd; \
7367 TCGv_i32 uimm; \
7368 if (unlikely(!ctx->altivec_enabled)) { \
7369 gen_exception(ctx, POWERPC_EXCP_VPU); \
7370 return; \
7371 } \
7372 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7373 rb = gen_avr_ptr(rB(ctx->opcode)); \
7374 rd = gen_avr_ptr(rD(ctx->opcode)); \
7375 gen_helper_##name (rd, rb, uimm); \
7376 tcg_temp_free_i32(uimm); \
7377 tcg_temp_free_ptr(rb); \
7378 tcg_temp_free_ptr(rd); \
7379 }
7380
7381 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7382 static void glue(gen_, name)(DisasContext *ctx) \
7383 { \
7384 TCGv_ptr rb, rd; \
7385 TCGv_i32 uimm; \
7386 \
7387 if (unlikely(!ctx->altivec_enabled)) { \
7388 gen_exception(ctx, POWERPC_EXCP_VPU); \
7389 return; \
7390 } \
7391 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7392 rb = gen_avr_ptr(rB(ctx->opcode)); \
7393 rd = gen_avr_ptr(rD(ctx->opcode)); \
7394 gen_helper_##name(cpu_env, rd, rb, uimm); \
7395 tcg_temp_free_i32(uimm); \
7396 tcg_temp_free_ptr(rb); \
7397 tcg_temp_free_ptr(rd); \
7398 }
7399
7400 GEN_VXFORM_UIMM(vspltb, 6, 8);
7401 GEN_VXFORM_UIMM(vsplth, 6, 9);
7402 GEN_VXFORM_UIMM(vspltw, 6, 10);
7403 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7404 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7405 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7406 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7407
7408 static void gen_vsldoi(DisasContext *ctx)
7409 {
7410 TCGv_ptr ra, rb, rd;
7411 TCGv_i32 sh;
7412 if (unlikely(!ctx->altivec_enabled)) {
7413 gen_exception(ctx, POWERPC_EXCP_VPU);
7414 return;
7415 }
7416 ra = gen_avr_ptr(rA(ctx->opcode));
7417 rb = gen_avr_ptr(rB(ctx->opcode));
7418 rd = gen_avr_ptr(rD(ctx->opcode));
7419 sh = tcg_const_i32(VSH(ctx->opcode));
7420 gen_helper_vsldoi (rd, ra, rb, sh);
7421 tcg_temp_free_ptr(ra);
7422 tcg_temp_free_ptr(rb);
7423 tcg_temp_free_ptr(rd);
7424 tcg_temp_free_i32(sh);
7425 }
7426
7427 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7428 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7429 { \
7430 TCGv_ptr ra, rb, rc, rd; \
7431 if (unlikely(!ctx->altivec_enabled)) { \
7432 gen_exception(ctx, POWERPC_EXCP_VPU); \
7433 return; \
7434 } \
7435 ra = gen_avr_ptr(rA(ctx->opcode)); \
7436 rb = gen_avr_ptr(rB(ctx->opcode)); \
7437 rc = gen_avr_ptr(rC(ctx->opcode)); \
7438 rd = gen_avr_ptr(rD(ctx->opcode)); \
7439 if (Rc(ctx->opcode)) { \
7440 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7441 } else { \
7442 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7443 } \
7444 tcg_temp_free_ptr(ra); \
7445 tcg_temp_free_ptr(rb); \
7446 tcg_temp_free_ptr(rc); \
7447 tcg_temp_free_ptr(rd); \
7448 }
7449
7450 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7451
7452 static void gen_vmladduhm(DisasContext *ctx)
7453 {
7454 TCGv_ptr ra, rb, rc, rd;
7455 if (unlikely(!ctx->altivec_enabled)) {
7456 gen_exception(ctx, POWERPC_EXCP_VPU);
7457 return;
7458 }
7459 ra = gen_avr_ptr(rA(ctx->opcode));
7460 rb = gen_avr_ptr(rB(ctx->opcode));
7461 rc = gen_avr_ptr(rC(ctx->opcode));
7462 rd = gen_avr_ptr(rD(ctx->opcode));
7463 gen_helper_vmladduhm(rd, ra, rb, rc);
7464 tcg_temp_free_ptr(ra);
7465 tcg_temp_free_ptr(rb);
7466 tcg_temp_free_ptr(rc);
7467 tcg_temp_free_ptr(rd);
7468 }
7469
7470 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7471 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7472 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7473 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7474 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7475
7476 GEN_VXFORM_NOA(vclzb, 1, 28)
7477 GEN_VXFORM_NOA(vclzh, 1, 29)
7478 GEN_VXFORM_NOA(vclzw, 1, 30)
7479 GEN_VXFORM_NOA(vclzd, 1, 31)
7480 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7481 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7482 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7483 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7484 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7485 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7486 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7487 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7488 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7489 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7490 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7491 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7492 GEN_VXFORM(vbpermq, 6, 21);
7493 GEN_VXFORM_NOA(vgbbd, 6, 20);
7494 GEN_VXFORM(vpmsumb, 4, 16)
7495 GEN_VXFORM(vpmsumh, 4, 17)
7496 GEN_VXFORM(vpmsumw, 4, 18)
7497 GEN_VXFORM(vpmsumd, 4, 19)
7498
7499 #define GEN_BCD(op) \
7500 static void gen_##op(DisasContext *ctx) \
7501 { \
7502 TCGv_ptr ra, rb, rd; \
7503 TCGv_i32 ps; \
7504 \
7505 if (unlikely(!ctx->altivec_enabled)) { \
7506 gen_exception(ctx, POWERPC_EXCP_VPU); \
7507 return; \
7508 } \
7509 \
7510 ra = gen_avr_ptr(rA(ctx->opcode)); \
7511 rb = gen_avr_ptr(rB(ctx->opcode)); \
7512 rd = gen_avr_ptr(rD(ctx->opcode)); \
7513 \
7514 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7515 \
7516 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7517 \
7518 tcg_temp_free_ptr(ra); \
7519 tcg_temp_free_ptr(rb); \
7520 tcg_temp_free_ptr(rd); \
7521 tcg_temp_free_i32(ps); \
7522 }
7523
7524 GEN_BCD(bcdadd)
7525 GEN_BCD(bcdsub)
7526
7527 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7528 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7529 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7530 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7531 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7532 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7533 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7534 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7535
7536 static void gen_vsbox(DisasContext *ctx)
7537 {
7538 TCGv_ptr ra, rd;
7539 if (unlikely(!ctx->altivec_enabled)) {
7540 gen_exception(ctx, POWERPC_EXCP_VPU);
7541 return;
7542 }
7543 ra = gen_avr_ptr(rA(ctx->opcode));
7544 rd = gen_avr_ptr(rD(ctx->opcode));
7545 gen_helper_vsbox(rd, ra);
7546 tcg_temp_free_ptr(ra);
7547 tcg_temp_free_ptr(rd);
7548 }
7549
7550 GEN_VXFORM(vcipher, 4, 20)
7551 GEN_VXFORM(vcipherlast, 4, 20)
7552 GEN_VXFORM(vncipher, 4, 21)
7553 GEN_VXFORM(vncipherlast, 4, 21)
7554
7555 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7556 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7557 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7558 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7559
7560 #define VSHASIGMA(op) \
7561 static void gen_##op(DisasContext *ctx) \
7562 { \
7563 TCGv_ptr ra, rd; \
7564 TCGv_i32 st_six; \
7565 if (unlikely(!ctx->altivec_enabled)) { \
7566 gen_exception(ctx, POWERPC_EXCP_VPU); \
7567 return; \
7568 } \
7569 ra = gen_avr_ptr(rA(ctx->opcode)); \
7570 rd = gen_avr_ptr(rD(ctx->opcode)); \
7571 st_six = tcg_const_i32(rB(ctx->opcode)); \
7572 gen_helper_##op(rd, ra, st_six); \
7573 tcg_temp_free_ptr(ra); \
7574 tcg_temp_free_ptr(rd); \
7575 tcg_temp_free_i32(st_six); \
7576 }
7577
7578 VSHASIGMA(vshasigmaw)
7579 VSHASIGMA(vshasigmad)
7580
7581 GEN_VXFORM3(vpermxor, 22, 0xFF)
7582 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7583 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7584
7585 /*** VSX extension ***/
7586
7587 static inline TCGv_i64 cpu_vsrh(int n)
7588 {
7589 if (n < 32) {
7590 return cpu_fpr[n];
7591 } else {
7592 return cpu_avrh[n-32];
7593 }
7594 }
7595
7596 static inline TCGv_i64 cpu_vsrl(int n)
7597 {
7598 if (n < 32) {
7599 return cpu_vsr[n];
7600 } else {
7601 return cpu_avrl[n-32];
7602 }
7603 }
7604
7605 #define VSX_LOAD_SCALAR(name, operation) \
7606 static void gen_##name(DisasContext *ctx) \
7607 { \
7608 TCGv EA; \
7609 if (unlikely(!ctx->vsx_enabled)) { \
7610 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7611 return; \
7612 } \
7613 gen_set_access_type(ctx, ACCESS_INT); \
7614 EA = tcg_temp_new(); \
7615 gen_addr_reg_index(ctx, EA); \
7616 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7617 /* NOTE: cpu_vsrl is undefined */ \
7618 tcg_temp_free(EA); \
7619 }
7620
7621 VSX_LOAD_SCALAR(lxsdx, ld64)
7622 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7623 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7624 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7625
7626 static void gen_lxvd2x(DisasContext *ctx)
7627 {
7628 TCGv EA;
7629 if (unlikely(!ctx->vsx_enabled)) {
7630 gen_exception(ctx, POWERPC_EXCP_VSXU);
7631 return;
7632 }
7633 gen_set_access_type(ctx, ACCESS_INT);
7634 EA = tcg_temp_new();
7635 gen_addr_reg_index(ctx, EA);
7636 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7637 tcg_gen_addi_tl(EA, EA, 8);
7638 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7639 tcg_temp_free(EA);
7640 }
7641
7642 static void gen_lxvdsx(DisasContext *ctx)
7643 {
7644 TCGv EA;
7645 if (unlikely(!ctx->vsx_enabled)) {
7646 gen_exception(ctx, POWERPC_EXCP_VSXU);
7647 return;
7648 }
7649 gen_set_access_type(ctx, ACCESS_INT);
7650 EA = tcg_temp_new();
7651 gen_addr_reg_index(ctx, EA);
7652 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7653 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7654 tcg_temp_free(EA);
7655 }
7656
7657 static void gen_lxvw4x(DisasContext *ctx)
7658 {
7659 TCGv EA;
7660 TCGv_i64 tmp;
7661 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7662 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7663 if (unlikely(!ctx->vsx_enabled)) {
7664 gen_exception(ctx, POWERPC_EXCP_VSXU);
7665 return;
7666 }
7667 gen_set_access_type(ctx, ACCESS_INT);
7668 EA = tcg_temp_new();
7669 tmp = tcg_temp_new_i64();
7670
7671 gen_addr_reg_index(ctx, EA);
7672 gen_qemu_ld32u_i64(ctx, tmp, EA);
7673 tcg_gen_addi_tl(EA, EA, 4);
7674 gen_qemu_ld32u_i64(ctx, xth, EA);
7675 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7676
7677 tcg_gen_addi_tl(EA, EA, 4);
7678 gen_qemu_ld32u_i64(ctx, tmp, EA);
7679 tcg_gen_addi_tl(EA, EA, 4);
7680 gen_qemu_ld32u_i64(ctx, xtl, EA);
7681 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7682
7683 tcg_temp_free(EA);
7684 tcg_temp_free_i64(tmp);
7685 }
7686
7687 #define VSX_STORE_SCALAR(name, operation) \
7688 static void gen_##name(DisasContext *ctx) \
7689 { \
7690 TCGv EA; \
7691 if (unlikely(!ctx->vsx_enabled)) { \
7692 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7693 return; \
7694 } \
7695 gen_set_access_type(ctx, ACCESS_INT); \
7696 EA = tcg_temp_new(); \
7697 gen_addr_reg_index(ctx, EA); \
7698 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7699 tcg_temp_free(EA); \
7700 }
7701
7702 VSX_STORE_SCALAR(stxsdx, st64)
7703 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7704 VSX_STORE_SCALAR(stxsspx, st32fs)
7705
7706 static void gen_stxvd2x(DisasContext *ctx)
7707 {
7708 TCGv EA;
7709 if (unlikely(!ctx->vsx_enabled)) {
7710 gen_exception(ctx, POWERPC_EXCP_VSXU);
7711 return;
7712 }
7713 gen_set_access_type(ctx, ACCESS_INT);
7714 EA = tcg_temp_new();
7715 gen_addr_reg_index(ctx, EA);
7716 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7717 tcg_gen_addi_tl(EA, EA, 8);
7718 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7719 tcg_temp_free(EA);
7720 }
7721
7722 static void gen_stxvw4x(DisasContext *ctx)
7723 {
7724 TCGv_i64 tmp;
7725 TCGv EA;
7726 if (unlikely(!ctx->vsx_enabled)) {
7727 gen_exception(ctx, POWERPC_EXCP_VSXU);
7728 return;
7729 }
7730 gen_set_access_type(ctx, ACCESS_INT);
7731 EA = tcg_temp_new();
7732 gen_addr_reg_index(ctx, EA);
7733 tmp = tcg_temp_new_i64();
7734
7735 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7736 gen_qemu_st32_i64(ctx, tmp, EA);
7737 tcg_gen_addi_tl(EA, EA, 4);
7738 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7739
7740 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7741 tcg_gen_addi_tl(EA, EA, 4);
7742 gen_qemu_st32_i64(ctx, tmp, EA);
7743 tcg_gen_addi_tl(EA, EA, 4);
7744 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7745
7746 tcg_temp_free(EA);
7747 tcg_temp_free_i64(tmp);
7748 }
7749
7750 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7751 static void gen_##name(DisasContext *ctx) \
7752 { \
7753 if (xS(ctx->opcode) < 32) { \
7754 if (unlikely(!ctx->fpu_enabled)) { \
7755 gen_exception(ctx, POWERPC_EXCP_FPU); \
7756 return; \
7757 } \
7758 } else { \
7759 if (unlikely(!ctx->altivec_enabled)) { \
7760 gen_exception(ctx, POWERPC_EXCP_VPU); \
7761 return; \
7762 } \
7763 } \
7764 TCGv_i64 tmp = tcg_temp_new_i64(); \
7765 tcg_gen_##tcgop1(tmp, source); \
7766 tcg_gen_##tcgop2(target, tmp); \
7767 tcg_temp_free_i64(tmp); \
7768 }
7769
7770
7771 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7772 cpu_vsrh(xS(ctx->opcode)))
7773 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7774 cpu_gpr[rA(ctx->opcode)])
7775 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7776 cpu_gpr[rA(ctx->opcode)])
7777
7778 #if defined(TARGET_PPC64)
7779 #define MV_VSRD(name, target, source) \
7780 static void gen_##name(DisasContext *ctx) \
7781 { \
7782 if (xS(ctx->opcode) < 32) { \
7783 if (unlikely(!ctx->fpu_enabled)) { \
7784 gen_exception(ctx, POWERPC_EXCP_FPU); \
7785 return; \
7786 } \
7787 } else { \
7788 if (unlikely(!ctx->altivec_enabled)) { \
7789 gen_exception(ctx, POWERPC_EXCP_VPU); \
7790 return; \
7791 } \
7792 } \
7793 tcg_gen_mov_i64(target, source); \
7794 }
7795
7796 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7797 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7798
7799 #endif
7800
7801 static void gen_xxpermdi(DisasContext *ctx)
7802 {
7803 if (unlikely(!ctx->vsx_enabled)) {
7804 gen_exception(ctx, POWERPC_EXCP_VSXU);
7805 return;
7806 }
7807
7808 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7809 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7810 TCGv_i64 xh, xl;
7811
7812 xh = tcg_temp_new_i64();
7813 xl = tcg_temp_new_i64();
7814
7815 if ((DM(ctx->opcode) & 2) == 0) {
7816 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7817 } else {
7818 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7819 }
7820 if ((DM(ctx->opcode) & 1) == 0) {
7821 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7822 } else {
7823 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7824 }
7825
7826 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7827 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7828
7829 tcg_temp_free_i64(xh);
7830 tcg_temp_free_i64(xl);
7831 } else {
7832 if ((DM(ctx->opcode) & 2) == 0) {
7833 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7834 } else {
7835 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7836 }
7837 if ((DM(ctx->opcode) & 1) == 0) {
7838 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7839 } else {
7840 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7841 }
7842 }
7843 }
7844
7845 #define OP_ABS 1
7846 #define OP_NABS 2
7847 #define OP_NEG 3
7848 #define OP_CPSGN 4
7849 #define SGN_MASK_DP 0x8000000000000000ull
7850 #define SGN_MASK_SP 0x8000000080000000ull
7851
7852 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7853 static void glue(gen_, name)(DisasContext * ctx) \
7854 { \
7855 TCGv_i64 xb, sgm; \
7856 if (unlikely(!ctx->vsx_enabled)) { \
7857 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7858 return; \
7859 } \
7860 xb = tcg_temp_new_i64(); \
7861 sgm = tcg_temp_new_i64(); \
7862 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7863 tcg_gen_movi_i64(sgm, sgn_mask); \
7864 switch (op) { \
7865 case OP_ABS: { \
7866 tcg_gen_andc_i64(xb, xb, sgm); \
7867 break; \
7868 } \
7869 case OP_NABS: { \
7870 tcg_gen_or_i64(xb, xb, sgm); \
7871 break; \
7872 } \
7873 case OP_NEG: { \
7874 tcg_gen_xor_i64(xb, xb, sgm); \
7875 break; \
7876 } \
7877 case OP_CPSGN: { \
7878 TCGv_i64 xa = tcg_temp_new_i64(); \
7879 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7880 tcg_gen_and_i64(xa, xa, sgm); \
7881 tcg_gen_andc_i64(xb, xb, sgm); \
7882 tcg_gen_or_i64(xb, xb, xa); \
7883 tcg_temp_free_i64(xa); \
7884 break; \
7885 } \
7886 } \
7887 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7888 tcg_temp_free_i64(xb); \
7889 tcg_temp_free_i64(sgm); \
7890 }
7891
7892 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7893 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7894 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7895 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7896
7897 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7898 static void glue(gen_, name)(DisasContext * ctx) \
7899 { \
7900 TCGv_i64 xbh, xbl, sgm; \
7901 if (unlikely(!ctx->vsx_enabled)) { \
7902 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7903 return; \
7904 } \
7905 xbh = tcg_temp_new_i64(); \
7906 xbl = tcg_temp_new_i64(); \
7907 sgm = tcg_temp_new_i64(); \
7908 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7909 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7910 tcg_gen_movi_i64(sgm, sgn_mask); \
7911 switch (op) { \
7912 case OP_ABS: { \
7913 tcg_gen_andc_i64(xbh, xbh, sgm); \
7914 tcg_gen_andc_i64(xbl, xbl, sgm); \
7915 break; \
7916 } \
7917 case OP_NABS: { \
7918 tcg_gen_or_i64(xbh, xbh, sgm); \
7919 tcg_gen_or_i64(xbl, xbl, sgm); \
7920 break; \
7921 } \
7922 case OP_NEG: { \
7923 tcg_gen_xor_i64(xbh, xbh, sgm); \
7924 tcg_gen_xor_i64(xbl, xbl, sgm); \
7925 break; \
7926 } \
7927 case OP_CPSGN: { \
7928 TCGv_i64 xah = tcg_temp_new_i64(); \
7929 TCGv_i64 xal = tcg_temp_new_i64(); \
7930 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7931 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7932 tcg_gen_and_i64(xah, xah, sgm); \
7933 tcg_gen_and_i64(xal, xal, sgm); \
7934 tcg_gen_andc_i64(xbh, xbh, sgm); \
7935 tcg_gen_andc_i64(xbl, xbl, sgm); \
7936 tcg_gen_or_i64(xbh, xbh, xah); \
7937 tcg_gen_or_i64(xbl, xbl, xal); \
7938 tcg_temp_free_i64(xah); \
7939 tcg_temp_free_i64(xal); \
7940 break; \
7941 } \
7942 } \
7943 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7944 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7945 tcg_temp_free_i64(xbh); \
7946 tcg_temp_free_i64(xbl); \
7947 tcg_temp_free_i64(sgm); \
7948 }
7949
7950 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7951 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7952 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7953 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7954 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7955 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7956 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7957 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7958
7959 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7960 static void gen_##name(DisasContext * ctx) \
7961 { \
7962 TCGv_i32 opc; \
7963 if (unlikely(!ctx->vsx_enabled)) { \
7964 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7965 return; \
7966 } \
7967 /* NIP cannot be restored if the memory exception comes from an helper */ \
7968 gen_update_nip(ctx, ctx->nip - 4); \
7969 opc = tcg_const_i32(ctx->opcode); \
7970 gen_helper_##name(cpu_env, opc); \
7971 tcg_temp_free_i32(opc); \
7972 }
7973
7974 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7975 static void gen_##name(DisasContext * ctx) \
7976 { \
7977 if (unlikely(!ctx->vsx_enabled)) { \
7978 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7979 return; \
7980 } \
7981 /* NIP cannot be restored if the exception comes */ \
7982 /* from a helper. */ \
7983 gen_update_nip(ctx, ctx->nip - 4); \
7984 \
7985 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7986 cpu_vsrh(xB(ctx->opcode))); \
7987 }
7988
7989 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8012 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8014 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8026
8027 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8028 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8029 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8030 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8031 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8032 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8033 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8034 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8035 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8036 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8037 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8038 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8039 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8040 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8041 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8042 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8043 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8044
8045 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8081
8082 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8106 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8107 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8108 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8109 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8110 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8111 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8112 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8113 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8114 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8115 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8116 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8117 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8118
8119 #define VSX_LOGICAL(name, tcg_op) \
8120 static void glue(gen_, name)(DisasContext * ctx) \
8121 { \
8122 if (unlikely(!ctx->vsx_enabled)) { \
8123 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8124 return; \
8125 } \
8126 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8127 cpu_vsrh(xB(ctx->opcode))); \
8128 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8129 cpu_vsrl(xB(ctx->opcode))); \
8130 }
8131
8132 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8133 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8134 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8135 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8136 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8137 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8138 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8139 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8140
8141 #define VSX_XXMRG(name, high) \
8142 static void glue(gen_, name)(DisasContext * ctx) \
8143 { \
8144 TCGv_i64 a0, a1, b0, b1; \
8145 if (unlikely(!ctx->vsx_enabled)) { \
8146 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8147 return; \
8148 } \
8149 a0 = tcg_temp_new_i64(); \
8150 a1 = tcg_temp_new_i64(); \
8151 b0 = tcg_temp_new_i64(); \
8152 b1 = tcg_temp_new_i64(); \
8153 if (high) { \
8154 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8155 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8156 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8157 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8158 } else { \
8159 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8160 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8161 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8162 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8163 } \
8164 tcg_gen_shri_i64(a0, a0, 32); \
8165 tcg_gen_shri_i64(b0, b0, 32); \
8166 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8167 b0, a0, 32, 32); \
8168 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8169 b1, a1, 32, 32); \
8170 tcg_temp_free_i64(a0); \
8171 tcg_temp_free_i64(a1); \
8172 tcg_temp_free_i64(b0); \
8173 tcg_temp_free_i64(b1); \
8174 }
8175
8176 VSX_XXMRG(xxmrghw, 1)
8177 VSX_XXMRG(xxmrglw, 0)
8178
8179 static void gen_xxsel(DisasContext * ctx)
8180 {
8181 TCGv_i64 a, b, c;
8182 if (unlikely(!ctx->vsx_enabled)) {
8183 gen_exception(ctx, POWERPC_EXCP_VSXU);
8184 return;
8185 }
8186 a = tcg_temp_new_i64();
8187 b = tcg_temp_new_i64();
8188 c = tcg_temp_new_i64();
8189
8190 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8191 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8192 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8193
8194 tcg_gen_and_i64(b, b, c);
8195 tcg_gen_andc_i64(a, a, c);
8196 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8197
8198 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8199 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8200 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8201
8202 tcg_gen_and_i64(b, b, c);
8203 tcg_gen_andc_i64(a, a, c);
8204 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8205
8206 tcg_temp_free_i64(a);
8207 tcg_temp_free_i64(b);
8208 tcg_temp_free_i64(c);
8209 }
8210
8211 static void gen_xxspltw(DisasContext *ctx)
8212 {
8213 TCGv_i64 b, b2;
8214 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8215 cpu_vsrl(xB(ctx->opcode)) :
8216 cpu_vsrh(xB(ctx->opcode));
8217
8218 if (unlikely(!ctx->vsx_enabled)) {
8219 gen_exception(ctx, POWERPC_EXCP_VSXU);
8220 return;
8221 }
8222
8223 b = tcg_temp_new_i64();
8224 b2 = tcg_temp_new_i64();
8225
8226 if (UIM(ctx->opcode) & 1) {
8227 tcg_gen_ext32u_i64(b, vsr);
8228 } else {
8229 tcg_gen_shri_i64(b, vsr, 32);
8230 }
8231
8232 tcg_gen_shli_i64(b2, b, 32);
8233 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8234 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8235
8236 tcg_temp_free_i64(b);
8237 tcg_temp_free_i64(b2);
8238 }
8239
8240 static void gen_xxsldwi(DisasContext *ctx)
8241 {
8242 TCGv_i64 xth, xtl;
8243 if (unlikely(!ctx->vsx_enabled)) {
8244 gen_exception(ctx, POWERPC_EXCP_VSXU);
8245 return;
8246 }
8247 xth = tcg_temp_new_i64();
8248 xtl = tcg_temp_new_i64();
8249
8250 switch (SHW(ctx->opcode)) {
8251 case 0: {
8252 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8253 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8254 break;
8255 }
8256 case 1: {
8257 TCGv_i64 t0 = tcg_temp_new_i64();
8258 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8259 tcg_gen_shli_i64(xth, xth, 32);
8260 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8261 tcg_gen_shri_i64(t0, t0, 32);
8262 tcg_gen_or_i64(xth, xth, t0);
8263 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8264 tcg_gen_shli_i64(xtl, xtl, 32);
8265 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8266 tcg_gen_shri_i64(t0, t0, 32);
8267 tcg_gen_or_i64(xtl, xtl, t0);
8268 tcg_temp_free_i64(t0);
8269 break;
8270 }
8271 case 2: {
8272 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8273 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8274 break;
8275 }
8276 case 3: {
8277 TCGv_i64 t0 = tcg_temp_new_i64();
8278 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8279 tcg_gen_shli_i64(xth, xth, 32);
8280 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8281 tcg_gen_shri_i64(t0, t0, 32);
8282 tcg_gen_or_i64(xth, xth, t0);
8283 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8284 tcg_gen_shli_i64(xtl, xtl, 32);
8285 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8286 tcg_gen_shri_i64(t0, t0, 32);
8287 tcg_gen_or_i64(xtl, xtl, t0);
8288 tcg_temp_free_i64(t0);
8289 break;
8290 }
8291 }
8292
8293 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8294 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8295
8296 tcg_temp_free_i64(xth);
8297 tcg_temp_free_i64(xtl);
8298 }
8299
8300 /*** Decimal Floating Point ***/
8301
8302 static inline TCGv_ptr gen_fprp_ptr(int reg)
8303 {
8304 TCGv_ptr r = tcg_temp_new_ptr();
8305 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8306 return r;
8307 }
8308
8309 #define GEN_DFP_T_A_B_Rc(name) \
8310 static void gen_##name(DisasContext *ctx) \
8311 { \
8312 TCGv_ptr rd, ra, rb; \
8313 if (unlikely(!ctx->fpu_enabled)) { \
8314 gen_exception(ctx, POWERPC_EXCP_FPU); \
8315 return; \
8316 } \
8317 gen_update_nip(ctx, ctx->nip - 4); \
8318 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8319 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8320 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8321 gen_helper_##name(cpu_env, rd, ra, rb); \
8322 if (unlikely(Rc(ctx->opcode) != 0)) { \
8323 gen_set_cr1_from_fpscr(ctx); \
8324 } \
8325 tcg_temp_free_ptr(rd); \
8326 tcg_temp_free_ptr(ra); \
8327 tcg_temp_free_ptr(rb); \
8328 }
8329
8330 #define GEN_DFP_BF_A_B(name) \
8331 static void gen_##name(DisasContext *ctx) \
8332 { \
8333 TCGv_ptr ra, rb; \
8334 if (unlikely(!ctx->fpu_enabled)) { \
8335 gen_exception(ctx, POWERPC_EXCP_FPU); \
8336 return; \
8337 } \
8338 gen_update_nip(ctx, ctx->nip - 4); \
8339 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8340 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8341 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8342 cpu_env, ra, rb); \
8343 tcg_temp_free_ptr(ra); \
8344 tcg_temp_free_ptr(rb); \
8345 }
8346
8347 #define GEN_DFP_BF_A_DCM(name) \
8348 static void gen_##name(DisasContext *ctx) \
8349 { \
8350 TCGv_ptr ra; \
8351 TCGv_i32 dcm; \
8352 if (unlikely(!ctx->fpu_enabled)) { \
8353 gen_exception(ctx, POWERPC_EXCP_FPU); \
8354 return; \
8355 } \
8356 gen_update_nip(ctx, ctx->nip - 4); \
8357 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8358 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8359 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8360 cpu_env, ra, dcm); \
8361 tcg_temp_free_ptr(ra); \
8362 tcg_temp_free_i32(dcm); \
8363 }
8364
8365 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8366 static void gen_##name(DisasContext *ctx) \
8367 { \
8368 TCGv_ptr rt, rb; \
8369 TCGv_i32 u32_1, u32_2; \
8370 if (unlikely(!ctx->fpu_enabled)) { \
8371 gen_exception(ctx, POWERPC_EXCP_FPU); \
8372 return; \
8373 } \
8374 gen_update_nip(ctx, ctx->nip - 4); \
8375 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8376 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8377 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8378 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8379 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8380 if (unlikely(Rc(ctx->opcode) != 0)) { \
8381 gen_set_cr1_from_fpscr(ctx); \
8382 } \
8383 tcg_temp_free_ptr(rt); \
8384 tcg_temp_free_ptr(rb); \
8385 tcg_temp_free_i32(u32_1); \
8386 tcg_temp_free_i32(u32_2); \
8387 }
8388
8389 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8390 static void gen_##name(DisasContext *ctx) \
8391 { \
8392 TCGv_ptr rt, ra, rb; \
8393 TCGv_i32 i32; \
8394 if (unlikely(!ctx->fpu_enabled)) { \
8395 gen_exception(ctx, POWERPC_EXCP_FPU); \
8396 return; \
8397 } \
8398 gen_update_nip(ctx, ctx->nip - 4); \
8399 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8400 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8401 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8402 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8403 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8404 if (unlikely(Rc(ctx->opcode) != 0)) { \
8405 gen_set_cr1_from_fpscr(ctx); \
8406 } \
8407 tcg_temp_free_ptr(rt); \
8408 tcg_temp_free_ptr(rb); \
8409 tcg_temp_free_ptr(ra); \
8410 tcg_temp_free_i32(i32); \
8411 }
8412
8413 #define GEN_DFP_T_B_Rc(name) \
8414 static void gen_##name(DisasContext *ctx) \
8415 { \
8416 TCGv_ptr rt, rb; \
8417 if (unlikely(!ctx->fpu_enabled)) { \
8418 gen_exception(ctx, POWERPC_EXCP_FPU); \
8419 return; \
8420 } \
8421 gen_update_nip(ctx, ctx->nip - 4); \
8422 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8423 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8424 gen_helper_##name(cpu_env, rt, rb); \
8425 if (unlikely(Rc(ctx->opcode) != 0)) { \
8426 gen_set_cr1_from_fpscr(ctx); \
8427 } \
8428 tcg_temp_free_ptr(rt); \
8429 tcg_temp_free_ptr(rb); \
8430 }
8431
8432 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8433 static void gen_##name(DisasContext *ctx) \
8434 { \
8435 TCGv_ptr rt, rs; \
8436 TCGv_i32 i32; \
8437 if (unlikely(!ctx->fpu_enabled)) { \
8438 gen_exception(ctx, POWERPC_EXCP_FPU); \
8439 return; \
8440 } \
8441 gen_update_nip(ctx, ctx->nip - 4); \
8442 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8443 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8444 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8445 gen_helper_##name(cpu_env, rt, rs, i32); \
8446 if (unlikely(Rc(ctx->opcode) != 0)) { \
8447 gen_set_cr1_from_fpscr(ctx); \
8448 } \
8449 tcg_temp_free_ptr(rt); \
8450 tcg_temp_free_ptr(rs); \
8451 tcg_temp_free_i32(i32); \
8452 }
8453
8454 GEN_DFP_T_A_B_Rc(dadd)
8455 GEN_DFP_T_A_B_Rc(daddq)
8456 GEN_DFP_T_A_B_Rc(dsub)
8457 GEN_DFP_T_A_B_Rc(dsubq)
8458 GEN_DFP_T_A_B_Rc(dmul)
8459 GEN_DFP_T_A_B_Rc(dmulq)
8460 GEN_DFP_T_A_B_Rc(ddiv)
8461 GEN_DFP_T_A_B_Rc(ddivq)
8462 GEN_DFP_BF_A_B(dcmpu)
8463 GEN_DFP_BF_A_B(dcmpuq)
8464 GEN_DFP_BF_A_B(dcmpo)
8465 GEN_DFP_BF_A_B(dcmpoq)
8466 GEN_DFP_BF_A_DCM(dtstdc)
8467 GEN_DFP_BF_A_DCM(dtstdcq)
8468 GEN_DFP_BF_A_DCM(dtstdg)
8469 GEN_DFP_BF_A_DCM(dtstdgq)
8470 GEN_DFP_BF_A_B(dtstex)
8471 GEN_DFP_BF_A_B(dtstexq)
8472 GEN_DFP_BF_A_B(dtstsf)
8473 GEN_DFP_BF_A_B(dtstsfq)
8474 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8475 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8476 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8477 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8478 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8479 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8480 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8481 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8482 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8483 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8484 GEN_DFP_T_B_Rc(dctdp)
8485 GEN_DFP_T_B_Rc(dctqpq)
8486 GEN_DFP_T_B_Rc(drsp)
8487 GEN_DFP_T_B_Rc(drdpq)
8488 GEN_DFP_T_B_Rc(dcffix)
8489 GEN_DFP_T_B_Rc(dcffixq)
8490 GEN_DFP_T_B_Rc(dctfix)
8491 GEN_DFP_T_B_Rc(dctfixq)
8492 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8493 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8494 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8495 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8496 GEN_DFP_T_B_Rc(dxex)
8497 GEN_DFP_T_B_Rc(dxexq)
8498 GEN_DFP_T_A_B_Rc(diex)
8499 GEN_DFP_T_A_B_Rc(diexq)
8500 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8501 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8502 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8503 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8504
8505 /*** SPE extension ***/
8506 /* Register moves */
8507
8508 static inline void gen_evmra(DisasContext *ctx)
8509 {
8510
8511 if (unlikely(!ctx->spe_enabled)) {
8512 gen_exception(ctx, POWERPC_EXCP_SPEU);
8513 return;
8514 }
8515
8516 TCGv_i64 tmp = tcg_temp_new_i64();
8517
8518 /* tmp := rA_lo + rA_hi << 32 */
8519 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8520
8521 /* spe_acc := tmp */
8522 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8523 tcg_temp_free_i64(tmp);
8524
8525 /* rD := rA */
8526 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8527 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8528 }
8529
8530 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8531 {
8532 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8533 }
8534
8535 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8536 {
8537 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8538 }
8539
8540 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8541 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8542 { \
8543 if (Rc(ctx->opcode)) \
8544 gen_##name1(ctx); \
8545 else \
8546 gen_##name0(ctx); \
8547 }
8548
8549 /* Handler for undefined SPE opcodes */
8550 static inline void gen_speundef(DisasContext *ctx)
8551 {
8552 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8553 }
8554
8555 /* SPE logic */
8556 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8557 static inline void gen_##name(DisasContext *ctx) \
8558 { \
8559 if (unlikely(!ctx->spe_enabled)) { \
8560 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8561 return; \
8562 } \
8563 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8564 cpu_gpr[rB(ctx->opcode)]); \
8565 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8566 cpu_gprh[rB(ctx->opcode)]); \
8567 }
8568
8569 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8570 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8571 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8572 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8573 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8574 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8575 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8576 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8577
8578 /* SPE logic immediate */
8579 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8580 static inline void gen_##name(DisasContext *ctx) \
8581 { \
8582 TCGv_i32 t0; \
8583 if (unlikely(!ctx->spe_enabled)) { \
8584 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8585 return; \
8586 } \
8587 t0 = tcg_temp_new_i32(); \
8588 \
8589 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8590 tcg_opi(t0, t0, rB(ctx->opcode)); \
8591 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8592 \
8593 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8594 tcg_opi(t0, t0, rB(ctx->opcode)); \
8595 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8596 \
8597 tcg_temp_free_i32(t0); \
8598 }
8599 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8600 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8601 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8602 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8603
8604 /* SPE arithmetic */
8605 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8606 static inline void gen_##name(DisasContext *ctx) \
8607 { \
8608 TCGv_i32 t0; \
8609 if (unlikely(!ctx->spe_enabled)) { \
8610 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8611 return; \
8612 } \
8613 t0 = tcg_temp_new_i32(); \
8614 \
8615 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8616 tcg_op(t0, t0); \
8617 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8618 \
8619 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8620 tcg_op(t0, t0); \
8621 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8622 \
8623 tcg_temp_free_i32(t0); \
8624 }
8625
8626 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8627 {
8628 TCGLabel *l1 = gen_new_label();
8629 TCGLabel *l2 = gen_new_label();
8630
8631 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8632 tcg_gen_neg_i32(ret, arg1);
8633 tcg_gen_br(l2);
8634 gen_set_label(l1);
8635 tcg_gen_mov_i32(ret, arg1);
8636 gen_set_label(l2);
8637 }
8638 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8639 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8640 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8641 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8642 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8643 {
8644 tcg_gen_addi_i32(ret, arg1, 0x8000);
8645 tcg_gen_ext16u_i32(ret, ret);
8646 }
8647 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8648 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8649 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8650
8651 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8652 static inline void gen_##name(DisasContext *ctx) \
8653 { \
8654 TCGv_i32 t0, t1; \
8655 if (unlikely(!ctx->spe_enabled)) { \
8656 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8657 return; \
8658 } \
8659 t0 = tcg_temp_new_i32(); \
8660 t1 = tcg_temp_new_i32(); \
8661 \
8662 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8663 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8664 tcg_op(t0, t0, t1); \
8665 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8666 \
8667 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8668 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8669 tcg_op(t0, t0, t1); \
8670 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8671 \
8672 tcg_temp_free_i32(t0); \
8673 tcg_temp_free_i32(t1); \
8674 }
8675
8676 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8677 {
8678 TCGLabel *l1 = gen_new_label();
8679 TCGLabel *l2 = gen_new_label();
8680 TCGv_i32 t0 = tcg_temp_local_new_i32();
8681
8682 /* No error here: 6 bits are used */
8683 tcg_gen_andi_i32(t0, arg2, 0x3F);
8684 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8685 tcg_gen_shr_i32(ret, arg1, t0);
8686 tcg_gen_br(l2);
8687 gen_set_label(l1);
8688 tcg_gen_movi_i32(ret, 0);
8689 gen_set_label(l2);
8690 tcg_temp_free_i32(t0);
8691 }
8692 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8693 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8694 {
8695 TCGLabel *l1 = gen_new_label();
8696 TCGLabel *l2 = gen_new_label();
8697 TCGv_i32 t0 = tcg_temp_local_new_i32();
8698
8699 /* No error here: 6 bits are used */
8700 tcg_gen_andi_i32(t0, arg2, 0x3F);
8701 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8702 tcg_gen_sar_i32(ret, arg1, t0);
8703 tcg_gen_br(l2);
8704 gen_set_label(l1);
8705 tcg_gen_movi_i32(ret, 0);
8706 gen_set_label(l2);
8707 tcg_temp_free_i32(t0);
8708 }
8709 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8710 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8711 {
8712 TCGLabel *l1 = gen_new_label();
8713 TCGLabel *l2 = gen_new_label();
8714 TCGv_i32 t0 = tcg_temp_local_new_i32();
8715
8716 /* No error here: 6 bits are used */
8717 tcg_gen_andi_i32(t0, arg2, 0x3F);
8718 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8719 tcg_gen_shl_i32(ret, arg1, t0);
8720 tcg_gen_br(l2);
8721 gen_set_label(l1);
8722 tcg_gen_movi_i32(ret, 0);
8723 gen_set_label(l2);
8724 tcg_temp_free_i32(t0);
8725 }
8726 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8727 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8728 {
8729 TCGv_i32 t0 = tcg_temp_new_i32();
8730 tcg_gen_andi_i32(t0, arg2, 0x1F);
8731 tcg_gen_rotl_i32(ret, arg1, t0);
8732 tcg_temp_free_i32(t0);
8733 }
8734 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8735 static inline void gen_evmergehi(DisasContext *ctx)
8736 {
8737 if (unlikely(!ctx->spe_enabled)) {
8738 gen_exception(ctx, POWERPC_EXCP_SPEU);
8739 return;
8740 }
8741 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8742 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8743 }
8744 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8745 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8746 {
8747 tcg_gen_sub_i32(ret, arg2, arg1);
8748 }
8749 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8750
8751 /* SPE arithmetic immediate */
8752 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8753 static inline void gen_##name(DisasContext *ctx) \
8754 { \
8755 TCGv_i32 t0; \
8756 if (unlikely(!ctx->spe_enabled)) { \
8757 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8758 return; \
8759 } \
8760 t0 = tcg_temp_new_i32(); \
8761 \
8762 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8763 tcg_op(t0, t0, rA(ctx->opcode)); \
8764 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8765 \
8766 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8767 tcg_op(t0, t0, rA(ctx->opcode)); \
8768 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8769 \
8770 tcg_temp_free_i32(t0); \
8771 }
8772 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8773 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8774
8775 /* SPE comparison */
8776 #define GEN_SPEOP_COMP(name, tcg_cond) \
8777 static inline void gen_##name(DisasContext *ctx) \
8778 { \
8779 if (unlikely(!ctx->spe_enabled)) { \
8780 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8781 return; \
8782 } \
8783 TCGLabel *l1 = gen_new_label(); \
8784 TCGLabel *l2 = gen_new_label(); \
8785 TCGLabel *l3 = gen_new_label(); \
8786 TCGLabel *l4 = gen_new_label(); \
8787 \
8788 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8789 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8790 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8791 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8792 \
8793 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8794 cpu_gpr[rB(ctx->opcode)], l1); \
8795 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8796 tcg_gen_br(l2); \
8797 gen_set_label(l1); \
8798 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8799 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8800 gen_set_label(l2); \
8801 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8802 cpu_gprh[rB(ctx->opcode)], l3); \
8803 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8804 ~(CRF_CH | CRF_CH_AND_CL)); \
8805 tcg_gen_br(l4); \
8806 gen_set_label(l3); \
8807 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8808 CRF_CH | CRF_CH_OR_CL); \
8809 gen_set_label(l4); \
8810 }
8811 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8812 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8813 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8814 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8815 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8816
8817 /* SPE misc */
8818 static inline void gen_brinc(DisasContext *ctx)
8819 {
8820 /* Note: brinc is usable even if SPE is disabled */
8821 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8822 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8823 }
8824 static inline void gen_evmergelo(DisasContext *ctx)
8825 {
8826 if (unlikely(!ctx->spe_enabled)) {
8827 gen_exception(ctx, POWERPC_EXCP_SPEU);
8828 return;
8829 }
8830 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8831 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8832 }
8833 static inline void gen_evmergehilo(DisasContext *ctx)
8834 {
8835 if (unlikely(!ctx->spe_enabled)) {
8836 gen_exception(ctx, POWERPC_EXCP_SPEU);
8837 return;
8838 }
8839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8840 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8841 }
8842 static inline void gen_evmergelohi(DisasContext *ctx)
8843 {
8844 if (unlikely(!ctx->spe_enabled)) {
8845 gen_exception(ctx, POWERPC_EXCP_SPEU);
8846 return;
8847 }
8848 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8849 TCGv tmp = tcg_temp_new();
8850 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8851 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8852 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8853 tcg_temp_free(tmp);
8854 } else {
8855 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8856 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8857 }
8858 }
8859 static inline void gen_evsplati(DisasContext *ctx)
8860 {
8861 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8862
8863 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8864 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8865 }
8866 static inline void gen_evsplatfi(DisasContext *ctx)
8867 {
8868 uint64_t imm = rA(ctx->opcode) << 27;
8869
8870 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8871 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8872 }
8873
8874 static inline void gen_evsel(DisasContext *ctx)
8875 {
8876 TCGLabel *l1 = gen_new_label();
8877 TCGLabel *l2 = gen_new_label();
8878 TCGLabel *l3 = gen_new_label();
8879 TCGLabel *l4 = gen_new_label();
8880 TCGv_i32 t0 = tcg_temp_local_new_i32();
8881
8882 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8883 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8884 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8885 tcg_gen_br(l2);
8886 gen_set_label(l1);
8887 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8888 gen_set_label(l2);
8889 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8890 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8891 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8892 tcg_gen_br(l4);
8893 gen_set_label(l3);
8894 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8895 gen_set_label(l4);
8896 tcg_temp_free_i32(t0);
8897 }
8898
8899 static void gen_evsel0(DisasContext *ctx)
8900 {
8901 gen_evsel(ctx);
8902 }
8903
8904 static void gen_evsel1(DisasContext *ctx)
8905 {
8906 gen_evsel(ctx);
8907 }
8908
8909 static void gen_evsel2(DisasContext *ctx)
8910 {
8911 gen_evsel(ctx);
8912 }
8913
8914 static void gen_evsel3(DisasContext *ctx)
8915 {
8916 gen_evsel(ctx);
8917 }
8918
8919 /* Multiply */
8920
8921 static inline void gen_evmwumi(DisasContext *ctx)
8922 {
8923 TCGv_i64 t0, t1;
8924
8925 if (unlikely(!ctx->spe_enabled)) {
8926 gen_exception(ctx, POWERPC_EXCP_SPEU);
8927 return;
8928 }
8929
8930 t0 = tcg_temp_new_i64();
8931 t1 = tcg_temp_new_i64();
8932
8933 /* t0 := rA; t1 := rB */
8934 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8935 tcg_gen_ext32u_i64(t0, t0);
8936 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8937 tcg_gen_ext32u_i64(t1, t1);
8938
8939 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8940
8941 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8942
8943 tcg_temp_free_i64(t0);
8944 tcg_temp_free_i64(t1);
8945 }
8946
8947 static inline void gen_evmwumia(DisasContext *ctx)
8948 {
8949 TCGv_i64 tmp;
8950
8951 if (unlikely(!ctx->spe_enabled)) {
8952 gen_exception(ctx, POWERPC_EXCP_SPEU);
8953 return;
8954 }
8955
8956 gen_evmwumi(ctx); /* rD := rA * rB */
8957
8958 tmp = tcg_temp_new_i64();
8959
8960 /* acc := rD */
8961 gen_load_gpr64(tmp, rD(ctx->opcode));
8962 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8963 tcg_temp_free_i64(tmp);
8964 }
8965
8966 static inline void gen_evmwumiaa(DisasContext *ctx)
8967 {
8968 TCGv_i64 acc;
8969 TCGv_i64 tmp;
8970
8971 if (unlikely(!ctx->spe_enabled)) {
8972 gen_exception(ctx, POWERPC_EXCP_SPEU);
8973 return;
8974 }
8975
8976 gen_evmwumi(ctx); /* rD := rA * rB */
8977
8978 acc = tcg_temp_new_i64();
8979 tmp = tcg_temp_new_i64();
8980
8981 /* tmp := rD */
8982 gen_load_gpr64(tmp, rD(ctx->opcode));
8983
8984 /* Load acc */
8985 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8986
8987 /* acc := tmp + acc */
8988 tcg_gen_add_i64(acc, acc, tmp);
8989
8990 /* Store acc */
8991 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8992
8993 /* rD := acc */
8994 gen_store_gpr64(rD(ctx->opcode), acc);
8995
8996 tcg_temp_free_i64(acc);
8997 tcg_temp_free_i64(tmp);
8998 }
8999
9000 static inline void gen_evmwsmi(DisasContext *ctx)
9001 {
9002 TCGv_i64 t0, t1;
9003
9004 if (unlikely(!ctx->spe_enabled)) {
9005 gen_exception(ctx, POWERPC_EXCP_SPEU);
9006 return;
9007 }
9008
9009 t0 = tcg_temp_new_i64();
9010 t1 = tcg_temp_new_i64();
9011
9012 /* t0 := rA; t1 := rB */
9013 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9014 tcg_gen_ext32s_i64(t0, t0);
9015 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9016 tcg_gen_ext32s_i64(t1, t1);
9017
9018 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9019
9020 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9021
9022 tcg_temp_free_i64(t0);
9023 tcg_temp_free_i64(t1);
9024 }
9025
9026 static inline void gen_evmwsmia(DisasContext *ctx)
9027 {
9028 TCGv_i64 tmp;
9029
9030 gen_evmwsmi(ctx); /* rD := rA * rB */
9031
9032 tmp = tcg_temp_new_i64();
9033
9034 /* acc := rD */
9035 gen_load_gpr64(tmp, rD(ctx->opcode));
9036 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9037
9038 tcg_temp_free_i64(tmp);
9039 }
9040
9041 static inline void gen_evmwsmiaa(DisasContext *ctx)
9042 {
9043 TCGv_i64 acc = tcg_temp_new_i64();
9044 TCGv_i64 tmp = tcg_temp_new_i64();
9045
9046 gen_evmwsmi(ctx); /* rD := rA * rB */
9047
9048 acc = tcg_temp_new_i64();
9049 tmp = tcg_temp_new_i64();
9050
9051 /* tmp := rD */
9052 gen_load_gpr64(tmp, rD(ctx->opcode));
9053
9054 /* Load acc */
9055 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9056
9057 /* acc := tmp + acc */
9058 tcg_gen_add_i64(acc, acc, tmp);
9059
9060 /* Store acc */
9061 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9062
9063 /* rD := acc */
9064 gen_store_gpr64(rD(ctx->opcode), acc);
9065
9066 tcg_temp_free_i64(acc);
9067 tcg_temp_free_i64(tmp);
9068 }
9069
9070 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9071 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9072 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9073 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9074 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9075 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9076 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9077 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9078 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9079 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9080 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9081 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9082 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9083 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9084 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9085 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9086 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9087 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9088 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9089 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9090 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9091 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9092 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9093 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9094 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9095 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9096 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9097 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9098 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9099
9100 /* SPE load and stores */
9101 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9102 {
9103 target_ulong uimm = rB(ctx->opcode);
9104
9105 if (rA(ctx->opcode) == 0) {
9106 tcg_gen_movi_tl(EA, uimm << sh);
9107 } else {
9108 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9109 if (NARROW_MODE(ctx)) {
9110 tcg_gen_ext32u_tl(EA, EA);
9111 }
9112 }
9113 }
9114
9115 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9116 {
9117 TCGv_i64 t0 = tcg_temp_new_i64();
9118 gen_qemu_ld64(ctx, t0, addr);
9119 gen_store_gpr64(rD(ctx->opcode), t0);
9120 tcg_temp_free_i64(t0);
9121 }
9122
9123 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9124 {
9125 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9126 gen_addr_add(ctx, addr, addr, 4);
9127 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9128 }
9129
9130 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9131 {
9132 TCGv t0 = tcg_temp_new();
9133 gen_qemu_ld16u(ctx, t0, addr);
9134 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9135 gen_addr_add(ctx, addr, addr, 2);
9136 gen_qemu_ld16u(ctx, t0, addr);
9137 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9138 gen_addr_add(ctx, addr, addr, 2);
9139 gen_qemu_ld16u(ctx, t0, addr);
9140 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9141 gen_addr_add(ctx, addr, addr, 2);
9142 gen_qemu_ld16u(ctx, t0, addr);
9143 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9144 tcg_temp_free(t0);
9145 }
9146
9147 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9148 {
9149 TCGv t0 = tcg_temp_new();
9150 gen_qemu_ld16u(ctx, t0, addr);
9151 tcg_gen_shli_tl(t0, t0, 16);
9152 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9153 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9154 tcg_temp_free(t0);
9155 }
9156
9157 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9158 {
9159 TCGv t0 = tcg_temp_new();
9160 gen_qemu_ld16u(ctx, t0, addr);
9161 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9162 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9163 tcg_temp_free(t0);
9164 }
9165
9166 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9167 {
9168 TCGv t0 = tcg_temp_new();
9169 gen_qemu_ld16s(ctx, t0, addr);
9170 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9171 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9172 tcg_temp_free(t0);
9173 }
9174
9175 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9176 {
9177 TCGv t0 = tcg_temp_new();
9178 gen_qemu_ld16u(ctx, t0, addr);
9179 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9180 gen_addr_add(ctx, addr, addr, 2);
9181 gen_qemu_ld16u(ctx, t0, addr);
9182 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9183 tcg_temp_free(t0);
9184 }
9185
9186 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9187 {
9188 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9189 gen_addr_add(ctx, addr, addr, 2);
9190 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9191 }
9192
9193 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9194 {
9195 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9196 gen_addr_add(ctx, addr, addr, 2);
9197 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9198 }
9199
9200 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9201 {
9202 TCGv t0 = tcg_temp_new();
9203 gen_qemu_ld32u(ctx, t0, addr);
9204 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9205 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9206 tcg_temp_free(t0);
9207 }
9208
9209 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9210 {
9211 TCGv t0 = tcg_temp_new();
9212 gen_qemu_ld16u(ctx, t0, addr);
9213 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9214 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9215 gen_addr_add(ctx, addr, addr, 2);
9216 gen_qemu_ld16u(ctx, t0, addr);
9217 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9218 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9219 tcg_temp_free(t0);
9220 }
9221
9222 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9223 {
9224 TCGv_i64 t0 = tcg_temp_new_i64();
9225 gen_load_gpr64(t0, rS(ctx->opcode));
9226 gen_qemu_st64(ctx, t0, addr);
9227 tcg_temp_free_i64(t0);
9228 }
9229
9230 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9231 {
9232 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9233 gen_addr_add(ctx, addr, addr, 4);
9234 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9235 }
9236
9237 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9238 {
9239 TCGv t0 = tcg_temp_new();
9240 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9241 gen_qemu_st16(ctx, t0, addr);
9242 gen_addr_add(ctx, addr, addr, 2);
9243 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9244 gen_addr_add(ctx, addr, addr, 2);
9245 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9246 gen_qemu_st16(ctx, t0, addr);
9247 tcg_temp_free(t0);
9248 gen_addr_add(ctx, addr, addr, 2);
9249 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9250 }
9251
9252 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9253 {
9254 TCGv t0 = tcg_temp_new();
9255 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9256 gen_qemu_st16(ctx, t0, addr);
9257 gen_addr_add(ctx, addr, addr, 2);
9258 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9259 gen_qemu_st16(ctx, t0, addr);
9260 tcg_temp_free(t0);
9261 }
9262
9263 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9264 {
9265 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9266 gen_addr_add(ctx, addr, addr, 2);
9267 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9268 }
9269
9270 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9271 {
9272 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9273 }
9274
9275 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9276 {
9277 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9278 }
9279
9280 #define GEN_SPEOP_LDST(name, opc2, sh) \
9281 static void glue(gen_, name)(DisasContext *ctx) \
9282 { \
9283 TCGv t0; \
9284 if (unlikely(!ctx->spe_enabled)) { \
9285 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9286 return; \
9287 } \
9288 gen_set_access_type(ctx, ACCESS_INT); \
9289 t0 = tcg_temp_new(); \
9290 if (Rc(ctx->opcode)) { \
9291 gen_addr_spe_imm_index(ctx, t0, sh); \
9292 } else { \
9293 gen_addr_reg_index(ctx, t0); \
9294 } \
9295 gen_op_##name(ctx, t0); \
9296 tcg_temp_free(t0); \
9297 }
9298
9299 GEN_SPEOP_LDST(evldd, 0x00, 3);
9300 GEN_SPEOP_LDST(evldw, 0x01, 3);
9301 GEN_SPEOP_LDST(evldh, 0x02, 3);
9302 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9303 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9304 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9305 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9306 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9307 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9308 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9309 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9310
9311 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9312 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9313 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9314 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9315 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9316 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9317 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9318
9319 /* Multiply and add - TODO */
9320 #if 0
9321 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9322 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9324 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9325 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9326 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9330 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9331 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333
9334 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9336 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9337 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9340 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9341 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9342 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9343 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9346
9347 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9348 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9349 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9350 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9351 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9352
9353 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9354 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9355 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9356 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9358 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9359 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9360 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9361 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9362 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9363 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9364 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9365
9366 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9367 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9370
9371 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9372 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9373 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9374 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9376 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9378 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9379 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9380 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9381 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9382 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9383
9384 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9386 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9387 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9388 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389 #endif
9390
9391 /*** SPE floating-point extension ***/
9392 #define GEN_SPEFPUOP_CONV_32_32(name) \
9393 static inline void gen_##name(DisasContext *ctx) \
9394 { \
9395 TCGv_i32 t0 = tcg_temp_new_i32(); \
9396 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9397 gen_helper_##name(t0, cpu_env, t0); \
9398 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9399 tcg_temp_free_i32(t0); \
9400 }
9401 #define GEN_SPEFPUOP_CONV_32_64(name) \
9402 static inline void gen_##name(DisasContext *ctx) \
9403 { \
9404 TCGv_i64 t0 = tcg_temp_new_i64(); \
9405 TCGv_i32 t1 = tcg_temp_new_i32(); \
9406 gen_load_gpr64(t0, rB(ctx->opcode)); \
9407 gen_helper_##name(t1, cpu_env, t0); \
9408 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9409 tcg_temp_free_i64(t0); \
9410 tcg_temp_free_i32(t1); \
9411 }
9412 #define GEN_SPEFPUOP_CONV_64_32(name) \
9413 static inline void gen_##name(DisasContext *ctx) \
9414 { \
9415 TCGv_i64 t0 = tcg_temp_new_i64(); \
9416 TCGv_i32 t1 = tcg_temp_new_i32(); \
9417 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9418 gen_helper_##name(t0, cpu_env, t1); \
9419 gen_store_gpr64(rD(ctx->opcode), t0); \
9420 tcg_temp_free_i64(t0); \
9421 tcg_temp_free_i32(t1); \
9422 }
9423 #define GEN_SPEFPUOP_CONV_64_64(name) \
9424 static inline void gen_##name(DisasContext *ctx) \
9425 { \
9426 TCGv_i64 t0 = tcg_temp_new_i64(); \
9427 gen_load_gpr64(t0, rB(ctx->opcode)); \
9428 gen_helper_##name(t0, cpu_env, t0); \
9429 gen_store_gpr64(rD(ctx->opcode), t0); \
9430 tcg_temp_free_i64(t0); \
9431 }
9432 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9433 static inline void gen_##name(DisasContext *ctx) \
9434 { \
9435 TCGv_i32 t0, t1; \
9436 if (unlikely(!ctx->spe_enabled)) { \
9437 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9438 return; \
9439 } \
9440 t0 = tcg_temp_new_i32(); \
9441 t1 = tcg_temp_new_i32(); \
9442 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9443 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9444 gen_helper_##name(t0, cpu_env, t0, t1); \
9445 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9446 \
9447 tcg_temp_free_i32(t0); \
9448 tcg_temp_free_i32(t1); \
9449 }
9450 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9451 static inline void gen_##name(DisasContext *ctx) \
9452 { \
9453 TCGv_i64 t0, t1; \
9454 if (unlikely(!ctx->spe_enabled)) { \
9455 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9456 return; \
9457 } \
9458 t0 = tcg_temp_new_i64(); \
9459 t1 = tcg_temp_new_i64(); \
9460 gen_load_gpr64(t0, rA(ctx->opcode)); \
9461 gen_load_gpr64(t1, rB(ctx->opcode)); \
9462 gen_helper_##name(t0, cpu_env, t0, t1); \
9463 gen_store_gpr64(rD(ctx->opcode), t0); \
9464 tcg_temp_free_i64(t0); \
9465 tcg_temp_free_i64(t1); \
9466 }
9467 #define GEN_SPEFPUOP_COMP_32(name) \
9468 static inline void gen_##name(DisasContext *ctx) \
9469 { \
9470 TCGv_i32 t0, t1; \
9471 if (unlikely(!ctx->spe_enabled)) { \
9472 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9473 return; \
9474 } \
9475 t0 = tcg_temp_new_i32(); \
9476 t1 = tcg_temp_new_i32(); \
9477 \
9478 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9479 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9480 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9481 \
9482 tcg_temp_free_i32(t0); \
9483 tcg_temp_free_i32(t1); \
9484 }
9485 #define GEN_SPEFPUOP_COMP_64(name) \
9486 static inline void gen_##name(DisasContext *ctx) \
9487 { \
9488 TCGv_i64 t0, t1; \
9489 if (unlikely(!ctx->spe_enabled)) { \
9490 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9491 return; \
9492 } \
9493 t0 = tcg_temp_new_i64(); \
9494 t1 = tcg_temp_new_i64(); \
9495 gen_load_gpr64(t0, rA(ctx->opcode)); \
9496 gen_load_gpr64(t1, rB(ctx->opcode)); \
9497 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9498 tcg_temp_free_i64(t0); \
9499 tcg_temp_free_i64(t1); \
9500 }
9501
9502 /* Single precision floating-point vectors operations */
9503 /* Arithmetic */
9504 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9505 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9506 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9507 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9508 static inline void gen_evfsabs(DisasContext *ctx)
9509 {
9510 if (unlikely(!ctx->spe_enabled)) {
9511 gen_exception(ctx, POWERPC_EXCP_SPEU);
9512 return;
9513 }
9514 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9515 ~0x80000000);
9516 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9517 ~0x80000000);
9518 }
9519 static inline void gen_evfsnabs(DisasContext *ctx)
9520 {
9521 if (unlikely(!ctx->spe_enabled)) {
9522 gen_exception(ctx, POWERPC_EXCP_SPEU);
9523 return;
9524 }
9525 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9526 0x80000000);
9527 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9528 0x80000000);
9529 }
9530 static inline void gen_evfsneg(DisasContext *ctx)
9531 {
9532 if (unlikely(!ctx->spe_enabled)) {
9533 gen_exception(ctx, POWERPC_EXCP_SPEU);
9534 return;
9535 }
9536 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9537 0x80000000);
9538 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9539 0x80000000);
9540 }
9541
9542 /* Conversion */
9543 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9544 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9545 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9546 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9547 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9548 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9549 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9550 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9551 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9552 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9553
9554 /* Comparison */
9555 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9556 GEN_SPEFPUOP_COMP_64(evfscmplt);
9557 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9558 GEN_SPEFPUOP_COMP_64(evfststgt);
9559 GEN_SPEFPUOP_COMP_64(evfststlt);
9560 GEN_SPEFPUOP_COMP_64(evfststeq);
9561
9562 /* Opcodes definitions */
9563 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9564 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9565 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9566 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9567 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9568 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9569 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9570 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9571 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9572 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9573 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9574 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9575 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9576 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9577
9578 /* Single precision floating-point operations */
9579 /* Arithmetic */
9580 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9581 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9582 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9583 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9584 static inline void gen_efsabs(DisasContext *ctx)
9585 {
9586 if (unlikely(!ctx->spe_enabled)) {
9587 gen_exception(ctx, POWERPC_EXCP_SPEU);
9588 return;
9589 }
9590 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9591 }
9592 static inline void gen_efsnabs(DisasContext *ctx)
9593 {
9594 if (unlikely(!ctx->spe_enabled)) {
9595 gen_exception(ctx, POWERPC_EXCP_SPEU);
9596 return;
9597 }
9598 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9599 }
9600 static inline void gen_efsneg(DisasContext *ctx)
9601 {
9602 if (unlikely(!ctx->spe_enabled)) {
9603 gen_exception(ctx, POWERPC_EXCP_SPEU);
9604 return;
9605 }
9606 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9607 }
9608
9609 /* Conversion */
9610 GEN_SPEFPUOP_CONV_32_32(efscfui);
9611 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9612 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9613 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9614 GEN_SPEFPUOP_CONV_32_32(efsctui);
9615 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9616 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9617 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9618 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9619 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9620 GEN_SPEFPUOP_CONV_32_64(efscfd);
9621
9622 /* Comparison */
9623 GEN_SPEFPUOP_COMP_32(efscmpgt);
9624 GEN_SPEFPUOP_COMP_32(efscmplt);
9625 GEN_SPEFPUOP_COMP_32(efscmpeq);
9626 GEN_SPEFPUOP_COMP_32(efststgt);
9627 GEN_SPEFPUOP_COMP_32(efststlt);
9628 GEN_SPEFPUOP_COMP_32(efststeq);
9629
9630 /* Opcodes definitions */
9631 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9632 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9633 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9634 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9635 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9636 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9637 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9638 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9639 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9640 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9641 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9642 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9643 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9644 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9645
9646 /* Double precision floating-point operations */
9647 /* Arithmetic */
9648 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9649 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9650 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9651 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9652 static inline void gen_efdabs(DisasContext *ctx)
9653 {
9654 if (unlikely(!ctx->spe_enabled)) {
9655 gen_exception(ctx, POWERPC_EXCP_SPEU);
9656 return;
9657 }
9658 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9659 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9660 ~0x80000000);
9661 }
9662 static inline void gen_efdnabs(DisasContext *ctx)
9663 {
9664 if (unlikely(!ctx->spe_enabled)) {
9665 gen_exception(ctx, POWERPC_EXCP_SPEU);
9666 return;
9667 }
9668 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9669 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9670 0x80000000);
9671 }
9672 static inline void gen_efdneg(DisasContext *ctx)
9673 {
9674 if (unlikely(!ctx->spe_enabled)) {
9675 gen_exception(ctx, POWERPC_EXCP_SPEU);
9676 return;
9677 }
9678 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9679 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9680 0x80000000);
9681 }
9682
9683 /* Conversion */
9684 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9685 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9686 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9687 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9688 GEN_SPEFPUOP_CONV_32_64(efdctui);
9689 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9690 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9691 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9692 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9693 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9694 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9695 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9696 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9697 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9698 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9699
9700 /* Comparison */
9701 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9702 GEN_SPEFPUOP_COMP_64(efdcmplt);
9703 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9704 GEN_SPEFPUOP_COMP_64(efdtstgt);
9705 GEN_SPEFPUOP_COMP_64(efdtstlt);
9706 GEN_SPEFPUOP_COMP_64(efdtsteq);
9707
9708 /* Opcodes definitions */
9709 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9710 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9711 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9712 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9713 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9714 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9715 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9716 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9717 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9718 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9719 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9720 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9721 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9722 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9723 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9724 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9725
9726 static void gen_tbegin(DisasContext *ctx)
9727 {
9728 if (unlikely(!ctx->tm_enabled)) {
9729 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9730 return;
9731 }
9732 gen_helper_tbegin(cpu_env);
9733 }
9734
9735 #define GEN_TM_NOOP(name) \
9736 static inline void gen_##name(DisasContext *ctx) \
9737 { \
9738 if (unlikely(!ctx->tm_enabled)) { \
9739 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9740 return; \
9741 } \
9742 /* Because tbegin always fails in QEMU, these user \
9743 * space instructions all have a simple implementation: \
9744 * \
9745 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9746 * = 0b0 || 0b00 || 0b0 \
9747 */ \
9748 tcg_gen_movi_i32(cpu_crf[0], 0); \
9749 }
9750
9751 GEN_TM_NOOP(tend);
9752 GEN_TM_NOOP(tabort);
9753 GEN_TM_NOOP(tabortwc);
9754 GEN_TM_NOOP(tabortwci);
9755 GEN_TM_NOOP(tabortdc);
9756 GEN_TM_NOOP(tabortdci);
9757 GEN_TM_NOOP(tsr);
9758
9759 static void gen_tcheck(DisasContext *ctx)
9760 {
9761 if (unlikely(!ctx->tm_enabled)) {
9762 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9763 return;
9764 }
9765 /* Because tbegin always fails, the tcheck implementation
9766 * is simple:
9767 *
9768 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9769 * = 0b1 || 0b00 || 0b0
9770 */
9771 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9772 }
9773
9774 #if defined(CONFIG_USER_ONLY)
9775 #define GEN_TM_PRIV_NOOP(name) \
9776 static inline void gen_##name(DisasContext *ctx) \
9777 { \
9778 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9779 }
9780
9781 #else
9782
9783 #define GEN_TM_PRIV_NOOP(name) \
9784 static inline void gen_##name(DisasContext *ctx) \
9785 { \
9786 CHK_SV; \
9787 if (unlikely(!ctx->tm_enabled)) { \
9788 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9789 return; \
9790 } \
9791 /* Because tbegin always fails, the implementation is \
9792 * simple: \
9793 * \
9794 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9795 * = 0b0 || 0b00 | 0b0 \
9796 */ \
9797 tcg_gen_movi_i32(cpu_crf[0], 0); \
9798 }
9799
9800 #endif
9801
9802 GEN_TM_PRIV_NOOP(treclaim);
9803 GEN_TM_PRIV_NOOP(trechkpt);
9804
9805 static opcode_t opcodes[] = {
9806 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9807 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9808 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9809 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9810 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9811 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9812 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9813 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9814 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9815 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9816 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9817 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9818 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9819 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9820 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9821 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9822 #if defined(TARGET_PPC64)
9823 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9824 #endif
9825 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9826 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9827 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9828 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9829 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9830 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9831 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9832 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9833 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9834 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9835 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9836 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9837 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9838 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9839 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9840 #if defined(TARGET_PPC64)
9841 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9842 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9843 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9844 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9845 #endif
9846 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9847 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9848 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9849 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9850 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9851 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9852 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9853 #if defined(TARGET_PPC64)
9854 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9855 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9856 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9857 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9858 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9859 #endif
9860 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9861 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9862 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9863 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9864 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9865 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9866 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9867 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9868 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9869 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9870 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9871 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9872 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9873 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9874 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9875 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9876 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9877 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9878 #if defined(TARGET_PPC64)
9879 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9880 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9881 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9882 #endif
9883 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9884 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9885 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9886 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9887 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9888 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9889 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9890 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9891 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9892 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9893 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9894 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9895 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9896 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9897 #if defined(TARGET_PPC64)
9898 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9899 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9900 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9901 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9902 #endif
9903 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9904 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9905 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9906 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9907 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9908 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9909 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9910 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9911 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9912 #if defined(TARGET_PPC64)
9913 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9914 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9915 #endif
9916 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9917 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9918 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9919 #if defined(TARGET_PPC64)
9920 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9921 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9922 #endif
9923 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9924 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9925 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9926 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9927 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9928 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9929 #if defined(TARGET_PPC64)
9930 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9931 #endif
9932 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
9933 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9934 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9935 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9936 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9937 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9938 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9939 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9940 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9941 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9942 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9943 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9944 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9945 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9946 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9947 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9948 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9949 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9950 #if defined(TARGET_PPC64)
9951 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9952 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9953 PPC_SEGMENT_64B),
9954 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9955 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9956 PPC_SEGMENT_64B),
9957 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9958 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9959 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9960 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
9961 #endif
9962 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9963 /* XXX Those instructions will need to be handled differently for
9964 * different ISA versions */
9965 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
9966 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
9967 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9968 #if defined(TARGET_PPC64)
9969 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
9970 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9971 #endif
9972 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9973 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9974 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9975 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9976 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9977 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9978 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9979 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9980 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9981 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9982 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9983 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9984 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9985 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9986 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9987 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9988 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9989 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9990 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9991 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9992 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9993 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9994 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9995 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9996 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9997 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9998 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9999 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10000 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10001 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10002 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10003 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10004 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10005 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10006 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10007 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10008 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10009 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10010 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10011 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10012 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10013 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10014 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10015 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10016 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10017 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10018 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10019 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10020 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10021 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10022 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10023 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10024 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10025 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10026 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10027 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10028 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10029 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10030 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10031 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10032 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10033 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10034 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10035 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10036 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10037 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10038 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10039 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10040 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10041 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10042 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10043 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10044 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10045 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10046 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10047 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10048 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10049 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10050 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10051 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10052 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10053 PPC_NONE, PPC2_BOOKE206),
10054 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10055 PPC_NONE, PPC2_BOOKE206),
10056 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10057 PPC_NONE, PPC2_BOOKE206),
10058 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10059 PPC_NONE, PPC2_BOOKE206),
10060 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10061 PPC_NONE, PPC2_BOOKE206),
10062 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10063 PPC_NONE, PPC2_PRCNTL),
10064 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10065 PPC_NONE, PPC2_PRCNTL),
10066 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10067 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10068 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10069 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10070 PPC_BOOKE, PPC2_BOOKE206),
10071 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10072 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10073 PPC_BOOKE, PPC2_BOOKE206),
10074 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10075 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10076 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10077 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10078 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10079 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10080 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10081 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10082 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10083
10084 #undef GEN_INT_ARITH_ADD
10085 #undef GEN_INT_ARITH_ADD_CONST
10086 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10087 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10088 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10089 add_ca, compute_ca, compute_ov) \
10090 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10091 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10092 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10093 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10094 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10095 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10096 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10097 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10098 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10099 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10100 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10101
10102 #undef GEN_INT_ARITH_DIVW
10103 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10104 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10105 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10106 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10107 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10108 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10109 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10110 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10111 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10112 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10113
10114 #if defined(TARGET_PPC64)
10115 #undef GEN_INT_ARITH_DIVD
10116 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10117 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10118 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10119 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10120 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10121 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10122
10123 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10124 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10125 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10126 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10127
10128 #undef GEN_INT_ARITH_MUL_HELPER
10129 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10130 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10131 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10132 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10133 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10134 #endif
10135
10136 #undef GEN_INT_ARITH_SUBF
10137 #undef GEN_INT_ARITH_SUBF_CONST
10138 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10139 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10140 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10141 add_ca, compute_ca, compute_ov) \
10142 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10143 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10144 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10145 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10146 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10147 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10148 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10149 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10150 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10151 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10152 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10153
10154 #undef GEN_LOGICAL1
10155 #undef GEN_LOGICAL2
10156 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10157 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10158 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10159 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10160 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10161 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10162 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10163 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10164 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10165 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10166 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10167 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10168 #if defined(TARGET_PPC64)
10169 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10170 #endif
10171
10172 #if defined(TARGET_PPC64)
10173 #undef GEN_PPC64_R2
10174 #undef GEN_PPC64_R4
10175 #define GEN_PPC64_R2(name, opc1, opc2) \
10176 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10177 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10178 PPC_64B)
10179 #define GEN_PPC64_R4(name, opc1, opc2) \
10180 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10181 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10182 PPC_64B), \
10183 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10184 PPC_64B), \
10185 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10186 PPC_64B)
10187 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10188 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10189 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10190 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10191 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10192 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10193 #endif
10194
10195 #undef _GEN_FLOAT_ACB
10196 #undef GEN_FLOAT_ACB
10197 #undef _GEN_FLOAT_AB
10198 #undef GEN_FLOAT_AB
10199 #undef _GEN_FLOAT_AC
10200 #undef GEN_FLOAT_AC
10201 #undef GEN_FLOAT_B
10202 #undef GEN_FLOAT_BS
10203 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10204 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10205 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10206 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10207 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10208 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10209 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10210 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10211 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10212 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10213 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10214 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10215 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10216 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10217 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10218 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10219 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10220 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10221 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10222
10223 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10224 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10225 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10226 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10227 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10228 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10229 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10230 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10231 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10232 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10233 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10234 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10235 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10236 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10237 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10238 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10239 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10240 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10241 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10242 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10243 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10244 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10245 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10246 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10247 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10248 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10249 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10250 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10251 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10252 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10253 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10254
10255 #undef GEN_LD
10256 #undef GEN_LDU
10257 #undef GEN_LDUX
10258 #undef GEN_LDX_E
10259 #undef GEN_LDS
10260 #define GEN_LD(name, ldop, opc, type) \
10261 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10262 #define GEN_LDU(name, ldop, opc, type) \
10263 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10264 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10265 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10266 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
10267 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10268 #define GEN_LDS(name, ldop, op, type) \
10269 GEN_LD(name, ldop, op | 0x20, type) \
10270 GEN_LDU(name, ldop, op | 0x21, type) \
10271 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10272 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10273
10274 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10275 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10276 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10277 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10278 #if defined(TARGET_PPC64)
10279 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10280 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10281 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10282 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10283 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
10284
10285 /* HV/P7 and later only */
10286 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
10287 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
10288 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
10289 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
10290 #endif
10291 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10292 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10293
10294 #undef GEN_ST
10295 #undef GEN_STU
10296 #undef GEN_STUX
10297 #undef GEN_STX_E
10298 #undef GEN_STS
10299 #define GEN_ST(name, stop, opc, type) \
10300 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10301 #define GEN_STU(name, stop, opc, type) \
10302 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10303 #define GEN_STUX(name, stop, opc2, opc3, type) \
10304 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10305 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
10306 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10307 #define GEN_STS(name, stop, op, type) \
10308 GEN_ST(name, stop, op | 0x20, type) \
10309 GEN_STU(name, stop, op | 0x21, type) \
10310 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10311 GEN_STX(name, stop, 0x17, op | 0x00, type)
10312
10313 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10314 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10315 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10316 #if defined(TARGET_PPC64)
10317 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10318 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10319 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
10320 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
10321 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
10322 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
10323 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
10324 #endif
10325 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10326 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10327
10328 #undef GEN_LDF
10329 #undef GEN_LDUF
10330 #undef GEN_LDUXF
10331 #undef GEN_LDXF
10332 #undef GEN_LDFS
10333 #define GEN_LDF(name, ldop, opc, type) \
10334 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10335 #define GEN_LDUF(name, ldop, opc, type) \
10336 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10337 #define GEN_LDUXF(name, ldop, opc, type) \
10338 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10339 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10340 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10341 #define GEN_LDFS(name, ldop, op, type) \
10342 GEN_LDF(name, ldop, op | 0x20, type) \
10343 GEN_LDUF(name, ldop, op | 0x21, type) \
10344 GEN_LDUXF(name, ldop, op | 0x01, type) \
10345 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10346
10347 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10348 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10349 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10350 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10351 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10352 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10353
10354 #undef GEN_STF
10355 #undef GEN_STUF
10356 #undef GEN_STUXF
10357 #undef GEN_STXF
10358 #undef GEN_STFS
10359 #define GEN_STF(name, stop, opc, type) \
10360 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10361 #define GEN_STUF(name, stop, opc, type) \
10362 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10363 #define GEN_STUXF(name, stop, opc, type) \
10364 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10365 #define GEN_STXF(name, stop, opc2, opc3, type) \
10366 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10367 #define GEN_STFS(name, stop, op, type) \
10368 GEN_STF(name, stop, op | 0x20, type) \
10369 GEN_STUF(name, stop, op | 0x21, type) \
10370 GEN_STUXF(name, stop, op | 0x01, type) \
10371 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10372
10373 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10374 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10375 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10376 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10377 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10378
10379 #undef GEN_CRLOGIC
10380 #define GEN_CRLOGIC(name, tcg_op, opc) \
10381 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10382 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10383 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10384 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10385 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10386 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10387 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10388 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10389 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10390
10391 #undef GEN_MAC_HANDLER
10392 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10393 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10394 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10395 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10396 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10397 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10398 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10399 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10400 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10401 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10402 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10403 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10404 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10405 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10406 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10407 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10408 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10409 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10410 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10411 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10412 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10413 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10414 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10415 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10416 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10417 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10418 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10419 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10420 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10421 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10422 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10423 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10424 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10425 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10426 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10427 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10428 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10429 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10430 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10431 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10432 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10433 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10434 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10435 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10436
10437 #undef GEN_VR_LDX
10438 #undef GEN_VR_STX
10439 #undef GEN_VR_LVE
10440 #undef GEN_VR_STVE
10441 #define GEN_VR_LDX(name, opc2, opc3) \
10442 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10443 #define GEN_VR_STX(name, opc2, opc3) \
10444 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10445 #define GEN_VR_LVE(name, opc2, opc3) \
10446 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10447 #define GEN_VR_STVE(name, opc2, opc3) \
10448 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10449 GEN_VR_LDX(lvx, 0x07, 0x03),
10450 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10451 GEN_VR_LVE(bx, 0x07, 0x00),
10452 GEN_VR_LVE(hx, 0x07, 0x01),
10453 GEN_VR_LVE(wx, 0x07, 0x02),
10454 GEN_VR_STX(svx, 0x07, 0x07),
10455 GEN_VR_STX(svxl, 0x07, 0x0F),
10456 GEN_VR_STVE(bx, 0x07, 0x04),
10457 GEN_VR_STVE(hx, 0x07, 0x05),
10458 GEN_VR_STVE(wx, 0x07, 0x06),
10459
10460 #undef GEN_VX_LOGICAL
10461 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10462 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10463
10464 #undef GEN_VX_LOGICAL_207
10465 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10466 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10467
10468 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10469 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10470 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10471 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10472 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10473 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10474 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10475 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10476
10477 #undef GEN_VXFORM
10478 #define GEN_VXFORM(name, opc2, opc3) \
10479 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10480
10481 #undef GEN_VXFORM_207
10482 #define GEN_VXFORM_207(name, opc2, opc3) \
10483 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10484
10485 #undef GEN_VXFORM_DUAL
10486 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10487 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10488
10489 #undef GEN_VXRFORM_DUAL
10490 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10491 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10492 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10493
10494 GEN_VXFORM(vaddubm, 0, 0),
10495 GEN_VXFORM(vadduhm, 0, 1),
10496 GEN_VXFORM(vadduwm, 0, 2),
10497 GEN_VXFORM_207(vaddudm, 0, 3),
10498 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10499 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10500 GEN_VXFORM(vsubuwm, 0, 18),
10501 GEN_VXFORM_207(vsubudm, 0, 19),
10502 GEN_VXFORM(vmaxub, 1, 0),
10503 GEN_VXFORM(vmaxuh, 1, 1),
10504 GEN_VXFORM(vmaxuw, 1, 2),
10505 GEN_VXFORM_207(vmaxud, 1, 3),
10506 GEN_VXFORM(vmaxsb, 1, 4),
10507 GEN_VXFORM(vmaxsh, 1, 5),
10508 GEN_VXFORM(vmaxsw, 1, 6),
10509 GEN_VXFORM_207(vmaxsd, 1, 7),
10510 GEN_VXFORM(vminub, 1, 8),
10511 GEN_VXFORM(vminuh, 1, 9),
10512 GEN_VXFORM(vminuw, 1, 10),
10513 GEN_VXFORM_207(vminud, 1, 11),
10514 GEN_VXFORM(vminsb, 1, 12),
10515 GEN_VXFORM(vminsh, 1, 13),
10516 GEN_VXFORM(vminsw, 1, 14),
10517 GEN_VXFORM_207(vminsd, 1, 15),
10518 GEN_VXFORM(vavgub, 1, 16),
10519 GEN_VXFORM(vavguh, 1, 17),
10520 GEN_VXFORM(vavguw, 1, 18),
10521 GEN_VXFORM(vavgsb, 1, 20),
10522 GEN_VXFORM(vavgsh, 1, 21),
10523 GEN_VXFORM(vavgsw, 1, 22),
10524 GEN_VXFORM(vmrghb, 6, 0),
10525 GEN_VXFORM(vmrghh, 6, 1),
10526 GEN_VXFORM(vmrghw, 6, 2),
10527 GEN_VXFORM(vmrglb, 6, 4),
10528 GEN_VXFORM(vmrglh, 6, 5),
10529 GEN_VXFORM(vmrglw, 6, 6),
10530 GEN_VXFORM_207(vmrgew, 6, 30),
10531 GEN_VXFORM_207(vmrgow, 6, 26),
10532 GEN_VXFORM(vmuloub, 4, 0),
10533 GEN_VXFORM(vmulouh, 4, 1),
10534 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10535 GEN_VXFORM(vmulosb, 4, 4),
10536 GEN_VXFORM(vmulosh, 4, 5),
10537 GEN_VXFORM_207(vmulosw, 4, 6),
10538 GEN_VXFORM(vmuleub, 4, 8),
10539 GEN_VXFORM(vmuleuh, 4, 9),
10540 GEN_VXFORM_207(vmuleuw, 4, 10),
10541 GEN_VXFORM(vmulesb, 4, 12),
10542 GEN_VXFORM(vmulesh, 4, 13),
10543 GEN_VXFORM_207(vmulesw, 4, 14),
10544 GEN_VXFORM(vslb, 2, 4),
10545 GEN_VXFORM(vslh, 2, 5),
10546 GEN_VXFORM(vslw, 2, 6),
10547 GEN_VXFORM_207(vsld, 2, 23),
10548 GEN_VXFORM(vsrb, 2, 8),
10549 GEN_VXFORM(vsrh, 2, 9),
10550 GEN_VXFORM(vsrw, 2, 10),
10551 GEN_VXFORM_207(vsrd, 2, 27),
10552 GEN_VXFORM(vsrab, 2, 12),
10553 GEN_VXFORM(vsrah, 2, 13),
10554 GEN_VXFORM(vsraw, 2, 14),
10555 GEN_VXFORM_207(vsrad, 2, 15),
10556 GEN_VXFORM(vslo, 6, 16),
10557 GEN_VXFORM(vsro, 6, 17),
10558 GEN_VXFORM(vaddcuw, 0, 6),
10559 GEN_VXFORM(vsubcuw, 0, 22),
10560 GEN_VXFORM(vaddubs, 0, 8),
10561 GEN_VXFORM(vadduhs, 0, 9),
10562 GEN_VXFORM(vadduws, 0, 10),
10563 GEN_VXFORM(vaddsbs, 0, 12),
10564 GEN_VXFORM(vaddshs, 0, 13),
10565 GEN_VXFORM(vaddsws, 0, 14),
10566 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10567 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10568 GEN_VXFORM(vsubuws, 0, 26),
10569 GEN_VXFORM(vsubsbs, 0, 28),
10570 GEN_VXFORM(vsubshs, 0, 29),
10571 GEN_VXFORM(vsubsws, 0, 30),
10572 GEN_VXFORM_207(vadduqm, 0, 4),
10573 GEN_VXFORM_207(vaddcuq, 0, 5),
10574 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10575 GEN_VXFORM_207(vsubuqm, 0, 20),
10576 GEN_VXFORM_207(vsubcuq, 0, 21),
10577 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10578 GEN_VXFORM(vrlb, 2, 0),
10579 GEN_VXFORM(vrlh, 2, 1),
10580 GEN_VXFORM(vrlw, 2, 2),
10581 GEN_VXFORM_207(vrld, 2, 3),
10582 GEN_VXFORM(vsl, 2, 7),
10583 GEN_VXFORM(vsr, 2, 11),
10584 GEN_VXFORM(vpkuhum, 7, 0),
10585 GEN_VXFORM(vpkuwum, 7, 1),
10586 GEN_VXFORM_207(vpkudum, 7, 17),
10587 GEN_VXFORM(vpkuhus, 7, 2),
10588 GEN_VXFORM(vpkuwus, 7, 3),
10589 GEN_VXFORM_207(vpkudus, 7, 19),
10590 GEN_VXFORM(vpkshus, 7, 4),
10591 GEN_VXFORM(vpkswus, 7, 5),
10592 GEN_VXFORM_207(vpksdus, 7, 21),
10593 GEN_VXFORM(vpkshss, 7, 6),
10594 GEN_VXFORM(vpkswss, 7, 7),
10595 GEN_VXFORM_207(vpksdss, 7, 23),
10596 GEN_VXFORM(vpkpx, 7, 12),
10597 GEN_VXFORM(vsum4ubs, 4, 24),
10598 GEN_VXFORM(vsum4sbs, 4, 28),
10599 GEN_VXFORM(vsum4shs, 4, 25),
10600 GEN_VXFORM(vsum2sws, 4, 26),
10601 GEN_VXFORM(vsumsws, 4, 30),
10602 GEN_VXFORM(vaddfp, 5, 0),
10603 GEN_VXFORM(vsubfp, 5, 1),
10604 GEN_VXFORM(vmaxfp, 5, 16),
10605 GEN_VXFORM(vminfp, 5, 17),
10606
10607 #undef GEN_VXRFORM1
10608 #undef GEN_VXRFORM
10609 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10610 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10611 #define GEN_VXRFORM(name, opc2, opc3) \
10612 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10613 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10614 GEN_VXRFORM(vcmpequb, 3, 0)
10615 GEN_VXRFORM(vcmpequh, 3, 1)
10616 GEN_VXRFORM(vcmpequw, 3, 2)
10617 GEN_VXRFORM(vcmpgtsb, 3, 12)
10618 GEN_VXRFORM(vcmpgtsh, 3, 13)
10619 GEN_VXRFORM(vcmpgtsw, 3, 14)
10620 GEN_VXRFORM(vcmpgtub, 3, 8)
10621 GEN_VXRFORM(vcmpgtuh, 3, 9)
10622 GEN_VXRFORM(vcmpgtuw, 3, 10)
10623 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10624 GEN_VXRFORM(vcmpgefp, 3, 7)
10625 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10626 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10627
10628 #undef GEN_VXFORM_SIMM
10629 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10630 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10631 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10632 GEN_VXFORM_SIMM(vspltish, 6, 13),
10633 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10634
10635 #undef GEN_VXFORM_NOA
10636 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10637 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10638 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10639 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10640 GEN_VXFORM_207(vupkhsw, 7, 25),
10641 GEN_VXFORM_NOA(vupklsb, 7, 10),
10642 GEN_VXFORM_NOA(vupklsh, 7, 11),
10643 GEN_VXFORM_207(vupklsw, 7, 27),
10644 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10645 GEN_VXFORM_NOA(vupklpx, 7, 15),
10646 GEN_VXFORM_NOA(vrefp, 5, 4),
10647 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10648 GEN_VXFORM_NOA(vexptefp, 5, 6),
10649 GEN_VXFORM_NOA(vlogefp, 5, 7),
10650 GEN_VXFORM_NOA(vrfim, 5, 11),
10651 GEN_VXFORM_NOA(vrfin, 5, 8),
10652 GEN_VXFORM_NOA(vrfip, 5, 10),
10653 GEN_VXFORM_NOA(vrfiz, 5, 9),
10654
10655 #undef GEN_VXFORM_UIMM
10656 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10657 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10658 GEN_VXFORM_UIMM(vspltb, 6, 8),
10659 GEN_VXFORM_UIMM(vsplth, 6, 9),
10660 GEN_VXFORM_UIMM(vspltw, 6, 10),
10661 GEN_VXFORM_UIMM(vcfux, 5, 12),
10662 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10663 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10664 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10665
10666 #undef GEN_VAFORM_PAIRED
10667 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10668 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10669 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10670 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10671 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10672 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10673 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10674 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10675
10676 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10677 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10678 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10679 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10680
10681 GEN_VXFORM_207(vbpermq, 6, 21),
10682 GEN_VXFORM_207(vgbbd, 6, 20),
10683 GEN_VXFORM_207(vpmsumb, 4, 16),
10684 GEN_VXFORM_207(vpmsumh, 4, 17),
10685 GEN_VXFORM_207(vpmsumw, 4, 18),
10686 GEN_VXFORM_207(vpmsumd, 4, 19),
10687
10688 GEN_VXFORM_207(vsbox, 4, 23),
10689
10690 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10691 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10692
10693 GEN_VXFORM_207(vshasigmaw, 1, 26),
10694 GEN_VXFORM_207(vshasigmad, 1, 27),
10695
10696 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10697
10698 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10699 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10700 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10701 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10702 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10703 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10704 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10705
10706 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10707 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10708 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10709 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10710 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10711
10712 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10713 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10714 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10715 #if defined(TARGET_PPC64)
10716 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10717 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10718 #endif
10719
10720 #undef GEN_XX2FORM
10721 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10724
10725 #undef GEN_XX3FORM
10726 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10728 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10729 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10730 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10731
10732 #undef GEN_XX2IFORM
10733 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10735 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10736 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10737 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10738
10739 #undef GEN_XX3_RC_FORM
10740 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10741 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10742 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10743 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10744 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10745 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10746 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10747 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10748 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10749
10750 #undef GEN_XX3FORM_DM
10751 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10752 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10753 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10754 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10755 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10756 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10757 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10758 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10759 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10760 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10761 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10762 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10763 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10764 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10765 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10766 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10767 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10768
10769 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10770 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10771 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10772 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10773
10774 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10775 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10776 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10777 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10778 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10779 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10780 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10781 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10782
10783 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10784 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10785 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10786 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10787 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10788 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10789 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10790 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10791 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10792 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10793 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10794 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10795 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10796 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10797 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10798 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10799 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10800 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10801 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10802 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10803 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10804 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10805 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10806 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10807 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10808 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10809 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10810 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10811 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10812 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10813 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10814 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10815 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10816 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10817 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10818 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10819
10820 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10821 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10822 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10823 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10824 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10825 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10826 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10827 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10828 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10829 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10830 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10831 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10832 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10833 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10834 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10835 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10836 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10837 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10838
10839 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10840 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10841 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10842 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10843 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10844 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10845 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10846 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10847 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10848 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10849 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10850 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10851 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10852 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10853 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10854 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10855 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10856 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10857 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10858 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10859 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10860 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10861 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10862 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10863 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10864 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10865 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10866 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10867 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10868 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10869 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10870 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10871 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10872 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10873 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10874 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10875
10876 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10877 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10878 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10879 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10880 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10881 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10882 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10883 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10884 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10885 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10886 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10887 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10888 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10889 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10890 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10891 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10892 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10893 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10894 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10895 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10896 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10897 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10898 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10899 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10900 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10901 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10902 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10903 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10904 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10905 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10906 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10907 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10908 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10909 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10910 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10911 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10912
10913 #undef VSX_LOGICAL
10914 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10915 GEN_XX3FORM(name, opc2, opc3, fl2)
10916
10917 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10918 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10919 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10920 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10921 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10922 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10923 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10924 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10925 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10926 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10927 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10928 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10929
10930 #define GEN_XXSEL_ROW(opc3) \
10931 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10932 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10933 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10934 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10935 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10936 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10937 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10938 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10939
10940 GEN_XXSEL_ROW(0x00)
10941 GEN_XXSEL_ROW(0x01)
10942 GEN_XXSEL_ROW(0x02)
10943 GEN_XXSEL_ROW(0x03)
10944 GEN_XXSEL_ROW(0x04)
10945 GEN_XXSEL_ROW(0x05)
10946 GEN_XXSEL_ROW(0x06)
10947 GEN_XXSEL_ROW(0x07)
10948 GEN_XXSEL_ROW(0x08)
10949 GEN_XXSEL_ROW(0x09)
10950 GEN_XXSEL_ROW(0x0A)
10951 GEN_XXSEL_ROW(0x0B)
10952 GEN_XXSEL_ROW(0x0C)
10953 GEN_XXSEL_ROW(0x0D)
10954 GEN_XXSEL_ROW(0x0E)
10955 GEN_XXSEL_ROW(0x0F)
10956 GEN_XXSEL_ROW(0x10)
10957 GEN_XXSEL_ROW(0x11)
10958 GEN_XXSEL_ROW(0x12)
10959 GEN_XXSEL_ROW(0x13)
10960 GEN_XXSEL_ROW(0x14)
10961 GEN_XXSEL_ROW(0x15)
10962 GEN_XXSEL_ROW(0x16)
10963 GEN_XXSEL_ROW(0x17)
10964 GEN_XXSEL_ROW(0x18)
10965 GEN_XXSEL_ROW(0x19)
10966 GEN_XXSEL_ROW(0x1A)
10967 GEN_XXSEL_ROW(0x1B)
10968 GEN_XXSEL_ROW(0x1C)
10969 GEN_XXSEL_ROW(0x1D)
10970 GEN_XXSEL_ROW(0x1E)
10971 GEN_XXSEL_ROW(0x1F)
10972
10973 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10974
10975 #undef GEN_DFP_T_A_B_Rc
10976 #undef GEN_DFP_BF_A_B
10977 #undef GEN_DFP_BF_A_DCM
10978 #undef GEN_DFP_T_B_U32_U32_Rc
10979 #undef GEN_DFP_T_A_B_I32_Rc
10980 #undef GEN_DFP_T_B_Rc
10981 #undef GEN_DFP_T_FPR_I32_Rc
10982
10983 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10984 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10985
10986 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10987 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10988 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10989
10990 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10991 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10992 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10993 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10994 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10995
10996 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10997 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10998
10999 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11000 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11001 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11002
11003 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11004 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11005 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11006 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11007 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11008
11009 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11010 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11011
11012 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11013 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11014
11015 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11016 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11017
11018 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11019 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11020
11021 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11022 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11023
11024 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11025 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11026
11027 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11028 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11029
11030 #define GEN_DFP_BF_A_B(name, op1, op2) \
11031 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11032
11033 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11034 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11035
11036 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11037 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11038
11039 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11040 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11041
11042 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11043 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11044
11045 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11046 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11047
11048 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11049 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11050
11051 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11052 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11053
11054 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11055 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11056
11057 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11058 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11059
11060 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11061 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11062
11063 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11064 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11065
11066 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11067 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11068
11069 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11070 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11071
11072 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11073 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11074
11075 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11076 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11077
11078 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11079 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11080
11081 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11082 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11083
11084 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11085 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11086 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11087 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11088 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11089 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11090 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11091 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11092 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11093 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11094 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11095 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11096 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11097 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11098 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11099 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11100 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11101 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11102 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11103 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11104 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11105 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11106 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11107 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11108 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11109 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11110 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11111 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11112 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11113 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11114 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11115 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11116 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11117 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11118 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11119 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11120 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11121 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11122 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11123 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11124 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11125 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11126 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11127 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11128 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11129 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11130 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11131 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11132 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11133 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11134
11135 #undef GEN_SPE
11136 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11137 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11138 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11139 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11140 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11141 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11142 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11143 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11144 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11145 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11146 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11147 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11148 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11149 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11150 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11151 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11152 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11153 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11154 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11155 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11156 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11157 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11158 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11159 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11160 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11161 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11162 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11163 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11164 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11165 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11166 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11167
11168 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11169 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11170 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11171 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11172 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11173 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11174 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11175 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11176 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11177 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11178 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11179 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11180 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11181 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11182
11183 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11184 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11185 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11186 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11187 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11188 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11189 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11190 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11191 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11192 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11193 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11194 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11195 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11196 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11197
11198 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11199 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11200 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11201 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11202 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11203 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11204 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11205 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11206 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11207 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11208 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11209 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11210 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11211 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11212 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11213 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11214
11215 #undef GEN_SPEOP_LDST
11216 #define GEN_SPEOP_LDST(name, opc2, sh) \
11217 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11218 GEN_SPEOP_LDST(evldd, 0x00, 3),
11219 GEN_SPEOP_LDST(evldw, 0x01, 3),
11220 GEN_SPEOP_LDST(evldh, 0x02, 3),
11221 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11222 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11223 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11224 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11225 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11226 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11227 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11228 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11229
11230 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11231 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11232 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11233 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11234 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11235 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11236 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11237
11238 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11239 PPC_NONE, PPC2_TM),
11240 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11241 PPC_NONE, PPC2_TM),
11242 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11243 PPC_NONE, PPC2_TM),
11244 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11245 PPC_NONE, PPC2_TM),
11246 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11247 PPC_NONE, PPC2_TM),
11248 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11249 PPC_NONE, PPC2_TM),
11250 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11251 PPC_NONE, PPC2_TM),
11252 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11253 PPC_NONE, PPC2_TM),
11254 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11255 PPC_NONE, PPC2_TM),
11256 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11257 PPC_NONE, PPC2_TM),
11258 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11259 PPC_NONE, PPC2_TM),
11260 };
11261
11262 #include "helper_regs.h"
11263 #include "translate_init.c"
11264
11265 /*****************************************************************************/
11266 /* Misc PowerPC helpers */
11267 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11268 int flags)
11269 {
11270 #define RGPL 4
11271 #define RFPL 4
11272
11273 PowerPCCPU *cpu = POWERPC_CPU(cs);
11274 CPUPPCState *env = &cpu->env;
11275 int i;
11276
11277 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11278 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11279 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11280 cs->cpu_index);
11281 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11282 TARGET_FMT_lx " iidx %d didx %d\n",
11283 env->msr, env->spr[SPR_HID0],
11284 env->hflags, env->immu_idx, env->dmmu_idx);
11285 #if !defined(NO_TIMER_DUMP)
11286 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11287 #if !defined(CONFIG_USER_ONLY)
11288 " DECR %08" PRIu32
11289 #endif
11290 "\n",
11291 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11292 #if !defined(CONFIG_USER_ONLY)
11293 , cpu_ppc_load_decr(env)
11294 #endif
11295 );
11296 #endif
11297 for (i = 0; i < 32; i++) {
11298 if ((i & (RGPL - 1)) == 0)
11299 cpu_fprintf(f, "GPR%02d", i);
11300 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11301 if ((i & (RGPL - 1)) == (RGPL - 1))
11302 cpu_fprintf(f, "\n");
11303 }
11304 cpu_fprintf(f, "CR ");
11305 for (i = 0; i < 8; i++)
11306 cpu_fprintf(f, "%01x", env->crf[i]);
11307 cpu_fprintf(f, " [");
11308 for (i = 0; i < 8; i++) {
11309 char a = '-';
11310 if (env->crf[i] & 0x08)
11311 a = 'L';
11312 else if (env->crf[i] & 0x04)
11313 a = 'G';
11314 else if (env->crf[i] & 0x02)
11315 a = 'E';
11316 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11317 }
11318 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11319 env->reserve_addr);
11320 for (i = 0; i < 32; i++) {
11321 if ((i & (RFPL - 1)) == 0)
11322 cpu_fprintf(f, "FPR%02d", i);
11323 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11324 if ((i & (RFPL - 1)) == (RFPL - 1))
11325 cpu_fprintf(f, "\n");
11326 }
11327 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11328 #if !defined(CONFIG_USER_ONLY)
11329 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11330 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11331 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11332 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11333
11334 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11335 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11336 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11337 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11338
11339 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11340 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11341 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11342 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11343
11344 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11345 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11346 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11347 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11348 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11349
11350 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11351 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11352 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11353 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11354
11355 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11356 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11357 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11358 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11359
11360 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11361 " EPR " TARGET_FMT_lx "\n",
11362 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11363 env->spr[SPR_BOOKE_EPR]);
11364
11365 /* FSL-specific */
11366 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11367 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11368 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11369 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11370
11371 /*
11372 * IVORs are left out as they are large and do not change often --
11373 * they can be read with "p $ivor0", "p $ivor1", etc.
11374 */
11375 }
11376
11377 #if defined(TARGET_PPC64)
11378 if (env->flags & POWERPC_FLAG_CFAR) {
11379 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11380 }
11381 #endif
11382
11383 switch (env->mmu_model) {
11384 case POWERPC_MMU_32B:
11385 case POWERPC_MMU_601:
11386 case POWERPC_MMU_SOFT_6xx:
11387 case POWERPC_MMU_SOFT_74xx:
11388 #if defined(TARGET_PPC64)
11389 case POWERPC_MMU_64B:
11390 case POWERPC_MMU_2_03:
11391 case POWERPC_MMU_2_06:
11392 case POWERPC_MMU_2_06a:
11393 case POWERPC_MMU_2_07:
11394 case POWERPC_MMU_2_07a:
11395 #endif
11396 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11397 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11398 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11399 break;
11400 case POWERPC_MMU_BOOKE206:
11401 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11402 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11403 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11404 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11405
11406 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11407 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11408 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11409 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11410
11411 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11412 " TLB1CFG " TARGET_FMT_lx "\n",
11413 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11414 env->spr[SPR_BOOKE_TLB1CFG]);
11415 break;
11416 default:
11417 break;
11418 }
11419 #endif
11420
11421 #undef RGPL
11422 #undef RFPL
11423 }
11424
11425 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11426 fprintf_function cpu_fprintf, int flags)
11427 {
11428 #if defined(DO_PPC_STATISTICS)
11429 PowerPCCPU *cpu = POWERPC_CPU(cs);
11430 opc_handler_t **t1, **t2, **t3, *handler;
11431 int op1, op2, op3;
11432
11433 t1 = cpu->env.opcodes;
11434 for (op1 = 0; op1 < 64; op1++) {
11435 handler = t1[op1];
11436 if (is_indirect_opcode(handler)) {
11437 t2 = ind_table(handler);
11438 for (op2 = 0; op2 < 32; op2++) {
11439 handler = t2[op2];
11440 if (is_indirect_opcode(handler)) {
11441 t3 = ind_table(handler);
11442 for (op3 = 0; op3 < 32; op3++) {
11443 handler = t3[op3];
11444 if (handler->count == 0)
11445 continue;
11446 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11447 "%016" PRIx64 " %" PRId64 "\n",
11448 op1, op2, op3, op1, (op3 << 5) | op2,
11449 handler->oname,
11450 handler->count, handler->count);
11451 }
11452 } else {
11453 if (handler->count == 0)
11454 continue;
11455 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11456 "%016" PRIx64 " %" PRId64 "\n",
11457 op1, op2, op1, op2, handler->oname,
11458 handler->count, handler->count);
11459 }
11460 }
11461 } else {
11462 if (handler->count == 0)
11463 continue;
11464 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11465 " %" PRId64 "\n",
11466 op1, op1, handler->oname,
11467 handler->count, handler->count);
11468 }
11469 }
11470 #endif
11471 }
11472
11473 /*****************************************************************************/
11474 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11475 {
11476 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11477 CPUState *cs = CPU(cpu);
11478 DisasContext ctx, *ctxp = &ctx;
11479 opc_handler_t **table, *handler;
11480 target_ulong pc_start;
11481 int num_insns;
11482 int max_insns;
11483
11484 pc_start = tb->pc;
11485 ctx.nip = pc_start;
11486 ctx.tb = tb;
11487 ctx.exception = POWERPC_EXCP_NONE;
11488 ctx.spr_cb = env->spr_cb;
11489 ctx.pr = msr_pr;
11490 ctx.mem_idx = env->dmmu_idx;
11491 ctx.dr = msr_dr;
11492 #if !defined(CONFIG_USER_ONLY)
11493 ctx.hv = msr_hv || !env->has_hv_mode;
11494 #endif
11495 ctx.insns_flags = env->insns_flags;
11496 ctx.insns_flags2 = env->insns_flags2;
11497 ctx.access_type = -1;
11498 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
11499 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11500 #if defined(TARGET_PPC64)
11501 ctx.sf_mode = msr_is_64bit(env, env->msr);
11502 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11503 #endif
11504 if (env->mmu_model == POWERPC_MMU_32B ||
11505 env->mmu_model == POWERPC_MMU_601 ||
11506 (env->mmu_model & POWERPC_MMU_64B))
11507 ctx.lazy_tlb_flush = true;
11508
11509 ctx.fpu_enabled = !!msr_fp;
11510 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11511 ctx.spe_enabled = !!msr_spe;
11512 else
11513 ctx.spe_enabled = false;
11514 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11515 ctx.altivec_enabled = !!msr_vr;
11516 else
11517 ctx.altivec_enabled = false;
11518 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11519 ctx.vsx_enabled = !!msr_vsx;
11520 } else {
11521 ctx.vsx_enabled = false;
11522 }
11523 #if defined(TARGET_PPC64)
11524 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11525 ctx.tm_enabled = !!msr_tm;
11526 } else {
11527 ctx.tm_enabled = false;
11528 }
11529 #endif
11530 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11531 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11532 else
11533 ctx.singlestep_enabled = 0;
11534 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11535 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11536 if (unlikely(cs->singlestep_enabled)) {
11537 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11538 }
11539 #if defined (DO_SINGLE_STEP) && 0
11540 /* Single step trace mode */
11541 msr_se = 1;
11542 #endif
11543 num_insns = 0;
11544 max_insns = tb->cflags & CF_COUNT_MASK;
11545 if (max_insns == 0) {
11546 max_insns = CF_COUNT_MASK;
11547 }
11548 if (max_insns > TCG_MAX_INSNS) {
11549 max_insns = TCG_MAX_INSNS;
11550 }
11551
11552 gen_tb_start(tb);
11553 tcg_clear_temp_count();
11554 /* Set env in case of segfault during code fetch */
11555 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11556 tcg_gen_insn_start(ctx.nip);
11557 num_insns++;
11558
11559 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11560 gen_debug_exception(ctxp);
11561 /* The address covered by the breakpoint must be included in
11562 [tb->pc, tb->pc + tb->size) in order to for it to be
11563 properly cleared -- thus we increment the PC here so that
11564 the logic setting tb->size below does the right thing. */
11565 ctx.nip += 4;
11566 break;
11567 }
11568
11569 LOG_DISAS("----------------\n");
11570 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11571 ctx.nip, ctx.mem_idx, (int)msr_ir);
11572 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11573 gen_io_start();
11574 if (unlikely(need_byteswap(&ctx))) {
11575 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11576 } else {
11577 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11578 }
11579 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11580 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11581 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11582 ctx.nip += 4;
11583 table = env->opcodes;
11584 handler = table[opc1(ctx.opcode)];
11585 if (is_indirect_opcode(handler)) {
11586 table = ind_table(handler);
11587 handler = table[opc2(ctx.opcode)];
11588 if (is_indirect_opcode(handler)) {
11589 table = ind_table(handler);
11590 handler = table[opc3(ctx.opcode)];
11591 }
11592 }
11593 /* Is opcode *REALLY* valid ? */
11594 if (unlikely(handler->handler == &gen_invalid)) {
11595 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11596 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11597 opc1(ctx.opcode), opc2(ctx.opcode),
11598 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11599 } else {
11600 uint32_t inval;
11601
11602 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11603 inval = handler->inval2;
11604 } else {
11605 inval = handler->inval1;
11606 }
11607
11608 if (unlikely((ctx.opcode & inval) != 0)) {
11609 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11610 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11611 ctx.opcode & inval, opc1(ctx.opcode),
11612 opc2(ctx.opcode), opc3(ctx.opcode),
11613 ctx.opcode, ctx.nip - 4);
11614 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11615 break;
11616 }
11617 }
11618 (*(handler->handler))(&ctx);
11619 #if defined(DO_PPC_STATISTICS)
11620 handler->count++;
11621 #endif
11622 /* Check trace mode exceptions */
11623 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11624 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11625 ctx.exception != POWERPC_SYSCALL &&
11626 ctx.exception != POWERPC_EXCP_TRAP &&
11627 ctx.exception != POWERPC_EXCP_BRANCH)) {
11628 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11629 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11630 (cs->singlestep_enabled) ||
11631 singlestep ||
11632 num_insns >= max_insns)) {
11633 /* if we reach a page boundary or are single stepping, stop
11634 * generation
11635 */
11636 break;
11637 }
11638 if (tcg_check_temp_count()) {
11639 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11640 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11641 ctx.opcode);
11642 exit(1);
11643 }
11644 }
11645 if (tb->cflags & CF_LAST_IO)
11646 gen_io_end();
11647 if (ctx.exception == POWERPC_EXCP_NONE) {
11648 gen_goto_tb(&ctx, 0, ctx.nip);
11649 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11650 if (unlikely(cs->singlestep_enabled)) {
11651 gen_debug_exception(ctxp);
11652 }
11653 /* Generate the return instruction */
11654 tcg_gen_exit_tb(0);
11655 }
11656 gen_tb_end(tb, num_insns);
11657
11658 tb->size = ctx.nip - pc_start;
11659 tb->icount = num_insns;
11660
11661 #if defined(DEBUG_DISAS)
11662 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11663 && qemu_log_in_addr_range(pc_start)) {
11664 int flags;
11665 flags = env->bfd_mach;
11666 flags |= ctx.le_mode << 16;
11667 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11668 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11669 qemu_log("\n");
11670 }
11671 #endif
11672 }
11673
11674 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11675 target_ulong *data)
11676 {
11677 env->nip = data[0];
11678 }
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