include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "exec/memory.h"
   5 #include "sysemu/dma.h"
   6
   7 /* PCI includes legacy ISA access.  */
   8 #include "hw/isa/isa.h"
   9
  10 #include "hw/pci/pcie.h"
  11
  12 extern bool pci_available;
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  21 #define PCI_BUS_MAX             256
  22 #define PCI_DEVFN_MAX           256
  23 #define PCI_SLOT_MAX            32
  24 #define PCI_FUNC_MAX            8
  25
  26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  27 #include "hw/pci/pci_ids.h"
  28
  29 /* QEMU-specific Vendor and Device ID definitions */
  30
  31 /* IBM (0x1014) */
  32 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  33 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  34
  35 /* Hitachi (0x1054) */
  36 #define PCI_VENDOR_ID_HITACHI            0x1054
  37 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  38
  39 /* Apple (0x106b) */
  40 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  44 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  45
  46 /* Realtek (0x10ec) */
  47 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  48
  49 /* Xilinx (0x10ee) */
  50 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  51
  52 /* Marvell (0x11ab) */
  53 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  54
  55 /* QEMU/Bochs VGA (0x1234) */
  56 #define PCI_VENDOR_ID_QEMU               0x1234
  57 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  58 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
  59
  60 /* VMWare (0x15ad) */
  61 #define PCI_VENDOR_ID_VMWARE             0x15ad
  62 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  63 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  64 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  65 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  66 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  67 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  68 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  69
  70 /* Intel (0x8086) */
  71 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  72 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  73 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  74
  75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  76 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  78 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  79
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88 #define PCI_DEVICE_ID_VIRTIO_PMEM        0x1013
  89 #define PCI_DEVICE_ID_VIRTIO_IOMMU       0x1014
  90 #define PCI_DEVICE_ID_VIRTIO_MEM         0x1015
  91
  92 #define PCI_VENDOR_ID_REDHAT             0x1b36
  93 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  94 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  95 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  96 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  97 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  98 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  99 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
 100 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
 101 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
 102 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 103 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 104 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 105 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 106 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 107 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 108 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 109
 110 #define FMT_PCIBUS                      PRIx64
 111
 112 typedef uint64_t pcibus_t;
 113
 114 struct PCIHostDeviceAddress {
 115     unsigned int domain;
 116     unsigned int bus;
 117     unsigned int slot;
 118     unsigned int function;
 119 };
 120
 121 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 122                                 uint32_t address, uint32_t data, int len);
 123 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 124                                    uint32_t address, int len);
 125 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 126                                 pcibus_t addr, pcibus_t size, int type);
 127 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 128
 129 typedef struct PCIIORegion {
 130     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 131 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 132     pcibus_t size;
 133     uint8_t type;
 134     MemoryRegion *memory;
 135     MemoryRegion *address_space;
 136 } PCIIORegion;
 137
 138 #define PCI_ROM_SLOT 6
 139 #define PCI_NUM_REGIONS 7
 140
 141 enum {
 142     QEMU_PCI_VGA_MEM,
 143     QEMU_PCI_VGA_IO_LO,
 144     QEMU_PCI_VGA_IO_HI,
 145     QEMU_PCI_VGA_NUM_REGIONS,
 146 };
 147
 148 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 149 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 150 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 151 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 152 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 153 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 154
 155 #include "hw/pci/pci_regs.h"
 156
 157 /* PCI HEADER_TYPE */
 158 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 159
 160 /* Size of the standard PCI config header */
 161 #define PCI_CONFIG_HEADER_SIZE 0x40
 162 /* Size of the standard PCI config space */
 163 #define PCI_CONFIG_SPACE_SIZE 0x100
 164 /* Size of the standard PCIe config space: 4KB */
 165 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 166
 167 #define PCI_NUM_PINS 4 /* A-D */
 168
 169 /* Bits in cap_present field. */
 170 enum {
 171     QEMU_PCI_CAP_MSI = 0x1,
 172     QEMU_PCI_CAP_MSIX = 0x2,
 173     QEMU_PCI_CAP_EXPRESS = 0x4,
 174
 175     /* multifunction capable device */
 176 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 177     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 178
 179     /* command register SERR bit enabled - unused since QEMU v5.0 */
 180 #define QEMU_PCI_CAP_SERR_BITNR 4
 181     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 182     /* Standard hot plug controller. */
 183 #define QEMU_PCI_SHPC_BITNR 5
 184     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 185 #define QEMU_PCI_SLOTID_BITNR 6
 186     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 187     /* PCI Express capability - Power Controller Present */
 188 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 189     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 190     /* Link active status in endpoint capability is always set */
 191 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 192     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 193 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 194     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 195 };
 196
 197 #define TYPE_PCI_DEVICE "pci-device"
 198 #define PCI_DEVICE(obj) \
 199      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 200 #define PCI_DEVICE_CLASS(klass) \
 201      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 202 #define PCI_DEVICE_GET_CLASS(obj) \
 203      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 204
 205 /* Implemented by devices that can be plugged on PCI Express buses */
 206 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 207
 208 /* Implemented by devices that can be plugged on Conventional PCI buses */
 209 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 210
 211 typedef struct PCIINTxRoute {
 212     enum {
 213         PCI_INTX_ENABLED,
 214         PCI_INTX_INVERTED,
 215         PCI_INTX_DISABLED,
 216     } mode;
 217     int irq;
 218 } PCIINTxRoute;
 219
 220 typedef struct PCIDeviceClass {
 221     DeviceClass parent_class;
 222
 223     void (*realize)(PCIDevice *dev, Error **errp);
 224     PCIUnregisterFunc *exit;
 225     PCIConfigReadFunc *config_read;
 226     PCIConfigWriteFunc *config_write;
 227
 228     uint16_t vendor_id;
 229     uint16_t device_id;
 230     uint8_t revision;
 231     uint16_t class_id;
 232     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 233     uint16_t subsystem_id;              /* only for header type = 0 */
 234
 235     /*
 236      * pci-to-pci bridge or normal device.
 237      * This doesn't mean pci host switch.
 238      * When card bus bridge is supported, this would be enhanced.
 239      */
 240     bool is_bridge;
 241
 242     /* rom bar */
 243     const char *romfile;
 244 } PCIDeviceClass;
 245
 246 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 247 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 248                                       MSIMessage msg);
 249 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 250 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 251                                       unsigned int vector_start,
 252                                       unsigned int vector_end);
 253
 254 enum PCIReqIDType {
 255     PCI_REQ_ID_INVALID = 0,
 256     PCI_REQ_ID_BDF,
 257     PCI_REQ_ID_SECONDARY_BUS,
 258     PCI_REQ_ID_MAX,
 259 };
 260 typedef enum PCIReqIDType PCIReqIDType;
 261
 262 struct PCIReqIDCache {
 263     PCIDevice *dev;
 264     PCIReqIDType type;
 265 };
 266 typedef struct PCIReqIDCache PCIReqIDCache;
 267
 268 struct PCIDevice {
 269     DeviceState qdev;
 270     bool partially_hotplugged;
 271
 272     /* PCI config space */
 273     uint8_t *config;
 274
 275     /* Used to enable config checks on load. Note that writable bits are
 276      * never checked even if set in cmask. */
 277     uint8_t *cmask;
 278
 279     /* Used to implement R/W bytes */
 280     uint8_t *wmask;
 281
 282     /* Used to implement RW1C(Write 1 to Clear) bytes */
 283     uint8_t *w1cmask;
 284
 285     /* Used to allocate config space for capabilities. */
 286     uint8_t *used;
 287
 288     /* the following fields are read only */
 289     int32_t devfn;
 290     /* Cached device to fetch requester ID from, to avoid the PCI
 291      * tree walking every time we invoke PCI request (e.g.,
 292      * MSI). For conventional PCI root complex, this field is
 293      * meaningless. */
 294     PCIReqIDCache requester_id_cache;
 295     char name[64];
 296     PCIIORegion io_regions[PCI_NUM_REGIONS];
 297     AddressSpace bus_master_as;
 298     MemoryRegion bus_master_container_region;
 299     MemoryRegion bus_master_enable_region;
 300
 301     /* do not access the following fields */
 302     PCIConfigReadFunc *config_read;
 303     PCIConfigWriteFunc *config_write;
 304
 305     /* Legacy PCI VGA regions */
 306     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 307     bool has_vga;
 308
 309     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 310     uint8_t irq_state;
 311
 312     /* Capability bits */
 313     uint32_t cap_present;
 314
 315     /* Offset of MSI-X capability in config space */
 316     uint8_t msix_cap;
 317
 318     /* MSI-X entries */
 319     int msix_entries_nr;
 320
 321     /* Space to store MSIX table & pending bit array */
 322     uint8_t *msix_table;
 323     uint8_t *msix_pba;
 324     /* MemoryRegion container for msix exclusive BAR setup */
 325     MemoryRegion msix_exclusive_bar;
 326     /* Memory Regions for MSIX table and pending bit entries. */
 327     MemoryRegion msix_table_mmio;
 328     MemoryRegion msix_pba_mmio;
 329     /* Reference-count for entries actually in use by driver. */
 330     unsigned *msix_entry_used;
 331     /* MSIX function mask set or MSIX disabled */
 332     bool msix_function_masked;
 333     /* Version id needed for VMState */
 334     int32_t version_id;
 335
 336     /* Offset of MSI capability in config space */
 337     uint8_t msi_cap;
 338
 339     /* PCI Express */
 340     PCIExpressDevice exp;
 341
 342     /* SHPC */
 343     SHPCDevice *shpc;
 344
 345     /* Location of option rom */
 346     char *romfile;
 347     bool has_rom;
 348     MemoryRegion rom;
 349     uint32_t rom_bar;
 350
 351     /* INTx routing notifier */
 352     PCIINTxRoutingNotifier intx_routing_notifier;
 353
 354     /* MSI-X notifiers */
 355     MSIVectorUseNotifier msix_vector_use_notifier;
 356     MSIVectorReleaseNotifier msix_vector_release_notifier;
 357     MSIVectorPollNotifier msix_vector_poll_notifier;
 358
 359     /* ID of standby device in net_failover pair */
 360     char *failover_pair_id;
 361 };
 362
 363 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 364                       uint8_t attr, MemoryRegion *memory);
 365 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 366                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 367 void pci_unregister_vga(PCIDevice *pci_dev);
 368 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 369
 370 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 371                        uint8_t offset, uint8_t size,
 372                        Error **errp);
 373
 374 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 375
 376 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 377
 378
 379 uint32_t pci_default_read_config(PCIDevice *d,
 380                                  uint32_t address, int len);
 381 void pci_default_write_config(PCIDevice *d,
 382                               uint32_t address, uint32_t val, int len);
 383 void pci_device_save(PCIDevice *s, QEMUFile *f);
 384 int pci_device_load(PCIDevice *s, QEMUFile *f);
 385 MemoryRegion *pci_address_space(PCIDevice *dev);
 386 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 387
 388 /*
 389  * Should not normally be used by devices. For use by sPAPR target
 390  * where QEMU emulates firmware.
 391  */
 392 int pci_bar(PCIDevice *d, int reg);
 393
 394 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 395 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 396 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 397
 398 #define TYPE_PCI_BUS "PCI"
 399 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 400 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 401 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 402 #define TYPE_PCIE_BUS "PCIE"
 403
 404 bool pci_bus_is_express(PCIBus *bus);
 405
 406 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 407                               const char *name,
 408                               MemoryRegion *address_space_mem,
 409                               MemoryRegion *address_space_io,
 410                               uint8_t devfn_min, const char *typename);
 411 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 412                          MemoryRegion *address_space_mem,
 413                          MemoryRegion *address_space_io,
 414                          uint8_t devfn_min, const char *typename);
 415 void pci_root_bus_cleanup(PCIBus *bus);
 416 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 417                   void *irq_opaque, int nirq);
 418 void pci_bus_irqs_cleanup(PCIBus *bus);
 419 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 420 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 421 static inline int pci_swizzle(int slot, int pin)
 422 {
 423     return (slot + pin) % PCI_NUM_PINS;
 424 }
 425 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 426 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 427                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 428                               void *irq_opaque,
 429                               MemoryRegion *address_space_mem,
 430                               MemoryRegion *address_space_io,
 431                               uint8_t devfn_min, int nirq,
 432                               const char *typename);
 433 void pci_unregister_root_bus(PCIBus *bus);
 434 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 435 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 436 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 437 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 438 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 439                                           PCIINTxRoutingNotifier notifier);
 440 void pci_device_reset(PCIDevice *dev);
 441
 442 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 443                                const char *default_model,
 444                                const char *default_devaddr);
 445
 446 PCIDevice *pci_vga_init(PCIBus *bus);
 447
 448 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 449 {
 450     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 451 }
 452 int pci_bus_num(PCIBus *s);
 453 static inline int pci_dev_bus_num(const PCIDevice *dev)
 454 {
 455     return pci_bus_num(pci_get_bus(dev));
 456 }
 457
 458 int pci_bus_numa_node(PCIBus *bus);
 459 void pci_for_each_device(PCIBus *bus, int bus_num,
 460                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 461                          void *opaque);
 462 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 463                                  void (*fn)(PCIBus *bus, PCIDevice *d,
 464                                             void *opaque),
 465                                  void *opaque);
 466 void pci_for_each_bus_depth_first(PCIBus *bus,
 467                                   void *(*begin)(PCIBus *bus, void *parent_state),
 468                                   void (*end)(PCIBus *bus, void *state),
 469                                   void *parent_state);
 470 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 471
 472 /* Use this wrapper when specific scan order is not required. */
 473 static inline
 474 void pci_for_each_bus(PCIBus *bus,
 475                       void (*fn)(PCIBus *bus, void *opaque),
 476                       void *opaque)
 477 {
 478     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 479 }
 480
 481 PCIBus *pci_device_root_bus(const PCIDevice *d);
 482 const char *pci_root_bus_path(PCIDevice *dev);
 483 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 484 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 485 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 486
 487 void pci_device_deassert_intx(PCIDevice *dev);
 488
 489 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 490
 491 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 492 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 493
 494 static inline void
 495 pci_set_byte(uint8_t *config, uint8_t val)
 496 {
 497     *config = val;
 498 }
 499
 500 static inline uint8_t
 501 pci_get_byte(const uint8_t *config)
 502 {
 503     return *config;
 504 }
 505
 506 static inline void
 507 pci_set_word(uint8_t *config, uint16_t val)
 508 {
 509     stw_le_p(config, val);
 510 }
 511
 512 static inline uint16_t
 513 pci_get_word(const uint8_t *config)
 514 {
 515     return lduw_le_p(config);
 516 }
 517
 518 static inline void
 519 pci_set_long(uint8_t *config, uint32_t val)
 520 {
 521     stl_le_p(config, val);
 522 }
 523
 524 static inline uint32_t
 525 pci_get_long(const uint8_t *config)
 526 {
 527     return ldl_le_p(config);
 528 }
 529
 530 /*
 531  * PCI capabilities and/or their fields
 532  * are generally DWORD aligned only so
 533  * mechanism used by pci_set/get_quad()
 534  * must be tolerant to unaligned pointers
 535  *
 536  */
 537 static inline void
 538 pci_set_quad(uint8_t *config, uint64_t val)
 539 {
 540     stq_le_p(config, val);
 541 }
 542
 543 static inline uint64_t
 544 pci_get_quad(const uint8_t *config)
 545 {
 546     return ldq_le_p(config);
 547 }
 548
 549 static inline void
 550 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 551 {
 552     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 553 }
 554
 555 static inline void
 556 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 557 {
 558     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 559 }
 560
 561 static inline void
 562 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 563 {
 564     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 565 }
 566
 567 static inline void
 568 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 569 {
 570     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 571 }
 572
 573 static inline void
 574 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 575 {
 576     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 577 }
 578
 579 static inline void
 580 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 581 {
 582     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 583 }
 584
 585 /*
 586  * helper functions to do bit mask operation on configuration space.
 587  * Just to set bit, use test-and-set and discard returned value.
 588  * Just to clear bit, use test-and-clear and discard returned value.
 589  * NOTE: They aren't atomic.
 590  */
 591 static inline uint8_t
 592 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 593 {
 594     uint8_t val = pci_get_byte(config);
 595     pci_set_byte(config, val & ~mask);
 596     return val & mask;
 597 }
 598
 599 static inline uint8_t
 600 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 601 {
 602     uint8_t val = pci_get_byte(config);
 603     pci_set_byte(config, val | mask);
 604     return val & mask;
 605 }
 606
 607 static inline uint16_t
 608 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 609 {
 610     uint16_t val = pci_get_word(config);
 611     pci_set_word(config, val & ~mask);
 612     return val & mask;
 613 }
 614
 615 static inline uint16_t
 616 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 617 {
 618     uint16_t val = pci_get_word(config);
 619     pci_set_word(config, val | mask);
 620     return val & mask;
 621 }
 622
 623 static inline uint32_t
 624 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 625 {
 626     uint32_t val = pci_get_long(config);
 627     pci_set_long(config, val & ~mask);
 628     return val & mask;
 629 }
 630
 631 static inline uint32_t
 632 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 633 {
 634     uint32_t val = pci_get_long(config);
 635     pci_set_long(config, val | mask);
 636     return val & mask;
 637 }
 638
 639 static inline uint64_t
 640 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 641 {
 642     uint64_t val = pci_get_quad(config);
 643     pci_set_quad(config, val & ~mask);
 644     return val & mask;
 645 }
 646
 647 static inline uint64_t
 648 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 649 {
 650     uint64_t val = pci_get_quad(config);
 651     pci_set_quad(config, val | mask);
 652     return val & mask;
 653 }
 654
 655 /* Access a register specified by a mask */
 656 static inline void
 657 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 658 {
 659     uint8_t val = pci_get_byte(config);
 660     uint8_t rval = reg << ctz32(mask);
 661     pci_set_byte(config, (~mask & val) | (mask & rval));
 662 }
 663
 664 static inline uint8_t
 665 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 666 {
 667     uint8_t val = pci_get_byte(config);
 668     return (val & mask) >> ctz32(mask);
 669 }
 670
 671 static inline void
 672 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 673 {
 674     uint16_t val = pci_get_word(config);
 675     uint16_t rval = reg << ctz32(mask);
 676     pci_set_word(config, (~mask & val) | (mask & rval));
 677 }
 678
 679 static inline uint16_t
 680 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 681 {
 682     uint16_t val = pci_get_word(config);
 683     return (val & mask) >> ctz32(mask);
 684 }
 685
 686 static inline void
 687 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 688 {
 689     uint32_t val = pci_get_long(config);
 690     uint32_t rval = reg << ctz32(mask);
 691     pci_set_long(config, (~mask & val) | (mask & rval));
 692 }
 693
 694 static inline uint32_t
 695 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 696 {
 697     uint32_t val = pci_get_long(config);
 698     return (val & mask) >> ctz32(mask);
 699 }
 700
 701 static inline void
 702 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 703 {
 704     uint64_t val = pci_get_quad(config);
 705     uint64_t rval = reg << ctz32(mask);
 706     pci_set_quad(config, (~mask & val) | (mask & rval));
 707 }
 708
 709 static inline uint64_t
 710 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 711 {
 712     uint64_t val = pci_get_quad(config);
 713     return (val & mask) >> ctz32(mask);
 714 }
 715
 716 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
 717                                     const char *name);
 718 PCIDevice *pci_new(int devfn, const char *name);
 719 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
 720
 721 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 722                                            bool multifunction,
 723                                            const char *name);
 724 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 725
 726 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
 727
 728 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 729 void pci_set_irq(PCIDevice *pci_dev, int level);
 730
 731 static inline void pci_irq_assert(PCIDevice *pci_dev)
 732 {
 733     pci_set_irq(pci_dev, 1);
 734 }
 735
 736 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 737 {
 738     pci_set_irq(pci_dev, 0);
 739 }
 740
 741 /*
 742  * FIXME: PCI does not work this way.
 743  * All the callers to this method should be fixed.
 744  */
 745 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 746 {
 747     pci_irq_assert(pci_dev);
 748     pci_irq_deassert(pci_dev);
 749 }
 750
 751 static inline int pci_is_express(const PCIDevice *d)
 752 {
 753     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 754 }
 755
 756 static inline int pci_is_express_downstream_port(const PCIDevice *d)
 757 {
 758     uint8_t type;
 759
 760     if (!pci_is_express(d) || !d->exp.exp_cap) {
 761         return 0;
 762     }
 763
 764     type = pcie_cap_get_type(d);
 765
 766     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
 767 }
 768
 769 static inline uint32_t pci_config_size(const PCIDevice *d)
 770 {
 771     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 772 }
 773
 774 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 775 {
 776     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 777 }
 778
 779 uint16_t pci_requester_id(PCIDevice *dev);
 780
 781 /* DMA access functions */
 782 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 783 {
 784     return &dev->bus_master_as;
 785 }
 786
 787 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 788                              void *buf, dma_addr_t len, DMADirection dir)
 789 {
 790     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 791     return 0;
 792 }
 793
 794 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 795                                void *buf, dma_addr_t len)
 796 {
 797     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 798 }
 799
 800 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 801                                 const void *buf, dma_addr_t len)
 802 {
 803     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 804 }
 805
 806 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 807     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 808                                                    dma_addr_t addr)     \
 809     {                                                                   \
 810         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 811     }                                                                   \
 812     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 813                                         dma_addr_t addr, uint##_bits##_t val) \
 814     {                                                                   \
 815         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 816     }
 817
 818 PCI_DMA_DEFINE_LDST(ub, b, 8);
 819 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 820 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 821 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 822 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 823 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 824 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 825
 826 #undef PCI_DMA_DEFINE_LDST
 827
 828 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 829                                 dma_addr_t *plen, DMADirection dir)
 830 {
 831     void *buf;
 832
 833     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 834     return buf;
 835 }
 836
 837 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 838                                  DMADirection dir, dma_addr_t access_len)
 839 {
 840     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 841 }
 842
 843 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 844                                        int alloc_hint)
 845 {
 846     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 847 }
 848
 849 extern const VMStateDescription vmstate_pci_device;
 850
 851 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 852     .name       = (stringify(_field)),                               \
 853     .size       = sizeof(PCIDevice),                                 \
 854     .vmsd       = &vmstate_pci_device,                               \
 855     .flags      = VMS_STRUCT,                                        \
 856     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 857 }
 858
 859 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 860     .name       = (stringify(_field)),                               \
 861     .size       = sizeof(PCIDevice),                                 \
 862     .vmsd       = &vmstate_pci_device,                               \
 863     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 864     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 865 }
 866
 867 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 868
 869 #endif