2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
25 #include "qemu/host-utils.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "trace-tcg.h"
34 #define CPU_SINGLE_STEP 0x1
35 #define CPU_BRANCH_STEP 0x2
36 #define GDBSTUB_SINGLE_STEP 0x4
38 /* Include definitions for instructions classes and implementations flags */
39 //#define PPC_DEBUG_DISAS
40 //#define DO_PPC_STATISTICS
42 #ifdef PPC_DEBUG_DISAS
43 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
45 # define LOG_DISAS(...) do { } while (0)
47 /*****************************************************************************/
48 /* Code translation helpers */
50 /* global register indexes */
51 static TCGv_ptr cpu_env
;
52 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
53 + 10*4 + 22*5 /* SPE GPRh */
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 10*5 + 22*6 /* VSR */
58 static TCGv cpu_gpr
[32];
59 static TCGv cpu_gprh
[32];
60 static TCGv_i64 cpu_fpr
[32];
61 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
62 static TCGv_i64 cpu_vsr
[32];
63 static TCGv_i32 cpu_crf
[8];
68 #if defined(TARGET_PPC64)
71 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
72 static TCGv cpu_reserve
;
73 static TCGv cpu_fpscr
;
74 static TCGv_i32 cpu_access_type
;
76 #include "exec/gen-icount.h"
78 void ppc_translate_init(void)
82 size_t cpu_reg_names_size
;
83 static int done_init
= 0;
88 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
91 cpu_reg_names_size
= sizeof(cpu_reg_names
);
93 for (i
= 0; i
< 8; i
++) {
94 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
95 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
96 offsetof(CPUPPCState
, crf
[i
]), p
);
98 cpu_reg_names_size
-= 5;
101 for (i
= 0; i
< 32; i
++) {
102 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
103 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
104 offsetof(CPUPPCState
, gpr
[i
]), p
);
105 p
+= (i
< 10) ? 3 : 4;
106 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
107 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
108 cpu_gprh
[i
] = tcg_global_mem_new(TCG_AREG0
,
109 offsetof(CPUPPCState
, gprh
[i
]), p
);
110 p
+= (i
< 10) ? 4 : 5;
111 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
140 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
141 cpu_vsr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
142 offsetof(CPUPPCState
, vsr
[i
]), p
);
143 p
+= (i
< 10) ? 5 : 6;
144 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
147 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
148 offsetof(CPUPPCState
, nip
), "nip");
150 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
151 offsetof(CPUPPCState
, msr
), "msr");
153 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
154 offsetof(CPUPPCState
, ctr
), "ctr");
156 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
157 offsetof(CPUPPCState
, lr
), "lr");
159 #if defined(TARGET_PPC64)
160 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
161 offsetof(CPUPPCState
, cfar
), "cfar");
164 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
165 offsetof(CPUPPCState
, xer
), "xer");
166 cpu_so
= tcg_global_mem_new(TCG_AREG0
,
167 offsetof(CPUPPCState
, so
), "SO");
168 cpu_ov
= tcg_global_mem_new(TCG_AREG0
,
169 offsetof(CPUPPCState
, ov
), "OV");
170 cpu_ca
= tcg_global_mem_new(TCG_AREG0
,
171 offsetof(CPUPPCState
, ca
), "CA");
173 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
174 offsetof(CPUPPCState
, reserve_addr
),
177 cpu_fpscr
= tcg_global_mem_new(TCG_AREG0
,
178 offsetof(CPUPPCState
, fpscr
), "fpscr");
180 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
181 offsetof(CPUPPCState
, access_type
), "access_type");
186 /* internal defines */
187 struct DisasContext
{
188 struct TranslationBlock
*tb
;
192 /* Routine used to access memory */
196 /* Translation flags */
198 TCGMemOp default_tcg_memop_mask
;
199 #if defined(TARGET_PPC64)
208 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
209 int singlestep_enabled
;
210 uint64_t insns_flags
;
211 uint64_t insns_flags2
;
214 /* Return true iff byteswap is needed in a scalar memop */
215 static inline bool need_byteswap(const DisasContext
*ctx
)
217 #if defined(TARGET_WORDS_BIGENDIAN)
220 return !ctx
->le_mode
;
224 /* True when active word size < size of target_long. */
226 # define NARROW_MODE(C) (!(C)->sf_mode)
228 # define NARROW_MODE(C) 0
231 struct opc_handler_t
{
232 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
234 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
236 /* instruction type */
238 /* extended instruction type */
241 void (*handler
)(DisasContext
*ctx
);
242 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 #if defined(DO_PPC_STATISTICS)
250 static inline void gen_reset_fpstatus(void)
252 gen_helper_reset_fpstatus(cpu_env
);
255 static inline void gen_compute_fprf(TCGv_i64 arg
)
257 gen_helper_compute_fprf(cpu_env
, arg
);
258 gen_helper_float_check_status(cpu_env
);
261 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
263 if (ctx
->access_type
!= access_type
) {
264 tcg_gen_movi_i32(cpu_access_type
, access_type
);
265 ctx
->access_type
= access_type
;
269 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
271 if (NARROW_MODE(ctx
)) {
274 tcg_gen_movi_tl(cpu_nip
, nip
);
277 void gen_update_current_nip(void *opaque
)
279 DisasContext
*ctx
= opaque
;
281 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
284 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
287 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
288 gen_update_nip(ctx
, ctx
->nip
);
290 t0
= tcg_const_i32(excp
);
291 t1
= tcg_const_i32(error
);
292 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
293 tcg_temp_free_i32(t0
);
294 tcg_temp_free_i32(t1
);
295 ctx
->exception
= (excp
);
298 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
301 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
302 gen_update_nip(ctx
, ctx
->nip
);
304 t0
= tcg_const_i32(excp
);
305 gen_helper_raise_exception(cpu_env
, t0
);
306 tcg_temp_free_i32(t0
);
307 ctx
->exception
= (excp
);
310 static inline void gen_debug_exception(DisasContext
*ctx
)
314 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
315 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
316 gen_update_nip(ctx
, ctx
->nip
);
318 t0
= tcg_const_i32(EXCP_DEBUG
);
319 gen_helper_raise_exception(cpu_env
, t0
);
320 tcg_temp_free_i32(t0
);
323 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
325 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
328 /* Stop translation */
329 static inline void gen_stop_exception(DisasContext
*ctx
)
331 gen_update_nip(ctx
, ctx
->nip
);
332 ctx
->exception
= POWERPC_EXCP_STOP
;
335 #ifndef CONFIG_USER_ONLY
336 /* No need to update nip here, as execution flow will change */
337 static inline void gen_sync_exception(DisasContext
*ctx
)
339 ctx
->exception
= POWERPC_EXCP_SYNC
;
343 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
344 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
346 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
349 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
350 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
352 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
355 typedef struct opcode_t
{
356 unsigned char opc1
, opc2
, opc3
;
357 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
358 unsigned char pad
[5];
360 unsigned char pad
[1];
362 opc_handler_t handler
;
366 /*****************************************************************************/
367 /*** Instruction decoding ***/
368 #define EXTRACT_HELPER(name, shift, nb) \
369 static inline uint32_t name(uint32_t opcode) \
371 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 #define EXTRACT_SHELPER(name, shift, nb) \
375 static inline int32_t name(uint32_t opcode) \
377 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
381 static inline uint32_t name(uint32_t opcode) \
383 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
384 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 EXTRACT_HELPER(opc1
, 26, 6);
389 EXTRACT_HELPER(opc2
, 1, 5);
391 EXTRACT_HELPER(opc3
, 6, 5);
392 /* Update Cr0 flags */
393 EXTRACT_HELPER(Rc
, 0, 1);
394 /* Update Cr6 flags (Altivec) */
395 EXTRACT_HELPER(Rc21
, 10, 1);
397 EXTRACT_HELPER(rD
, 21, 5);
399 EXTRACT_HELPER(rS
, 21, 5);
401 EXTRACT_HELPER(rA
, 16, 5);
403 EXTRACT_HELPER(rB
, 11, 5);
405 EXTRACT_HELPER(rC
, 6, 5);
407 EXTRACT_HELPER(crfD
, 23, 3);
408 EXTRACT_HELPER(crfS
, 18, 3);
409 EXTRACT_HELPER(crbD
, 21, 5);
410 EXTRACT_HELPER(crbA
, 16, 5);
411 EXTRACT_HELPER(crbB
, 11, 5);
413 EXTRACT_HELPER(_SPR
, 11, 10);
414 static inline uint32_t SPR(uint32_t opcode
)
416 uint32_t sprn
= _SPR(opcode
);
418 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
420 /*** Get constants ***/
421 /* 16 bits signed immediate value */
422 EXTRACT_SHELPER(SIMM
, 0, 16);
423 /* 16 bits unsigned immediate value */
424 EXTRACT_HELPER(UIMM
, 0, 16);
425 /* 5 bits signed immediate value */
426 EXTRACT_HELPER(SIMM5
, 16, 5);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(UIMM5
, 16, 5);
430 EXTRACT_HELPER(NB
, 11, 5);
432 EXTRACT_HELPER(SH
, 11, 5);
433 /* Vector shift count */
434 EXTRACT_HELPER(VSH
, 6, 4);
436 EXTRACT_HELPER(MB
, 6, 5);
438 EXTRACT_HELPER(ME
, 1, 5);
440 EXTRACT_HELPER(TO
, 21, 5);
442 EXTRACT_HELPER(CRM
, 12, 8);
444 #ifndef CONFIG_USER_ONLY
445 EXTRACT_HELPER(SR
, 16, 4);
449 EXTRACT_HELPER(FPBF
, 23, 3);
450 EXTRACT_HELPER(FPIMM
, 12, 4);
451 EXTRACT_HELPER(FPL
, 25, 1);
452 EXTRACT_HELPER(FPFLM
, 17, 8);
453 EXTRACT_HELPER(FPW
, 16, 1);
455 /*** Jump target decoding ***/
456 /* Immediate address */
457 static inline target_ulong
LI(uint32_t opcode
)
459 return (opcode
>> 0) & 0x03FFFFFC;
462 static inline uint32_t BD(uint32_t opcode
)
464 return (opcode
>> 0) & 0xFFFC;
467 EXTRACT_HELPER(BO
, 21, 5);
468 EXTRACT_HELPER(BI
, 16, 5);
469 /* Absolute/relative address */
470 EXTRACT_HELPER(AA
, 1, 1);
472 EXTRACT_HELPER(LK
, 0, 1);
475 EXTRACT_HELPER(DCM
, 10, 6)
478 EXTRACT_HELPER(RMC
, 9, 2)
480 /* Create a mask between <start> and <end> bits */
481 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
485 #if defined(TARGET_PPC64)
486 if (likely(start
== 0)) {
487 ret
= UINT64_MAX
<< (63 - end
);
488 } else if (likely(end
== 63)) {
489 ret
= UINT64_MAX
>> start
;
492 if (likely(start
== 0)) {
493 ret
= UINT32_MAX
<< (31 - end
);
494 } else if (likely(end
== 31)) {
495 ret
= UINT32_MAX
>> start
;
499 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
500 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
501 if (unlikely(start
> end
))
508 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
509 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
510 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
511 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
512 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
513 EXTRACT_HELPER(DM
, 8, 2);
514 EXTRACT_HELPER(UIM
, 16, 2);
515 EXTRACT_HELPER(SHW
, 8, 2);
516 EXTRACT_HELPER(SP
, 19, 2);
517 /*****************************************************************************/
518 /* PowerPC instructions table */
520 #if defined(DO_PPC_STATISTICS)
521 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 .handler = &gen_##name, \
532 .oname = stringify(name), \
534 .oname = stringify(name), \
536 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
547 .handler = &gen_##name, \
548 .oname = stringify(name), \
550 .oname = stringify(name), \
552 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
562 .handler = &gen_##name, \
568 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
578 .handler = &gen_##name, \
580 .oname = stringify(name), \
582 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
593 .handler = &gen_##name, \
595 .oname = stringify(name), \
597 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
607 .handler = &gen_##name, \
613 /* SPR load/store helpers */
614 static inline void gen_load_spr(TCGv t
, int reg
)
616 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
619 static inline void gen_store_spr(int reg
, TCGv t
)
621 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
624 /* Invalid instruction */
625 static void gen_invalid(DisasContext
*ctx
)
627 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
630 static opc_handler_t invalid_handler
= {
631 .inval1
= 0xFFFFFFFF,
632 .inval2
= 0xFFFFFFFF,
635 .handler
= gen_invalid
,
638 /*** Integer comparison ***/
640 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
642 TCGv t0
= tcg_temp_new();
643 TCGv_i32 t1
= tcg_temp_new_i32();
645 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
647 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
648 tcg_gen_trunc_tl_i32(t1
, t0
);
649 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
650 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
652 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
653 tcg_gen_trunc_tl_i32(t1
, t0
);
654 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
655 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
657 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
658 tcg_gen_trunc_tl_i32(t1
, t0
);
659 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
660 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
663 tcg_temp_free_i32(t1
);
666 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
668 TCGv t0
= tcg_const_tl(arg1
);
669 gen_op_cmp(arg0
, t0
, s
, crf
);
673 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
679 tcg_gen_ext32s_tl(t0
, arg0
);
680 tcg_gen_ext32s_tl(t1
, arg1
);
682 tcg_gen_ext32u_tl(t0
, arg0
);
683 tcg_gen_ext32u_tl(t1
, arg1
);
685 gen_op_cmp(t0
, t1
, s
, crf
);
690 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
692 TCGv t0
= tcg_const_tl(arg1
);
693 gen_op_cmp32(arg0
, t0
, s
, crf
);
697 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
699 if (NARROW_MODE(ctx
)) {
700 gen_op_cmpi32(reg
, 0, 1, 0);
702 gen_op_cmpi(reg
, 0, 1, 0);
707 static void gen_cmp(DisasContext
*ctx
)
709 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
710 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
711 1, crfD(ctx
->opcode
));
713 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
714 1, crfD(ctx
->opcode
));
719 static void gen_cmpi(DisasContext
*ctx
)
721 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
722 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
723 1, crfD(ctx
->opcode
));
725 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
726 1, crfD(ctx
->opcode
));
731 static void gen_cmpl(DisasContext
*ctx
)
733 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
734 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
735 0, crfD(ctx
->opcode
));
737 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
738 0, crfD(ctx
->opcode
));
743 static void gen_cmpli(DisasContext
*ctx
)
745 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
746 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
747 0, crfD(ctx
->opcode
));
749 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
750 0, crfD(ctx
->opcode
));
754 /* isel (PowerPC 2.03 specification) */
755 static void gen_isel(DisasContext
*ctx
)
758 uint32_t bi
= rC(ctx
->opcode
);
762 l1
= gen_new_label();
763 l2
= gen_new_label();
765 mask
= 0x08 >> (bi
& 0x03);
766 t0
= tcg_temp_new_i32();
767 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
768 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
769 if (rA(ctx
->opcode
) == 0)
770 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
772 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
775 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
777 tcg_temp_free_i32(t0
);
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext
*ctx
)
783 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
784 cpu_gpr
[rB(ctx
->opcode
)]);
787 /*** Integer arithmetic ***/
789 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
790 TCGv arg1
, TCGv arg2
, int sub
)
792 TCGv t0
= tcg_temp_new();
794 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
795 tcg_gen_xor_tl(t0
, arg1
, arg2
);
797 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
799 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
802 if (NARROW_MODE(ctx
)) {
803 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
805 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
806 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
809 /* Common add function */
810 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
811 TCGv arg2
, bool add_ca
, bool compute_ca
,
812 bool compute_ov
, bool compute_rc0
)
816 if (compute_ca
|| compute_ov
) {
821 if (NARROW_MODE(ctx
)) {
822 /* Caution: a non-obvious corner case of the spec is that we
823 must produce the *entire* 64-bit addition, but produce the
824 carry into bit 32. */
825 TCGv t1
= tcg_temp_new();
826 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
827 tcg_gen_add_tl(t0
, arg1
, arg2
);
829 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
831 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
833 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
834 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
836 TCGv zero
= tcg_const_tl(0);
838 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
839 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
841 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
846 tcg_gen_add_tl(t0
, arg1
, arg2
);
848 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
853 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
855 if (unlikely(compute_rc0
)) {
856 gen_set_Rc0(ctx
, t0
);
859 if (!TCGV_EQUAL(t0
, ret
)) {
860 tcg_gen_mov_tl(ret
, t0
);
864 /* Add functions with two operands */
865 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
866 static void glue(gen_, name)(DisasContext *ctx) \
868 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
869 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
870 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 /* Add functions with one operand and one immediate */
873 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
874 add_ca, compute_ca, compute_ov) \
875 static void glue(gen_, name)(DisasContext *ctx) \
877 TCGv t0 = tcg_const_tl(const_val); \
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
879 cpu_gpr[rA(ctx->opcode)], t0, \
880 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
884 /* add add. addo addo. */
885 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
886 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
887 /* addc addc. addco addco. */
888 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
889 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
890 /* adde adde. addeo addeo. */
891 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
892 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
893 /* addme addme. addmeo addmeo. */
894 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
895 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
896 /* addze addze. addzeo addzeo.*/
897 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
900 static void gen_addi(DisasContext
*ctx
)
902 target_long simm
= SIMM(ctx
->opcode
);
904 if (rA(ctx
->opcode
) == 0) {
906 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
908 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
909 cpu_gpr
[rA(ctx
->opcode
)], simm
);
913 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
915 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
916 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
917 c
, 0, 1, 0, compute_rc0
);
921 static void gen_addic(DisasContext
*ctx
)
923 gen_op_addic(ctx
, 0);
926 static void gen_addic_(DisasContext
*ctx
)
928 gen_op_addic(ctx
, 1);
932 static void gen_addis(DisasContext
*ctx
)
934 target_long simm
= SIMM(ctx
->opcode
);
936 if (rA(ctx
->opcode
) == 0) {
938 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
940 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
941 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
945 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
946 TCGv arg2
, int sign
, int compute_ov
)
948 TCGLabel
*l1
= gen_new_label();
949 TCGLabel
*l2
= gen_new_label();
950 TCGv_i32 t0
= tcg_temp_local_new_i32();
951 TCGv_i32 t1
= tcg_temp_local_new_i32();
953 tcg_gen_trunc_tl_i32(t0
, arg1
);
954 tcg_gen_trunc_tl_i32(t1
, arg2
);
955 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
957 TCGLabel
*l3
= gen_new_label();
958 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
959 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
961 tcg_gen_div_i32(t0
, t0
, t1
);
963 tcg_gen_divu_i32(t0
, t0
, t1
);
966 tcg_gen_movi_tl(cpu_ov
, 0);
971 tcg_gen_sari_i32(t0
, t0
, 31);
973 tcg_gen_movi_i32(t0
, 0);
976 tcg_gen_movi_tl(cpu_ov
, 1);
977 tcg_gen_movi_tl(cpu_so
, 1);
980 tcg_gen_extu_i32_tl(ret
, t0
);
981 tcg_temp_free_i32(t0
);
982 tcg_temp_free_i32(t1
);
983 if (unlikely(Rc(ctx
->opcode
) != 0))
984 gen_set_Rc0(ctx
, ret
);
987 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
988 static void glue(gen_, name)(DisasContext *ctx) \
990 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
991 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 /* divwu divwu. divwuo divwuo. */
995 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
996 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
997 /* divw divw. divwo divwo. */
998 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
999 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1001 /* div[wd]eu[o][.] */
1002 #define GEN_DIVE(name, hlpr, compute_ov) \
1003 static void gen_##name(DisasContext *ctx) \
1005 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1006 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1007 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1008 tcg_temp_free_i32(t0); \
1009 if (unlikely(Rc(ctx->opcode) != 0)) { \
1010 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1014 GEN_DIVE(divweu
, divweu
, 0);
1015 GEN_DIVE(divweuo
, divweu
, 1);
1016 GEN_DIVE(divwe
, divwe
, 0);
1017 GEN_DIVE(divweo
, divwe
, 1);
1019 #if defined(TARGET_PPC64)
1020 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1021 TCGv arg2
, int sign
, int compute_ov
)
1023 TCGLabel
*l1
= gen_new_label();
1024 TCGLabel
*l2
= gen_new_label();
1026 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1028 TCGLabel
*l3
= gen_new_label();
1029 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1030 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1032 tcg_gen_div_i64(ret
, arg1
, arg2
);
1034 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1037 tcg_gen_movi_tl(cpu_ov
, 0);
1042 tcg_gen_sari_i64(ret
, arg1
, 63);
1044 tcg_gen_movi_i64(ret
, 0);
1047 tcg_gen_movi_tl(cpu_ov
, 1);
1048 tcg_gen_movi_tl(cpu_so
, 1);
1051 if (unlikely(Rc(ctx
->opcode
) != 0))
1052 gen_set_Rc0(ctx
, ret
);
1054 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1055 static void glue(gen_, name)(DisasContext *ctx) \
1057 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1058 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1059 sign, compute_ov); \
1061 /* divwu divwu. divwuo divwuo. */
1062 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1063 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1064 /* divw divw. divwo divwo. */
1065 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1066 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1068 GEN_DIVE(divdeu
, divdeu
, 0);
1069 GEN_DIVE(divdeuo
, divdeu
, 1);
1070 GEN_DIVE(divde
, divde
, 0);
1071 GEN_DIVE(divdeo
, divde
, 1);
1075 static void gen_mulhw(DisasContext
*ctx
)
1077 TCGv_i32 t0
= tcg_temp_new_i32();
1078 TCGv_i32 t1
= tcg_temp_new_i32();
1080 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1081 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1082 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1083 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1084 tcg_temp_free_i32(t0
);
1085 tcg_temp_free_i32(t1
);
1086 if (unlikely(Rc(ctx
->opcode
) != 0))
1087 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1090 /* mulhwu mulhwu. */
1091 static void gen_mulhwu(DisasContext
*ctx
)
1093 TCGv_i32 t0
= tcg_temp_new_i32();
1094 TCGv_i32 t1
= tcg_temp_new_i32();
1096 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1097 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1098 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1099 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1100 tcg_temp_free_i32(t0
);
1101 tcg_temp_free_i32(t1
);
1102 if (unlikely(Rc(ctx
->opcode
) != 0))
1103 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1107 static void gen_mullw(DisasContext
*ctx
)
1109 #if defined(TARGET_PPC64)
1111 t0
= tcg_temp_new_i64();
1112 t1
= tcg_temp_new_i64();
1113 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1114 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1115 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1119 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1120 cpu_gpr
[rB(ctx
->opcode
)]);
1122 if (unlikely(Rc(ctx
->opcode
) != 0))
1123 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1126 /* mullwo mullwo. */
1127 static void gen_mullwo(DisasContext
*ctx
)
1129 TCGv_i32 t0
= tcg_temp_new_i32();
1130 TCGv_i32 t1
= tcg_temp_new_i32();
1132 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1133 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1134 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1135 #if defined(TARGET_PPC64)
1136 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1138 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1141 tcg_gen_sari_i32(t0
, t0
, 31);
1142 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1143 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1144 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1146 tcg_temp_free_i32(t0
);
1147 tcg_temp_free_i32(t1
);
1148 if (unlikely(Rc(ctx
->opcode
) != 0))
1149 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1153 static void gen_mulli(DisasContext
*ctx
)
1155 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1159 #if defined(TARGET_PPC64)
1161 static void gen_mulhd(DisasContext
*ctx
)
1163 TCGv lo
= tcg_temp_new();
1164 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1165 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1167 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1168 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1172 /* mulhdu mulhdu. */
1173 static void gen_mulhdu(DisasContext
*ctx
)
1175 TCGv lo
= tcg_temp_new();
1176 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1177 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1179 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1180 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1185 static void gen_mulld(DisasContext
*ctx
)
1187 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1188 cpu_gpr
[rB(ctx
->opcode
)]);
1189 if (unlikely(Rc(ctx
->opcode
) != 0))
1190 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1193 /* mulldo mulldo. */
1194 static void gen_mulldo(DisasContext
*ctx
)
1196 TCGv_i64 t0
= tcg_temp_new_i64();
1197 TCGv_i64 t1
= tcg_temp_new_i64();
1199 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1200 cpu_gpr
[rB(ctx
->opcode
)]);
1201 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1203 tcg_gen_sari_i64(t0
, t0
, 63);
1204 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1205 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1207 tcg_temp_free_i64(t0
);
1208 tcg_temp_free_i64(t1
);
1210 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1211 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1216 /* Common subf function */
1217 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1218 TCGv arg2
, bool add_ca
, bool compute_ca
,
1219 bool compute_ov
, bool compute_rc0
)
1223 if (compute_ca
|| compute_ov
) {
1224 t0
= tcg_temp_new();
1228 /* dest = ~arg1 + arg2 [+ ca]. */
1229 if (NARROW_MODE(ctx
)) {
1230 /* Caution: a non-obvious corner case of the spec is that we
1231 must produce the *entire* 64-bit addition, but produce the
1232 carry into bit 32. */
1233 TCGv inv1
= tcg_temp_new();
1234 TCGv t1
= tcg_temp_new();
1235 tcg_gen_not_tl(inv1
, arg1
);
1237 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1239 tcg_gen_addi_tl(t0
, arg2
, 1);
1241 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1242 tcg_gen_add_tl(t0
, t0
, inv1
);
1243 tcg_temp_free(inv1
);
1244 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1246 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1247 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1248 } else if (add_ca
) {
1249 TCGv zero
, inv1
= tcg_temp_new();
1250 tcg_gen_not_tl(inv1
, arg1
);
1251 zero
= tcg_const_tl(0);
1252 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1253 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1254 tcg_temp_free(zero
);
1255 tcg_temp_free(inv1
);
1257 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1258 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1260 } else if (add_ca
) {
1261 /* Since we're ignoring carry-out, we can simplify the
1262 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1263 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1264 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1265 tcg_gen_subi_tl(t0
, t0
, 1);
1267 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1271 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1273 if (unlikely(compute_rc0
)) {
1274 gen_set_Rc0(ctx
, t0
);
1277 if (!TCGV_EQUAL(t0
, ret
)) {
1278 tcg_gen_mov_tl(ret
, t0
);
1282 /* Sub functions with Two operands functions */
1283 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1284 static void glue(gen_, name)(DisasContext *ctx) \
1286 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1287 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1288 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1290 /* Sub functions with one operand and one immediate */
1291 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1292 add_ca, compute_ca, compute_ov) \
1293 static void glue(gen_, name)(DisasContext *ctx) \
1295 TCGv t0 = tcg_const_tl(const_val); \
1296 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1297 cpu_gpr[rA(ctx->opcode)], t0, \
1298 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1299 tcg_temp_free(t0); \
1301 /* subf subf. subfo subfo. */
1302 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1303 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1304 /* subfc subfc. subfco subfco. */
1305 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1306 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1307 /* subfe subfe. subfeo subfo. */
1308 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1310 /* subfme subfme. subfmeo subfmeo. */
1311 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1312 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1313 /* subfze subfze. subfzeo subfzeo.*/
1314 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1315 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1318 static void gen_subfic(DisasContext
*ctx
)
1320 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1321 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1326 /* neg neg. nego nego. */
1327 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1329 TCGv zero
= tcg_const_tl(0);
1330 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1331 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1332 tcg_temp_free(zero
);
1335 static void gen_neg(DisasContext
*ctx
)
1337 gen_op_arith_neg(ctx
, 0);
1340 static void gen_nego(DisasContext
*ctx
)
1342 gen_op_arith_neg(ctx
, 1);
1345 /*** Integer logical ***/
1346 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1347 static void glue(gen_, name)(DisasContext *ctx) \
1349 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1350 cpu_gpr[rB(ctx->opcode)]); \
1351 if (unlikely(Rc(ctx->opcode) != 0)) \
1352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1355 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1356 static void glue(gen_, name)(DisasContext *ctx) \
1358 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1359 if (unlikely(Rc(ctx->opcode) != 0)) \
1360 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1364 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1366 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1369 static void gen_andi_(DisasContext
*ctx
)
1371 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1372 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1376 static void gen_andis_(DisasContext
*ctx
)
1378 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1379 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1383 static void gen_cntlzw(DisasContext
*ctx
)
1385 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1386 if (unlikely(Rc(ctx
->opcode
) != 0))
1387 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1390 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1391 /* extsb & extsb. */
1392 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1393 /* extsh & extsh. */
1394 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1396 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1398 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1401 static void gen_or(DisasContext
*ctx
)
1405 rs
= rS(ctx
->opcode
);
1406 ra
= rA(ctx
->opcode
);
1407 rb
= rB(ctx
->opcode
);
1408 /* Optimisation for mr. ri case */
1409 if (rs
!= ra
|| rs
!= rb
) {
1411 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1413 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1414 if (unlikely(Rc(ctx
->opcode
) != 0))
1415 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1416 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1417 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1418 #if defined(TARGET_PPC64)
1424 /* Set process priority to low */
1428 /* Set process priority to medium-low */
1432 /* Set process priority to normal */
1435 #if !defined(CONFIG_USER_ONLY)
1438 /* Set process priority to very low */
1444 /* Set process priority to medium-hight */
1450 /* Set process priority to high */
1456 /* Set process priority to very high */
1466 TCGv t0
= tcg_temp_new();
1467 gen_load_spr(t0
, SPR_PPR
);
1468 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1469 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1470 gen_store_spr(SPR_PPR
, t0
);
1477 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1480 static void gen_xor(DisasContext
*ctx
)
1482 /* Optimisation for "set to zero" case */
1483 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1484 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1486 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1487 if (unlikely(Rc(ctx
->opcode
) != 0))
1488 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1492 static void gen_ori(DisasContext
*ctx
)
1494 target_ulong uimm
= UIMM(ctx
->opcode
);
1496 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1498 /* XXX: should handle special NOPs for POWER series */
1501 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1505 static void gen_oris(DisasContext
*ctx
)
1507 target_ulong uimm
= UIMM(ctx
->opcode
);
1509 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1513 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1517 static void gen_xori(DisasContext
*ctx
)
1519 target_ulong uimm
= UIMM(ctx
->opcode
);
1521 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1525 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1529 static void gen_xoris(DisasContext
*ctx
)
1531 target_ulong uimm
= UIMM(ctx
->opcode
);
1533 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1537 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1540 /* popcntb : PowerPC 2.03 specification */
1541 static void gen_popcntb(DisasContext
*ctx
)
1543 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1546 static void gen_popcntw(DisasContext
*ctx
)
1548 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1551 #if defined(TARGET_PPC64)
1552 /* popcntd: PowerPC 2.06 specification */
1553 static void gen_popcntd(DisasContext
*ctx
)
1555 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1559 /* prtyw: PowerPC 2.05 specification */
1560 static void gen_prtyw(DisasContext
*ctx
)
1562 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1563 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1564 TCGv t0
= tcg_temp_new();
1565 tcg_gen_shri_tl(t0
, rs
, 16);
1566 tcg_gen_xor_tl(ra
, rs
, t0
);
1567 tcg_gen_shri_tl(t0
, ra
, 8);
1568 tcg_gen_xor_tl(ra
, ra
, t0
);
1569 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1573 #if defined(TARGET_PPC64)
1574 /* prtyd: PowerPC 2.05 specification */
1575 static void gen_prtyd(DisasContext
*ctx
)
1577 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1578 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1579 TCGv t0
= tcg_temp_new();
1580 tcg_gen_shri_tl(t0
, rs
, 32);
1581 tcg_gen_xor_tl(ra
, rs
, t0
);
1582 tcg_gen_shri_tl(t0
, ra
, 16);
1583 tcg_gen_xor_tl(ra
, ra
, t0
);
1584 tcg_gen_shri_tl(t0
, ra
, 8);
1585 tcg_gen_xor_tl(ra
, ra
, t0
);
1586 tcg_gen_andi_tl(ra
, ra
, 1);
1591 #if defined(TARGET_PPC64)
1593 static void gen_bpermd(DisasContext
*ctx
)
1595 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1596 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1600 #if defined(TARGET_PPC64)
1601 /* extsw & extsw. */
1602 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1605 static void gen_cntlzd(DisasContext
*ctx
)
1607 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1608 if (unlikely(Rc(ctx
->opcode
) != 0))
1609 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1613 /*** Integer rotate ***/
1615 /* rlwimi & rlwimi. */
1616 static void gen_rlwimi(DisasContext
*ctx
)
1618 uint32_t mb
, me
, sh
;
1620 mb
= MB(ctx
->opcode
);
1621 me
= ME(ctx
->opcode
);
1622 sh
= SH(ctx
->opcode
);
1623 if (likely(sh
== (31-me
) && mb
<= me
)) {
1624 tcg_gen_deposit_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1625 cpu_gpr
[rS(ctx
->opcode
)], sh
, me
- mb
+ 1);
1629 TCGv t0
= tcg_temp_new();
1630 #if defined(TARGET_PPC64)
1631 tcg_gen_deposit_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)],
1632 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1633 tcg_gen_rotli_i64(t0
, t0
, sh
);
1635 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1637 #if defined(TARGET_PPC64)
1641 mask
= MASK(mb
, me
);
1642 t1
= tcg_temp_new();
1643 tcg_gen_andi_tl(t0
, t0
, mask
);
1644 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1645 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1649 if (unlikely(Rc(ctx
->opcode
) != 0))
1650 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1653 /* rlwinm & rlwinm. */
1654 static void gen_rlwinm(DisasContext
*ctx
)
1656 uint32_t mb
, me
, sh
;
1658 sh
= SH(ctx
->opcode
);
1659 mb
= MB(ctx
->opcode
);
1660 me
= ME(ctx
->opcode
);
1662 if (likely(mb
== 0 && me
== (31 - sh
))) {
1663 if (likely(sh
== 0)) {
1664 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1666 TCGv t0
= tcg_temp_new();
1667 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1668 tcg_gen_shli_tl(t0
, t0
, sh
);
1669 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1672 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1673 TCGv t0
= tcg_temp_new();
1674 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1675 tcg_gen_shri_tl(t0
, t0
, mb
);
1676 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1678 } else if (likely(mb
== 0 && me
== 31)) {
1679 TCGv_i32 t0
= tcg_temp_new_i32();
1680 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1681 tcg_gen_rotli_i32(t0
, t0
, sh
);
1682 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1683 tcg_temp_free_i32(t0
);
1685 TCGv t0
= tcg_temp_new();
1686 #if defined(TARGET_PPC64)
1687 tcg_gen_deposit_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)],
1688 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1689 tcg_gen_rotli_i64(t0
, t0
, sh
);
1691 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1693 #if defined(TARGET_PPC64)
1697 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1700 if (unlikely(Rc(ctx
->opcode
) != 0))
1701 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1704 /* rlwnm & rlwnm. */
1705 static void gen_rlwnm(DisasContext
*ctx
)
1708 mb
= MB(ctx
->opcode
);
1709 me
= ME(ctx
->opcode
);
1711 if (likely(mb
== 0 && me
== 31)) {
1713 t0
= tcg_temp_new_i32();
1714 t1
= tcg_temp_new_i32();
1715 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
1716 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1717 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1718 tcg_gen_rotl_i32(t1
, t1
, t0
);
1719 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
1720 tcg_temp_free_i32(t0
);
1721 tcg_temp_free_i32(t1
);
1724 #if defined(TARGET_PPC64)
1728 t0
= tcg_temp_new();
1729 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1730 #if defined(TARGET_PPC64)
1731 t1
= tcg_temp_new_i64();
1732 tcg_gen_deposit_i64(t1
, cpu_gpr
[rS(ctx
->opcode
)],
1733 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1734 tcg_gen_rotl_i64(t0
, t1
, t0
);
1735 tcg_temp_free_i64(t1
);
1737 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1739 if (unlikely(mb
!= 0 || me
!= 31)) {
1740 #if defined(TARGET_PPC64)
1744 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1746 tcg_gen_andi_tl(t0
, t0
, MASK(32, 63));
1747 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1751 if (unlikely(Rc(ctx
->opcode
) != 0))
1752 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1755 #if defined(TARGET_PPC64)
1756 #define GEN_PPC64_R2(name, opc1, opc2) \
1757 static void glue(gen_, name##0)(DisasContext *ctx) \
1759 gen_##name(ctx, 0); \
1762 static void glue(gen_, name##1)(DisasContext *ctx) \
1764 gen_##name(ctx, 1); \
1766 #define GEN_PPC64_R4(name, opc1, opc2) \
1767 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 gen_##name(ctx, 0, 0); \
1772 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 gen_##name(ctx, 0, 1); \
1777 static void glue(gen_, name##2)(DisasContext *ctx) \
1779 gen_##name(ctx, 1, 0); \
1782 static void glue(gen_, name##3)(DisasContext *ctx) \
1784 gen_##name(ctx, 1, 1); \
1787 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1790 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1791 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1792 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1793 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1795 TCGv t0
= tcg_temp_new();
1796 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1797 if (likely(mb
== 0 && me
== 63)) {
1798 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1800 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1804 if (unlikely(Rc(ctx
->opcode
) != 0))
1805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1807 /* rldicl - rldicl. */
1808 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1812 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1813 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1814 gen_rldinm(ctx
, mb
, 63, sh
);
1816 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1817 /* rldicr - rldicr. */
1818 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1822 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1823 me
= MB(ctx
->opcode
) | (men
<< 5);
1824 gen_rldinm(ctx
, 0, me
, sh
);
1826 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1827 /* rldic - rldic. */
1828 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1832 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1833 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1834 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1836 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1838 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1842 t0
= tcg_temp_new();
1843 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1844 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1845 if (unlikely(mb
!= 0 || me
!= 63)) {
1846 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1848 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1851 if (unlikely(Rc(ctx
->opcode
) != 0))
1852 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1855 /* rldcl - rldcl. */
1856 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1860 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1861 gen_rldnm(ctx
, mb
, 63);
1863 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1864 /* rldcr - rldcr. */
1865 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1869 me
= MB(ctx
->opcode
) | (men
<< 5);
1870 gen_rldnm(ctx
, 0, me
);
1872 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1873 /* rldimi - rldimi. */
1874 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1876 uint32_t sh
, mb
, me
;
1878 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1879 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1881 if (unlikely(sh
== 0 && mb
== 0)) {
1882 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1887 t0
= tcg_temp_new();
1888 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1889 t1
= tcg_temp_new();
1890 mask
= MASK(mb
, me
);
1891 tcg_gen_andi_tl(t0
, t0
, mask
);
1892 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1893 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1897 if (unlikely(Rc(ctx
->opcode
) != 0))
1898 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1900 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1903 /*** Integer shift ***/
1906 static void gen_slw(DisasContext
*ctx
)
1910 t0
= tcg_temp_new();
1911 /* AND rS with a mask that is 0 when rB >= 0x20 */
1912 #if defined(TARGET_PPC64)
1913 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1914 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1916 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1917 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1919 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1920 t1
= tcg_temp_new();
1921 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1922 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1925 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1926 if (unlikely(Rc(ctx
->opcode
) != 0))
1927 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1931 static void gen_sraw(DisasContext
*ctx
)
1933 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1934 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1935 if (unlikely(Rc(ctx
->opcode
) != 0))
1936 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1939 /* srawi & srawi. */
1940 static void gen_srawi(DisasContext
*ctx
)
1942 int sh
= SH(ctx
->opcode
);
1943 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1944 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1946 tcg_gen_ext32s_tl(dst
, src
);
1947 tcg_gen_movi_tl(cpu_ca
, 0);
1950 tcg_gen_ext32s_tl(dst
, src
);
1951 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
1952 t0
= tcg_temp_new();
1953 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
1954 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1956 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1957 tcg_gen_sari_tl(dst
, dst
, sh
);
1959 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1960 gen_set_Rc0(ctx
, dst
);
1965 static void gen_srw(DisasContext
*ctx
)
1969 t0
= tcg_temp_new();
1970 /* AND rS with a mask that is 0 when rB >= 0x20 */
1971 #if defined(TARGET_PPC64)
1972 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1973 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1975 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1976 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1978 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1979 tcg_gen_ext32u_tl(t0
, t0
);
1980 t1
= tcg_temp_new();
1981 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1982 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1985 if (unlikely(Rc(ctx
->opcode
) != 0))
1986 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1989 #if defined(TARGET_PPC64)
1991 static void gen_sld(DisasContext
*ctx
)
1995 t0
= tcg_temp_new();
1996 /* AND rS with a mask that is 0 when rB >= 0x40 */
1997 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1998 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1999 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2000 t1
= tcg_temp_new();
2001 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2002 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2005 if (unlikely(Rc(ctx
->opcode
) != 0))
2006 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2010 static void gen_srad(DisasContext
*ctx
)
2012 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2013 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2014 if (unlikely(Rc(ctx
->opcode
) != 0))
2015 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2017 /* sradi & sradi. */
2018 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2020 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2021 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2022 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2024 tcg_gen_mov_tl(dst
, src
);
2025 tcg_gen_movi_tl(cpu_ca
, 0);
2028 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2029 t0
= tcg_temp_new();
2030 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2031 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2033 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2034 tcg_gen_sari_tl(dst
, src
, sh
);
2036 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2037 gen_set_Rc0(ctx
, dst
);
2041 static void gen_sradi0(DisasContext
*ctx
)
2046 static void gen_sradi1(DisasContext
*ctx
)
2052 static void gen_srd(DisasContext
*ctx
)
2056 t0
= tcg_temp_new();
2057 /* AND rS with a mask that is 0 when rB >= 0x40 */
2058 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2059 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2060 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2061 t1
= tcg_temp_new();
2062 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2063 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2066 if (unlikely(Rc(ctx
->opcode
) != 0))
2067 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2071 #if defined(TARGET_PPC64)
2072 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2074 TCGv_i32 tmp
= tcg_temp_new_i32();
2075 tcg_gen_trunc_tl_i32(tmp
, cpu_fpscr
);
2076 tcg_gen_shri_i32(cpu_crf
[1], tmp
, 28);
2077 tcg_temp_free_i32(tmp
);
2080 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2082 tcg_gen_shri_tl(cpu_crf
[1], cpu_fpscr
, 28);
2086 /*** Floating-Point arithmetic ***/
2087 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2088 static void gen_f##name(DisasContext *ctx) \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2098 cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2102 cpu_fpr[rD(ctx->opcode)]); \
2105 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2107 if (unlikely(Rc(ctx->opcode) != 0)) { \
2108 gen_set_cr1_from_fpscr(ctx); \
2112 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2113 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2114 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2116 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2117 static void gen_f##name(DisasContext *ctx) \
2119 if (unlikely(!ctx->fpu_enabled)) { \
2120 gen_exception(ctx, POWERPC_EXCP_FPU); \
2123 /* NIP cannot be restored if the memory exception comes from an helper */ \
2124 gen_update_nip(ctx, ctx->nip - 4); \
2125 gen_reset_fpstatus(); \
2126 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2127 cpu_fpr[rA(ctx->opcode)], \
2128 cpu_fpr[rB(ctx->opcode)]); \
2130 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2131 cpu_fpr[rD(ctx->opcode)]); \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2136 if (unlikely(Rc(ctx->opcode) != 0)) { \
2137 gen_set_cr1_from_fpscr(ctx); \
2140 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2141 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2142 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2145 static void gen_f##name(DisasContext *ctx) \
2147 if (unlikely(!ctx->fpu_enabled)) { \
2148 gen_exception(ctx, POWERPC_EXCP_FPU); \
2151 /* NIP cannot be restored if the memory exception comes from an helper */ \
2152 gen_update_nip(ctx, ctx->nip - 4); \
2153 gen_reset_fpstatus(); \
2154 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2155 cpu_fpr[rA(ctx->opcode)], \
2156 cpu_fpr[rC(ctx->opcode)]); \
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2159 cpu_fpr[rD(ctx->opcode)]); \
2162 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2164 if (unlikely(Rc(ctx->opcode) != 0)) { \
2165 gen_set_cr1_from_fpscr(ctx); \
2168 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2169 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2170 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2172 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2173 static void gen_f##name(DisasContext *ctx) \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
2181 gen_reset_fpstatus(); \
2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2192 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2193 static void gen_f##name(DisasContext *ctx) \
2195 if (unlikely(!ctx->fpu_enabled)) { \
2196 gen_exception(ctx, POWERPC_EXCP_FPU); \
2199 /* NIP cannot be restored if the memory exception comes from an helper */ \
2200 gen_update_nip(ctx, ctx->nip - 4); \
2201 gen_reset_fpstatus(); \
2202 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2203 cpu_fpr[rB(ctx->opcode)]); \
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2207 if (unlikely(Rc(ctx->opcode) != 0)) { \
2208 gen_set_cr1_from_fpscr(ctx); \
2213 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2215 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2217 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2220 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2223 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2226 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2229 static void gen_frsqrtes(DisasContext
*ctx
)
2231 if (unlikely(!ctx
->fpu_enabled
)) {
2232 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx
, ctx
->nip
- 4);
2237 gen_reset_fpstatus();
2238 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2239 cpu_fpr
[rB(ctx
->opcode
)]);
2240 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2241 cpu_fpr
[rD(ctx
->opcode
)]);
2242 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2243 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2244 gen_set_cr1_from_fpscr(ctx
);
2249 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2251 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2255 static void gen_fsqrt(DisasContext
*ctx
)
2257 if (unlikely(!ctx
->fpu_enabled
)) {
2258 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2261 /* NIP cannot be restored if the memory exception comes from an helper */
2262 gen_update_nip(ctx
, ctx
->nip
- 4);
2263 gen_reset_fpstatus();
2264 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2265 cpu_fpr
[rB(ctx
->opcode
)]);
2266 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2267 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2268 gen_set_cr1_from_fpscr(ctx
);
2272 static void gen_fsqrts(DisasContext
*ctx
)
2274 if (unlikely(!ctx
->fpu_enabled
)) {
2275 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2278 /* NIP cannot be restored if the memory exception comes from an helper */
2279 gen_update_nip(ctx
, ctx
->nip
- 4);
2280 gen_reset_fpstatus();
2281 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2282 cpu_fpr
[rB(ctx
->opcode
)]);
2283 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2284 cpu_fpr
[rD(ctx
->opcode
)]);
2285 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2286 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2287 gen_set_cr1_from_fpscr(ctx
);
2291 /*** Floating-Point multiply-and-add ***/
2292 /* fmadd - fmadds */
2293 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2294 /* fmsub - fmsubs */
2295 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2296 /* fnmadd - fnmadds */
2297 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2298 /* fnmsub - fnmsubs */
2299 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2301 /*** Floating-Point round & convert ***/
2303 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2305 GEN_FLOAT_B(ctiwu
, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206
);
2307 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2309 GEN_FLOAT_B(ctiwuz
, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206
);
2311 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2313 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64
);
2315 GEN_FLOAT_B(cfids
, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206
);
2317 GEN_FLOAT_B(cfidu
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2319 GEN_FLOAT_B(cfidus
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2321 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC2_FP_CVT_S64
);
2323 GEN_FLOAT_B(ctidu
, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2325 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC2_FP_CVT_S64
);
2327 GEN_FLOAT_B(ctiduz
, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2330 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2332 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2334 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2336 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2338 static void gen_ftdiv(DisasContext
*ctx
)
2340 if (unlikely(!ctx
->fpu_enabled
)) {
2341 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2344 gen_helper_ftdiv(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2345 cpu_fpr
[rB(ctx
->opcode
)]);
2348 static void gen_ftsqrt(DisasContext
*ctx
)
2350 if (unlikely(!ctx
->fpu_enabled
)) {
2351 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2354 gen_helper_ftsqrt(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2359 /*** Floating-Point compare ***/
2362 static void gen_fcmpo(DisasContext
*ctx
)
2365 if (unlikely(!ctx
->fpu_enabled
)) {
2366 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx
, ctx
->nip
- 4);
2371 gen_reset_fpstatus();
2372 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2373 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2374 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2375 tcg_temp_free_i32(crf
);
2376 gen_helper_float_check_status(cpu_env
);
2380 static void gen_fcmpu(DisasContext
*ctx
)
2383 if (unlikely(!ctx
->fpu_enabled
)) {
2384 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2387 /* NIP cannot be restored if the memory exception comes from an helper */
2388 gen_update_nip(ctx
, ctx
->nip
- 4);
2389 gen_reset_fpstatus();
2390 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2391 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2392 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2393 tcg_temp_free_i32(crf
);
2394 gen_helper_float_check_status(cpu_env
);
2397 /*** Floating-point move ***/
2399 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2400 static void gen_fabs(DisasContext
*ctx
)
2402 if (unlikely(!ctx
->fpu_enabled
)) {
2403 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2406 tcg_gen_andi_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2408 if (unlikely(Rc(ctx
->opcode
))) {
2409 gen_set_cr1_from_fpscr(ctx
);
2414 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2415 static void gen_fmr(DisasContext
*ctx
)
2417 if (unlikely(!ctx
->fpu_enabled
)) {
2418 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2421 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2422 if (unlikely(Rc(ctx
->opcode
))) {
2423 gen_set_cr1_from_fpscr(ctx
);
2428 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2429 static void gen_fnabs(DisasContext
*ctx
)
2431 if (unlikely(!ctx
->fpu_enabled
)) {
2432 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2435 tcg_gen_ori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2437 if (unlikely(Rc(ctx
->opcode
))) {
2438 gen_set_cr1_from_fpscr(ctx
);
2443 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2444 static void gen_fneg(DisasContext
*ctx
)
2446 if (unlikely(!ctx
->fpu_enabled
)) {
2447 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2450 tcg_gen_xori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2452 if (unlikely(Rc(ctx
->opcode
))) {
2453 gen_set_cr1_from_fpscr(ctx
);
2457 /* fcpsgn: PowerPC 2.05 specification */
2458 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2459 static void gen_fcpsgn(DisasContext
*ctx
)
2461 if (unlikely(!ctx
->fpu_enabled
)) {
2462 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2465 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2466 cpu_fpr
[rB(ctx
->opcode
)], 0, 63);
2467 if (unlikely(Rc(ctx
->opcode
))) {
2468 gen_set_cr1_from_fpscr(ctx
);
2472 static void gen_fmrgew(DisasContext
*ctx
)
2475 if (unlikely(!ctx
->fpu_enabled
)) {
2476 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2479 b0
= tcg_temp_new_i64();
2480 tcg_gen_shri_i64(b0
, cpu_fpr
[rB(ctx
->opcode
)], 32);
2481 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2483 tcg_temp_free_i64(b0
);
2486 static void gen_fmrgow(DisasContext
*ctx
)
2488 if (unlikely(!ctx
->fpu_enabled
)) {
2489 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2492 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)],
2493 cpu_fpr
[rB(ctx
->opcode
)],
2494 cpu_fpr
[rA(ctx
->opcode
)],
2498 /*** Floating-Point status & ctrl register ***/
2501 static void gen_mcrfs(DisasContext
*ctx
)
2503 TCGv tmp
= tcg_temp_new();
2505 TCGv_i64 tnew_fpscr
= tcg_temp_new_i64();
2510 if (unlikely(!ctx
->fpu_enabled
)) {
2511 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2514 bfa
= crfS(ctx
->opcode
);
2517 tcg_gen_shri_tl(tmp
, cpu_fpscr
, shift
);
2518 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2519 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2521 tcg_gen_extu_tl_i64(tnew_fpscr
, cpu_fpscr
);
2522 /* Only the exception bits (including FX) should be cleared if read */
2523 tcg_gen_andi_i64(tnew_fpscr
, tnew_fpscr
, ~((0xF << shift
) & FP_EX_CLEAR_BITS
));
2524 /* FEX and VX need to be updated, so don't set fpscr directly */
2525 tmask
= tcg_const_i32(1 << nibble
);
2526 gen_helper_store_fpscr(cpu_env
, tnew_fpscr
, tmask
);
2527 tcg_temp_free_i32(tmask
);
2528 tcg_temp_free_i64(tnew_fpscr
);
2532 static void gen_mffs(DisasContext
*ctx
)
2534 if (unlikely(!ctx
->fpu_enabled
)) {
2535 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2538 gen_reset_fpstatus();
2539 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2540 if (unlikely(Rc(ctx
->opcode
))) {
2541 gen_set_cr1_from_fpscr(ctx
);
2546 static void gen_mtfsb0(DisasContext
*ctx
)
2550 if (unlikely(!ctx
->fpu_enabled
)) {
2551 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2554 crb
= 31 - crbD(ctx
->opcode
);
2555 gen_reset_fpstatus();
2556 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2558 /* NIP cannot be restored if the memory exception comes from an helper */
2559 gen_update_nip(ctx
, ctx
->nip
- 4);
2560 t0
= tcg_const_i32(crb
);
2561 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2562 tcg_temp_free_i32(t0
);
2564 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2565 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2566 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2571 static void gen_mtfsb1(DisasContext
*ctx
)
2575 if (unlikely(!ctx
->fpu_enabled
)) {
2576 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2579 crb
= 31 - crbD(ctx
->opcode
);
2580 gen_reset_fpstatus();
2581 /* XXX: we pretend we can only do IEEE floating-point computations */
2582 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2584 /* NIP cannot be restored if the memory exception comes from an helper */
2585 gen_update_nip(ctx
, ctx
->nip
- 4);
2586 t0
= tcg_const_i32(crb
);
2587 gen_helper_fpscr_setbit(cpu_env
, t0
);
2588 tcg_temp_free_i32(t0
);
2590 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2591 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2592 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2594 /* We can raise a differed exception */
2595 gen_helper_float_check_status(cpu_env
);
2599 static void gen_mtfsf(DisasContext
*ctx
)
2604 if (unlikely(!ctx
->fpu_enabled
)) {
2605 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2608 flm
= FPFLM(ctx
->opcode
);
2609 l
= FPL(ctx
->opcode
);
2610 w
= FPW(ctx
->opcode
);
2611 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2612 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2615 /* NIP cannot be restored if the memory exception comes from an helper */
2616 gen_update_nip(ctx
, ctx
->nip
- 4);
2617 gen_reset_fpstatus();
2619 t0
= tcg_const_i32((ctx
->insns_flags2
& PPC2_ISA205
) ? 0xffff : 0xff);
2621 t0
= tcg_const_i32(flm
<< (w
* 8));
2623 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2624 tcg_temp_free_i32(t0
);
2625 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2626 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2627 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2629 /* We can raise a differed exception */
2630 gen_helper_float_check_status(cpu_env
);
2634 static void gen_mtfsfi(DisasContext
*ctx
)
2640 if (unlikely(!ctx
->fpu_enabled
)) {
2641 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2644 w
= FPW(ctx
->opcode
);
2645 bf
= FPBF(ctx
->opcode
);
2646 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2647 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2650 sh
= (8 * w
) + 7 - bf
;
2651 /* NIP cannot be restored if the memory exception comes from an helper */
2652 gen_update_nip(ctx
, ctx
->nip
- 4);
2653 gen_reset_fpstatus();
2654 t0
= tcg_const_i64(((uint64_t)FPIMM(ctx
->opcode
)) << (4 * sh
));
2655 t1
= tcg_const_i32(1 << sh
);
2656 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2657 tcg_temp_free_i64(t0
);
2658 tcg_temp_free_i32(t1
);
2659 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2660 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2661 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2663 /* We can raise a differed exception */
2664 gen_helper_float_check_status(cpu_env
);
2667 /*** Addressing modes ***/
2668 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2669 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2672 target_long simm
= SIMM(ctx
->opcode
);
2675 if (rA(ctx
->opcode
) == 0) {
2676 if (NARROW_MODE(ctx
)) {
2677 simm
= (uint32_t)simm
;
2679 tcg_gen_movi_tl(EA
, simm
);
2680 } else if (likely(simm
!= 0)) {
2681 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2682 if (NARROW_MODE(ctx
)) {
2683 tcg_gen_ext32u_tl(EA
, EA
);
2686 if (NARROW_MODE(ctx
)) {
2687 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2689 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2694 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2696 if (rA(ctx
->opcode
) == 0) {
2697 if (NARROW_MODE(ctx
)) {
2698 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2700 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2703 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2704 if (NARROW_MODE(ctx
)) {
2705 tcg_gen_ext32u_tl(EA
, EA
);
2710 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2712 if (rA(ctx
->opcode
) == 0) {
2713 tcg_gen_movi_tl(EA
, 0);
2714 } else if (NARROW_MODE(ctx
)) {
2715 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2717 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2721 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2724 tcg_gen_addi_tl(ret
, arg1
, val
);
2725 if (NARROW_MODE(ctx
)) {
2726 tcg_gen_ext32u_tl(ret
, ret
);
2730 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2732 TCGLabel
*l1
= gen_new_label();
2733 TCGv t0
= tcg_temp_new();
2735 /* NIP cannot be restored if the memory exception comes from an helper */
2736 gen_update_nip(ctx
, ctx
->nip
- 4);
2737 tcg_gen_andi_tl(t0
, EA
, mask
);
2738 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2739 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2740 t2
= tcg_const_i32(0);
2741 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2742 tcg_temp_free_i32(t1
);
2743 tcg_temp_free_i32(t2
);
2748 /*** Integer load ***/
2749 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2751 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2754 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2756 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2757 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2760 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2762 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2763 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2766 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2768 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2769 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2772 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2774 TCGv tmp
= tcg_temp_new();
2775 gen_qemu_ld32u(ctx
, tmp
, addr
);
2776 tcg_gen_extu_tl_i64(val
, tmp
);
2780 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2782 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2783 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2786 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2788 TCGv tmp
= tcg_temp_new();
2789 gen_qemu_ld32s(ctx
, tmp
, addr
);
2790 tcg_gen_ext_tl_i64(val
, tmp
);
2794 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2796 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2797 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2800 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2802 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2805 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2807 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2808 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2811 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2813 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2814 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2817 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2819 TCGv tmp
= tcg_temp_new();
2820 tcg_gen_trunc_i64_tl(tmp
, val
);
2821 gen_qemu_st32(ctx
, tmp
, addr
);
2825 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2827 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2828 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2831 #define GEN_LD(name, ldop, opc, type) \
2832 static void glue(gen_, name)(DisasContext *ctx) \
2835 gen_set_access_type(ctx, ACCESS_INT); \
2836 EA = tcg_temp_new(); \
2837 gen_addr_imm_index(ctx, EA, 0); \
2838 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
2842 #define GEN_LDU(name, ldop, opc, type) \
2843 static void glue(gen_, name##u)(DisasContext *ctx) \
2846 if (unlikely(rA(ctx->opcode) == 0 || \
2847 rA(ctx->opcode) == rD(ctx->opcode))) { \
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2851 gen_set_access_type(ctx, ACCESS_INT); \
2852 EA = tcg_temp_new(); \
2853 if (type == PPC_64B) \
2854 gen_addr_imm_index(ctx, EA, 0x03); \
2856 gen_addr_imm_index(ctx, EA, 0); \
2857 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2858 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2859 tcg_temp_free(EA); \
2862 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2863 static void glue(gen_, name##ux)(DisasContext *ctx) \
2866 if (unlikely(rA(ctx->opcode) == 0 || \
2867 rA(ctx->opcode) == rD(ctx->opcode))) { \
2868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2871 gen_set_access_type(ctx, ACCESS_INT); \
2872 EA = tcg_temp_new(); \
2873 gen_addr_reg_index(ctx, EA); \
2874 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2876 tcg_temp_free(EA); \
2879 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2880 static void glue(gen_, name##x)(DisasContext *ctx) \
2883 gen_set_access_type(ctx, ACCESS_INT); \
2884 EA = tcg_temp_new(); \
2885 gen_addr_reg_index(ctx, EA); \
2886 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2887 tcg_temp_free(EA); \
2889 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2890 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2892 #define GEN_LDS(name, ldop, op, type) \
2893 GEN_LD(name, ldop, op | 0x20, type); \
2894 GEN_LDU(name, ldop, op | 0x21, type); \
2895 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2896 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2898 /* lbz lbzu lbzux lbzx */
2899 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2900 /* lha lhau lhaux lhax */
2901 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2902 /* lhz lhzu lhzux lhzx */
2903 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2904 /* lwz lwzu lwzux lwzx */
2905 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2906 #if defined(TARGET_PPC64)
2908 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2910 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2912 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2914 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2916 static void gen_ld(DisasContext
*ctx
)
2919 if (Rc(ctx
->opcode
)) {
2920 if (unlikely(rA(ctx
->opcode
) == 0 ||
2921 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2922 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2926 gen_set_access_type(ctx
, ACCESS_INT
);
2927 EA
= tcg_temp_new();
2928 gen_addr_imm_index(ctx
, EA
, 0x03);
2929 if (ctx
->opcode
& 0x02) {
2930 /* lwa (lwau is undefined) */
2931 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2934 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2936 if (Rc(ctx
->opcode
))
2937 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2942 static void gen_lq(DisasContext
*ctx
)
2947 /* lq is a legal user mode instruction starting in ISA 2.07 */
2948 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2949 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2951 if (!legal_in_user_mode
&& ctx
->pr
) {
2952 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2956 if (!le_is_supported
&& ctx
->le_mode
) {
2957 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2961 ra
= rA(ctx
->opcode
);
2962 rd
= rD(ctx
->opcode
);
2963 if (unlikely((rd
& 1) || rd
== ra
)) {
2964 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2968 gen_set_access_type(ctx
, ACCESS_INT
);
2969 EA
= tcg_temp_new();
2970 gen_addr_imm_index(ctx
, EA
, 0x0F);
2972 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2973 64-bit byteswap already. */
2974 if (unlikely(ctx
->le_mode
)) {
2975 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2976 gen_addr_add(ctx
, EA
, EA
, 8);
2977 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2979 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2980 gen_addr_add(ctx
, EA
, EA
, 8);
2981 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2987 /*** Integer store ***/
2988 #define GEN_ST(name, stop, opc, type) \
2989 static void glue(gen_, name)(DisasContext *ctx) \
2992 gen_set_access_type(ctx, ACCESS_INT); \
2993 EA = tcg_temp_new(); \
2994 gen_addr_imm_index(ctx, EA, 0); \
2995 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2996 tcg_temp_free(EA); \
2999 #define GEN_STU(name, stop, opc, type) \
3000 static void glue(gen_, stop##u)(DisasContext *ctx) \
3003 if (unlikely(rA(ctx->opcode) == 0)) { \
3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3007 gen_set_access_type(ctx, ACCESS_INT); \
3008 EA = tcg_temp_new(); \
3009 if (type == PPC_64B) \
3010 gen_addr_imm_index(ctx, EA, 0x03); \
3012 gen_addr_imm_index(ctx, EA, 0); \
3013 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3015 tcg_temp_free(EA); \
3018 #define GEN_STUX(name, stop, opc2, opc3, type) \
3019 static void glue(gen_, name##ux)(DisasContext *ctx) \
3022 if (unlikely(rA(ctx->opcode) == 0)) { \
3023 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3026 gen_set_access_type(ctx, ACCESS_INT); \
3027 EA = tcg_temp_new(); \
3028 gen_addr_reg_index(ctx, EA); \
3029 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3030 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3031 tcg_temp_free(EA); \
3034 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3035 static void glue(gen_, name##x)(DisasContext *ctx) \
3038 gen_set_access_type(ctx, ACCESS_INT); \
3039 EA = tcg_temp_new(); \
3040 gen_addr_reg_index(ctx, EA); \
3041 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3042 tcg_temp_free(EA); \
3044 #define GEN_STX(name, stop, opc2, opc3, type) \
3045 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3047 #define GEN_STS(name, stop, op, type) \
3048 GEN_ST(name, stop, op | 0x20, type); \
3049 GEN_STU(name, stop, op | 0x21, type); \
3050 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3051 GEN_STX(name, stop, 0x17, op | 0x00, type)
3053 /* stb stbu stbux stbx */
3054 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
3055 /* sth sthu sthux sthx */
3056 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
3057 /* stw stwu stwux stwx */
3058 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
3059 #if defined(TARGET_PPC64)
3060 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
3061 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
3063 static void gen_std(DisasContext
*ctx
)
3068 rs
= rS(ctx
->opcode
);
3069 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
3071 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3072 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3074 if (!legal_in_user_mode
&& ctx
->pr
) {
3075 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3079 if (!le_is_supported
&& ctx
->le_mode
) {
3080 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
3084 if (unlikely(rs
& 1)) {
3085 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3088 gen_set_access_type(ctx
, ACCESS_INT
);
3089 EA
= tcg_temp_new();
3090 gen_addr_imm_index(ctx
, EA
, 0x03);
3092 /* We only need to swap high and low halves. gen_qemu_st64 does
3093 necessary 64-bit byteswap already. */
3094 if (unlikely(ctx
->le_mode
)) {
3095 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3096 gen_addr_add(ctx
, EA
, EA
, 8);
3097 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3099 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3100 gen_addr_add(ctx
, EA
, EA
, 8);
3101 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3106 if (Rc(ctx
->opcode
)) {
3107 if (unlikely(rA(ctx
->opcode
) == 0)) {
3108 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3112 gen_set_access_type(ctx
, ACCESS_INT
);
3113 EA
= tcg_temp_new();
3114 gen_addr_imm_index(ctx
, EA
, 0x03);
3115 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3116 if (Rc(ctx
->opcode
))
3117 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
3122 /*** Integer load and store with byte reverse ***/
3125 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3127 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3128 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3130 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3133 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3135 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3136 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3138 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3140 #if defined(TARGET_PPC64)
3142 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3144 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3145 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3147 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
3148 #endif /* TARGET_PPC64 */
3151 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3153 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3154 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3156 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3159 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3161 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3162 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3164 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3166 #if defined(TARGET_PPC64)
3168 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3170 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3171 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3173 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
3174 #endif /* TARGET_PPC64 */
3176 /*** Integer load and store multiple ***/
3179 static void gen_lmw(DisasContext
*ctx
)
3183 gen_set_access_type(ctx
, ACCESS_INT
);
3184 /* NIP cannot be restored if the memory exception comes from an helper */
3185 gen_update_nip(ctx
, ctx
->nip
- 4);
3186 t0
= tcg_temp_new();
3187 t1
= tcg_const_i32(rD(ctx
->opcode
));
3188 gen_addr_imm_index(ctx
, t0
, 0);
3189 gen_helper_lmw(cpu_env
, t0
, t1
);
3191 tcg_temp_free_i32(t1
);
3195 static void gen_stmw(DisasContext
*ctx
)
3199 gen_set_access_type(ctx
, ACCESS_INT
);
3200 /* NIP cannot be restored if the memory exception comes from an helper */
3201 gen_update_nip(ctx
, ctx
->nip
- 4);
3202 t0
= tcg_temp_new();
3203 t1
= tcg_const_i32(rS(ctx
->opcode
));
3204 gen_addr_imm_index(ctx
, t0
, 0);
3205 gen_helper_stmw(cpu_env
, t0
, t1
);
3207 tcg_temp_free_i32(t1
);
3210 /*** Integer load and store strings ***/
3213 /* PowerPC32 specification says we must generate an exception if
3214 * rA is in the range of registers to be loaded.
3215 * In an other hand, IBM says this is valid, but rA won't be loaded.
3216 * For now, I'll follow the spec...
3218 static void gen_lswi(DisasContext
*ctx
)
3222 int nb
= NB(ctx
->opcode
);
3223 int start
= rD(ctx
->opcode
);
3224 int ra
= rA(ctx
->opcode
);
3230 if (unlikely(((start
+ nr
) > 32 &&
3231 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3232 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3233 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3236 gen_set_access_type(ctx
, ACCESS_INT
);
3237 /* NIP cannot be restored if the memory exception comes from an helper */
3238 gen_update_nip(ctx
, ctx
->nip
- 4);
3239 t0
= tcg_temp_new();
3240 gen_addr_register(ctx
, t0
);
3241 t1
= tcg_const_i32(nb
);
3242 t2
= tcg_const_i32(start
);
3243 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3245 tcg_temp_free_i32(t1
);
3246 tcg_temp_free_i32(t2
);
3250 static void gen_lswx(DisasContext
*ctx
)
3253 TCGv_i32 t1
, t2
, t3
;
3254 gen_set_access_type(ctx
, ACCESS_INT
);
3255 /* NIP cannot be restored if the memory exception comes from an helper */
3256 gen_update_nip(ctx
, ctx
->nip
- 4);
3257 t0
= tcg_temp_new();
3258 gen_addr_reg_index(ctx
, t0
);
3259 t1
= tcg_const_i32(rD(ctx
->opcode
));
3260 t2
= tcg_const_i32(rA(ctx
->opcode
));
3261 t3
= tcg_const_i32(rB(ctx
->opcode
));
3262 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3264 tcg_temp_free_i32(t1
);
3265 tcg_temp_free_i32(t2
);
3266 tcg_temp_free_i32(t3
);
3270 static void gen_stswi(DisasContext
*ctx
)
3274 int nb
= NB(ctx
->opcode
);
3275 gen_set_access_type(ctx
, ACCESS_INT
);
3276 /* NIP cannot be restored if the memory exception comes from an helper */
3277 gen_update_nip(ctx
, ctx
->nip
- 4);
3278 t0
= tcg_temp_new();
3279 gen_addr_register(ctx
, t0
);
3282 t1
= tcg_const_i32(nb
);
3283 t2
= tcg_const_i32(rS(ctx
->opcode
));
3284 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3286 tcg_temp_free_i32(t1
);
3287 tcg_temp_free_i32(t2
);
3291 static void gen_stswx(DisasContext
*ctx
)
3295 gen_set_access_type(ctx
, ACCESS_INT
);
3296 /* NIP cannot be restored if the memory exception comes from an helper */
3297 gen_update_nip(ctx
, ctx
->nip
- 4);
3298 t0
= tcg_temp_new();
3299 gen_addr_reg_index(ctx
, t0
);
3300 t1
= tcg_temp_new_i32();
3301 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3302 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3303 t2
= tcg_const_i32(rS(ctx
->opcode
));
3304 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3306 tcg_temp_free_i32(t1
);
3307 tcg_temp_free_i32(t2
);
3310 /*** Memory synchronisation ***/
3312 static void gen_eieio(DisasContext
*ctx
)
3317 static void gen_isync(DisasContext
*ctx
)
3319 gen_stop_exception(ctx
);
3322 #define LARX(name, len, loadop) \
3323 static void gen_##name(DisasContext *ctx) \
3326 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3327 gen_set_access_type(ctx, ACCESS_RES); \
3328 t0 = tcg_temp_local_new(); \
3329 gen_addr_reg_index(ctx, t0); \
3331 gen_check_align(ctx, t0, (len)-1); \
3333 gen_qemu_##loadop(ctx, gpr, t0); \
3334 tcg_gen_mov_tl(cpu_reserve, t0); \
3335 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3336 tcg_temp_free(t0); \
3340 LARX(lbarx
, 1, ld8u
);
3341 LARX(lharx
, 2, ld16u
);
3342 LARX(lwarx
, 4, ld32u
);
3345 #if defined(CONFIG_USER_ONLY)
3346 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3349 TCGv t0
= tcg_temp_new();
3350 uint32_t save_exception
= ctx
->exception
;
3352 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3353 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3354 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3356 gen_update_nip(ctx
, ctx
->nip
-4);
3357 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3358 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3359 ctx
->exception
= save_exception
;
3362 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3367 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3368 l1
= gen_new_label();
3369 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3370 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3371 #if defined(TARGET_PPC64)
3373 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3377 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3378 } else if (size
== 2) {
3379 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3380 #if defined(TARGET_PPC64)
3381 } else if (size
== 16) {
3382 TCGv gpr1
, gpr2
, EA8
;
3383 if (unlikely(ctx
->le_mode
)) {
3384 gpr1
= cpu_gpr
[reg
+1];
3385 gpr2
= cpu_gpr
[reg
];
3387 gpr1
= cpu_gpr
[reg
];
3388 gpr2
= cpu_gpr
[reg
+1];
3390 gen_qemu_st64(ctx
, gpr1
, EA
);
3391 EA8
= tcg_temp_local_new();
3392 gen_addr_add(ctx
, EA8
, EA
, 8);
3393 gen_qemu_st64(ctx
, gpr2
, EA8
);
3397 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3400 tcg_gen_movi_tl(cpu_reserve
, -1);
3404 #define STCX(name, len) \
3405 static void gen_##name(DisasContext *ctx) \
3408 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3409 gen_inval_exception(ctx, \
3410 POWERPC_EXCP_INVAL_INVAL); \
3413 gen_set_access_type(ctx, ACCESS_RES); \
3414 t0 = tcg_temp_local_new(); \
3415 gen_addr_reg_index(ctx, t0); \
3417 gen_check_align(ctx, t0, (len)-1); \
3419 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3420 tcg_temp_free(t0); \
3427 #if defined(TARGET_PPC64)
3429 LARX(ldarx
, 8, ld64
);
3432 static void gen_lqarx(DisasContext
*ctx
)
3435 int rd
= rD(ctx
->opcode
);
3438 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3439 (rd
== rB(ctx
->opcode
)))) {
3440 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3444 gen_set_access_type(ctx
, ACCESS_RES
);
3445 EA
= tcg_temp_local_new();
3446 gen_addr_reg_index(ctx
, EA
);
3447 gen_check_align(ctx
, EA
, 15);
3448 if (unlikely(ctx
->le_mode
)) {
3449 gpr1
= cpu_gpr
[rd
+1];
3453 gpr2
= cpu_gpr
[rd
+1];
3455 gen_qemu_ld64(ctx
, gpr1
, EA
);
3456 tcg_gen_mov_tl(cpu_reserve
, EA
);
3458 gen_addr_add(ctx
, EA
, EA
, 8);
3459 gen_qemu_ld64(ctx
, gpr2
, EA
);
3461 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3462 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3470 #endif /* defined(TARGET_PPC64) */
3473 static void gen_sync(DisasContext
*ctx
)
3478 static void gen_wait(DisasContext
*ctx
)
3480 TCGv_i32 t0
= tcg_temp_new_i32();
3481 tcg_gen_st_i32(t0
, cpu_env
,
3482 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3483 tcg_temp_free_i32(t0
);
3484 /* Stop translation, as the CPU is supposed to sleep from now */
3485 gen_exception_err(ctx
, EXCP_HLT
, 1);
3488 /*** Floating-point load ***/
3489 #define GEN_LDF(name, ldop, opc, type) \
3490 static void glue(gen_, name)(DisasContext *ctx) \
3493 if (unlikely(!ctx->fpu_enabled)) { \
3494 gen_exception(ctx, POWERPC_EXCP_FPU); \
3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
3498 EA = tcg_temp_new(); \
3499 gen_addr_imm_index(ctx, EA, 0); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3501 tcg_temp_free(EA); \
3504 #define GEN_LDUF(name, ldop, opc, type) \
3505 static void glue(gen_, name##u)(DisasContext *ctx) \
3508 if (unlikely(!ctx->fpu_enabled)) { \
3509 gen_exception(ctx, POWERPC_EXCP_FPU); \
3512 if (unlikely(rA(ctx->opcode) == 0)) { \
3513 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3516 gen_set_access_type(ctx, ACCESS_FLOAT); \
3517 EA = tcg_temp_new(); \
3518 gen_addr_imm_index(ctx, EA, 0); \
3519 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3520 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3521 tcg_temp_free(EA); \
3524 #define GEN_LDUXF(name, ldop, opc, type) \
3525 static void glue(gen_, name##ux)(DisasContext *ctx) \
3528 if (unlikely(!ctx->fpu_enabled)) { \
3529 gen_exception(ctx, POWERPC_EXCP_FPU); \
3532 if (unlikely(rA(ctx->opcode) == 0)) { \
3533 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3536 gen_set_access_type(ctx, ACCESS_FLOAT); \
3537 EA = tcg_temp_new(); \
3538 gen_addr_reg_index(ctx, EA); \
3539 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3541 tcg_temp_free(EA); \
3544 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3545 static void glue(gen_, name##x)(DisasContext *ctx) \
3548 if (unlikely(!ctx->fpu_enabled)) { \
3549 gen_exception(ctx, POWERPC_EXCP_FPU); \
3552 gen_set_access_type(ctx, ACCESS_FLOAT); \
3553 EA = tcg_temp_new(); \
3554 gen_addr_reg_index(ctx, EA); \
3555 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3556 tcg_temp_free(EA); \
3559 #define GEN_LDFS(name, ldop, op, type) \
3560 GEN_LDF(name, ldop, op | 0x20, type); \
3561 GEN_LDUF(name, ldop, op | 0x21, type); \
3562 GEN_LDUXF(name, ldop, op | 0x01, type); \
3563 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3565 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3567 TCGv t0
= tcg_temp_new();
3568 TCGv_i32 t1
= tcg_temp_new_i32();
3569 gen_qemu_ld32u(ctx
, t0
, arg2
);
3570 tcg_gen_trunc_tl_i32(t1
, t0
);
3572 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3573 tcg_temp_free_i32(t1
);
3576 /* lfd lfdu lfdux lfdx */
3577 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3578 /* lfs lfsu lfsux lfsx */
3579 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3582 static void gen_lfdp(DisasContext
*ctx
)
3585 if (unlikely(!ctx
->fpu_enabled
)) {
3586 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3589 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3590 EA
= tcg_temp_new();
3591 gen_addr_imm_index(ctx
, EA
, 0);
3592 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3593 64-bit byteswap already. */
3594 if (unlikely(ctx
->le_mode
)) {
3595 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3596 tcg_gen_addi_tl(EA
, EA
, 8);
3597 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3599 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3600 tcg_gen_addi_tl(EA
, EA
, 8);
3601 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3607 static void gen_lfdpx(DisasContext
*ctx
)
3610 if (unlikely(!ctx
->fpu_enabled
)) {
3611 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3614 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3615 EA
= tcg_temp_new();
3616 gen_addr_reg_index(ctx
, EA
);
3617 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3618 64-bit byteswap already. */
3619 if (unlikely(ctx
->le_mode
)) {
3620 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3621 tcg_gen_addi_tl(EA
, EA
, 8);
3622 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3624 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3625 tcg_gen_addi_tl(EA
, EA
, 8);
3626 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3632 static void gen_lfiwax(DisasContext
*ctx
)
3636 if (unlikely(!ctx
->fpu_enabled
)) {
3637 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3640 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3641 EA
= tcg_temp_new();
3642 t0
= tcg_temp_new();
3643 gen_addr_reg_index(ctx
, EA
);
3644 gen_qemu_ld32s(ctx
, t0
, EA
);
3645 tcg_gen_ext_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], t0
);
3651 static void gen_lfiwzx(DisasContext
*ctx
)
3654 if (unlikely(!ctx
->fpu_enabled
)) {
3655 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3658 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3659 EA
= tcg_temp_new();
3660 gen_addr_reg_index(ctx
, EA
);
3661 gen_qemu_ld32u_i64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3664 /*** Floating-point store ***/
3665 #define GEN_STF(name, stop, opc, type) \
3666 static void glue(gen_, name)(DisasContext *ctx) \
3669 if (unlikely(!ctx->fpu_enabled)) { \
3670 gen_exception(ctx, POWERPC_EXCP_FPU); \
3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
3674 EA = tcg_temp_new(); \
3675 gen_addr_imm_index(ctx, EA, 0); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3677 tcg_temp_free(EA); \
3680 #define GEN_STUF(name, stop, opc, type) \
3681 static void glue(gen_, name##u)(DisasContext *ctx) \
3684 if (unlikely(!ctx->fpu_enabled)) { \
3685 gen_exception(ctx, POWERPC_EXCP_FPU); \
3688 if (unlikely(rA(ctx->opcode) == 0)) { \
3689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3692 gen_set_access_type(ctx, ACCESS_FLOAT); \
3693 EA = tcg_temp_new(); \
3694 gen_addr_imm_index(ctx, EA, 0); \
3695 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3697 tcg_temp_free(EA); \
3700 #define GEN_STUXF(name, stop, opc, type) \
3701 static void glue(gen_, name##ux)(DisasContext *ctx) \
3704 if (unlikely(!ctx->fpu_enabled)) { \
3705 gen_exception(ctx, POWERPC_EXCP_FPU); \
3708 if (unlikely(rA(ctx->opcode) == 0)) { \
3709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3712 gen_set_access_type(ctx, ACCESS_FLOAT); \
3713 EA = tcg_temp_new(); \
3714 gen_addr_reg_index(ctx, EA); \
3715 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3716 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3717 tcg_temp_free(EA); \
3720 #define GEN_STXF(name, stop, opc2, opc3, type) \
3721 static void glue(gen_, name##x)(DisasContext *ctx) \
3724 if (unlikely(!ctx->fpu_enabled)) { \
3725 gen_exception(ctx, POWERPC_EXCP_FPU); \
3728 gen_set_access_type(ctx, ACCESS_FLOAT); \
3729 EA = tcg_temp_new(); \
3730 gen_addr_reg_index(ctx, EA); \
3731 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3732 tcg_temp_free(EA); \
3735 #define GEN_STFS(name, stop, op, type) \
3736 GEN_STF(name, stop, op | 0x20, type); \
3737 GEN_STUF(name, stop, op | 0x21, type); \
3738 GEN_STUXF(name, stop, op | 0x01, type); \
3739 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3741 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3743 TCGv_i32 t0
= tcg_temp_new_i32();
3744 TCGv t1
= tcg_temp_new();
3745 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3746 tcg_gen_extu_i32_tl(t1
, t0
);
3747 tcg_temp_free_i32(t0
);
3748 gen_qemu_st32(ctx
, t1
, arg2
);
3752 /* stfd stfdu stfdux stfdx */
3753 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3754 /* stfs stfsu stfsux stfsx */
3755 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3758 static void gen_stfdp(DisasContext
*ctx
)
3761 if (unlikely(!ctx
->fpu_enabled
)) {
3762 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3765 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3766 EA
= tcg_temp_new();
3767 gen_addr_imm_index(ctx
, EA
, 0);
3768 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3769 64-bit byteswap already. */
3770 if (unlikely(ctx
->le_mode
)) {
3771 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3772 tcg_gen_addi_tl(EA
, EA
, 8);
3773 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3775 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3776 tcg_gen_addi_tl(EA
, EA
, 8);
3777 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3783 static void gen_stfdpx(DisasContext
*ctx
)
3786 if (unlikely(!ctx
->fpu_enabled
)) {
3787 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3790 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3791 EA
= tcg_temp_new();
3792 gen_addr_reg_index(ctx
, EA
);
3793 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3794 64-bit byteswap already. */
3795 if (unlikely(ctx
->le_mode
)) {
3796 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3797 tcg_gen_addi_tl(EA
, EA
, 8);
3798 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3800 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3801 tcg_gen_addi_tl(EA
, EA
, 8);
3802 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3808 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3810 TCGv t0
= tcg_temp_new();
3811 tcg_gen_trunc_i64_tl(t0
, arg1
),
3812 gen_qemu_st32(ctx
, t0
, arg2
);
3816 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3818 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3820 #if defined(TARGET_PPC64)
3822 tcg_gen_movi_tl(cpu_cfar
, nip
);
3827 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3829 TranslationBlock
*tb
;
3831 if (NARROW_MODE(ctx
)) {
3832 dest
= (uint32_t) dest
;
3834 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3835 likely(!ctx
->singlestep_enabled
)) {
3837 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3838 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
3840 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3841 if (unlikely(ctx
->singlestep_enabled
)) {
3842 if ((ctx
->singlestep_enabled
&
3843 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3844 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3845 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3846 target_ulong tmp
= ctx
->nip
;
3848 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3851 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3852 gen_debug_exception(ctx
);
3859 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3861 if (NARROW_MODE(ctx
)) {
3862 nip
= (uint32_t)nip
;
3864 tcg_gen_movi_tl(cpu_lr
, nip
);
3868 static void gen_b(DisasContext
*ctx
)
3870 target_ulong li
, target
;
3872 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3873 /* sign extend LI */
3874 li
= LI(ctx
->opcode
);
3875 li
= (li
^ 0x02000000) - 0x02000000;
3876 if (likely(AA(ctx
->opcode
) == 0)) {
3877 target
= ctx
->nip
+ li
- 4;
3881 if (LK(ctx
->opcode
)) {
3882 gen_setlr(ctx
, ctx
->nip
);
3884 gen_update_cfar(ctx
, ctx
->nip
);
3885 gen_goto_tb(ctx
, 0, target
);
3893 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3895 uint32_t bo
= BO(ctx
->opcode
);
3899 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3900 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3901 target
= tcg_temp_local_new();
3902 if (type
== BCOND_CTR
)
3903 tcg_gen_mov_tl(target
, cpu_ctr
);
3904 else if (type
== BCOND_TAR
)
3905 gen_load_spr(target
, SPR_TAR
);
3907 tcg_gen_mov_tl(target
, cpu_lr
);
3909 TCGV_UNUSED(target
);
3911 if (LK(ctx
->opcode
))
3912 gen_setlr(ctx
, ctx
->nip
);
3913 l1
= gen_new_label();
3914 if ((bo
& 0x4) == 0) {
3915 /* Decrement and test CTR */
3916 TCGv temp
= tcg_temp_new();
3917 if (unlikely(type
== BCOND_CTR
)) {
3918 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3921 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3922 if (NARROW_MODE(ctx
)) {
3923 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3925 tcg_gen_mov_tl(temp
, cpu_ctr
);
3928 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3930 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3932 tcg_temp_free(temp
);
3934 if ((bo
& 0x10) == 0) {
3936 uint32_t bi
= BI(ctx
->opcode
);
3937 uint32_t mask
= 0x08 >> (bi
& 0x03);
3938 TCGv_i32 temp
= tcg_temp_new_i32();
3941 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3942 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3944 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3945 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3947 tcg_temp_free_i32(temp
);
3949 gen_update_cfar(ctx
, ctx
->nip
);
3950 if (type
== BCOND_IM
) {
3951 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3952 if (likely(AA(ctx
->opcode
) == 0)) {
3953 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3955 gen_goto_tb(ctx
, 0, li
);
3958 gen_goto_tb(ctx
, 1, ctx
->nip
);
3960 if (NARROW_MODE(ctx
)) {
3961 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3963 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3967 gen_update_nip(ctx
, ctx
->nip
);
3970 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3971 tcg_temp_free(target
);
3975 static void gen_bc(DisasContext
*ctx
)
3977 gen_bcond(ctx
, BCOND_IM
);
3980 static void gen_bcctr(DisasContext
*ctx
)
3982 gen_bcond(ctx
, BCOND_CTR
);
3985 static void gen_bclr(DisasContext
*ctx
)
3987 gen_bcond(ctx
, BCOND_LR
);
3990 static void gen_bctar(DisasContext
*ctx
)
3992 gen_bcond(ctx
, BCOND_TAR
);
3995 /*** Condition register logical ***/
3996 #define GEN_CRLOGIC(name, tcg_op, opc) \
3997 static void glue(gen_, name)(DisasContext *ctx) \
4002 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4003 t0 = tcg_temp_new_i32(); \
4005 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4007 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4009 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4010 t1 = tcg_temp_new_i32(); \
4011 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4013 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4015 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4017 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4018 tcg_op(t0, t0, t1); \
4019 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4020 tcg_gen_andi_i32(t0, t0, bitmask); \
4021 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4022 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4023 tcg_temp_free_i32(t0); \
4024 tcg_temp_free_i32(t1); \
4028 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
4030 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
4032 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
4034 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
4036 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
4038 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
4040 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
4042 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
4045 static void gen_mcrf(DisasContext
*ctx
)
4047 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
4050 /*** System linkage ***/
4052 /* rfi (supervisor only) */
4053 static void gen_rfi(DisasContext
*ctx
)
4055 #if defined(CONFIG_USER_ONLY)
4056 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4058 /* Restore CPU state */
4059 if (unlikely(ctx
->pr
)) {
4060 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4063 gen_update_cfar(ctx
, ctx
->nip
);
4064 gen_helper_rfi(cpu_env
);
4065 gen_sync_exception(ctx
);
4069 #if defined(TARGET_PPC64)
4070 static void gen_rfid(DisasContext
*ctx
)
4072 #if defined(CONFIG_USER_ONLY)
4073 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4075 /* Restore CPU state */
4076 if (unlikely(ctx
->pr
)) {
4077 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4080 gen_update_cfar(ctx
, ctx
->nip
);
4081 gen_helper_rfid(cpu_env
);
4082 gen_sync_exception(ctx
);
4086 static void gen_hrfid(DisasContext
*ctx
)
4088 #if defined(CONFIG_USER_ONLY)
4089 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4091 /* Restore CPU state */
4092 if (unlikely(!ctx
->hv
)) {
4093 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4096 gen_helper_hrfid(cpu_env
);
4097 gen_sync_exception(ctx
);
4103 #if defined(CONFIG_USER_ONLY)
4104 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4106 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4108 static void gen_sc(DisasContext
*ctx
)
4112 lev
= (ctx
->opcode
>> 5) & 0x7F;
4113 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4119 static void gen_tw(DisasContext
*ctx
)
4121 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4122 /* Update the nip since this might generate a trap exception */
4123 gen_update_nip(ctx
, ctx
->nip
);
4124 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4126 tcg_temp_free_i32(t0
);
4130 static void gen_twi(DisasContext
*ctx
)
4132 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4133 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4134 /* Update the nip since this might generate a trap exception */
4135 gen_update_nip(ctx
, ctx
->nip
);
4136 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4138 tcg_temp_free_i32(t1
);
4141 #if defined(TARGET_PPC64)
4143 static void gen_td(DisasContext
*ctx
)
4145 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4146 /* Update the nip since this might generate a trap exception */
4147 gen_update_nip(ctx
, ctx
->nip
);
4148 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4150 tcg_temp_free_i32(t0
);
4154 static void gen_tdi(DisasContext
*ctx
)
4156 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4157 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4158 /* Update the nip since this might generate a trap exception */
4159 gen_update_nip(ctx
, ctx
->nip
);
4160 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4162 tcg_temp_free_i32(t1
);
4166 /*** Processor control ***/
4168 static void gen_read_xer(TCGv dst
)
4170 TCGv t0
= tcg_temp_new();
4171 TCGv t1
= tcg_temp_new();
4172 TCGv t2
= tcg_temp_new();
4173 tcg_gen_mov_tl(dst
, cpu_xer
);
4174 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4175 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4176 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4177 tcg_gen_or_tl(t0
, t0
, t1
);
4178 tcg_gen_or_tl(dst
, dst
, t2
);
4179 tcg_gen_or_tl(dst
, dst
, t0
);
4185 static void gen_write_xer(TCGv src
)
4187 tcg_gen_andi_tl(cpu_xer
, src
,
4188 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
4189 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
4190 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
4191 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
4192 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
4193 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
4194 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
4198 static void gen_mcrxr(DisasContext
*ctx
)
4200 TCGv_i32 t0
= tcg_temp_new_i32();
4201 TCGv_i32 t1
= tcg_temp_new_i32();
4202 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4204 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4205 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4206 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4207 tcg_gen_shli_i32(t0
, t0
, 3);
4208 tcg_gen_shli_i32(t1
, t1
, 2);
4209 tcg_gen_shli_i32(dst
, dst
, 1);
4210 tcg_gen_or_i32(dst
, dst
, t0
);
4211 tcg_gen_or_i32(dst
, dst
, t1
);
4212 tcg_temp_free_i32(t0
);
4213 tcg_temp_free_i32(t1
);
4215 tcg_gen_movi_tl(cpu_so
, 0);
4216 tcg_gen_movi_tl(cpu_ov
, 0);
4217 tcg_gen_movi_tl(cpu_ca
, 0);
4221 static void gen_mfcr(DisasContext
*ctx
)
4225 if (likely(ctx
->opcode
& 0x00100000)) {
4226 crm
= CRM(ctx
->opcode
);
4227 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4229 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4230 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4231 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4234 TCGv_i32 t0
= tcg_temp_new_i32();
4235 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4236 tcg_gen_shli_i32(t0
, t0
, 4);
4237 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4238 tcg_gen_shli_i32(t0
, t0
, 4);
4239 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4240 tcg_gen_shli_i32(t0
, t0
, 4);
4241 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4242 tcg_gen_shli_i32(t0
, t0
, 4);
4243 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4244 tcg_gen_shli_i32(t0
, t0
, 4);
4245 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4246 tcg_gen_shli_i32(t0
, t0
, 4);
4247 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4248 tcg_gen_shli_i32(t0
, t0
, 4);
4249 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4250 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4251 tcg_temp_free_i32(t0
);
4256 static void gen_mfmsr(DisasContext
*ctx
)
4258 #if defined(CONFIG_USER_ONLY)
4259 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4261 if (unlikely(ctx
->pr
)) {
4262 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4265 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4269 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4272 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4273 printf("ERROR: try to access SPR %d !\n", sprn
);
4276 #define SPR_NOACCESS (&spr_noaccess)
4279 static inline void gen_op_mfspr(DisasContext
*ctx
)
4281 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4282 uint32_t sprn
= SPR(ctx
->opcode
);
4284 #if !defined(CONFIG_USER_ONLY)
4286 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4288 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4291 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4292 if (likely(read_cb
!= NULL
)) {
4293 if (likely(read_cb
!= SPR_NOACCESS
)) {
4294 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4296 /* Privilege exception */
4297 /* This is a hack to avoid warnings when running Linux:
4298 * this OS breaks the PowerPC virtualisation model,
4299 * allowing userland application to read the PVR
4301 if (sprn
!= SPR_PVR
) {
4302 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
4303 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4304 if (qemu_log_separate()) {
4305 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4306 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4309 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4313 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
4314 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4315 if (qemu_log_separate()) {
4316 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4317 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4319 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4323 static void gen_mfspr(DisasContext
*ctx
)
4329 static void gen_mftb(DisasContext
*ctx
)
4335 static void gen_mtcrf(DisasContext
*ctx
)
4339 crm
= CRM(ctx
->opcode
);
4340 if (likely((ctx
->opcode
& 0x00100000))) {
4341 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4342 TCGv_i32 temp
= tcg_temp_new_i32();
4344 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4345 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4346 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4347 tcg_temp_free_i32(temp
);
4350 TCGv_i32 temp
= tcg_temp_new_i32();
4351 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4352 for (crn
= 0 ; crn
< 8 ; crn
++) {
4353 if (crm
& (1 << crn
)) {
4354 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4355 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4358 tcg_temp_free_i32(temp
);
4363 #if defined(TARGET_PPC64)
4364 static void gen_mtmsrd(DisasContext
*ctx
)
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4369 if (unlikely(ctx
->pr
)) {
4370 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4373 if (ctx
->opcode
& 0x00010000) {
4374 /* Special form that does not need any synchronisation */
4375 TCGv t0
= tcg_temp_new();
4376 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4377 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4378 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4381 /* XXX: we need to update nip before the store
4382 * if we enter power saving mode, we will exit the loop
4383 * directly from ppc_store_msr
4385 gen_update_nip(ctx
, ctx
->nip
);
4386 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4387 /* Must stop the translation as machine state (may have) changed */
4388 /* Note that mtmsr is not always defined as context-synchronizing */
4389 gen_stop_exception(ctx
);
4395 static void gen_mtmsr(DisasContext
*ctx
)
4397 #if defined(CONFIG_USER_ONLY)
4398 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4400 if (unlikely(ctx
->pr
)) {
4401 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4404 if (ctx
->opcode
& 0x00010000) {
4405 /* Special form that does not need any synchronisation */
4406 TCGv t0
= tcg_temp_new();
4407 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4408 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4409 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4412 TCGv msr
= tcg_temp_new();
4414 /* XXX: we need to update nip before the store
4415 * if we enter power saving mode, we will exit the loop
4416 * directly from ppc_store_msr
4418 gen_update_nip(ctx
, ctx
->nip
);
4419 #if defined(TARGET_PPC64)
4420 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4422 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4424 gen_helper_store_msr(cpu_env
, msr
);
4426 /* Must stop the translation as machine state (may have) changed */
4427 /* Note that mtmsr is not always defined as context-synchronizing */
4428 gen_stop_exception(ctx
);
4434 static void gen_mtspr(DisasContext
*ctx
)
4436 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4437 uint32_t sprn
= SPR(ctx
->opcode
);
4439 #if !defined(CONFIG_USER_ONLY)
4441 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4443 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4446 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4447 if (likely(write_cb
!= NULL
)) {
4448 if (likely(write_cb
!= SPR_NOACCESS
)) {
4449 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4451 /* Privilege exception */
4452 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
4453 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4454 if (qemu_log_separate()) {
4455 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4456 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4458 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4462 if (qemu_log_separate()) {
4463 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4464 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4466 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
4467 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4468 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4472 /*** Cache management ***/
4475 static void gen_dcbf(DisasContext
*ctx
)
4477 /* XXX: specification says this is treated as a load by the MMU */
4479 gen_set_access_type(ctx
, ACCESS_CACHE
);
4480 t0
= tcg_temp_new();
4481 gen_addr_reg_index(ctx
, t0
);
4482 gen_qemu_ld8u(ctx
, t0
, t0
);
4486 /* dcbi (Supervisor only) */
4487 static void gen_dcbi(DisasContext
*ctx
)
4489 #if defined(CONFIG_USER_ONLY)
4490 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4493 if (unlikely(ctx
->pr
)) {
4494 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4497 EA
= tcg_temp_new();
4498 gen_set_access_type(ctx
, ACCESS_CACHE
);
4499 gen_addr_reg_index(ctx
, EA
);
4500 val
= tcg_temp_new();
4501 /* XXX: specification says this should be treated as a store by the MMU */
4502 gen_qemu_ld8u(ctx
, val
, EA
);
4503 gen_qemu_st8(ctx
, val
, EA
);
4510 static void gen_dcbst(DisasContext
*ctx
)
4512 /* XXX: specification say this is treated as a load by the MMU */
4514 gen_set_access_type(ctx
, ACCESS_CACHE
);
4515 t0
= tcg_temp_new();
4516 gen_addr_reg_index(ctx
, t0
);
4517 gen_qemu_ld8u(ctx
, t0
, t0
);
4522 static void gen_dcbt(DisasContext
*ctx
)
4524 /* interpreted as no-op */
4525 /* XXX: specification say this is treated as a load by the MMU
4526 * but does not generate any exception
4531 static void gen_dcbtst(DisasContext
*ctx
)
4533 /* interpreted as no-op */
4534 /* XXX: specification say this is treated as a load by the MMU
4535 * but does not generate any exception
4540 static void gen_dcbtls(DisasContext
*ctx
)
4542 /* Always fails locking the cache */
4543 TCGv t0
= tcg_temp_new();
4544 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4545 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4546 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4551 static void gen_dcbz(DisasContext
*ctx
)
4554 TCGv_i32 tcgv_is_dcbzl
;
4555 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4557 gen_set_access_type(ctx
, ACCESS_CACHE
);
4558 /* NIP cannot be restored if the memory exception comes from an helper */
4559 gen_update_nip(ctx
, ctx
->nip
- 4);
4560 tcgv_addr
= tcg_temp_new();
4561 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4563 gen_addr_reg_index(ctx
, tcgv_addr
);
4564 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4566 tcg_temp_free(tcgv_addr
);
4567 tcg_temp_free_i32(tcgv_is_dcbzl
);
4571 static void gen_dst(DisasContext
*ctx
)
4573 if (rA(ctx
->opcode
) == 0) {
4574 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4576 /* interpreted as no-op */
4581 static void gen_dstst(DisasContext
*ctx
)
4583 if (rA(ctx
->opcode
) == 0) {
4584 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4586 /* interpreted as no-op */
4592 static void gen_dss(DisasContext
*ctx
)
4594 /* interpreted as no-op */
4598 static void gen_icbi(DisasContext
*ctx
)
4601 gen_set_access_type(ctx
, ACCESS_CACHE
);
4602 /* NIP cannot be restored if the memory exception comes from an helper */
4603 gen_update_nip(ctx
, ctx
->nip
- 4);
4604 t0
= tcg_temp_new();
4605 gen_addr_reg_index(ctx
, t0
);
4606 gen_helper_icbi(cpu_env
, t0
);
4612 static void gen_dcba(DisasContext
*ctx
)
4614 /* interpreted as no-op */
4615 /* XXX: specification say this is treated as a store by the MMU
4616 * but does not generate any exception
4620 /*** Segment register manipulation ***/
4621 /* Supervisor only: */
4624 static void gen_mfsr(DisasContext
*ctx
)
4626 #if defined(CONFIG_USER_ONLY)
4627 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4630 if (unlikely(ctx
->pr
)) {
4631 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4634 t0
= tcg_const_tl(SR(ctx
->opcode
));
4635 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4641 static void gen_mfsrin(DisasContext
*ctx
)
4643 #if defined(CONFIG_USER_ONLY)
4644 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4647 if (unlikely(ctx
->pr
)) {
4648 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4651 t0
= tcg_temp_new();
4652 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4653 tcg_gen_andi_tl(t0
, t0
, 0xF);
4654 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4660 static void gen_mtsr(DisasContext
*ctx
)
4662 #if defined(CONFIG_USER_ONLY)
4663 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4666 if (unlikely(ctx
->pr
)) {
4667 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4670 t0
= tcg_const_tl(SR(ctx
->opcode
));
4671 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4677 static void gen_mtsrin(DisasContext
*ctx
)
4679 #if defined(CONFIG_USER_ONLY)
4680 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4683 if (unlikely(ctx
->pr
)) {
4684 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4687 t0
= tcg_temp_new();
4688 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4689 tcg_gen_andi_tl(t0
, t0
, 0xF);
4690 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4695 #if defined(TARGET_PPC64)
4696 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4699 static void gen_mfsr_64b(DisasContext
*ctx
)
4701 #if defined(CONFIG_USER_ONLY)
4702 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4705 if (unlikely(ctx
->pr
)) {
4706 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4709 t0
= tcg_const_tl(SR(ctx
->opcode
));
4710 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4716 static void gen_mfsrin_64b(DisasContext
*ctx
)
4718 #if defined(CONFIG_USER_ONLY)
4719 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4722 if (unlikely(ctx
->pr
)) {
4723 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4726 t0
= tcg_temp_new();
4727 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4728 tcg_gen_andi_tl(t0
, t0
, 0xF);
4729 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4735 static void gen_mtsr_64b(DisasContext
*ctx
)
4737 #if defined(CONFIG_USER_ONLY)
4738 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4741 if (unlikely(ctx
->pr
)) {
4742 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4745 t0
= tcg_const_tl(SR(ctx
->opcode
));
4746 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4752 static void gen_mtsrin_64b(DisasContext
*ctx
)
4754 #if defined(CONFIG_USER_ONLY)
4755 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4758 if (unlikely(ctx
->pr
)) {
4759 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4762 t0
= tcg_temp_new();
4763 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4764 tcg_gen_andi_tl(t0
, t0
, 0xF);
4765 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4771 static void gen_slbmte(DisasContext
*ctx
)
4773 #if defined(CONFIG_USER_ONLY)
4774 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4776 if (unlikely(ctx
->pr
)) {
4777 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4780 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4781 cpu_gpr
[rS(ctx
->opcode
)]);
4785 static void gen_slbmfee(DisasContext
*ctx
)
4787 #if defined(CONFIG_USER_ONLY)
4788 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4790 if (unlikely(ctx
->pr
)) {
4791 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4794 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4795 cpu_gpr
[rB(ctx
->opcode
)]);
4799 static void gen_slbmfev(DisasContext
*ctx
)
4801 #if defined(CONFIG_USER_ONLY)
4802 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4804 if (unlikely(ctx
->pr
)) {
4805 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4808 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4809 cpu_gpr
[rB(ctx
->opcode
)]);
4812 #endif /* defined(TARGET_PPC64) */
4814 /*** Lookaside buffer management ***/
4815 /* Optional & supervisor only: */
4818 static void gen_tlbia(DisasContext
*ctx
)
4820 #if defined(CONFIG_USER_ONLY)
4821 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4823 if (unlikely(ctx
->pr
)) {
4824 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4827 gen_helper_tlbia(cpu_env
);
4832 static void gen_tlbiel(DisasContext
*ctx
)
4834 #if defined(CONFIG_USER_ONLY)
4835 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4837 if (unlikely(ctx
->pr
)) {
4838 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4841 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4846 static void gen_tlbie(DisasContext
*ctx
)
4848 #if defined(CONFIG_USER_ONLY)
4849 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4851 if (unlikely(ctx
->pr
)) {
4852 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4855 if (NARROW_MODE(ctx
)) {
4856 TCGv t0
= tcg_temp_new();
4857 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4858 gen_helper_tlbie(cpu_env
, t0
);
4861 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4867 static void gen_tlbsync(DisasContext
*ctx
)
4869 #if defined(CONFIG_USER_ONLY)
4870 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4872 if (unlikely(ctx
->pr
)) {
4873 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4876 /* This has no effect: it should ensure that all previous
4877 * tlbie have completed
4879 gen_stop_exception(ctx
);
4883 #if defined(TARGET_PPC64)
4885 static void gen_slbia(DisasContext
*ctx
)
4887 #if defined(CONFIG_USER_ONLY)
4888 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4890 if (unlikely(ctx
->pr
)) {
4891 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4894 gen_helper_slbia(cpu_env
);
4899 static void gen_slbie(DisasContext
*ctx
)
4901 #if defined(CONFIG_USER_ONLY)
4902 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4904 if (unlikely(ctx
->pr
)) {
4905 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4908 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4913 /*** External control ***/
4917 static void gen_eciwx(DisasContext
*ctx
)
4920 /* Should check EAR[E] ! */
4921 gen_set_access_type(ctx
, ACCESS_EXT
);
4922 t0
= tcg_temp_new();
4923 gen_addr_reg_index(ctx
, t0
);
4924 gen_check_align(ctx
, t0
, 0x03);
4925 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4930 static void gen_ecowx(DisasContext
*ctx
)
4933 /* Should check EAR[E] ! */
4934 gen_set_access_type(ctx
, ACCESS_EXT
);
4935 t0
= tcg_temp_new();
4936 gen_addr_reg_index(ctx
, t0
);
4937 gen_check_align(ctx
, t0
, 0x03);
4938 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4942 /* PowerPC 601 specific instructions */
4945 static void gen_abs(DisasContext
*ctx
)
4947 TCGLabel
*l1
= gen_new_label();
4948 TCGLabel
*l2
= gen_new_label();
4949 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4950 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4953 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4955 if (unlikely(Rc(ctx
->opcode
) != 0))
4956 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4960 static void gen_abso(DisasContext
*ctx
)
4962 TCGLabel
*l1
= gen_new_label();
4963 TCGLabel
*l2
= gen_new_label();
4964 TCGLabel
*l3
= gen_new_label();
4965 /* Start with XER OV disabled, the most likely case */
4966 tcg_gen_movi_tl(cpu_ov
, 0);
4967 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4968 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4969 tcg_gen_movi_tl(cpu_ov
, 1);
4970 tcg_gen_movi_tl(cpu_so
, 1);
4973 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4976 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4978 if (unlikely(Rc(ctx
->opcode
) != 0))
4979 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4983 static void gen_clcs(DisasContext
*ctx
)
4985 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4986 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4987 tcg_temp_free_i32(t0
);
4988 /* Rc=1 sets CR0 to an undefined state */
4992 static void gen_div(DisasContext
*ctx
)
4994 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4995 cpu_gpr
[rB(ctx
->opcode
)]);
4996 if (unlikely(Rc(ctx
->opcode
) != 0))
4997 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5001 static void gen_divo(DisasContext
*ctx
)
5003 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5004 cpu_gpr
[rB(ctx
->opcode
)]);
5005 if (unlikely(Rc(ctx
->opcode
) != 0))
5006 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5010 static void gen_divs(DisasContext
*ctx
)
5012 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5013 cpu_gpr
[rB(ctx
->opcode
)]);
5014 if (unlikely(Rc(ctx
->opcode
) != 0))
5015 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5018 /* divso - divso. */
5019 static void gen_divso(DisasContext
*ctx
)
5021 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5022 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5023 if (unlikely(Rc(ctx
->opcode
) != 0))
5024 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5028 static void gen_doz(DisasContext
*ctx
)
5030 TCGLabel
*l1
= gen_new_label();
5031 TCGLabel
*l2
= gen_new_label();
5032 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5033 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5036 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5038 if (unlikely(Rc(ctx
->opcode
) != 0))
5039 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5043 static void gen_dozo(DisasContext
*ctx
)
5045 TCGLabel
*l1
= gen_new_label();
5046 TCGLabel
*l2
= gen_new_label();
5047 TCGv t0
= tcg_temp_new();
5048 TCGv t1
= tcg_temp_new();
5049 TCGv t2
= tcg_temp_new();
5050 /* Start with XER OV disabled, the most likely case */
5051 tcg_gen_movi_tl(cpu_ov
, 0);
5052 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5053 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5054 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5055 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5056 tcg_gen_andc_tl(t1
, t1
, t2
);
5057 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5058 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5059 tcg_gen_movi_tl(cpu_ov
, 1);
5060 tcg_gen_movi_tl(cpu_so
, 1);
5063 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5068 if (unlikely(Rc(ctx
->opcode
) != 0))
5069 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5073 static void gen_dozi(DisasContext
*ctx
)
5075 target_long simm
= SIMM(ctx
->opcode
);
5076 TCGLabel
*l1
= gen_new_label();
5077 TCGLabel
*l2
= gen_new_label();
5078 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5079 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5082 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5084 if (unlikely(Rc(ctx
->opcode
) != 0))
5085 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5088 /* lscbx - lscbx. */
5089 static void gen_lscbx(DisasContext
*ctx
)
5091 TCGv t0
= tcg_temp_new();
5092 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5093 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5094 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5096 gen_addr_reg_index(ctx
, t0
);
5097 /* NIP cannot be restored if the memory exception comes from an helper */
5098 gen_update_nip(ctx
, ctx
->nip
- 4);
5099 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5100 tcg_temp_free_i32(t1
);
5101 tcg_temp_free_i32(t2
);
5102 tcg_temp_free_i32(t3
);
5103 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5104 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5105 if (unlikely(Rc(ctx
->opcode
) != 0))
5106 gen_set_Rc0(ctx
, t0
);
5110 /* maskg - maskg. */
5111 static void gen_maskg(DisasContext
*ctx
)
5113 TCGLabel
*l1
= gen_new_label();
5114 TCGv t0
= tcg_temp_new();
5115 TCGv t1
= tcg_temp_new();
5116 TCGv t2
= tcg_temp_new();
5117 TCGv t3
= tcg_temp_new();
5118 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5119 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5120 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5121 tcg_gen_addi_tl(t2
, t0
, 1);
5122 tcg_gen_shr_tl(t2
, t3
, t2
);
5123 tcg_gen_shr_tl(t3
, t3
, t1
);
5124 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5125 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5126 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5132 if (unlikely(Rc(ctx
->opcode
) != 0))
5133 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5136 /* maskir - maskir. */
5137 static void gen_maskir(DisasContext
*ctx
)
5139 TCGv t0
= tcg_temp_new();
5140 TCGv t1
= tcg_temp_new();
5141 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5142 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5143 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5146 if (unlikely(Rc(ctx
->opcode
) != 0))
5147 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5151 static void gen_mul(DisasContext
*ctx
)
5153 TCGv_i64 t0
= tcg_temp_new_i64();
5154 TCGv_i64 t1
= tcg_temp_new_i64();
5155 TCGv t2
= tcg_temp_new();
5156 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5157 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5158 tcg_gen_mul_i64(t0
, t0
, t1
);
5159 tcg_gen_trunc_i64_tl(t2
, t0
);
5160 gen_store_spr(SPR_MQ
, t2
);
5161 tcg_gen_shri_i64(t1
, t0
, 32);
5162 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5163 tcg_temp_free_i64(t0
);
5164 tcg_temp_free_i64(t1
);
5166 if (unlikely(Rc(ctx
->opcode
) != 0))
5167 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5171 static void gen_mulo(DisasContext
*ctx
)
5173 TCGLabel
*l1
= gen_new_label();
5174 TCGv_i64 t0
= tcg_temp_new_i64();
5175 TCGv_i64 t1
= tcg_temp_new_i64();
5176 TCGv t2
= tcg_temp_new();
5177 /* Start with XER OV disabled, the most likely case */
5178 tcg_gen_movi_tl(cpu_ov
, 0);
5179 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5180 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5181 tcg_gen_mul_i64(t0
, t0
, t1
);
5182 tcg_gen_trunc_i64_tl(t2
, t0
);
5183 gen_store_spr(SPR_MQ
, t2
);
5184 tcg_gen_shri_i64(t1
, t0
, 32);
5185 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5186 tcg_gen_ext32s_i64(t1
, t0
);
5187 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5188 tcg_gen_movi_tl(cpu_ov
, 1);
5189 tcg_gen_movi_tl(cpu_so
, 1);
5191 tcg_temp_free_i64(t0
);
5192 tcg_temp_free_i64(t1
);
5194 if (unlikely(Rc(ctx
->opcode
) != 0))
5195 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5199 static void gen_nabs(DisasContext
*ctx
)
5201 TCGLabel
*l1
= gen_new_label();
5202 TCGLabel
*l2
= gen_new_label();
5203 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5204 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5207 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5209 if (unlikely(Rc(ctx
->opcode
) != 0))
5210 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5213 /* nabso - nabso. */
5214 static void gen_nabso(DisasContext
*ctx
)
5216 TCGLabel
*l1
= gen_new_label();
5217 TCGLabel
*l2
= gen_new_label();
5218 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5219 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5222 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5224 /* nabs never overflows */
5225 tcg_gen_movi_tl(cpu_ov
, 0);
5226 if (unlikely(Rc(ctx
->opcode
) != 0))
5227 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5231 static void gen_rlmi(DisasContext
*ctx
)
5233 uint32_t mb
= MB(ctx
->opcode
);
5234 uint32_t me
= ME(ctx
->opcode
);
5235 TCGv t0
= tcg_temp_new();
5236 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5237 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5238 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5239 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5240 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5242 if (unlikely(Rc(ctx
->opcode
) != 0))
5243 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5247 static void gen_rrib(DisasContext
*ctx
)
5249 TCGv t0
= tcg_temp_new();
5250 TCGv t1
= tcg_temp_new();
5251 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5252 tcg_gen_movi_tl(t1
, 0x80000000);
5253 tcg_gen_shr_tl(t1
, t1
, t0
);
5254 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5255 tcg_gen_and_tl(t0
, t0
, t1
);
5256 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5257 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5260 if (unlikely(Rc(ctx
->opcode
) != 0))
5261 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5265 static void gen_sle(DisasContext
*ctx
)
5267 TCGv t0
= tcg_temp_new();
5268 TCGv t1
= tcg_temp_new();
5269 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5270 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5271 tcg_gen_subfi_tl(t1
, 32, t1
);
5272 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5273 tcg_gen_or_tl(t1
, t0
, t1
);
5274 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5275 gen_store_spr(SPR_MQ
, t1
);
5278 if (unlikely(Rc(ctx
->opcode
) != 0))
5279 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5283 static void gen_sleq(DisasContext
*ctx
)
5285 TCGv t0
= tcg_temp_new();
5286 TCGv t1
= tcg_temp_new();
5287 TCGv t2
= tcg_temp_new();
5288 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5289 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5290 tcg_gen_shl_tl(t2
, t2
, t0
);
5291 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5292 gen_load_spr(t1
, SPR_MQ
);
5293 gen_store_spr(SPR_MQ
, t0
);
5294 tcg_gen_and_tl(t0
, t0
, t2
);
5295 tcg_gen_andc_tl(t1
, t1
, t2
);
5296 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5300 if (unlikely(Rc(ctx
->opcode
) != 0))
5301 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5305 static void gen_sliq(DisasContext
*ctx
)
5307 int sh
= SH(ctx
->opcode
);
5308 TCGv t0
= tcg_temp_new();
5309 TCGv t1
= tcg_temp_new();
5310 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5311 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5312 tcg_gen_or_tl(t1
, t0
, t1
);
5313 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5314 gen_store_spr(SPR_MQ
, t1
);
5317 if (unlikely(Rc(ctx
->opcode
) != 0))
5318 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5321 /* slliq - slliq. */
5322 static void gen_slliq(DisasContext
*ctx
)
5324 int sh
= SH(ctx
->opcode
);
5325 TCGv t0
= tcg_temp_new();
5326 TCGv t1
= tcg_temp_new();
5327 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5328 gen_load_spr(t1
, SPR_MQ
);
5329 gen_store_spr(SPR_MQ
, t0
);
5330 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5331 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5332 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5335 if (unlikely(Rc(ctx
->opcode
) != 0))
5336 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5340 static void gen_sllq(DisasContext
*ctx
)
5342 TCGLabel
*l1
= gen_new_label();
5343 TCGLabel
*l2
= gen_new_label();
5344 TCGv t0
= tcg_temp_local_new();
5345 TCGv t1
= tcg_temp_local_new();
5346 TCGv t2
= tcg_temp_local_new();
5347 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5348 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5349 tcg_gen_shl_tl(t1
, t1
, t2
);
5350 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5351 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5352 gen_load_spr(t0
, SPR_MQ
);
5353 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5356 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5357 gen_load_spr(t2
, SPR_MQ
);
5358 tcg_gen_andc_tl(t1
, t2
, t1
);
5359 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5364 if (unlikely(Rc(ctx
->opcode
) != 0))
5365 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5369 static void gen_slq(DisasContext
*ctx
)
5371 TCGLabel
*l1
= gen_new_label();
5372 TCGv t0
= tcg_temp_new();
5373 TCGv t1
= tcg_temp_new();
5374 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5375 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5376 tcg_gen_subfi_tl(t1
, 32, t1
);
5377 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5378 tcg_gen_or_tl(t1
, t0
, t1
);
5379 gen_store_spr(SPR_MQ
, t1
);
5380 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5381 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5382 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5383 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5387 if (unlikely(Rc(ctx
->opcode
) != 0))
5388 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5391 /* sraiq - sraiq. */
5392 static void gen_sraiq(DisasContext
*ctx
)
5394 int sh
= SH(ctx
->opcode
);
5395 TCGLabel
*l1
= gen_new_label();
5396 TCGv t0
= tcg_temp_new();
5397 TCGv t1
= tcg_temp_new();
5398 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5399 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5400 tcg_gen_or_tl(t0
, t0
, t1
);
5401 gen_store_spr(SPR_MQ
, t0
);
5402 tcg_gen_movi_tl(cpu_ca
, 0);
5403 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5404 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5405 tcg_gen_movi_tl(cpu_ca
, 1);
5407 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5410 if (unlikely(Rc(ctx
->opcode
) != 0))
5411 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5415 static void gen_sraq(DisasContext
*ctx
)
5417 TCGLabel
*l1
= gen_new_label();
5418 TCGLabel
*l2
= gen_new_label();
5419 TCGv t0
= tcg_temp_new();
5420 TCGv t1
= tcg_temp_local_new();
5421 TCGv t2
= tcg_temp_local_new();
5422 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5423 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5424 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5425 tcg_gen_subfi_tl(t2
, 32, t2
);
5426 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5427 tcg_gen_or_tl(t0
, t0
, t2
);
5428 gen_store_spr(SPR_MQ
, t0
);
5429 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5430 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5431 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5432 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5435 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5436 tcg_gen_movi_tl(cpu_ca
, 0);
5437 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5438 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5439 tcg_gen_movi_tl(cpu_ca
, 1);
5443 if (unlikely(Rc(ctx
->opcode
) != 0))
5444 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5448 static void gen_sre(DisasContext
*ctx
)
5450 TCGv t0
= tcg_temp_new();
5451 TCGv t1
= tcg_temp_new();
5452 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5453 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5454 tcg_gen_subfi_tl(t1
, 32, t1
);
5455 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5456 tcg_gen_or_tl(t1
, t0
, t1
);
5457 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5458 gen_store_spr(SPR_MQ
, t1
);
5461 if (unlikely(Rc(ctx
->opcode
) != 0))
5462 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5466 static void gen_srea(DisasContext
*ctx
)
5468 TCGv t0
= tcg_temp_new();
5469 TCGv t1
= tcg_temp_new();
5470 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5471 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5472 gen_store_spr(SPR_MQ
, t0
);
5473 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5476 if (unlikely(Rc(ctx
->opcode
) != 0))
5477 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5481 static void gen_sreq(DisasContext
*ctx
)
5483 TCGv t0
= tcg_temp_new();
5484 TCGv t1
= tcg_temp_new();
5485 TCGv t2
= tcg_temp_new();
5486 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5487 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5488 tcg_gen_shr_tl(t1
, t1
, t0
);
5489 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5490 gen_load_spr(t2
, SPR_MQ
);
5491 gen_store_spr(SPR_MQ
, t0
);
5492 tcg_gen_and_tl(t0
, t0
, t1
);
5493 tcg_gen_andc_tl(t2
, t2
, t1
);
5494 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5498 if (unlikely(Rc(ctx
->opcode
) != 0))
5499 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5503 static void gen_sriq(DisasContext
*ctx
)
5505 int sh
= SH(ctx
->opcode
);
5506 TCGv t0
= tcg_temp_new();
5507 TCGv t1
= tcg_temp_new();
5508 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5509 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5510 tcg_gen_or_tl(t1
, t0
, t1
);
5511 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5512 gen_store_spr(SPR_MQ
, t1
);
5515 if (unlikely(Rc(ctx
->opcode
) != 0))
5516 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5520 static void gen_srliq(DisasContext
*ctx
)
5522 int sh
= SH(ctx
->opcode
);
5523 TCGv t0
= tcg_temp_new();
5524 TCGv t1
= tcg_temp_new();
5525 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5526 gen_load_spr(t1
, SPR_MQ
);
5527 gen_store_spr(SPR_MQ
, t0
);
5528 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5529 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5530 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5533 if (unlikely(Rc(ctx
->opcode
) != 0))
5534 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5538 static void gen_srlq(DisasContext
*ctx
)
5540 TCGLabel
*l1
= gen_new_label();
5541 TCGLabel
*l2
= gen_new_label();
5542 TCGv t0
= tcg_temp_local_new();
5543 TCGv t1
= tcg_temp_local_new();
5544 TCGv t2
= tcg_temp_local_new();
5545 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5546 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5547 tcg_gen_shr_tl(t2
, t1
, t2
);
5548 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5549 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5550 gen_load_spr(t0
, SPR_MQ
);
5551 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5554 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5555 tcg_gen_and_tl(t0
, t0
, t2
);
5556 gen_load_spr(t1
, SPR_MQ
);
5557 tcg_gen_andc_tl(t1
, t1
, t2
);
5558 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5563 if (unlikely(Rc(ctx
->opcode
) != 0))
5564 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5568 static void gen_srq(DisasContext
*ctx
)
5570 TCGLabel
*l1
= gen_new_label();
5571 TCGv t0
= tcg_temp_new();
5572 TCGv t1
= tcg_temp_new();
5573 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5574 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5575 tcg_gen_subfi_tl(t1
, 32, t1
);
5576 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5577 tcg_gen_or_tl(t1
, t0
, t1
);
5578 gen_store_spr(SPR_MQ
, t1
);
5579 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5580 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5581 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5582 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5586 if (unlikely(Rc(ctx
->opcode
) != 0))
5587 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5590 /* PowerPC 602 specific instructions */
5593 static void gen_dsa(DisasContext
*ctx
)
5596 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5600 static void gen_esa(DisasContext
*ctx
)
5603 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5607 static void gen_mfrom(DisasContext
*ctx
)
5609 #if defined(CONFIG_USER_ONLY)
5610 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5612 if (unlikely(ctx
->pr
)) {
5613 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5616 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5620 /* 602 - 603 - G2 TLB management */
5623 static void gen_tlbld_6xx(DisasContext
*ctx
)
5625 #if defined(CONFIG_USER_ONLY)
5626 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5628 if (unlikely(ctx
->pr
)) {
5629 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5632 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5637 static void gen_tlbli_6xx(DisasContext
*ctx
)
5639 #if defined(CONFIG_USER_ONLY)
5640 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5642 if (unlikely(ctx
->pr
)) {
5643 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5646 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5650 /* 74xx TLB management */
5653 static void gen_tlbld_74xx(DisasContext
*ctx
)
5655 #if defined(CONFIG_USER_ONLY)
5656 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5658 if (unlikely(ctx
->pr
)) {
5659 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5662 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5667 static void gen_tlbli_74xx(DisasContext
*ctx
)
5669 #if defined(CONFIG_USER_ONLY)
5670 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5672 if (unlikely(ctx
->pr
)) {
5673 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5676 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5680 /* POWER instructions not in PowerPC 601 */
5683 static void gen_clf(DisasContext
*ctx
)
5685 /* Cache line flush: implemented as no-op */
5689 static void gen_cli(DisasContext
*ctx
)
5691 /* Cache line invalidate: privileged and treated as no-op */
5692 #if defined(CONFIG_USER_ONLY)
5693 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5695 if (unlikely(ctx
->pr
)) {
5696 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5703 static void gen_dclst(DisasContext
*ctx
)
5705 /* Data cache line store: treated as no-op */
5708 static void gen_mfsri(DisasContext
*ctx
)
5710 #if defined(CONFIG_USER_ONLY)
5711 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5713 int ra
= rA(ctx
->opcode
);
5714 int rd
= rD(ctx
->opcode
);
5716 if (unlikely(ctx
->pr
)) {
5717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5720 t0
= tcg_temp_new();
5721 gen_addr_reg_index(ctx
, t0
);
5722 tcg_gen_shri_tl(t0
, t0
, 28);
5723 tcg_gen_andi_tl(t0
, t0
, 0xF);
5724 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5726 if (ra
!= 0 && ra
!= rd
)
5727 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5731 static void gen_rac(DisasContext
*ctx
)
5733 #if defined(CONFIG_USER_ONLY)
5734 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5737 if (unlikely(ctx
->pr
)) {
5738 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5741 t0
= tcg_temp_new();
5742 gen_addr_reg_index(ctx
, t0
);
5743 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5748 static void gen_rfsvc(DisasContext
*ctx
)
5750 #if defined(CONFIG_USER_ONLY)
5751 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5753 if (unlikely(ctx
->pr
)) {
5754 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5757 gen_helper_rfsvc(cpu_env
);
5758 gen_sync_exception(ctx
);
5762 /* svc is not implemented for now */
5764 /* POWER2 specific instructions */
5765 /* Quad manipulation (load/store two floats at a time) */
5768 static void gen_lfq(DisasContext
*ctx
)
5770 int rd
= rD(ctx
->opcode
);
5772 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5773 t0
= tcg_temp_new();
5774 gen_addr_imm_index(ctx
, t0
, 0);
5775 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5776 gen_addr_add(ctx
, t0
, t0
, 8);
5777 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5782 static void gen_lfqu(DisasContext
*ctx
)
5784 int ra
= rA(ctx
->opcode
);
5785 int rd
= rD(ctx
->opcode
);
5787 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5788 t0
= tcg_temp_new();
5789 t1
= tcg_temp_new();
5790 gen_addr_imm_index(ctx
, t0
, 0);
5791 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5792 gen_addr_add(ctx
, t1
, t0
, 8);
5793 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5795 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5801 static void gen_lfqux(DisasContext
*ctx
)
5803 int ra
= rA(ctx
->opcode
);
5804 int rd
= rD(ctx
->opcode
);
5805 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5807 t0
= tcg_temp_new();
5808 gen_addr_reg_index(ctx
, t0
);
5809 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5810 t1
= tcg_temp_new();
5811 gen_addr_add(ctx
, t1
, t0
, 8);
5812 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5815 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5820 static void gen_lfqx(DisasContext
*ctx
)
5822 int rd
= rD(ctx
->opcode
);
5824 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5825 t0
= tcg_temp_new();
5826 gen_addr_reg_index(ctx
, t0
);
5827 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5828 gen_addr_add(ctx
, t0
, t0
, 8);
5829 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5834 static void gen_stfq(DisasContext
*ctx
)
5836 int rd
= rD(ctx
->opcode
);
5838 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5839 t0
= tcg_temp_new();
5840 gen_addr_imm_index(ctx
, t0
, 0);
5841 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5842 gen_addr_add(ctx
, t0
, t0
, 8);
5843 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5848 static void gen_stfqu(DisasContext
*ctx
)
5850 int ra
= rA(ctx
->opcode
);
5851 int rd
= rD(ctx
->opcode
);
5853 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5854 t0
= tcg_temp_new();
5855 gen_addr_imm_index(ctx
, t0
, 0);
5856 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5857 t1
= tcg_temp_new();
5858 gen_addr_add(ctx
, t1
, t0
, 8);
5859 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5862 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5867 static void gen_stfqux(DisasContext
*ctx
)
5869 int ra
= rA(ctx
->opcode
);
5870 int rd
= rD(ctx
->opcode
);
5872 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5873 t0
= tcg_temp_new();
5874 gen_addr_reg_index(ctx
, t0
);
5875 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5876 t1
= tcg_temp_new();
5877 gen_addr_add(ctx
, t1
, t0
, 8);
5878 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5881 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5886 static void gen_stfqx(DisasContext
*ctx
)
5888 int rd
= rD(ctx
->opcode
);
5890 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5891 t0
= tcg_temp_new();
5892 gen_addr_reg_index(ctx
, t0
);
5893 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5894 gen_addr_add(ctx
, t0
, t0
, 8);
5895 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5899 /* BookE specific instructions */
5901 /* XXX: not implemented on 440 ? */
5902 static void gen_mfapidi(DisasContext
*ctx
)
5905 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5908 /* XXX: not implemented on 440 ? */
5909 static void gen_tlbiva(DisasContext
*ctx
)
5911 #if defined(CONFIG_USER_ONLY)
5912 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5915 if (unlikely(ctx
->pr
)) {
5916 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5919 t0
= tcg_temp_new();
5920 gen_addr_reg_index(ctx
, t0
);
5921 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5926 /* All 405 MAC instructions are translated here */
5927 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5928 int ra
, int rb
, int rt
, int Rc
)
5932 t0
= tcg_temp_local_new();
5933 t1
= tcg_temp_local_new();
5935 switch (opc3
& 0x0D) {
5937 /* macchw - macchw. - macchwo - macchwo. */
5938 /* macchws - macchws. - macchwso - macchwso. */
5939 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5940 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5941 /* mulchw - mulchw. */
5942 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5943 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5944 tcg_gen_ext16s_tl(t1
, t1
);
5947 /* macchwu - macchwu. - macchwuo - macchwuo. */
5948 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5949 /* mulchwu - mulchwu. */
5950 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5951 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5952 tcg_gen_ext16u_tl(t1
, t1
);
5955 /* machhw - machhw. - machhwo - machhwo. */
5956 /* machhws - machhws. - machhwso - machhwso. */
5957 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5958 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5959 /* mulhhw - mulhhw. */
5960 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5961 tcg_gen_ext16s_tl(t0
, t0
);
5962 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5963 tcg_gen_ext16s_tl(t1
, t1
);
5966 /* machhwu - machhwu. - machhwuo - machhwuo. */
5967 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5968 /* mulhhwu - mulhhwu. */
5969 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5970 tcg_gen_ext16u_tl(t0
, t0
);
5971 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5972 tcg_gen_ext16u_tl(t1
, t1
);
5975 /* maclhw - maclhw. - maclhwo - maclhwo. */
5976 /* maclhws - maclhws. - maclhwso - maclhwso. */
5977 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5978 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5979 /* mullhw - mullhw. */
5980 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5981 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5984 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5985 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5986 /* mullhwu - mullhwu. */
5987 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5988 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5992 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5993 tcg_gen_mul_tl(t1
, t0
, t1
);
5995 /* nmultiply-and-accumulate (0x0E) */
5996 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5998 /* multiply-and-accumulate (0x0C) */
5999 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6003 /* Check overflow and/or saturate */
6004 TCGLabel
*l1
= gen_new_label();
6007 /* Start with XER OV disabled, the most likely case */
6008 tcg_gen_movi_tl(cpu_ov
, 0);
6012 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6013 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6014 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6015 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6018 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6019 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6023 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6026 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6030 /* Check overflow */
6031 tcg_gen_movi_tl(cpu_ov
, 1);
6032 tcg_gen_movi_tl(cpu_so
, 1);
6035 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6038 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6042 if (unlikely(Rc
) != 0) {
6044 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6048 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6049 static void glue(gen_, name)(DisasContext *ctx) \
6051 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6052 rD(ctx->opcode), Rc(ctx->opcode)); \
6055 /* macchw - macchw. */
6056 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6057 /* macchwo - macchwo. */
6058 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6059 /* macchws - macchws. */
6060 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6061 /* macchwso - macchwso. */
6062 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6063 /* macchwsu - macchwsu. */
6064 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6065 /* macchwsuo - macchwsuo. */
6066 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6067 /* macchwu - macchwu. */
6068 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6069 /* macchwuo - macchwuo. */
6070 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6071 /* machhw - machhw. */
6072 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6073 /* machhwo - machhwo. */
6074 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6075 /* machhws - machhws. */
6076 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6077 /* machhwso - machhwso. */
6078 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6079 /* machhwsu - machhwsu. */
6080 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6081 /* machhwsuo - machhwsuo. */
6082 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6083 /* machhwu - machhwu. */
6084 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6085 /* machhwuo - machhwuo. */
6086 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6087 /* maclhw - maclhw. */
6088 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6089 /* maclhwo - maclhwo. */
6090 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6091 /* maclhws - maclhws. */
6092 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6093 /* maclhwso - maclhwso. */
6094 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6095 /* maclhwu - maclhwu. */
6096 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6097 /* maclhwuo - maclhwuo. */
6098 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6099 /* maclhwsu - maclhwsu. */
6100 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6101 /* maclhwsuo - maclhwsuo. */
6102 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6103 /* nmacchw - nmacchw. */
6104 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6105 /* nmacchwo - nmacchwo. */
6106 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6107 /* nmacchws - nmacchws. */
6108 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6109 /* nmacchwso - nmacchwso. */
6110 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6111 /* nmachhw - nmachhw. */
6112 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6113 /* nmachhwo - nmachhwo. */
6114 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6115 /* nmachhws - nmachhws. */
6116 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6117 /* nmachhwso - nmachhwso. */
6118 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6119 /* nmaclhw - nmaclhw. */
6120 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6121 /* nmaclhwo - nmaclhwo. */
6122 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6123 /* nmaclhws - nmaclhws. */
6124 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6125 /* nmaclhwso - nmaclhwso. */
6126 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6128 /* mulchw - mulchw. */
6129 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6130 /* mulchwu - mulchwu. */
6131 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6132 /* mulhhw - mulhhw. */
6133 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6134 /* mulhhwu - mulhhwu. */
6135 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6136 /* mullhw - mullhw. */
6137 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6138 /* mullhwu - mullhwu. */
6139 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6142 static void gen_mfdcr(DisasContext
*ctx
)
6144 #if defined(CONFIG_USER_ONLY)
6145 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6148 if (unlikely(ctx
->pr
)) {
6149 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6152 /* NIP cannot be restored if the memory exception comes from an helper */
6153 gen_update_nip(ctx
, ctx
->nip
- 4);
6154 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6155 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6156 tcg_temp_free(dcrn
);
6161 static void gen_mtdcr(DisasContext
*ctx
)
6163 #if defined(CONFIG_USER_ONLY)
6164 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6167 if (unlikely(ctx
->pr
)) {
6168 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6171 /* NIP cannot be restored if the memory exception comes from an helper */
6172 gen_update_nip(ctx
, ctx
->nip
- 4);
6173 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6174 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6175 tcg_temp_free(dcrn
);
6180 /* XXX: not implemented on 440 ? */
6181 static void gen_mfdcrx(DisasContext
*ctx
)
6183 #if defined(CONFIG_USER_ONLY)
6184 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6186 if (unlikely(ctx
->pr
)) {
6187 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6190 /* NIP cannot be restored if the memory exception comes from an helper */
6191 gen_update_nip(ctx
, ctx
->nip
- 4);
6192 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6193 cpu_gpr
[rA(ctx
->opcode
)]);
6194 /* Note: Rc update flag set leads to undefined state of Rc0 */
6199 /* XXX: not implemented on 440 ? */
6200 static void gen_mtdcrx(DisasContext
*ctx
)
6202 #if defined(CONFIG_USER_ONLY)
6203 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6205 if (unlikely(ctx
->pr
)) {
6206 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6209 /* NIP cannot be restored if the memory exception comes from an helper */
6210 gen_update_nip(ctx
, ctx
->nip
- 4);
6211 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6212 cpu_gpr
[rS(ctx
->opcode
)]);
6213 /* Note: Rc update flag set leads to undefined state of Rc0 */
6217 /* mfdcrux (PPC 460) : user-mode access to DCR */
6218 static void gen_mfdcrux(DisasContext
*ctx
)
6220 /* NIP cannot be restored if the memory exception comes from an helper */
6221 gen_update_nip(ctx
, ctx
->nip
- 4);
6222 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6223 cpu_gpr
[rA(ctx
->opcode
)]);
6224 /* Note: Rc update flag set leads to undefined state of Rc0 */
6227 /* mtdcrux (PPC 460) : user-mode access to DCR */
6228 static void gen_mtdcrux(DisasContext
*ctx
)
6230 /* NIP cannot be restored if the memory exception comes from an helper */
6231 gen_update_nip(ctx
, ctx
->nip
- 4);
6232 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6233 cpu_gpr
[rS(ctx
->opcode
)]);
6234 /* Note: Rc update flag set leads to undefined state of Rc0 */
6238 static void gen_dccci(DisasContext
*ctx
)
6240 #if defined(CONFIG_USER_ONLY)
6241 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6243 if (unlikely(ctx
->pr
)) {
6244 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6247 /* interpreted as no-op */
6252 static void gen_dcread(DisasContext
*ctx
)
6254 #if defined(CONFIG_USER_ONLY)
6255 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6258 if (unlikely(ctx
->pr
)) {
6259 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6262 gen_set_access_type(ctx
, ACCESS_CACHE
);
6263 EA
= tcg_temp_new();
6264 gen_addr_reg_index(ctx
, EA
);
6265 val
= tcg_temp_new();
6266 gen_qemu_ld32u(ctx
, val
, EA
);
6268 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6274 static void gen_icbt_40x(DisasContext
*ctx
)
6276 /* interpreted as no-op */
6277 /* XXX: specification say this is treated as a load by the MMU
6278 * but does not generate any exception
6283 static void gen_iccci(DisasContext
*ctx
)
6285 #if defined(CONFIG_USER_ONLY)
6286 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6288 if (unlikely(ctx
->pr
)) {
6289 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6292 /* interpreted as no-op */
6297 static void gen_icread(DisasContext
*ctx
)
6299 #if defined(CONFIG_USER_ONLY)
6300 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6302 if (unlikely(ctx
->pr
)) {
6303 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6306 /* interpreted as no-op */
6310 /* rfci (supervisor only) */
6311 static void gen_rfci_40x(DisasContext
*ctx
)
6313 #if defined(CONFIG_USER_ONLY)
6314 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6316 if (unlikely(ctx
->pr
)) {
6317 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6320 /* Restore CPU state */
6321 gen_helper_40x_rfci(cpu_env
);
6322 gen_sync_exception(ctx
);
6326 static void gen_rfci(DisasContext
*ctx
)
6328 #if defined(CONFIG_USER_ONLY)
6329 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6331 if (unlikely(ctx
->pr
)) {
6332 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6335 /* Restore CPU state */
6336 gen_helper_rfci(cpu_env
);
6337 gen_sync_exception(ctx
);
6341 /* BookE specific */
6343 /* XXX: not implemented on 440 ? */
6344 static void gen_rfdi(DisasContext
*ctx
)
6346 #if defined(CONFIG_USER_ONLY)
6347 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6349 if (unlikely(ctx
->pr
)) {
6350 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6353 /* Restore CPU state */
6354 gen_helper_rfdi(cpu_env
);
6355 gen_sync_exception(ctx
);
6359 /* XXX: not implemented on 440 ? */
6360 static void gen_rfmci(DisasContext
*ctx
)
6362 #if defined(CONFIG_USER_ONLY)
6363 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6365 if (unlikely(ctx
->pr
)) {
6366 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6369 /* Restore CPU state */
6370 gen_helper_rfmci(cpu_env
);
6371 gen_sync_exception(ctx
);
6375 /* TLB management - PowerPC 405 implementation */
6378 static void gen_tlbre_40x(DisasContext
*ctx
)
6380 #if defined(CONFIG_USER_ONLY)
6381 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6383 if (unlikely(ctx
->pr
)) {
6384 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6387 switch (rB(ctx
->opcode
)) {
6389 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6390 cpu_gpr
[rA(ctx
->opcode
)]);
6393 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6394 cpu_gpr
[rA(ctx
->opcode
)]);
6397 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6403 /* tlbsx - tlbsx. */
6404 static void gen_tlbsx_40x(DisasContext
*ctx
)
6406 #if defined(CONFIG_USER_ONLY)
6407 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6410 if (unlikely(ctx
->pr
)) {
6411 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6414 t0
= tcg_temp_new();
6415 gen_addr_reg_index(ctx
, t0
);
6416 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6418 if (Rc(ctx
->opcode
)) {
6419 TCGLabel
*l1
= gen_new_label();
6420 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6421 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6422 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6429 static void gen_tlbwe_40x(DisasContext
*ctx
)
6431 #if defined(CONFIG_USER_ONLY)
6432 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6434 if (unlikely(ctx
->pr
)) {
6435 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6438 switch (rB(ctx
->opcode
)) {
6440 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6441 cpu_gpr
[rS(ctx
->opcode
)]);
6444 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6445 cpu_gpr
[rS(ctx
->opcode
)]);
6448 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6454 /* TLB management - PowerPC 440 implementation */
6457 static void gen_tlbre_440(DisasContext
*ctx
)
6459 #if defined(CONFIG_USER_ONLY)
6460 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6462 if (unlikely(ctx
->pr
)) {
6463 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6466 switch (rB(ctx
->opcode
)) {
6471 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6472 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6473 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6474 tcg_temp_free_i32(t0
);
6478 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6484 /* tlbsx - tlbsx. */
6485 static void gen_tlbsx_440(DisasContext
*ctx
)
6487 #if defined(CONFIG_USER_ONLY)
6488 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6491 if (unlikely(ctx
->pr
)) {
6492 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6495 t0
= tcg_temp_new();
6496 gen_addr_reg_index(ctx
, t0
);
6497 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6499 if (Rc(ctx
->opcode
)) {
6500 TCGLabel
*l1
= gen_new_label();
6501 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6502 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6503 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6510 static void gen_tlbwe_440(DisasContext
*ctx
)
6512 #if defined(CONFIG_USER_ONLY)
6513 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6515 if (unlikely(ctx
->pr
)) {
6516 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6519 switch (rB(ctx
->opcode
)) {
6524 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6525 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6526 cpu_gpr
[rS(ctx
->opcode
)]);
6527 tcg_temp_free_i32(t0
);
6531 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6537 /* TLB management - PowerPC BookE 2.06 implementation */
6540 static void gen_tlbre_booke206(DisasContext
*ctx
)
6542 #if defined(CONFIG_USER_ONLY)
6543 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6545 if (unlikely(ctx
->pr
)) {
6546 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6550 gen_helper_booke206_tlbre(cpu_env
);
6554 /* tlbsx - tlbsx. */
6555 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6557 #if defined(CONFIG_USER_ONLY)
6558 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6561 if (unlikely(ctx
->pr
)) {
6562 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6566 if (rA(ctx
->opcode
)) {
6567 t0
= tcg_temp_new();
6568 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6570 t0
= tcg_const_tl(0);
6573 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6574 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6580 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6582 #if defined(CONFIG_USER_ONLY)
6583 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6585 if (unlikely(ctx
->pr
)) {
6586 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6589 gen_update_nip(ctx
, ctx
->nip
- 4);
6590 gen_helper_booke206_tlbwe(cpu_env
);
6594 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6596 #if defined(CONFIG_USER_ONLY)
6597 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6600 if (unlikely(ctx
->pr
)) {
6601 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6605 t0
= tcg_temp_new();
6606 gen_addr_reg_index(ctx
, t0
);
6608 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6613 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6615 #if defined(CONFIG_USER_ONLY)
6616 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6619 if (unlikely(ctx
->pr
)) {
6620 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6624 t0
= tcg_temp_new();
6625 gen_addr_reg_index(ctx
, t0
);
6627 switch((ctx
->opcode
>> 21) & 0x3) {
6629 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6632 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6635 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6638 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6648 static void gen_wrtee(DisasContext
*ctx
)
6650 #if defined(CONFIG_USER_ONLY)
6651 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6654 if (unlikely(ctx
->pr
)) {
6655 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6658 t0
= tcg_temp_new();
6659 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6660 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6661 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6663 /* Stop translation to have a chance to raise an exception
6664 * if we just set msr_ee to 1
6666 gen_stop_exception(ctx
);
6671 static void gen_wrteei(DisasContext
*ctx
)
6673 #if defined(CONFIG_USER_ONLY)
6674 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6676 if (unlikely(ctx
->pr
)) {
6677 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6680 if (ctx
->opcode
& 0x00008000) {
6681 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6682 /* Stop translation to have a chance to raise an exception */
6683 gen_stop_exception(ctx
);
6685 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6690 /* PowerPC 440 specific instructions */
6693 static void gen_dlmzb(DisasContext
*ctx
)
6695 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6696 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6697 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6698 tcg_temp_free_i32(t0
);
6701 /* mbar replaces eieio on 440 */
6702 static void gen_mbar(DisasContext
*ctx
)
6704 /* interpreted as no-op */
6707 /* msync replaces sync on 440 */
6708 static void gen_msync_4xx(DisasContext
*ctx
)
6710 /* interpreted as no-op */
6714 static void gen_icbt_440(DisasContext
*ctx
)
6716 /* interpreted as no-op */
6717 /* XXX: specification say this is treated as a load by the MMU
6718 * but does not generate any exception
6722 /* Embedded.Processor Control */
6724 static void gen_msgclr(DisasContext
*ctx
)
6726 #if defined(CONFIG_USER_ONLY)
6727 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6729 if (unlikely(ctx
->pr
)) {
6730 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6734 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6738 static void gen_msgsnd(DisasContext
*ctx
)
6740 #if defined(CONFIG_USER_ONLY)
6741 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6743 if (unlikely(ctx
->pr
)) {
6744 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6748 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6752 /*** Altivec vector extension ***/
6753 /* Altivec registers moves */
6755 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6757 TCGv_ptr r
= tcg_temp_new_ptr();
6758 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6762 #define GEN_VR_LDX(name, opc2, opc3) \
6763 static void glue(gen_, name)(DisasContext *ctx) \
6766 if (unlikely(!ctx->altivec_enabled)) { \
6767 gen_exception(ctx, POWERPC_EXCP_VPU); \
6770 gen_set_access_type(ctx, ACCESS_INT); \
6771 EA = tcg_temp_new(); \
6772 gen_addr_reg_index(ctx, EA); \
6773 tcg_gen_andi_tl(EA, EA, ~0xf); \
6774 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6775 64-bit byteswap already. */ \
6776 if (ctx->le_mode) { \
6777 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6778 tcg_gen_addi_tl(EA, EA, 8); \
6779 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6781 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6782 tcg_gen_addi_tl(EA, EA, 8); \
6783 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6785 tcg_temp_free(EA); \
6788 #define GEN_VR_STX(name, opc2, opc3) \
6789 static void gen_st##name(DisasContext *ctx) \
6792 if (unlikely(!ctx->altivec_enabled)) { \
6793 gen_exception(ctx, POWERPC_EXCP_VPU); \
6796 gen_set_access_type(ctx, ACCESS_INT); \
6797 EA = tcg_temp_new(); \
6798 gen_addr_reg_index(ctx, EA); \
6799 tcg_gen_andi_tl(EA, EA, ~0xf); \
6800 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6801 64-bit byteswap already. */ \
6802 if (ctx->le_mode) { \
6803 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6804 tcg_gen_addi_tl(EA, EA, 8); \
6805 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6807 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6808 tcg_gen_addi_tl(EA, EA, 8); \
6809 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6811 tcg_temp_free(EA); \
6814 #define GEN_VR_LVE(name, opc2, opc3, size) \
6815 static void gen_lve##name(DisasContext *ctx) \
6819 if (unlikely(!ctx->altivec_enabled)) { \
6820 gen_exception(ctx, POWERPC_EXCP_VPU); \
6823 gen_set_access_type(ctx, ACCESS_INT); \
6824 EA = tcg_temp_new(); \
6825 gen_addr_reg_index(ctx, EA); \
6827 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6829 rs = gen_avr_ptr(rS(ctx->opcode)); \
6830 gen_helper_lve##name(cpu_env, rs, EA); \
6831 tcg_temp_free(EA); \
6832 tcg_temp_free_ptr(rs); \
6835 #define GEN_VR_STVE(name, opc2, opc3, size) \
6836 static void gen_stve##name(DisasContext *ctx) \
6840 if (unlikely(!ctx->altivec_enabled)) { \
6841 gen_exception(ctx, POWERPC_EXCP_VPU); \
6844 gen_set_access_type(ctx, ACCESS_INT); \
6845 EA = tcg_temp_new(); \
6846 gen_addr_reg_index(ctx, EA); \
6848 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6850 rs = gen_avr_ptr(rS(ctx->opcode)); \
6851 gen_helper_stve##name(cpu_env, rs, EA); \
6852 tcg_temp_free(EA); \
6853 tcg_temp_free_ptr(rs); \
6856 GEN_VR_LDX(lvx
, 0x07, 0x03);
6857 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6858 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6860 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
6861 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
6862 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
6864 GEN_VR_STX(svx
, 0x07, 0x07);
6865 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6866 GEN_VR_STX(svxl
, 0x07, 0x0F);
6868 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
6869 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
6870 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
6872 static void gen_lvsl(DisasContext
*ctx
)
6876 if (unlikely(!ctx
->altivec_enabled
)) {
6877 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6880 EA
= tcg_temp_new();
6881 gen_addr_reg_index(ctx
, EA
);
6882 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6883 gen_helper_lvsl(rd
, EA
);
6885 tcg_temp_free_ptr(rd
);
6888 static void gen_lvsr(DisasContext
*ctx
)
6892 if (unlikely(!ctx
->altivec_enabled
)) {
6893 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6896 EA
= tcg_temp_new();
6897 gen_addr_reg_index(ctx
, EA
);
6898 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6899 gen_helper_lvsr(rd
, EA
);
6901 tcg_temp_free_ptr(rd
);
6904 static void gen_mfvscr(DisasContext
*ctx
)
6907 if (unlikely(!ctx
->altivec_enabled
)) {
6908 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6911 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6912 t
= tcg_temp_new_i32();
6913 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6914 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6915 tcg_temp_free_i32(t
);
6918 static void gen_mtvscr(DisasContext
*ctx
)
6921 if (unlikely(!ctx
->altivec_enabled
)) {
6922 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6925 p
= gen_avr_ptr(rB(ctx
->opcode
));
6926 gen_helper_mtvscr(cpu_env
, p
);
6927 tcg_temp_free_ptr(p
);
6930 /* Logical operations */
6931 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6932 static void glue(gen_, name)(DisasContext *ctx) \
6934 if (unlikely(!ctx->altivec_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_VPU); \
6938 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6939 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6942 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6943 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6944 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6945 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6946 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6947 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
6948 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
6949 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
6951 #define GEN_VXFORM(name, opc2, opc3) \
6952 static void glue(gen_, name)(DisasContext *ctx) \
6954 TCGv_ptr ra, rb, rd; \
6955 if (unlikely(!ctx->altivec_enabled)) { \
6956 gen_exception(ctx, POWERPC_EXCP_VPU); \
6959 ra = gen_avr_ptr(rA(ctx->opcode)); \
6960 rb = gen_avr_ptr(rB(ctx->opcode)); \
6961 rd = gen_avr_ptr(rD(ctx->opcode)); \
6962 gen_helper_##name (rd, ra, rb); \
6963 tcg_temp_free_ptr(ra); \
6964 tcg_temp_free_ptr(rb); \
6965 tcg_temp_free_ptr(rd); \
6968 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6969 static void glue(gen_, name)(DisasContext *ctx) \
6971 TCGv_ptr ra, rb, rd; \
6972 if (unlikely(!ctx->altivec_enabled)) { \
6973 gen_exception(ctx, POWERPC_EXCP_VPU); \
6976 ra = gen_avr_ptr(rA(ctx->opcode)); \
6977 rb = gen_avr_ptr(rB(ctx->opcode)); \
6978 rd = gen_avr_ptr(rD(ctx->opcode)); \
6979 gen_helper_##name(cpu_env, rd, ra, rb); \
6980 tcg_temp_free_ptr(ra); \
6981 tcg_temp_free_ptr(rb); \
6982 tcg_temp_free_ptr(rd); \
6985 #define GEN_VXFORM3(name, opc2, opc3) \
6986 static void glue(gen_, name)(DisasContext *ctx) \
6988 TCGv_ptr ra, rb, rc, rd; \
6989 if (unlikely(!ctx->altivec_enabled)) { \
6990 gen_exception(ctx, POWERPC_EXCP_VPU); \
6993 ra = gen_avr_ptr(rA(ctx->opcode)); \
6994 rb = gen_avr_ptr(rB(ctx->opcode)); \
6995 rc = gen_avr_ptr(rC(ctx->opcode)); \
6996 rd = gen_avr_ptr(rD(ctx->opcode)); \
6997 gen_helper_##name(rd, ra, rb, rc); \
6998 tcg_temp_free_ptr(ra); \
6999 tcg_temp_free_ptr(rb); \
7000 tcg_temp_free_ptr(rc); \
7001 tcg_temp_free_ptr(rd); \
7005 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7006 * an opcode bit. In general, these pairs come from different
7007 * versions of the ISA, so we must also support a pair of flags for
7010 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7011 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7013 if ((Rc(ctx->opcode) == 0) && \
7014 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7016 } else if ((Rc(ctx->opcode) == 1) && \
7017 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7020 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7024 GEN_VXFORM(vaddubm
, 0, 0);
7025 GEN_VXFORM(vadduhm
, 0, 1);
7026 GEN_VXFORM(vadduwm
, 0, 2);
7027 GEN_VXFORM(vaddudm
, 0, 3);
7028 GEN_VXFORM(vsububm
, 0, 16);
7029 GEN_VXFORM(vsubuhm
, 0, 17);
7030 GEN_VXFORM(vsubuwm
, 0, 18);
7031 GEN_VXFORM(vsubudm
, 0, 19);
7032 GEN_VXFORM(vmaxub
, 1, 0);
7033 GEN_VXFORM(vmaxuh
, 1, 1);
7034 GEN_VXFORM(vmaxuw
, 1, 2);
7035 GEN_VXFORM(vmaxud
, 1, 3);
7036 GEN_VXFORM(vmaxsb
, 1, 4);
7037 GEN_VXFORM(vmaxsh
, 1, 5);
7038 GEN_VXFORM(vmaxsw
, 1, 6);
7039 GEN_VXFORM(vmaxsd
, 1, 7);
7040 GEN_VXFORM(vminub
, 1, 8);
7041 GEN_VXFORM(vminuh
, 1, 9);
7042 GEN_VXFORM(vminuw
, 1, 10);
7043 GEN_VXFORM(vminud
, 1, 11);
7044 GEN_VXFORM(vminsb
, 1, 12);
7045 GEN_VXFORM(vminsh
, 1, 13);
7046 GEN_VXFORM(vminsw
, 1, 14);
7047 GEN_VXFORM(vminsd
, 1, 15);
7048 GEN_VXFORM(vavgub
, 1, 16);
7049 GEN_VXFORM(vavguh
, 1, 17);
7050 GEN_VXFORM(vavguw
, 1, 18);
7051 GEN_VXFORM(vavgsb
, 1, 20);
7052 GEN_VXFORM(vavgsh
, 1, 21);
7053 GEN_VXFORM(vavgsw
, 1, 22);
7054 GEN_VXFORM(vmrghb
, 6, 0);
7055 GEN_VXFORM(vmrghh
, 6, 1);
7056 GEN_VXFORM(vmrghw
, 6, 2);
7057 GEN_VXFORM(vmrglb
, 6, 4);
7058 GEN_VXFORM(vmrglh
, 6, 5);
7059 GEN_VXFORM(vmrglw
, 6, 6);
7061 static void gen_vmrgew(DisasContext
*ctx
)
7065 if (unlikely(!ctx
->altivec_enabled
)) {
7066 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7069 VT
= rD(ctx
->opcode
);
7070 VA
= rA(ctx
->opcode
);
7071 VB
= rB(ctx
->opcode
);
7072 tmp
= tcg_temp_new_i64();
7073 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
7074 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
7075 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
7076 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
7077 tcg_temp_free_i64(tmp
);
7080 static void gen_vmrgow(DisasContext
*ctx
)
7083 if (unlikely(!ctx
->altivec_enabled
)) {
7084 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7087 VT
= rD(ctx
->opcode
);
7088 VA
= rA(ctx
->opcode
);
7089 VB
= rB(ctx
->opcode
);
7091 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
7092 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
7095 GEN_VXFORM(vmuloub
, 4, 0);
7096 GEN_VXFORM(vmulouh
, 4, 1);
7097 GEN_VXFORM(vmulouw
, 4, 2);
7098 GEN_VXFORM(vmuluwm
, 4, 2);
7099 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
7100 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
7101 GEN_VXFORM(vmulosb
, 4, 4);
7102 GEN_VXFORM(vmulosh
, 4, 5);
7103 GEN_VXFORM(vmulosw
, 4, 6);
7104 GEN_VXFORM(vmuleub
, 4, 8);
7105 GEN_VXFORM(vmuleuh
, 4, 9);
7106 GEN_VXFORM(vmuleuw
, 4, 10);
7107 GEN_VXFORM(vmulesb
, 4, 12);
7108 GEN_VXFORM(vmulesh
, 4, 13);
7109 GEN_VXFORM(vmulesw
, 4, 14);
7110 GEN_VXFORM(vslb
, 2, 4);
7111 GEN_VXFORM(vslh
, 2, 5);
7112 GEN_VXFORM(vslw
, 2, 6);
7113 GEN_VXFORM(vsld
, 2, 23);
7114 GEN_VXFORM(vsrb
, 2, 8);
7115 GEN_VXFORM(vsrh
, 2, 9);
7116 GEN_VXFORM(vsrw
, 2, 10);
7117 GEN_VXFORM(vsrd
, 2, 27);
7118 GEN_VXFORM(vsrab
, 2, 12);
7119 GEN_VXFORM(vsrah
, 2, 13);
7120 GEN_VXFORM(vsraw
, 2, 14);
7121 GEN_VXFORM(vsrad
, 2, 15);
7122 GEN_VXFORM(vslo
, 6, 16);
7123 GEN_VXFORM(vsro
, 6, 17);
7124 GEN_VXFORM(vaddcuw
, 0, 6);
7125 GEN_VXFORM(vsubcuw
, 0, 22);
7126 GEN_VXFORM_ENV(vaddubs
, 0, 8);
7127 GEN_VXFORM_ENV(vadduhs
, 0, 9);
7128 GEN_VXFORM_ENV(vadduws
, 0, 10);
7129 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
7130 GEN_VXFORM_ENV(vaddshs
, 0, 13);
7131 GEN_VXFORM_ENV(vaddsws
, 0, 14);
7132 GEN_VXFORM_ENV(vsububs
, 0, 24);
7133 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
7134 GEN_VXFORM_ENV(vsubuws
, 0, 26);
7135 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
7136 GEN_VXFORM_ENV(vsubshs
, 0, 29);
7137 GEN_VXFORM_ENV(vsubsws
, 0, 30);
7138 GEN_VXFORM(vadduqm
, 0, 4);
7139 GEN_VXFORM(vaddcuq
, 0, 5);
7140 GEN_VXFORM3(vaddeuqm
, 30, 0);
7141 GEN_VXFORM3(vaddecuq
, 30, 0);
7142 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7143 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7144 GEN_VXFORM(vsubuqm
, 0, 20);
7145 GEN_VXFORM(vsubcuq
, 0, 21);
7146 GEN_VXFORM3(vsubeuqm
, 31, 0);
7147 GEN_VXFORM3(vsubecuq
, 31, 0);
7148 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7149 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7150 GEN_VXFORM(vrlb
, 2, 0);
7151 GEN_VXFORM(vrlh
, 2, 1);
7152 GEN_VXFORM(vrlw
, 2, 2);
7153 GEN_VXFORM(vrld
, 2, 3);
7154 GEN_VXFORM(vsl
, 2, 7);
7155 GEN_VXFORM(vsr
, 2, 11);
7156 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
7157 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
7158 GEN_VXFORM_ENV(vpkudum
, 7, 17);
7159 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
7160 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
7161 GEN_VXFORM_ENV(vpkudus
, 7, 19);
7162 GEN_VXFORM_ENV(vpkshus
, 7, 4);
7163 GEN_VXFORM_ENV(vpkswus
, 7, 5);
7164 GEN_VXFORM_ENV(vpksdus
, 7, 21);
7165 GEN_VXFORM_ENV(vpkshss
, 7, 6);
7166 GEN_VXFORM_ENV(vpkswss
, 7, 7);
7167 GEN_VXFORM_ENV(vpksdss
, 7, 23);
7168 GEN_VXFORM(vpkpx
, 7, 12);
7169 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
7170 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
7171 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
7172 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
7173 GEN_VXFORM_ENV(vsumsws
, 4, 30);
7174 GEN_VXFORM_ENV(vaddfp
, 5, 0);
7175 GEN_VXFORM_ENV(vsubfp
, 5, 1);
7176 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
7177 GEN_VXFORM_ENV(vminfp
, 5, 17);
7179 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7180 static void glue(gen_, name)(DisasContext *ctx) \
7182 TCGv_ptr ra, rb, rd; \
7183 if (unlikely(!ctx->altivec_enabled)) { \
7184 gen_exception(ctx, POWERPC_EXCP_VPU); \
7187 ra = gen_avr_ptr(rA(ctx->opcode)); \
7188 rb = gen_avr_ptr(rB(ctx->opcode)); \
7189 rd = gen_avr_ptr(rD(ctx->opcode)); \
7190 gen_helper_##opname(cpu_env, rd, ra, rb); \
7191 tcg_temp_free_ptr(ra); \
7192 tcg_temp_free_ptr(rb); \
7193 tcg_temp_free_ptr(rd); \
7196 #define GEN_VXRFORM(name, opc2, opc3) \
7197 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7198 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7201 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7202 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7203 * come from different versions of the ISA, so we must also support a
7204 * pair of flags for each instruction.
7206 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7207 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7209 if ((Rc(ctx->opcode) == 0) && \
7210 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7211 if (Rc21(ctx->opcode) == 0) { \
7214 gen_##name0##_(ctx); \
7216 } else if ((Rc(ctx->opcode) == 1) && \
7217 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7218 if (Rc21(ctx->opcode) == 0) { \
7221 gen_##name1##_(ctx); \
7224 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7228 GEN_VXRFORM(vcmpequb
, 3, 0)
7229 GEN_VXRFORM(vcmpequh
, 3, 1)
7230 GEN_VXRFORM(vcmpequw
, 3, 2)
7231 GEN_VXRFORM(vcmpequd
, 3, 3)
7232 GEN_VXRFORM(vcmpgtsb
, 3, 12)
7233 GEN_VXRFORM(vcmpgtsh
, 3, 13)
7234 GEN_VXRFORM(vcmpgtsw
, 3, 14)
7235 GEN_VXRFORM(vcmpgtsd
, 3, 15)
7236 GEN_VXRFORM(vcmpgtub
, 3, 8)
7237 GEN_VXRFORM(vcmpgtuh
, 3, 9)
7238 GEN_VXRFORM(vcmpgtuw
, 3, 10)
7239 GEN_VXRFORM(vcmpgtud
, 3, 11)
7240 GEN_VXRFORM(vcmpeqfp
, 3, 3)
7241 GEN_VXRFORM(vcmpgefp
, 3, 7)
7242 GEN_VXRFORM(vcmpgtfp
, 3, 11)
7243 GEN_VXRFORM(vcmpbfp
, 3, 15)
7245 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
7246 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7247 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
7248 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7249 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
7250 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
7252 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7253 static void glue(gen_, name)(DisasContext *ctx) \
7257 if (unlikely(!ctx->altivec_enabled)) { \
7258 gen_exception(ctx, POWERPC_EXCP_VPU); \
7261 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7262 rd = gen_avr_ptr(rD(ctx->opcode)); \
7263 gen_helper_##name (rd, simm); \
7264 tcg_temp_free_i32(simm); \
7265 tcg_temp_free_ptr(rd); \
7268 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
7269 GEN_VXFORM_SIMM(vspltish
, 6, 13);
7270 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
7272 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7273 static void glue(gen_, name)(DisasContext *ctx) \
7276 if (unlikely(!ctx->altivec_enabled)) { \
7277 gen_exception(ctx, POWERPC_EXCP_VPU); \
7280 rb = gen_avr_ptr(rB(ctx->opcode)); \
7281 rd = gen_avr_ptr(rD(ctx->opcode)); \
7282 gen_helper_##name (rd, rb); \
7283 tcg_temp_free_ptr(rb); \
7284 tcg_temp_free_ptr(rd); \
7287 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7288 static void glue(gen_, name)(DisasContext *ctx) \
7292 if (unlikely(!ctx->altivec_enabled)) { \
7293 gen_exception(ctx, POWERPC_EXCP_VPU); \
7296 rb = gen_avr_ptr(rB(ctx->opcode)); \
7297 rd = gen_avr_ptr(rD(ctx->opcode)); \
7298 gen_helper_##name(cpu_env, rd, rb); \
7299 tcg_temp_free_ptr(rb); \
7300 tcg_temp_free_ptr(rd); \
7303 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
7304 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
7305 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
7306 GEN_VXFORM_NOA(vupklsb
, 7, 10);
7307 GEN_VXFORM_NOA(vupklsh
, 7, 11);
7308 GEN_VXFORM_NOA(vupklsw
, 7, 27);
7309 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
7310 GEN_VXFORM_NOA(vupklpx
, 7, 15);
7311 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
7312 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
7313 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
7314 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
7315 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
7316 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
7317 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
7318 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
7320 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7321 static void glue(gen_, name)(DisasContext *ctx) \
7325 if (unlikely(!ctx->altivec_enabled)) { \
7326 gen_exception(ctx, POWERPC_EXCP_VPU); \
7329 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7330 rd = gen_avr_ptr(rD(ctx->opcode)); \
7331 gen_helper_##name (rd, simm); \
7332 tcg_temp_free_i32(simm); \
7333 tcg_temp_free_ptr(rd); \
7336 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7337 static void glue(gen_, name)(DisasContext *ctx) \
7341 if (unlikely(!ctx->altivec_enabled)) { \
7342 gen_exception(ctx, POWERPC_EXCP_VPU); \
7345 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7346 rb = gen_avr_ptr(rB(ctx->opcode)); \
7347 rd = gen_avr_ptr(rD(ctx->opcode)); \
7348 gen_helper_##name (rd, rb, uimm); \
7349 tcg_temp_free_i32(uimm); \
7350 tcg_temp_free_ptr(rb); \
7351 tcg_temp_free_ptr(rd); \
7354 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7355 static void glue(gen_, name)(DisasContext *ctx) \
7360 if (unlikely(!ctx->altivec_enabled)) { \
7361 gen_exception(ctx, POWERPC_EXCP_VPU); \
7364 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7365 rb = gen_avr_ptr(rB(ctx->opcode)); \
7366 rd = gen_avr_ptr(rD(ctx->opcode)); \
7367 gen_helper_##name(cpu_env, rd, rb, uimm); \
7368 tcg_temp_free_i32(uimm); \
7369 tcg_temp_free_ptr(rb); \
7370 tcg_temp_free_ptr(rd); \
7373 GEN_VXFORM_UIMM(vspltb
, 6, 8);
7374 GEN_VXFORM_UIMM(vsplth
, 6, 9);
7375 GEN_VXFORM_UIMM(vspltw
, 6, 10);
7376 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
7377 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
7378 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
7379 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
7381 static void gen_vsldoi(DisasContext
*ctx
)
7383 TCGv_ptr ra
, rb
, rd
;
7385 if (unlikely(!ctx
->altivec_enabled
)) {
7386 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7389 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7390 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7391 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7392 sh
= tcg_const_i32(VSH(ctx
->opcode
));
7393 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
7394 tcg_temp_free_ptr(ra
);
7395 tcg_temp_free_ptr(rb
);
7396 tcg_temp_free_ptr(rd
);
7397 tcg_temp_free_i32(sh
);
7400 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7401 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7403 TCGv_ptr ra, rb, rc, rd; \
7404 if (unlikely(!ctx->altivec_enabled)) { \
7405 gen_exception(ctx, POWERPC_EXCP_VPU); \
7408 ra = gen_avr_ptr(rA(ctx->opcode)); \
7409 rb = gen_avr_ptr(rB(ctx->opcode)); \
7410 rc = gen_avr_ptr(rC(ctx->opcode)); \
7411 rd = gen_avr_ptr(rD(ctx->opcode)); \
7412 if (Rc(ctx->opcode)) { \
7413 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7415 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7417 tcg_temp_free_ptr(ra); \
7418 tcg_temp_free_ptr(rb); \
7419 tcg_temp_free_ptr(rc); \
7420 tcg_temp_free_ptr(rd); \
7423 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
7425 static void gen_vmladduhm(DisasContext
*ctx
)
7427 TCGv_ptr ra
, rb
, rc
, rd
;
7428 if (unlikely(!ctx
->altivec_enabled
)) {
7429 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7432 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7433 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7434 rc
= gen_avr_ptr(rC(ctx
->opcode
));
7435 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7436 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
7437 tcg_temp_free_ptr(ra
);
7438 tcg_temp_free_ptr(rb
);
7439 tcg_temp_free_ptr(rc
);
7440 tcg_temp_free_ptr(rd
);
7443 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
7444 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
7445 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
7446 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
7447 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
7449 GEN_VXFORM_NOA(vclzb
, 1, 28)
7450 GEN_VXFORM_NOA(vclzh
, 1, 29)
7451 GEN_VXFORM_NOA(vclzw
, 1, 30)
7452 GEN_VXFORM_NOA(vclzd
, 1, 31)
7453 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
7454 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
7455 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
7456 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
7457 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7458 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
7459 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7460 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
7461 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7462 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
7463 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7464 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7465 GEN_VXFORM(vbpermq
, 6, 21);
7466 GEN_VXFORM_NOA(vgbbd
, 6, 20);
7467 GEN_VXFORM(vpmsumb
, 4, 16)
7468 GEN_VXFORM(vpmsumh
, 4, 17)
7469 GEN_VXFORM(vpmsumw
, 4, 18)
7470 GEN_VXFORM(vpmsumd
, 4, 19)
7472 #define GEN_BCD(op) \
7473 static void gen_##op(DisasContext *ctx) \
7475 TCGv_ptr ra, rb, rd; \
7478 if (unlikely(!ctx->altivec_enabled)) { \
7479 gen_exception(ctx, POWERPC_EXCP_VPU); \
7483 ra = gen_avr_ptr(rA(ctx->opcode)); \
7484 rb = gen_avr_ptr(rB(ctx->opcode)); \
7485 rd = gen_avr_ptr(rD(ctx->opcode)); \
7487 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7489 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7491 tcg_temp_free_ptr(ra); \
7492 tcg_temp_free_ptr(rb); \
7493 tcg_temp_free_ptr(rd); \
7494 tcg_temp_free_i32(ps); \
7500 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
7501 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7502 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
7503 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7504 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
7505 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7506 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
7507 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7509 static void gen_vsbox(DisasContext
*ctx
)
7512 if (unlikely(!ctx
->altivec_enabled
)) {
7513 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7516 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7517 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7518 gen_helper_vsbox(rd
, ra
);
7519 tcg_temp_free_ptr(ra
);
7520 tcg_temp_free_ptr(rd
);
7523 GEN_VXFORM(vcipher
, 4, 20)
7524 GEN_VXFORM(vcipherlast
, 4, 20)
7525 GEN_VXFORM(vncipher
, 4, 21)
7526 GEN_VXFORM(vncipherlast
, 4, 21)
7528 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7529 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7530 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7531 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7533 #define VSHASIGMA(op) \
7534 static void gen_##op(DisasContext *ctx) \
7538 if (unlikely(!ctx->altivec_enabled)) { \
7539 gen_exception(ctx, POWERPC_EXCP_VPU); \
7542 ra = gen_avr_ptr(rA(ctx->opcode)); \
7543 rd = gen_avr_ptr(rD(ctx->opcode)); \
7544 st_six = tcg_const_i32(rB(ctx->opcode)); \
7545 gen_helper_##op(rd, ra, st_six); \
7546 tcg_temp_free_ptr(ra); \
7547 tcg_temp_free_ptr(rd); \
7548 tcg_temp_free_i32(st_six); \
7551 VSHASIGMA(vshasigmaw
)
7552 VSHASIGMA(vshasigmad
)
7554 GEN_VXFORM3(vpermxor
, 22, 0xFF)
7555 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
7556 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
7558 /*** VSX extension ***/
7560 static inline TCGv_i64
cpu_vsrh(int n
)
7565 return cpu_avrh
[n
-32];
7569 static inline TCGv_i64
cpu_vsrl(int n
)
7574 return cpu_avrl
[n
-32];
7578 #define VSX_LOAD_SCALAR(name, operation) \
7579 static void gen_##name(DisasContext *ctx) \
7582 if (unlikely(!ctx->vsx_enabled)) { \
7583 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7586 gen_set_access_type(ctx, ACCESS_INT); \
7587 EA = tcg_temp_new(); \
7588 gen_addr_reg_index(ctx, EA); \
7589 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7590 /* NOTE: cpu_vsrl is undefined */ \
7591 tcg_temp_free(EA); \
7594 VSX_LOAD_SCALAR(lxsdx
, ld64
)
7595 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
7596 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
7597 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
7599 static void gen_lxvd2x(DisasContext
*ctx
)
7602 if (unlikely(!ctx
->vsx_enabled
)) {
7603 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7606 gen_set_access_type(ctx
, ACCESS_INT
);
7607 EA
= tcg_temp_new();
7608 gen_addr_reg_index(ctx
, EA
);
7609 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7610 tcg_gen_addi_tl(EA
, EA
, 8);
7611 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
7615 static void gen_lxvdsx(DisasContext
*ctx
)
7618 if (unlikely(!ctx
->vsx_enabled
)) {
7619 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7622 gen_set_access_type(ctx
, ACCESS_INT
);
7623 EA
= tcg_temp_new();
7624 gen_addr_reg_index(ctx
, EA
);
7625 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7626 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
7630 static void gen_lxvw4x(DisasContext
*ctx
)
7634 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
7635 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
7636 if (unlikely(!ctx
->vsx_enabled
)) {
7637 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7640 gen_set_access_type(ctx
, ACCESS_INT
);
7641 EA
= tcg_temp_new();
7642 tmp
= tcg_temp_new_i64();
7644 gen_addr_reg_index(ctx
, EA
);
7645 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7646 tcg_gen_addi_tl(EA
, EA
, 4);
7647 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
7648 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
7650 tcg_gen_addi_tl(EA
, EA
, 4);
7651 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7652 tcg_gen_addi_tl(EA
, EA
, 4);
7653 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
7654 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
7657 tcg_temp_free_i64(tmp
);
7660 #define VSX_STORE_SCALAR(name, operation) \
7661 static void gen_##name(DisasContext *ctx) \
7664 if (unlikely(!ctx->vsx_enabled)) { \
7665 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7668 gen_set_access_type(ctx, ACCESS_INT); \
7669 EA = tcg_temp_new(); \
7670 gen_addr_reg_index(ctx, EA); \
7671 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7672 tcg_temp_free(EA); \
7675 VSX_STORE_SCALAR(stxsdx
, st64
)
7676 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
7677 VSX_STORE_SCALAR(stxsspx
, st32fs
)
7679 static void gen_stxvd2x(DisasContext
*ctx
)
7682 if (unlikely(!ctx
->vsx_enabled
)) {
7683 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7686 gen_set_access_type(ctx
, ACCESS_INT
);
7687 EA
= tcg_temp_new();
7688 gen_addr_reg_index(ctx
, EA
);
7689 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7690 tcg_gen_addi_tl(EA
, EA
, 8);
7691 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7695 static void gen_stxvw4x(DisasContext
*ctx
)
7699 if (unlikely(!ctx
->vsx_enabled
)) {
7700 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7703 gen_set_access_type(ctx
, ACCESS_INT
);
7704 EA
= tcg_temp_new();
7705 gen_addr_reg_index(ctx
, EA
);
7706 tmp
= tcg_temp_new_i64();
7708 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
7709 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7710 tcg_gen_addi_tl(EA
, EA
, 4);
7711 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7713 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
7714 tcg_gen_addi_tl(EA
, EA
, 4);
7715 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7716 tcg_gen_addi_tl(EA
, EA
, 4);
7717 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7720 tcg_temp_free_i64(tmp
);
7723 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7724 static void gen_##name(DisasContext *ctx) \
7726 if (xS(ctx->opcode) < 32) { \
7727 if (unlikely(!ctx->fpu_enabled)) { \
7728 gen_exception(ctx, POWERPC_EXCP_FPU); \
7732 if (unlikely(!ctx->altivec_enabled)) { \
7733 gen_exception(ctx, POWERPC_EXCP_VPU); \
7737 TCGv_i64 tmp = tcg_temp_new_i64(); \
7738 tcg_gen_##tcgop1(tmp, source); \
7739 tcg_gen_##tcgop2(target, tmp); \
7740 tcg_temp_free_i64(tmp); \
7744 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
7745 cpu_vsrh(xS(ctx
->opcode
)))
7746 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7747 cpu_gpr
[rA(ctx
->opcode
)])
7748 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7749 cpu_gpr
[rA(ctx
->opcode
)])
7751 #if defined(TARGET_PPC64)
7752 #define MV_VSRD(name, target, source) \
7753 static void gen_##name(DisasContext *ctx) \
7755 if (xS(ctx->opcode) < 32) { \
7756 if (unlikely(!ctx->fpu_enabled)) { \
7757 gen_exception(ctx, POWERPC_EXCP_FPU); \
7761 if (unlikely(!ctx->altivec_enabled)) { \
7762 gen_exception(ctx, POWERPC_EXCP_VPU); \
7766 tcg_gen_mov_i64(target, source); \
7769 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
7770 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
7774 static void gen_xxpermdi(DisasContext
*ctx
)
7776 if (unlikely(!ctx
->vsx_enabled
)) {
7777 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7781 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
7782 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
7785 xh
= tcg_temp_new_i64();
7786 xl
= tcg_temp_new_i64();
7788 if ((DM(ctx
->opcode
) & 2) == 0) {
7789 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
7791 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
7793 if ((DM(ctx
->opcode
) & 1) == 0) {
7794 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
7796 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
7799 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
7800 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
7802 tcg_temp_free_i64(xh
);
7803 tcg_temp_free_i64(xl
);
7805 if ((DM(ctx
->opcode
) & 2) == 0) {
7806 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
7808 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
7810 if ((DM(ctx
->opcode
) & 1) == 0) {
7811 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
7813 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
7822 #define SGN_MASK_DP 0x8000000000000000ull
7823 #define SGN_MASK_SP 0x8000000080000000ull
7825 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7826 static void glue(gen_, name)(DisasContext * ctx) \
7829 if (unlikely(!ctx->vsx_enabled)) { \
7830 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7833 xb = tcg_temp_new_i64(); \
7834 sgm = tcg_temp_new_i64(); \
7835 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7836 tcg_gen_movi_i64(sgm, sgn_mask); \
7839 tcg_gen_andc_i64(xb, xb, sgm); \
7843 tcg_gen_or_i64(xb, xb, sgm); \
7847 tcg_gen_xor_i64(xb, xb, sgm); \
7851 TCGv_i64 xa = tcg_temp_new_i64(); \
7852 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7853 tcg_gen_and_i64(xa, xa, sgm); \
7854 tcg_gen_andc_i64(xb, xb, sgm); \
7855 tcg_gen_or_i64(xb, xb, xa); \
7856 tcg_temp_free_i64(xa); \
7860 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7861 tcg_temp_free_i64(xb); \
7862 tcg_temp_free_i64(sgm); \
7865 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
7866 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
7867 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
7868 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7870 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7871 static void glue(gen_, name)(DisasContext * ctx) \
7873 TCGv_i64 xbh, xbl, sgm; \
7874 if (unlikely(!ctx->vsx_enabled)) { \
7875 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7878 xbh = tcg_temp_new_i64(); \
7879 xbl = tcg_temp_new_i64(); \
7880 sgm = tcg_temp_new_i64(); \
7881 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7882 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7883 tcg_gen_movi_i64(sgm, sgn_mask); \
7886 tcg_gen_andc_i64(xbh, xbh, sgm); \
7887 tcg_gen_andc_i64(xbl, xbl, sgm); \
7891 tcg_gen_or_i64(xbh, xbh, sgm); \
7892 tcg_gen_or_i64(xbl, xbl, sgm); \
7896 tcg_gen_xor_i64(xbh, xbh, sgm); \
7897 tcg_gen_xor_i64(xbl, xbl, sgm); \
7901 TCGv_i64 xah = tcg_temp_new_i64(); \
7902 TCGv_i64 xal = tcg_temp_new_i64(); \
7903 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7904 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7905 tcg_gen_and_i64(xah, xah, sgm); \
7906 tcg_gen_and_i64(xal, xal, sgm); \
7907 tcg_gen_andc_i64(xbh, xbh, sgm); \
7908 tcg_gen_andc_i64(xbl, xbl, sgm); \
7909 tcg_gen_or_i64(xbh, xbh, xah); \
7910 tcg_gen_or_i64(xbl, xbl, xal); \
7911 tcg_temp_free_i64(xah); \
7912 tcg_temp_free_i64(xal); \
7916 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7917 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7918 tcg_temp_free_i64(xbh); \
7919 tcg_temp_free_i64(xbl); \
7920 tcg_temp_free_i64(sgm); \
7923 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
7924 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
7925 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
7926 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7927 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
7928 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
7929 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
7930 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
7932 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7933 static void gen_##name(DisasContext * ctx) \
7936 if (unlikely(!ctx->vsx_enabled)) { \
7937 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7940 /* NIP cannot be restored if the memory exception comes from an helper */ \
7941 gen_update_nip(ctx, ctx->nip - 4); \
7942 opc = tcg_const_i32(ctx->opcode); \
7943 gen_helper_##name(cpu_env, opc); \
7944 tcg_temp_free_i32(opc); \
7947 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7948 static void gen_##name(DisasContext * ctx) \
7950 if (unlikely(!ctx->vsx_enabled)) { \
7951 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7954 /* NIP cannot be restored if the exception comes */ \
7955 /* from a helper. */ \
7956 gen_update_nip(ctx, ctx->nip - 4); \
7958 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7959 cpu_vsrh(xB(ctx->opcode))); \
7962 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
7963 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
7964 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
7965 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
7966 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
7967 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
7968 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
7969 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
7970 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
7971 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
7972 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
7973 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
7974 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
7975 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
7976 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
7977 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
7978 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
7979 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
7980 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
7981 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
7982 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
7983 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
7984 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
7985 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
7986 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
7987 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
7988 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
7989 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
7990 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
7991 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
7992 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
7993 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
7994 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
7995 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
7996 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
7997 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
7998 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
8000 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
8001 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
8002 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
8003 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
8004 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
8005 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
8006 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
8007 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
8008 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
8009 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
8010 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
8011 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
8012 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
8013 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
8014 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
8015 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
8016 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
8018 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
8019 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
8020 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
8021 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
8022 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
8023 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
8024 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
8025 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
8026 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
8027 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
8028 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
8029 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
8030 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
8031 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
8032 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
8033 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
8034 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
8035 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
8036 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
8037 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
8038 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
8039 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
8040 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
8041 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
8042 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
8043 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
8044 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
8045 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
8046 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
8047 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
8048 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
8049 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
8050 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
8051 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
8052 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
8053 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
8055 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
8056 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
8057 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
8058 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
8059 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
8060 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
8061 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
8062 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
8063 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
8064 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
8065 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
8066 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
8067 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
8068 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
8069 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
8070 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
8071 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
8072 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
8073 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
8074 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
8075 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
8076 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
8077 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
8078 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
8079 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
8080 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
8081 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
8082 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
8083 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
8084 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
8085 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
8086 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
8087 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
8088 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
8089 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
8090 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
8092 #define VSX_LOGICAL(name, tcg_op) \
8093 static void glue(gen_, name)(DisasContext * ctx) \
8095 if (unlikely(!ctx->vsx_enabled)) { \
8096 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8099 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8100 cpu_vsrh(xB(ctx->opcode))); \
8101 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8102 cpu_vsrl(xB(ctx->opcode))); \
8105 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
8106 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
8107 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
8108 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
8109 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
8110 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
8111 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
8112 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
8114 #define VSX_XXMRG(name, high) \
8115 static void glue(gen_, name)(DisasContext * ctx) \
8117 TCGv_i64 a0, a1, b0, b1; \
8118 if (unlikely(!ctx->vsx_enabled)) { \
8119 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8122 a0 = tcg_temp_new_i64(); \
8123 a1 = tcg_temp_new_i64(); \
8124 b0 = tcg_temp_new_i64(); \
8125 b1 = tcg_temp_new_i64(); \
8127 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8128 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8129 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8130 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8132 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8133 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8134 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8135 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8137 tcg_gen_shri_i64(a0, a0, 32); \
8138 tcg_gen_shri_i64(b0, b0, 32); \
8139 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8141 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8143 tcg_temp_free_i64(a0); \
8144 tcg_temp_free_i64(a1); \
8145 tcg_temp_free_i64(b0); \
8146 tcg_temp_free_i64(b1); \
8149 VSX_XXMRG(xxmrghw
, 1)
8150 VSX_XXMRG(xxmrglw
, 0)
8152 static void gen_xxsel(DisasContext
* ctx
)
8155 if (unlikely(!ctx
->vsx_enabled
)) {
8156 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8159 a
= tcg_temp_new_i64();
8160 b
= tcg_temp_new_i64();
8161 c
= tcg_temp_new_i64();
8163 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
8164 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
8165 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
8167 tcg_gen_and_i64(b
, b
, c
);
8168 tcg_gen_andc_i64(a
, a
, c
);
8169 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
8171 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
8172 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
8173 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
8175 tcg_gen_and_i64(b
, b
, c
);
8176 tcg_gen_andc_i64(a
, a
, c
);
8177 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
8179 tcg_temp_free_i64(a
);
8180 tcg_temp_free_i64(b
);
8181 tcg_temp_free_i64(c
);
8184 static void gen_xxspltw(DisasContext
*ctx
)
8187 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
8188 cpu_vsrl(xB(ctx
->opcode
)) :
8189 cpu_vsrh(xB(ctx
->opcode
));
8191 if (unlikely(!ctx
->vsx_enabled
)) {
8192 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8196 b
= tcg_temp_new_i64();
8197 b2
= tcg_temp_new_i64();
8199 if (UIM(ctx
->opcode
) & 1) {
8200 tcg_gen_ext32u_i64(b
, vsr
);
8202 tcg_gen_shri_i64(b
, vsr
, 32);
8205 tcg_gen_shli_i64(b2
, b
, 32);
8206 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
8207 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
8209 tcg_temp_free_i64(b
);
8210 tcg_temp_free_i64(b2
);
8213 static void gen_xxsldwi(DisasContext
*ctx
)
8216 if (unlikely(!ctx
->vsx_enabled
)) {
8217 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8220 xth
= tcg_temp_new_i64();
8221 xtl
= tcg_temp_new_i64();
8223 switch (SHW(ctx
->opcode
)) {
8225 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8226 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8230 TCGv_i64 t0
= tcg_temp_new_i64();
8231 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8232 tcg_gen_shli_i64(xth
, xth
, 32);
8233 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
8234 tcg_gen_shri_i64(t0
, t0
, 32);
8235 tcg_gen_or_i64(xth
, xth
, t0
);
8236 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8237 tcg_gen_shli_i64(xtl
, xtl
, 32);
8238 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8239 tcg_gen_shri_i64(t0
, t0
, 32);
8240 tcg_gen_or_i64(xtl
, xtl
, t0
);
8241 tcg_temp_free_i64(t0
);
8245 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8246 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8250 TCGv_i64 t0
= tcg_temp_new_i64();
8251 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8252 tcg_gen_shli_i64(xth
, xth
, 32);
8253 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8254 tcg_gen_shri_i64(t0
, t0
, 32);
8255 tcg_gen_or_i64(xth
, xth
, t0
);
8256 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8257 tcg_gen_shli_i64(xtl
, xtl
, 32);
8258 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
8259 tcg_gen_shri_i64(t0
, t0
, 32);
8260 tcg_gen_or_i64(xtl
, xtl
, t0
);
8261 tcg_temp_free_i64(t0
);
8266 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
8267 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
8269 tcg_temp_free_i64(xth
);
8270 tcg_temp_free_i64(xtl
);
8273 /*** Decimal Floating Point ***/
8275 static inline TCGv_ptr
gen_fprp_ptr(int reg
)
8277 TCGv_ptr r
= tcg_temp_new_ptr();
8278 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, fpr
[reg
]));
8282 #define GEN_DFP_T_A_B_Rc(name) \
8283 static void gen_##name(DisasContext *ctx) \
8285 TCGv_ptr rd, ra, rb; \
8286 if (unlikely(!ctx->fpu_enabled)) { \
8287 gen_exception(ctx, POWERPC_EXCP_FPU); \
8290 gen_update_nip(ctx, ctx->nip - 4); \
8291 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8292 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8293 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8294 gen_helper_##name(cpu_env, rd, ra, rb); \
8295 if (unlikely(Rc(ctx->opcode) != 0)) { \
8296 gen_set_cr1_from_fpscr(ctx); \
8298 tcg_temp_free_ptr(rd); \
8299 tcg_temp_free_ptr(ra); \
8300 tcg_temp_free_ptr(rb); \
8303 #define GEN_DFP_BF_A_B(name) \
8304 static void gen_##name(DisasContext *ctx) \
8307 if (unlikely(!ctx->fpu_enabled)) { \
8308 gen_exception(ctx, POWERPC_EXCP_FPU); \
8311 gen_update_nip(ctx, ctx->nip - 4); \
8312 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8313 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8314 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8316 tcg_temp_free_ptr(ra); \
8317 tcg_temp_free_ptr(rb); \
8320 #define GEN_DFP_BF_A_DCM(name) \
8321 static void gen_##name(DisasContext *ctx) \
8325 if (unlikely(!ctx->fpu_enabled)) { \
8326 gen_exception(ctx, POWERPC_EXCP_FPU); \
8329 gen_update_nip(ctx, ctx->nip - 4); \
8330 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8331 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8332 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8333 cpu_env, ra, dcm); \
8334 tcg_temp_free_ptr(ra); \
8335 tcg_temp_free_i32(dcm); \
8338 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8339 static void gen_##name(DisasContext *ctx) \
8342 TCGv_i32 u32_1, u32_2; \
8343 if (unlikely(!ctx->fpu_enabled)) { \
8344 gen_exception(ctx, POWERPC_EXCP_FPU); \
8347 gen_update_nip(ctx, ctx->nip - 4); \
8348 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8349 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8350 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8351 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8352 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8353 if (unlikely(Rc(ctx->opcode) != 0)) { \
8354 gen_set_cr1_from_fpscr(ctx); \
8356 tcg_temp_free_ptr(rt); \
8357 tcg_temp_free_ptr(rb); \
8358 tcg_temp_free_i32(u32_1); \
8359 tcg_temp_free_i32(u32_2); \
8362 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8363 static void gen_##name(DisasContext *ctx) \
8365 TCGv_ptr rt, ra, rb; \
8367 if (unlikely(!ctx->fpu_enabled)) { \
8368 gen_exception(ctx, POWERPC_EXCP_FPU); \
8371 gen_update_nip(ctx, ctx->nip - 4); \
8372 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8373 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8374 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8375 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8376 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8377 if (unlikely(Rc(ctx->opcode) != 0)) { \
8378 gen_set_cr1_from_fpscr(ctx); \
8380 tcg_temp_free_ptr(rt); \
8381 tcg_temp_free_ptr(rb); \
8382 tcg_temp_free_ptr(ra); \
8383 tcg_temp_free_i32(i32); \
8386 #define GEN_DFP_T_B_Rc(name) \
8387 static void gen_##name(DisasContext *ctx) \
8390 if (unlikely(!ctx->fpu_enabled)) { \
8391 gen_exception(ctx, POWERPC_EXCP_FPU); \
8394 gen_update_nip(ctx, ctx->nip - 4); \
8395 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8396 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8397 gen_helper_##name(cpu_env, rt, rb); \
8398 if (unlikely(Rc(ctx->opcode) != 0)) { \
8399 gen_set_cr1_from_fpscr(ctx); \
8401 tcg_temp_free_ptr(rt); \
8402 tcg_temp_free_ptr(rb); \
8405 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8406 static void gen_##name(DisasContext *ctx) \
8410 if (unlikely(!ctx->fpu_enabled)) { \
8411 gen_exception(ctx, POWERPC_EXCP_FPU); \
8414 gen_update_nip(ctx, ctx->nip - 4); \
8415 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8416 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8417 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8418 gen_helper_##name(cpu_env, rt, rs, i32); \
8419 if (unlikely(Rc(ctx->opcode) != 0)) { \
8420 gen_set_cr1_from_fpscr(ctx); \
8422 tcg_temp_free_ptr(rt); \
8423 tcg_temp_free_ptr(rs); \
8424 tcg_temp_free_i32(i32); \
8427 GEN_DFP_T_A_B_Rc(dadd
)
8428 GEN_DFP_T_A_B_Rc(daddq
)
8429 GEN_DFP_T_A_B_Rc(dsub
)
8430 GEN_DFP_T_A_B_Rc(dsubq
)
8431 GEN_DFP_T_A_B_Rc(dmul
)
8432 GEN_DFP_T_A_B_Rc(dmulq
)
8433 GEN_DFP_T_A_B_Rc(ddiv
)
8434 GEN_DFP_T_A_B_Rc(ddivq
)
8435 GEN_DFP_BF_A_B(dcmpu
)
8436 GEN_DFP_BF_A_B(dcmpuq
)
8437 GEN_DFP_BF_A_B(dcmpo
)
8438 GEN_DFP_BF_A_B(dcmpoq
)
8439 GEN_DFP_BF_A_DCM(dtstdc
)
8440 GEN_DFP_BF_A_DCM(dtstdcq
)
8441 GEN_DFP_BF_A_DCM(dtstdg
)
8442 GEN_DFP_BF_A_DCM(dtstdgq
)
8443 GEN_DFP_BF_A_B(dtstex
)
8444 GEN_DFP_BF_A_B(dtstexq
)
8445 GEN_DFP_BF_A_B(dtstsf
)
8446 GEN_DFP_BF_A_B(dtstsfq
)
8447 GEN_DFP_T_B_U32_U32_Rc(dquai
, SIMM5
, RMC
)
8448 GEN_DFP_T_B_U32_U32_Rc(dquaiq
, SIMM5
, RMC
)
8449 GEN_DFP_T_A_B_I32_Rc(dqua
, RMC
)
8450 GEN_DFP_T_A_B_I32_Rc(dquaq
, RMC
)
8451 GEN_DFP_T_A_B_I32_Rc(drrnd
, RMC
)
8452 GEN_DFP_T_A_B_I32_Rc(drrndq
, RMC
)
8453 GEN_DFP_T_B_U32_U32_Rc(drintx
, FPW
, RMC
)
8454 GEN_DFP_T_B_U32_U32_Rc(drintxq
, FPW
, RMC
)
8455 GEN_DFP_T_B_U32_U32_Rc(drintn
, FPW
, RMC
)
8456 GEN_DFP_T_B_U32_U32_Rc(drintnq
, FPW
, RMC
)
8457 GEN_DFP_T_B_Rc(dctdp
)
8458 GEN_DFP_T_B_Rc(dctqpq
)
8459 GEN_DFP_T_B_Rc(drsp
)
8460 GEN_DFP_T_B_Rc(drdpq
)
8461 GEN_DFP_T_B_Rc(dcffix
)
8462 GEN_DFP_T_B_Rc(dcffixq
)
8463 GEN_DFP_T_B_Rc(dctfix
)
8464 GEN_DFP_T_B_Rc(dctfixq
)
8465 GEN_DFP_T_FPR_I32_Rc(ddedpd
, rB
, SP
)
8466 GEN_DFP_T_FPR_I32_Rc(ddedpdq
, rB
, SP
)
8467 GEN_DFP_T_FPR_I32_Rc(denbcd
, rB
, SP
)
8468 GEN_DFP_T_FPR_I32_Rc(denbcdq
, rB
, SP
)
8469 GEN_DFP_T_B_Rc(dxex
)
8470 GEN_DFP_T_B_Rc(dxexq
)
8471 GEN_DFP_T_A_B_Rc(diex
)
8472 GEN_DFP_T_A_B_Rc(diexq
)
8473 GEN_DFP_T_FPR_I32_Rc(dscli
, rA
, DCM
)
8474 GEN_DFP_T_FPR_I32_Rc(dscliq
, rA
, DCM
)
8475 GEN_DFP_T_FPR_I32_Rc(dscri
, rA
, DCM
)
8476 GEN_DFP_T_FPR_I32_Rc(dscriq
, rA
, DCM
)
8478 /*** SPE extension ***/
8479 /* Register moves */
8481 static inline void gen_evmra(DisasContext
*ctx
)
8484 if (unlikely(!ctx
->spe_enabled
)) {
8485 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8489 TCGv_i64 tmp
= tcg_temp_new_i64();
8491 /* tmp := rA_lo + rA_hi << 32 */
8492 tcg_gen_concat_tl_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8494 /* spe_acc := tmp */
8495 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8496 tcg_temp_free_i64(tmp
);
8499 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8500 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8503 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
8505 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
8508 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
8510 tcg_gen_extr_i64_tl(cpu_gpr
[reg
], cpu_gprh
[reg
], t
);
8513 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8514 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8516 if (Rc(ctx->opcode)) \
8522 /* Handler for undefined SPE opcodes */
8523 static inline void gen_speundef(DisasContext
*ctx
)
8525 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
8529 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8530 static inline void gen_##name(DisasContext *ctx) \
8532 if (unlikely(!ctx->spe_enabled)) { \
8533 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8536 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8537 cpu_gpr[rB(ctx->opcode)]); \
8538 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8539 cpu_gprh[rB(ctx->opcode)]); \
8542 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
8543 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
8544 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
8545 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
8546 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
8547 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
8548 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
8549 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
8551 /* SPE logic immediate */
8552 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8553 static inline void gen_##name(DisasContext *ctx) \
8556 if (unlikely(!ctx->spe_enabled)) { \
8557 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8560 t0 = tcg_temp_new_i32(); \
8562 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8563 tcg_opi(t0, t0, rB(ctx->opcode)); \
8564 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8566 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8567 tcg_opi(t0, t0, rB(ctx->opcode)); \
8568 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8570 tcg_temp_free_i32(t0); \
8572 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
8573 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
8574 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
8575 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
8577 /* SPE arithmetic */
8578 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8579 static inline void gen_##name(DisasContext *ctx) \
8582 if (unlikely(!ctx->spe_enabled)) { \
8583 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8586 t0 = tcg_temp_new_i32(); \
8588 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8590 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8592 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8594 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8596 tcg_temp_free_i32(t0); \
8599 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
8601 TCGLabel
*l1
= gen_new_label();
8602 TCGLabel
*l2
= gen_new_label();
8604 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
8605 tcg_gen_neg_i32(ret
, arg1
);
8608 tcg_gen_mov_i32(ret
, arg1
);
8611 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
8612 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
8613 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
8614 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
8615 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
8617 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
8618 tcg_gen_ext16u_i32(ret
, ret
);
8620 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
8621 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
8622 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
8624 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8625 static inline void gen_##name(DisasContext *ctx) \
8628 if (unlikely(!ctx->spe_enabled)) { \
8629 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8632 t0 = tcg_temp_new_i32(); \
8633 t1 = tcg_temp_new_i32(); \
8635 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8636 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8637 tcg_op(t0, t0, t1); \
8638 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8640 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8641 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8642 tcg_op(t0, t0, t1); \
8643 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8645 tcg_temp_free_i32(t0); \
8646 tcg_temp_free_i32(t1); \
8649 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8651 TCGLabel
*l1
= gen_new_label();
8652 TCGLabel
*l2
= gen_new_label();
8653 TCGv_i32 t0
= tcg_temp_local_new_i32();
8655 /* No error here: 6 bits are used */
8656 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8657 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8658 tcg_gen_shr_i32(ret
, arg1
, t0
);
8661 tcg_gen_movi_i32(ret
, 0);
8663 tcg_temp_free_i32(t0
);
8665 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
8666 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8668 TCGLabel
*l1
= gen_new_label();
8669 TCGLabel
*l2
= gen_new_label();
8670 TCGv_i32 t0
= tcg_temp_local_new_i32();
8672 /* No error here: 6 bits are used */
8673 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8674 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8675 tcg_gen_sar_i32(ret
, arg1
, t0
);
8678 tcg_gen_movi_i32(ret
, 0);
8680 tcg_temp_free_i32(t0
);
8682 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
8683 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8685 TCGLabel
*l1
= gen_new_label();
8686 TCGLabel
*l2
= gen_new_label();
8687 TCGv_i32 t0
= tcg_temp_local_new_i32();
8689 /* No error here: 6 bits are used */
8690 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8691 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8692 tcg_gen_shl_i32(ret
, arg1
, t0
);
8695 tcg_gen_movi_i32(ret
, 0);
8697 tcg_temp_free_i32(t0
);
8699 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
8700 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8702 TCGv_i32 t0
= tcg_temp_new_i32();
8703 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
8704 tcg_gen_rotl_i32(ret
, arg1
, t0
);
8705 tcg_temp_free_i32(t0
);
8707 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
8708 static inline void gen_evmergehi(DisasContext
*ctx
)
8710 if (unlikely(!ctx
->spe_enabled
)) {
8711 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8714 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8715 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8717 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
8718 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8720 tcg_gen_sub_i32(ret
, arg2
, arg1
);
8722 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
8724 /* SPE arithmetic immediate */
8725 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8726 static inline void gen_##name(DisasContext *ctx) \
8729 if (unlikely(!ctx->spe_enabled)) { \
8730 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8733 t0 = tcg_temp_new_i32(); \
8735 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8736 tcg_op(t0, t0, rA(ctx->opcode)); \
8737 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8739 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8740 tcg_op(t0, t0, rA(ctx->opcode)); \
8741 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8743 tcg_temp_free_i32(t0); \
8745 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
8746 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
8748 /* SPE comparison */
8749 #define GEN_SPEOP_COMP(name, tcg_cond) \
8750 static inline void gen_##name(DisasContext *ctx) \
8752 if (unlikely(!ctx->spe_enabled)) { \
8753 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8756 TCGLabel *l1 = gen_new_label(); \
8757 TCGLabel *l2 = gen_new_label(); \
8758 TCGLabel *l3 = gen_new_label(); \
8759 TCGLabel *l4 = gen_new_label(); \
8761 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8762 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8763 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8764 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8766 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8767 cpu_gpr[rB(ctx->opcode)], l1); \
8768 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8770 gen_set_label(l1); \
8771 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8772 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8773 gen_set_label(l2); \
8774 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8775 cpu_gprh[rB(ctx->opcode)], l3); \
8776 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8777 ~(CRF_CH | CRF_CH_AND_CL)); \
8779 gen_set_label(l3); \
8780 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8781 CRF_CH | CRF_CH_OR_CL); \
8782 gen_set_label(l4); \
8784 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
8785 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
8786 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
8787 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
8788 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
8791 static inline void gen_brinc(DisasContext
*ctx
)
8793 /* Note: brinc is usable even if SPE is disabled */
8794 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
8795 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8797 static inline void gen_evmergelo(DisasContext
*ctx
)
8799 if (unlikely(!ctx
->spe_enabled
)) {
8800 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8803 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8804 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8806 static inline void gen_evmergehilo(DisasContext
*ctx
)
8808 if (unlikely(!ctx
->spe_enabled
)) {
8809 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8812 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8813 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8815 static inline void gen_evmergelohi(DisasContext
*ctx
)
8817 if (unlikely(!ctx
->spe_enabled
)) {
8818 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8821 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
8822 TCGv tmp
= tcg_temp_new();
8823 tcg_gen_mov_tl(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
8824 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8825 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
8828 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8829 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8832 static inline void gen_evsplati(DisasContext
*ctx
)
8834 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
8836 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8837 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8839 static inline void gen_evsplatfi(DisasContext
*ctx
)
8841 uint64_t imm
= rA(ctx
->opcode
) << 27;
8843 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8844 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8847 static inline void gen_evsel(DisasContext
*ctx
)
8849 TCGLabel
*l1
= gen_new_label();
8850 TCGLabel
*l2
= gen_new_label();
8851 TCGLabel
*l3
= gen_new_label();
8852 TCGLabel
*l4
= gen_new_label();
8853 TCGv_i32 t0
= tcg_temp_local_new_i32();
8855 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
8856 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
8857 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8860 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8862 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
8863 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
8864 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8867 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8869 tcg_temp_free_i32(t0
);
8872 static void gen_evsel0(DisasContext
*ctx
)
8877 static void gen_evsel1(DisasContext
*ctx
)
8882 static void gen_evsel2(DisasContext
*ctx
)
8887 static void gen_evsel3(DisasContext
*ctx
)
8894 static inline void gen_evmwumi(DisasContext
*ctx
)
8898 if (unlikely(!ctx
->spe_enabled
)) {
8899 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8903 t0
= tcg_temp_new_i64();
8904 t1
= tcg_temp_new_i64();
8906 /* t0 := rA; t1 := rB */
8907 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8908 tcg_gen_ext32u_i64(t0
, t0
);
8909 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8910 tcg_gen_ext32u_i64(t1
, t1
);
8912 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8914 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8916 tcg_temp_free_i64(t0
);
8917 tcg_temp_free_i64(t1
);
8920 static inline void gen_evmwumia(DisasContext
*ctx
)
8924 if (unlikely(!ctx
->spe_enabled
)) {
8925 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8929 gen_evmwumi(ctx
); /* rD := rA * rB */
8931 tmp
= tcg_temp_new_i64();
8934 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8935 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8936 tcg_temp_free_i64(tmp
);
8939 static inline void gen_evmwumiaa(DisasContext
*ctx
)
8944 if (unlikely(!ctx
->spe_enabled
)) {
8945 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8949 gen_evmwumi(ctx
); /* rD := rA * rB */
8951 acc
= tcg_temp_new_i64();
8952 tmp
= tcg_temp_new_i64();
8955 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8958 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8960 /* acc := tmp + acc */
8961 tcg_gen_add_i64(acc
, acc
, tmp
);
8964 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8967 gen_store_gpr64(rD(ctx
->opcode
), acc
);
8969 tcg_temp_free_i64(acc
);
8970 tcg_temp_free_i64(tmp
);
8973 static inline void gen_evmwsmi(DisasContext
*ctx
)
8977 if (unlikely(!ctx
->spe_enabled
)) {
8978 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8982 t0
= tcg_temp_new_i64();
8983 t1
= tcg_temp_new_i64();
8985 /* t0 := rA; t1 := rB */
8986 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8987 tcg_gen_ext32s_i64(t0
, t0
);
8988 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8989 tcg_gen_ext32s_i64(t1
, t1
);
8991 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8993 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8995 tcg_temp_free_i64(t0
);
8996 tcg_temp_free_i64(t1
);
8999 static inline void gen_evmwsmia(DisasContext
*ctx
)
9003 gen_evmwsmi(ctx
); /* rD := rA * rB */
9005 tmp
= tcg_temp_new_i64();
9008 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9009 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9011 tcg_temp_free_i64(tmp
);
9014 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
9016 TCGv_i64 acc
= tcg_temp_new_i64();
9017 TCGv_i64 tmp
= tcg_temp_new_i64();
9019 gen_evmwsmi(ctx
); /* rD := rA * rB */
9021 acc
= tcg_temp_new_i64();
9022 tmp
= tcg_temp_new_i64();
9025 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9028 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9030 /* acc := tmp + acc */
9031 tcg_gen_add_i64(acc
, acc
, tmp
);
9034 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9037 gen_store_gpr64(rD(ctx
->opcode
), acc
);
9039 tcg_temp_free_i64(acc
);
9040 tcg_temp_free_i64(tmp
);
9043 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9044 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9045 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9046 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9047 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9048 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9049 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9050 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
9051 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
9052 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9053 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9054 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9055 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9056 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9057 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9058 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9059 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9060 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9061 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9062 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
9063 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9064 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9065 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
9066 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
9067 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9068 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9069 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9070 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9071 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
9073 /* SPE load and stores */
9074 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
9076 target_ulong uimm
= rB(ctx
->opcode
);
9078 if (rA(ctx
->opcode
) == 0) {
9079 tcg_gen_movi_tl(EA
, uimm
<< sh
);
9081 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
9082 if (NARROW_MODE(ctx
)) {
9083 tcg_gen_ext32u_tl(EA
, EA
);
9088 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
9090 TCGv_i64 t0
= tcg_temp_new_i64();
9091 gen_qemu_ld64(ctx
, t0
, addr
);
9092 gen_store_gpr64(rD(ctx
->opcode
), t0
);
9093 tcg_temp_free_i64(t0
);
9096 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
9098 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9099 gen_addr_add(ctx
, addr
, addr
, 4);
9100 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9103 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
9105 TCGv t0
= tcg_temp_new();
9106 gen_qemu_ld16u(ctx
, t0
, addr
);
9107 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9108 gen_addr_add(ctx
, addr
, addr
, 2);
9109 gen_qemu_ld16u(ctx
, t0
, addr
);
9110 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9111 gen_addr_add(ctx
, addr
, addr
, 2);
9112 gen_qemu_ld16u(ctx
, t0
, addr
);
9113 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9114 gen_addr_add(ctx
, addr
, addr
, 2);
9115 gen_qemu_ld16u(ctx
, t0
, addr
);
9116 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
9120 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
9122 TCGv t0
= tcg_temp_new();
9123 gen_qemu_ld16u(ctx
, t0
, addr
);
9124 tcg_gen_shli_tl(t0
, t0
, 16);
9125 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9126 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9130 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
9132 TCGv t0
= tcg_temp_new();
9133 gen_qemu_ld16u(ctx
, t0
, addr
);
9134 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9135 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9139 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
9141 TCGv t0
= tcg_temp_new();
9142 gen_qemu_ld16s(ctx
, t0
, addr
);
9143 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9144 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9148 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
9150 TCGv t0
= tcg_temp_new();
9151 gen_qemu_ld16u(ctx
, t0
, addr
);
9152 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9153 gen_addr_add(ctx
, addr
, addr
, 2);
9154 gen_qemu_ld16u(ctx
, t0
, addr
);
9155 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9159 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
9161 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9162 gen_addr_add(ctx
, addr
, addr
, 2);
9163 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9166 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
9168 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9169 gen_addr_add(ctx
, addr
, addr
, 2);
9170 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9173 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
9175 TCGv t0
= tcg_temp_new();
9176 gen_qemu_ld32u(ctx
, t0
, addr
);
9177 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9178 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9182 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
9184 TCGv t0
= tcg_temp_new();
9185 gen_qemu_ld16u(ctx
, t0
, addr
);
9186 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9187 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9188 gen_addr_add(ctx
, addr
, addr
, 2);
9189 gen_qemu_ld16u(ctx
, t0
, addr
);
9190 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9191 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9195 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
9197 TCGv_i64 t0
= tcg_temp_new_i64();
9198 gen_load_gpr64(t0
, rS(ctx
->opcode
));
9199 gen_qemu_st64(ctx
, t0
, addr
);
9200 tcg_temp_free_i64(t0
);
9203 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
9205 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9206 gen_addr_add(ctx
, addr
, addr
, 4);
9207 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9210 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
9212 TCGv t0
= tcg_temp_new();
9213 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9214 gen_qemu_st16(ctx
, t0
, addr
);
9215 gen_addr_add(ctx
, addr
, addr
, 2);
9216 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9217 gen_addr_add(ctx
, addr
, addr
, 2);
9218 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9219 gen_qemu_st16(ctx
, t0
, addr
);
9221 gen_addr_add(ctx
, addr
, addr
, 2);
9222 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9225 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
9227 TCGv t0
= tcg_temp_new();
9228 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9229 gen_qemu_st16(ctx
, t0
, addr
);
9230 gen_addr_add(ctx
, addr
, addr
, 2);
9231 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9232 gen_qemu_st16(ctx
, t0
, addr
);
9236 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
9238 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9239 gen_addr_add(ctx
, addr
, addr
, 2);
9240 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9243 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
9245 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9248 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
9250 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9253 #define GEN_SPEOP_LDST(name, opc2, sh) \
9254 static void glue(gen_, name)(DisasContext *ctx) \
9257 if (unlikely(!ctx->spe_enabled)) { \
9258 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9261 gen_set_access_type(ctx, ACCESS_INT); \
9262 t0 = tcg_temp_new(); \
9263 if (Rc(ctx->opcode)) { \
9264 gen_addr_spe_imm_index(ctx, t0, sh); \
9266 gen_addr_reg_index(ctx, t0); \
9268 gen_op_##name(ctx, t0); \
9269 tcg_temp_free(t0); \
9272 GEN_SPEOP_LDST(evldd
, 0x00, 3);
9273 GEN_SPEOP_LDST(evldw
, 0x01, 3);
9274 GEN_SPEOP_LDST(evldh
, 0x02, 3);
9275 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
9276 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
9277 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
9278 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
9279 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
9280 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
9281 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
9282 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
9284 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
9285 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
9286 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
9287 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
9288 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
9289 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
9290 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
9292 /* Multiply and add - TODO */
9294 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
9295 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9296 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9297 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9298 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9299 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9300 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9301 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9302 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9303 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9304 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9305 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9307 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9308 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9309 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9310 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9311 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9312 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9313 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9314 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9315 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9316 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9317 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9318 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9320 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9321 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9322 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9323 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9324 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
9326 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9327 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9328 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9329 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9330 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9331 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9332 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9333 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9334 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9335 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9336 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9337 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9339 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9340 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9341 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9342 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9344 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9345 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9346 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9347 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9348 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9349 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9350 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9351 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9352 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9353 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9354 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9355 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9357 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9358 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9359 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9360 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9361 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9364 /*** SPE floating-point extension ***/
9365 #define GEN_SPEFPUOP_CONV_32_32(name) \
9366 static inline void gen_##name(DisasContext *ctx) \
9368 TCGv_i32 t0 = tcg_temp_new_i32(); \
9369 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9370 gen_helper_##name(t0, cpu_env, t0); \
9371 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9372 tcg_temp_free_i32(t0); \
9374 #define GEN_SPEFPUOP_CONV_32_64(name) \
9375 static inline void gen_##name(DisasContext *ctx) \
9377 TCGv_i64 t0 = tcg_temp_new_i64(); \
9378 TCGv_i32 t1 = tcg_temp_new_i32(); \
9379 gen_load_gpr64(t0, rB(ctx->opcode)); \
9380 gen_helper_##name(t1, cpu_env, t0); \
9381 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9382 tcg_temp_free_i64(t0); \
9383 tcg_temp_free_i32(t1); \
9385 #define GEN_SPEFPUOP_CONV_64_32(name) \
9386 static inline void gen_##name(DisasContext *ctx) \
9388 TCGv_i64 t0 = tcg_temp_new_i64(); \
9389 TCGv_i32 t1 = tcg_temp_new_i32(); \
9390 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9391 gen_helper_##name(t0, cpu_env, t1); \
9392 gen_store_gpr64(rD(ctx->opcode), t0); \
9393 tcg_temp_free_i64(t0); \
9394 tcg_temp_free_i32(t1); \
9396 #define GEN_SPEFPUOP_CONV_64_64(name) \
9397 static inline void gen_##name(DisasContext *ctx) \
9399 TCGv_i64 t0 = tcg_temp_new_i64(); \
9400 gen_load_gpr64(t0, rB(ctx->opcode)); \
9401 gen_helper_##name(t0, cpu_env, t0); \
9402 gen_store_gpr64(rD(ctx->opcode), t0); \
9403 tcg_temp_free_i64(t0); \
9405 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9406 static inline void gen_##name(DisasContext *ctx) \
9409 if (unlikely(!ctx->spe_enabled)) { \
9410 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9413 t0 = tcg_temp_new_i32(); \
9414 t1 = tcg_temp_new_i32(); \
9415 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9416 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9417 gen_helper_##name(t0, cpu_env, t0, t1); \
9418 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9420 tcg_temp_free_i32(t0); \
9421 tcg_temp_free_i32(t1); \
9423 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9424 static inline void gen_##name(DisasContext *ctx) \
9427 if (unlikely(!ctx->spe_enabled)) { \
9428 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9431 t0 = tcg_temp_new_i64(); \
9432 t1 = tcg_temp_new_i64(); \
9433 gen_load_gpr64(t0, rA(ctx->opcode)); \
9434 gen_load_gpr64(t1, rB(ctx->opcode)); \
9435 gen_helper_##name(t0, cpu_env, t0, t1); \
9436 gen_store_gpr64(rD(ctx->opcode), t0); \
9437 tcg_temp_free_i64(t0); \
9438 tcg_temp_free_i64(t1); \
9440 #define GEN_SPEFPUOP_COMP_32(name) \
9441 static inline void gen_##name(DisasContext *ctx) \
9444 if (unlikely(!ctx->spe_enabled)) { \
9445 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9448 t0 = tcg_temp_new_i32(); \
9449 t1 = tcg_temp_new_i32(); \
9451 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9452 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9453 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9455 tcg_temp_free_i32(t0); \
9456 tcg_temp_free_i32(t1); \
9458 #define GEN_SPEFPUOP_COMP_64(name) \
9459 static inline void gen_##name(DisasContext *ctx) \
9462 if (unlikely(!ctx->spe_enabled)) { \
9463 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9466 t0 = tcg_temp_new_i64(); \
9467 t1 = tcg_temp_new_i64(); \
9468 gen_load_gpr64(t0, rA(ctx->opcode)); \
9469 gen_load_gpr64(t1, rB(ctx->opcode)); \
9470 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9471 tcg_temp_free_i64(t0); \
9472 tcg_temp_free_i64(t1); \
9475 /* Single precision floating-point vectors operations */
9477 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
9478 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
9479 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
9480 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
9481 static inline void gen_evfsabs(DisasContext
*ctx
)
9483 if (unlikely(!ctx
->spe_enabled
)) {
9484 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9487 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9489 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9492 static inline void gen_evfsnabs(DisasContext
*ctx
)
9494 if (unlikely(!ctx
->spe_enabled
)) {
9495 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9498 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9500 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9503 static inline void gen_evfsneg(DisasContext
*ctx
)
9505 if (unlikely(!ctx
->spe_enabled
)) {
9506 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9509 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9511 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9516 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
9517 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
9518 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
9519 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
9520 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
9521 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
9522 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
9523 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
9524 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
9525 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
9528 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
9529 GEN_SPEFPUOP_COMP_64(evfscmplt
);
9530 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
9531 GEN_SPEFPUOP_COMP_64(evfststgt
);
9532 GEN_SPEFPUOP_COMP_64(evfststlt
);
9533 GEN_SPEFPUOP_COMP_64(evfststeq
);
9535 /* Opcodes definitions */
9536 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9537 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9538 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9539 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9540 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9541 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9542 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9543 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9544 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9545 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9546 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9547 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9548 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9549 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9551 /* Single precision floating-point operations */
9553 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
9554 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
9555 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
9556 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
9557 static inline void gen_efsabs(DisasContext
*ctx
)
9559 if (unlikely(!ctx
->spe_enabled
)) {
9560 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9563 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
9565 static inline void gen_efsnabs(DisasContext
*ctx
)
9567 if (unlikely(!ctx
->spe_enabled
)) {
9568 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9571 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9573 static inline void gen_efsneg(DisasContext
*ctx
)
9575 if (unlikely(!ctx
->spe_enabled
)) {
9576 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9579 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9583 GEN_SPEFPUOP_CONV_32_32(efscfui
);
9584 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
9585 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
9586 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
9587 GEN_SPEFPUOP_CONV_32_32(efsctui
);
9588 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
9589 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
9590 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
9591 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
9592 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
9593 GEN_SPEFPUOP_CONV_32_64(efscfd
);
9596 GEN_SPEFPUOP_COMP_32(efscmpgt
);
9597 GEN_SPEFPUOP_COMP_32(efscmplt
);
9598 GEN_SPEFPUOP_COMP_32(efscmpeq
);
9599 GEN_SPEFPUOP_COMP_32(efststgt
);
9600 GEN_SPEFPUOP_COMP_32(efststlt
);
9601 GEN_SPEFPUOP_COMP_32(efststeq
);
9603 /* Opcodes definitions */
9604 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9605 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9606 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9607 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9608 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9609 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
9610 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9611 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9612 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9613 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9614 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9615 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9616 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9617 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9619 /* Double precision floating-point operations */
9621 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
9622 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
9623 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
9624 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
9625 static inline void gen_efdabs(DisasContext
*ctx
)
9627 if (unlikely(!ctx
->spe_enabled
)) {
9628 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9631 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9632 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9635 static inline void gen_efdnabs(DisasContext
*ctx
)
9637 if (unlikely(!ctx
->spe_enabled
)) {
9638 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9641 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9642 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9645 static inline void gen_efdneg(DisasContext
*ctx
)
9647 if (unlikely(!ctx
->spe_enabled
)) {
9648 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9651 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9652 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9657 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
9658 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
9659 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
9660 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
9661 GEN_SPEFPUOP_CONV_32_64(efdctui
);
9662 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
9663 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
9664 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
9665 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
9666 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
9667 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
9668 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
9669 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
9670 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
9671 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
9674 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
9675 GEN_SPEFPUOP_COMP_64(efdcmplt
);
9676 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
9677 GEN_SPEFPUOP_COMP_64(efdtstgt
);
9678 GEN_SPEFPUOP_COMP_64(efdtstlt
);
9679 GEN_SPEFPUOP_COMP_64(efdtsteq
);
9681 /* Opcodes definitions */
9682 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9683 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9684 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
9685 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9686 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9687 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9688 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9689 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
9690 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9691 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9692 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9693 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9694 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9695 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9696 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9697 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9699 static void gen_tbegin(DisasContext
*ctx
)
9701 if (unlikely(!ctx
->tm_enabled
)) {
9702 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9705 gen_helper_tbegin(cpu_env
);
9708 #define GEN_TM_NOOP(name) \
9709 static inline void gen_##name(DisasContext *ctx) \
9711 if (unlikely(!ctx->tm_enabled)) { \
9712 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9715 /* Because tbegin always fails in QEMU, these user \
9716 * space instructions all have a simple implementation: \
9718 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9719 * = 0b0 || 0b00 || 0b0 \
9721 tcg_gen_movi_i32(cpu_crf[0], 0); \
9725 GEN_TM_NOOP(tabort
);
9726 GEN_TM_NOOP(tabortwc
);
9727 GEN_TM_NOOP(tabortwci
);
9728 GEN_TM_NOOP(tabortdc
);
9729 GEN_TM_NOOP(tabortdci
);
9732 static void gen_tcheck(DisasContext
*ctx
)
9734 if (unlikely(!ctx
->tm_enabled
)) {
9735 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9738 /* Because tbegin always fails, the tcheck implementation
9741 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9742 * = 0b1 || 0b00 || 0b0
9744 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
9747 #if defined(CONFIG_USER_ONLY)
9748 #define GEN_TM_PRIV_NOOP(name) \
9749 static inline void gen_##name(DisasContext *ctx) \
9751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9756 #define GEN_TM_PRIV_NOOP(name) \
9757 static inline void gen_##name(DisasContext *ctx) \
9759 if (unlikely(ctx->pr)) { \
9760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9763 if (unlikely(!ctx->tm_enabled)) { \
9764 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9767 /* Because tbegin always fails, the implementation is \
9770 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9771 * = 0b0 || 0b00 | 0b0 \
9773 tcg_gen_movi_i32(cpu_crf[0], 0); \
9778 GEN_TM_PRIV_NOOP(treclaim
);
9779 GEN_TM_PRIV_NOOP(trechkpt
);
9781 static opcode_t opcodes
[] = {
9782 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
9783 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
9784 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9785 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
9786 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9787 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9788 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
9789 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9790 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9791 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9792 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9793 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
9794 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
9795 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
9796 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
9797 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9798 #if defined(TARGET_PPC64)
9799 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
9801 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
9802 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
9803 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9804 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9805 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9806 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
9807 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
9808 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
9809 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9810 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9811 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9812 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9813 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
9814 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
9815 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9816 #if defined(TARGET_PPC64)
9817 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
9818 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
9819 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9820 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
9822 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9823 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9824 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9825 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
9826 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
9827 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
9828 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
9829 #if defined(TARGET_PPC64)
9830 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
9831 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
9832 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
9833 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
9834 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
9836 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
9837 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9838 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9839 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
9840 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
9841 GEN_HANDLER(fabs
, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT
),
9842 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
9843 GEN_HANDLER(fnabs
, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT
),
9844 GEN_HANDLER(fneg
, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT
),
9845 GEN_HANDLER_E(fcpsgn
, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE
, PPC2_ISA205
),
9846 GEN_HANDLER_E(fmrgew
, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9847 GEN_HANDLER_E(fmrgow
, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9848 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
9849 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
9850 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
9851 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
9852 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT
),
9853 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT
),
9854 #if defined(TARGET_PPC64)
9855 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9856 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
9857 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9859 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9860 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9861 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
9862 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
9863 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
9864 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
9865 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
9866 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
9867 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9868 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9869 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
9870 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9871 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9872 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
9873 #if defined(TARGET_PPC64)
9874 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
9875 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9876 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
9877 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9879 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
9880 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
9881 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9882 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9883 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
9884 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
9885 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
9886 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
9887 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
9888 #if defined(TARGET_PPC64)
9889 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
9890 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
9892 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
9893 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
9894 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9895 #if defined(TARGET_PPC64)
9896 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
9897 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9899 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
9900 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
9901 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
9902 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
9903 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
9904 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
9905 #if defined(TARGET_PPC64)
9906 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
9908 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
9909 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
9910 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
9911 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
9912 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
9913 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
9914 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
9915 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
9916 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
9917 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
9918 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
9919 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
9920 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
9921 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
9922 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
9923 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
9924 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
9925 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
9926 #if defined(TARGET_PPC64)
9927 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
9928 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9930 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
9931 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9933 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
9934 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
9935 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
9937 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
9938 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
9939 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
9940 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
9941 #if defined(TARGET_PPC64)
9942 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
9943 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
9945 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
9946 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
9947 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
9948 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
9949 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
9950 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
9951 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
9952 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
9953 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
9954 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
9955 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
9956 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9957 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
9958 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
9959 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
9960 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
9961 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
9962 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
9963 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
9964 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9965 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
9966 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
9967 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
9968 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
9969 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
9970 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
9971 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
9972 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
9973 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
9974 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
9975 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
9976 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
9977 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
9978 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
9979 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
9980 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
9981 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
9982 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
9983 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
9984 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
9985 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
9986 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
9987 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
9988 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
9989 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
9990 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
9991 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
9992 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
9993 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
9994 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9995 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9996 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
9997 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
9998 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9999 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10000 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
10001 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
10002 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
10003 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
10004 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
10005 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
10006 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
10007 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
10008 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
10009 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
10010 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
10011 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
10012 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
10013 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
10014 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
10015 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
10016 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
10017 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
10018 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
10019 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
10020 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
10021 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
10022 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
10023 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
10024 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
10025 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10026 PPC_NONE
, PPC2_BOOKE206
),
10027 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10028 PPC_NONE
, PPC2_BOOKE206
),
10029 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10030 PPC_NONE
, PPC2_BOOKE206
),
10031 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10032 PPC_NONE
, PPC2_BOOKE206
),
10033 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10034 PPC_NONE
, PPC2_BOOKE206
),
10035 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10036 PPC_NONE
, PPC2_PRCNTL
),
10037 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10038 PPC_NONE
, PPC2_PRCNTL
),
10039 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
10040 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
10041 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
10042 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
10043 PPC_BOOKE
, PPC2_BOOKE206
),
10044 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
10045 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10046 PPC_BOOKE
, PPC2_BOOKE206
),
10047 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
10048 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
10049 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
10050 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
10051 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
10052 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
10053 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
10054 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
10055 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
10057 #undef GEN_INT_ARITH_ADD
10058 #undef GEN_INT_ARITH_ADD_CONST
10059 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10060 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10061 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10062 add_ca, compute_ca, compute_ov) \
10063 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10064 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
10065 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
10066 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
10067 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
10068 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
10069 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
10070 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
10071 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
10072 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
10073 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
10075 #undef GEN_INT_ARITH_DIVW
10076 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10077 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10078 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
10079 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
10080 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
10081 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
10082 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10083 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10084 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10085 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10087 #if defined(TARGET_PPC64)
10088 #undef GEN_INT_ARITH_DIVD
10089 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10090 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10091 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
10092 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
10093 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
10094 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
10096 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10097 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10098 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10099 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10101 #undef GEN_INT_ARITH_MUL_HELPER
10102 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10103 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10104 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
10105 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
10106 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
10109 #undef GEN_INT_ARITH_SUBF
10110 #undef GEN_INT_ARITH_SUBF_CONST
10111 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10112 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10113 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10114 add_ca, compute_ca, compute_ov) \
10115 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10116 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
10117 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
10118 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
10119 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
10120 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
10121 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
10122 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
10123 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
10124 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
10125 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
10127 #undef GEN_LOGICAL1
10128 #undef GEN_LOGICAL2
10129 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10130 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10131 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10132 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10133 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
10134 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
10135 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
10136 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
10137 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
10138 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
10139 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
10140 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
10141 #if defined(TARGET_PPC64)
10142 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
10145 #if defined(TARGET_PPC64)
10146 #undef GEN_PPC64_R2
10147 #undef GEN_PPC64_R4
10148 #define GEN_PPC64_R2(name, opc1, opc2) \
10149 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10150 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10152 #define GEN_PPC64_R4(name, opc1, opc2) \
10153 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10154 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10156 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10158 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10160 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
10161 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
10162 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
10163 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
10164 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
10165 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
10168 #undef _GEN_FLOAT_ACB
10169 #undef GEN_FLOAT_ACB
10170 #undef _GEN_FLOAT_AB
10171 #undef GEN_FLOAT_AB
10172 #undef _GEN_FLOAT_AC
10173 #undef GEN_FLOAT_AC
10175 #undef GEN_FLOAT_BS
10176 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10177 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10178 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10179 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10180 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10181 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10182 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10183 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10184 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10185 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10186 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10187 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10188 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10189 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10190 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10191 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10192 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10193 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10194 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10196 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
10197 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
10198 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
10199 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
10200 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
10201 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
10202 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
10203 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
10204 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
10205 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
10206 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
10207 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
10208 GEN_HANDLER_E(ftdiv
, 0x3F, 0x00, 0x04, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10209 GEN_HANDLER_E(ftsqrt
, 0x3F, 0x00, 0x05, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10210 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
10211 GEN_HANDLER_E(fctiwu
, 0x3F, 0x0E, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10212 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
10213 GEN_HANDLER_E(fctiwuz
, 0x3F, 0x0F, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10214 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
10215 GEN_HANDLER_E(fcfid
, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10216 GEN_HANDLER_E(fcfids
, 0x3B, 0x0E, 0x1A, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10217 GEN_HANDLER_E(fcfidu
, 0x3F, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10218 GEN_HANDLER_E(fcfidus
, 0x3B, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10219 GEN_HANDLER_E(fctid
, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10220 GEN_HANDLER_E(fctidu
, 0x3F, 0x0E, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10221 GEN_HANDLER_E(fctidz
, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10222 GEN_HANDLER_E(fctiduz
, 0x3F, 0x0F, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10223 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
10224 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
10225 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
10226 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
10233 #define GEN_LD(name, ldop, opc, type) \
10234 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10235 #define GEN_LDU(name, ldop, opc, type) \
10236 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10237 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10238 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10239 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10240 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10241 #define GEN_LDS(name, ldop, op, type) \
10242 GEN_LD(name, ldop, op | 0x20, type) \
10243 GEN_LDU(name, ldop, op | 0x21, type) \
10244 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10245 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10247 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
10248 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
10249 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
10250 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
10251 #if defined(TARGET_PPC64)
10252 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
10253 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
10254 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
10255 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
10256 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
10258 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
10259 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
10266 #define GEN_ST(name, stop, opc, type) \
10267 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10268 #define GEN_STU(name, stop, opc, type) \
10269 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10270 #define GEN_STUX(name, stop, opc2, opc3, type) \
10271 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10272 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10273 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10274 #define GEN_STS(name, stop, op, type) \
10275 GEN_ST(name, stop, op | 0x20, type) \
10276 GEN_STU(name, stop, op | 0x21, type) \
10277 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10278 GEN_STX(name, stop, 0x17, op | 0x00, type)
10280 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
10281 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
10282 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
10283 #if defined(TARGET_PPC64)
10284 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
10285 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
10286 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
10288 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
10289 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
10296 #define GEN_LDF(name, ldop, opc, type) \
10297 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10298 #define GEN_LDUF(name, ldop, opc, type) \
10299 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10300 #define GEN_LDUXF(name, ldop, opc, type) \
10301 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10302 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10303 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10304 #define GEN_LDFS(name, ldop, op, type) \
10305 GEN_LDF(name, ldop, op | 0x20, type) \
10306 GEN_LDUF(name, ldop, op | 0x21, type) \
10307 GEN_LDUXF(name, ldop, op | 0x01, type) \
10308 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10310 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
10311 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
10312 GEN_HANDLER_E(lfiwax
, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE
, PPC2_ISA205
),
10313 GEN_HANDLER_E(lfiwzx
, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10314 GEN_HANDLER_E(lfdp
, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10315 GEN_HANDLER_E(lfdpx
, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10322 #define GEN_STF(name, stop, opc, type) \
10323 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10324 #define GEN_STUF(name, stop, opc, type) \
10325 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10326 #define GEN_STUXF(name, stop, opc, type) \
10327 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10328 #define GEN_STXF(name, stop, opc2, opc3, type) \
10329 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10330 #define GEN_STFS(name, stop, op, type) \
10331 GEN_STF(name, stop, op | 0x20, type) \
10332 GEN_STUF(name, stop, op | 0x21, type) \
10333 GEN_STUXF(name, stop, op | 0x01, type) \
10334 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10336 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
10337 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
10338 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
10339 GEN_HANDLER_E(stfdp
, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10340 GEN_HANDLER_E(stfdpx
, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10343 #define GEN_CRLOGIC(name, tcg_op, opc) \
10344 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10345 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
10346 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
10347 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
10348 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
10349 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
10350 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
10351 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
10352 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
10354 #undef GEN_MAC_HANDLER
10355 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10356 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10357 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
10358 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
10359 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
10360 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
10361 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
10362 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
10363 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
10364 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
10365 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
10366 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
10367 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
10368 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
10369 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
10370 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
10371 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
10372 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
10373 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
10374 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
10375 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
10376 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
10377 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
10378 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
10379 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
10380 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
10381 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
10382 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
10383 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
10384 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
10385 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
10386 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
10387 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
10388 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
10389 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
10390 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
10391 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
10392 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
10393 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
10394 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
10395 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
10396 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
10397 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
10398 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
10404 #define GEN_VR_LDX(name, opc2, opc3) \
10405 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10406 #define GEN_VR_STX(name, opc2, opc3) \
10407 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10408 #define GEN_VR_LVE(name, opc2, opc3) \
10409 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10410 #define GEN_VR_STVE(name, opc2, opc3) \
10411 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10412 GEN_VR_LDX(lvx
, 0x07, 0x03),
10413 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
10414 GEN_VR_LVE(bx
, 0x07, 0x00),
10415 GEN_VR_LVE(hx
, 0x07, 0x01),
10416 GEN_VR_LVE(wx
, 0x07, 0x02),
10417 GEN_VR_STX(svx
, 0x07, 0x07),
10418 GEN_VR_STX(svxl
, 0x07, 0x0F),
10419 GEN_VR_STVE(bx
, 0x07, 0x04),
10420 GEN_VR_STVE(hx
, 0x07, 0x05),
10421 GEN_VR_STVE(wx
, 0x07, 0x06),
10423 #undef GEN_VX_LOGICAL
10424 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10425 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10427 #undef GEN_VX_LOGICAL_207
10428 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10429 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10431 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
10432 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
10433 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
10434 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
10435 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
10436 GEN_VX_LOGICAL_207(veqv
, tcg_gen_eqv_i64
, 2, 26),
10437 GEN_VX_LOGICAL_207(vnand
, tcg_gen_nand_i64
, 2, 22),
10438 GEN_VX_LOGICAL_207(vorc
, tcg_gen_orc_i64
, 2, 21),
10441 #define GEN_VXFORM(name, opc2, opc3) \
10442 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10444 #undef GEN_VXFORM_207
10445 #define GEN_VXFORM_207(name, opc2, opc3) \
10446 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10448 #undef GEN_VXFORM_DUAL
10449 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10450 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10452 #undef GEN_VXRFORM_DUAL
10453 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10454 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10455 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10457 GEN_VXFORM(vaddubm
, 0, 0),
10458 GEN_VXFORM(vadduhm
, 0, 1),
10459 GEN_VXFORM(vadduwm
, 0, 2),
10460 GEN_VXFORM_207(vaddudm
, 0, 3),
10461 GEN_VXFORM_DUAL(vsububm
, bcdadd
, 0, 16, PPC_ALTIVEC
, PPC_NONE
),
10462 GEN_VXFORM_DUAL(vsubuhm
, bcdsub
, 0, 17, PPC_ALTIVEC
, PPC_NONE
),
10463 GEN_VXFORM(vsubuwm
, 0, 18),
10464 GEN_VXFORM_207(vsubudm
, 0, 19),
10465 GEN_VXFORM(vmaxub
, 1, 0),
10466 GEN_VXFORM(vmaxuh
, 1, 1),
10467 GEN_VXFORM(vmaxuw
, 1, 2),
10468 GEN_VXFORM_207(vmaxud
, 1, 3),
10469 GEN_VXFORM(vmaxsb
, 1, 4),
10470 GEN_VXFORM(vmaxsh
, 1, 5),
10471 GEN_VXFORM(vmaxsw
, 1, 6),
10472 GEN_VXFORM_207(vmaxsd
, 1, 7),
10473 GEN_VXFORM(vminub
, 1, 8),
10474 GEN_VXFORM(vminuh
, 1, 9),
10475 GEN_VXFORM(vminuw
, 1, 10),
10476 GEN_VXFORM_207(vminud
, 1, 11),
10477 GEN_VXFORM(vminsb
, 1, 12),
10478 GEN_VXFORM(vminsh
, 1, 13),
10479 GEN_VXFORM(vminsw
, 1, 14),
10480 GEN_VXFORM_207(vminsd
, 1, 15),
10481 GEN_VXFORM(vavgub
, 1, 16),
10482 GEN_VXFORM(vavguh
, 1, 17),
10483 GEN_VXFORM(vavguw
, 1, 18),
10484 GEN_VXFORM(vavgsb
, 1, 20),
10485 GEN_VXFORM(vavgsh
, 1, 21),
10486 GEN_VXFORM(vavgsw
, 1, 22),
10487 GEN_VXFORM(vmrghb
, 6, 0),
10488 GEN_VXFORM(vmrghh
, 6, 1),
10489 GEN_VXFORM(vmrghw
, 6, 2),
10490 GEN_VXFORM(vmrglb
, 6, 4),
10491 GEN_VXFORM(vmrglh
, 6, 5),
10492 GEN_VXFORM(vmrglw
, 6, 6),
10493 GEN_VXFORM_207(vmrgew
, 6, 30),
10494 GEN_VXFORM_207(vmrgow
, 6, 26),
10495 GEN_VXFORM(vmuloub
, 4, 0),
10496 GEN_VXFORM(vmulouh
, 4, 1),
10497 GEN_VXFORM_DUAL(vmulouw
, vmuluwm
, 4, 2, PPC_ALTIVEC
, PPC_NONE
),
10498 GEN_VXFORM(vmulosb
, 4, 4),
10499 GEN_VXFORM(vmulosh
, 4, 5),
10500 GEN_VXFORM_207(vmulosw
, 4, 6),
10501 GEN_VXFORM(vmuleub
, 4, 8),
10502 GEN_VXFORM(vmuleuh
, 4, 9),
10503 GEN_VXFORM_207(vmuleuw
, 4, 10),
10504 GEN_VXFORM(vmulesb
, 4, 12),
10505 GEN_VXFORM(vmulesh
, 4, 13),
10506 GEN_VXFORM_207(vmulesw
, 4, 14),
10507 GEN_VXFORM(vslb
, 2, 4),
10508 GEN_VXFORM(vslh
, 2, 5),
10509 GEN_VXFORM(vslw
, 2, 6),
10510 GEN_VXFORM_207(vsld
, 2, 23),
10511 GEN_VXFORM(vsrb
, 2, 8),
10512 GEN_VXFORM(vsrh
, 2, 9),
10513 GEN_VXFORM(vsrw
, 2, 10),
10514 GEN_VXFORM_207(vsrd
, 2, 27),
10515 GEN_VXFORM(vsrab
, 2, 12),
10516 GEN_VXFORM(vsrah
, 2, 13),
10517 GEN_VXFORM(vsraw
, 2, 14),
10518 GEN_VXFORM_207(vsrad
, 2, 15),
10519 GEN_VXFORM(vslo
, 6, 16),
10520 GEN_VXFORM(vsro
, 6, 17),
10521 GEN_VXFORM(vaddcuw
, 0, 6),
10522 GEN_VXFORM(vsubcuw
, 0, 22),
10523 GEN_VXFORM(vaddubs
, 0, 8),
10524 GEN_VXFORM(vadduhs
, 0, 9),
10525 GEN_VXFORM(vadduws
, 0, 10),
10526 GEN_VXFORM(vaddsbs
, 0, 12),
10527 GEN_VXFORM(vaddshs
, 0, 13),
10528 GEN_VXFORM(vaddsws
, 0, 14),
10529 GEN_VXFORM_DUAL(vsububs
, bcdadd
, 0, 24, PPC_ALTIVEC
, PPC_NONE
),
10530 GEN_VXFORM_DUAL(vsubuhs
, bcdsub
, 0, 25, PPC_ALTIVEC
, PPC_NONE
),
10531 GEN_VXFORM(vsubuws
, 0, 26),
10532 GEN_VXFORM(vsubsbs
, 0, 28),
10533 GEN_VXFORM(vsubshs
, 0, 29),
10534 GEN_VXFORM(vsubsws
, 0, 30),
10535 GEN_VXFORM_207(vadduqm
, 0, 4),
10536 GEN_VXFORM_207(vaddcuq
, 0, 5),
10537 GEN_VXFORM_DUAL(vaddeuqm
, vaddecuq
, 30, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10538 GEN_VXFORM_207(vsubuqm
, 0, 20),
10539 GEN_VXFORM_207(vsubcuq
, 0, 21),
10540 GEN_VXFORM_DUAL(vsubeuqm
, vsubecuq
, 31, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10541 GEN_VXFORM(vrlb
, 2, 0),
10542 GEN_VXFORM(vrlh
, 2, 1),
10543 GEN_VXFORM(vrlw
, 2, 2),
10544 GEN_VXFORM_207(vrld
, 2, 3),
10545 GEN_VXFORM(vsl
, 2, 7),
10546 GEN_VXFORM(vsr
, 2, 11),
10547 GEN_VXFORM(vpkuhum
, 7, 0),
10548 GEN_VXFORM(vpkuwum
, 7, 1),
10549 GEN_VXFORM_207(vpkudum
, 7, 17),
10550 GEN_VXFORM(vpkuhus
, 7, 2),
10551 GEN_VXFORM(vpkuwus
, 7, 3),
10552 GEN_VXFORM_207(vpkudus
, 7, 19),
10553 GEN_VXFORM(vpkshus
, 7, 4),
10554 GEN_VXFORM(vpkswus
, 7, 5),
10555 GEN_VXFORM_207(vpksdus
, 7, 21),
10556 GEN_VXFORM(vpkshss
, 7, 6),
10557 GEN_VXFORM(vpkswss
, 7, 7),
10558 GEN_VXFORM_207(vpksdss
, 7, 23),
10559 GEN_VXFORM(vpkpx
, 7, 12),
10560 GEN_VXFORM(vsum4ubs
, 4, 24),
10561 GEN_VXFORM(vsum4sbs
, 4, 28),
10562 GEN_VXFORM(vsum4shs
, 4, 25),
10563 GEN_VXFORM(vsum2sws
, 4, 26),
10564 GEN_VXFORM(vsumsws
, 4, 30),
10565 GEN_VXFORM(vaddfp
, 5, 0),
10566 GEN_VXFORM(vsubfp
, 5, 1),
10567 GEN_VXFORM(vmaxfp
, 5, 16),
10568 GEN_VXFORM(vminfp
, 5, 17),
10570 #undef GEN_VXRFORM1
10572 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10573 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10574 #define GEN_VXRFORM(name, opc2, opc3) \
10575 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10576 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10577 GEN_VXRFORM(vcmpequb
, 3, 0)
10578 GEN_VXRFORM(vcmpequh
, 3, 1)
10579 GEN_VXRFORM(vcmpequw
, 3, 2)
10580 GEN_VXRFORM(vcmpgtsb
, 3, 12)
10581 GEN_VXRFORM(vcmpgtsh
, 3, 13)
10582 GEN_VXRFORM(vcmpgtsw
, 3, 14)
10583 GEN_VXRFORM(vcmpgtub
, 3, 8)
10584 GEN_VXRFORM(vcmpgtuh
, 3, 9)
10585 GEN_VXRFORM(vcmpgtuw
, 3, 10)
10586 GEN_VXRFORM_DUAL(vcmpeqfp
, vcmpequd
, 3, 3, PPC_ALTIVEC
, PPC_NONE
)
10587 GEN_VXRFORM(vcmpgefp
, 3, 7)
10588 GEN_VXRFORM_DUAL(vcmpgtfp
, vcmpgtud
, 3, 11, PPC_ALTIVEC
, PPC_NONE
)
10589 GEN_VXRFORM_DUAL(vcmpbfp
, vcmpgtsd
, 3, 15, PPC_ALTIVEC
, PPC_NONE
)
10591 #undef GEN_VXFORM_SIMM
10592 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10593 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10594 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
10595 GEN_VXFORM_SIMM(vspltish
, 6, 13),
10596 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
10598 #undef GEN_VXFORM_NOA
10599 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10600 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10601 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
10602 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
10603 GEN_VXFORM_207(vupkhsw
, 7, 25),
10604 GEN_VXFORM_NOA(vupklsb
, 7, 10),
10605 GEN_VXFORM_NOA(vupklsh
, 7, 11),
10606 GEN_VXFORM_207(vupklsw
, 7, 27),
10607 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
10608 GEN_VXFORM_NOA(vupklpx
, 7, 15),
10609 GEN_VXFORM_NOA(vrefp
, 5, 4),
10610 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
10611 GEN_VXFORM_NOA(vexptefp
, 5, 6),
10612 GEN_VXFORM_NOA(vlogefp
, 5, 7),
10613 GEN_VXFORM_NOA(vrfim
, 5, 11),
10614 GEN_VXFORM_NOA(vrfin
, 5, 8),
10615 GEN_VXFORM_NOA(vrfip
, 5, 10),
10616 GEN_VXFORM_NOA(vrfiz
, 5, 9),
10618 #undef GEN_VXFORM_UIMM
10619 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10620 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10621 GEN_VXFORM_UIMM(vspltb
, 6, 8),
10622 GEN_VXFORM_UIMM(vsplth
, 6, 9),
10623 GEN_VXFORM_UIMM(vspltw
, 6, 10),
10624 GEN_VXFORM_UIMM(vcfux
, 5, 12),
10625 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
10626 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
10627 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
10629 #undef GEN_VAFORM_PAIRED
10630 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10631 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10632 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
10633 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
10634 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
10635 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
10636 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
10637 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
10639 GEN_VXFORM_DUAL(vclzb
, vpopcntb
, 1, 28, PPC_NONE
, PPC2_ALTIVEC_207
),
10640 GEN_VXFORM_DUAL(vclzh
, vpopcnth
, 1, 29, PPC_NONE
, PPC2_ALTIVEC_207
),
10641 GEN_VXFORM_DUAL(vclzw
, vpopcntw
, 1, 30, PPC_NONE
, PPC2_ALTIVEC_207
),
10642 GEN_VXFORM_DUAL(vclzd
, vpopcntd
, 1, 31, PPC_NONE
, PPC2_ALTIVEC_207
),
10644 GEN_VXFORM_207(vbpermq
, 6, 21),
10645 GEN_VXFORM_207(vgbbd
, 6, 20),
10646 GEN_VXFORM_207(vpmsumb
, 4, 16),
10647 GEN_VXFORM_207(vpmsumh
, 4, 17),
10648 GEN_VXFORM_207(vpmsumw
, 4, 18),
10649 GEN_VXFORM_207(vpmsumd
, 4, 19),
10651 GEN_VXFORM_207(vsbox
, 4, 23),
10653 GEN_VXFORM_DUAL(vcipher
, vcipherlast
, 4, 20, PPC_NONE
, PPC2_ALTIVEC_207
),
10654 GEN_VXFORM_DUAL(vncipher
, vncipherlast
, 4, 21, PPC_NONE
, PPC2_ALTIVEC_207
),
10656 GEN_VXFORM_207(vshasigmaw
, 1, 26),
10657 GEN_VXFORM_207(vshasigmad
, 1, 27),
10659 GEN_VXFORM_DUAL(vsldoi
, vpermxor
, 22, 0xFF, PPC_ALTIVEC
, PPC_NONE
),
10661 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
10662 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
10663 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
10664 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
10665 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
10666 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
10667 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
10669 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
10670 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
10671 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
10672 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
10673 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
10675 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10676 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10677 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10678 #if defined(TARGET_PPC64)
10679 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10680 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10684 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10689 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10690 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10691 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10695 #undef GEN_XX2IFORM
10696 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10702 #undef GEN_XX3_RC_FORM
10703 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10709 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10710 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10711 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10713 #undef GEN_XX3FORM_DM
10714 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10715 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10716 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10717 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10718 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10719 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10720 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10721 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10724 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10728 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10729 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10730 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10732 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
10733 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
10734 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
10735 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
10737 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
10738 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
10739 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
10740 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
10741 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
10742 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
10743 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
10744 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
10746 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
10747 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
10748 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
10749 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
10750 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
10751 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
10752 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
10753 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
10754 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
10755 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
10756 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
10757 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
10758 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
10759 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
10760 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
10761 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
10762 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
10763 GEN_XX2IFORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
10764 GEN_XX2IFORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
10765 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
10766 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
10767 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
10768 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
10769 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
10770 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
10771 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
10772 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
10773 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
10774 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
10775 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
10776 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
10777 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
10778 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
10779 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
10780 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
10781 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
10783 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
10784 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
10785 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
10786 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
10787 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
10788 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
10789 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
10790 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
10791 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
10792 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
10793 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
10794 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
10795 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
10796 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
10797 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
10798 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
10799 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
10800 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
10802 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
10803 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
10804 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
10805 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
10806 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
10807 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
10808 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
10809 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
10810 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
10811 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
10812 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
10813 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
10814 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
10815 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
10816 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
10817 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
10818 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
10819 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
10820 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
10821 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
10822 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
10823 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
10824 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
10825 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
10826 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
10827 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
10828 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
10829 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
10830 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
10831 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
10832 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
10833 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
10834 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
10835 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
10836 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
10837 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
10839 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
10840 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
10841 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
10842 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
10843 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
10844 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
10845 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
10846 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
10847 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
10848 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
10849 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
10850 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
10851 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
10852 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
10853 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
10854 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
10855 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
10856 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
10857 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
10858 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
10859 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
10860 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
10861 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
10862 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
10863 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
10864 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
10865 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
10866 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
10867 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
10868 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
10869 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
10870 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
10871 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
10872 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
10873 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
10874 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
10877 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10878 GEN_XX3FORM(name, opc2, opc3, fl2)
10880 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
10881 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
10882 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
10883 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
10884 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
10885 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
10886 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
10887 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
10888 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
10889 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
10890 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
10891 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
10893 #define GEN_XXSEL_ROW(opc3) \
10894 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10895 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10896 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10897 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10898 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10899 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10900 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10901 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10903 GEN_XXSEL_ROW(0x00)
10904 GEN_XXSEL_ROW(0x01)
10905 GEN_XXSEL_ROW(0x02)
10906 GEN_XXSEL_ROW(0x03)
10907 GEN_XXSEL_ROW(0x04)
10908 GEN_XXSEL_ROW(0x05)
10909 GEN_XXSEL_ROW(0x06)
10910 GEN_XXSEL_ROW(0x07)
10911 GEN_XXSEL_ROW(0x08)
10912 GEN_XXSEL_ROW(0x09)
10913 GEN_XXSEL_ROW(0x0A)
10914 GEN_XXSEL_ROW(0x0B)
10915 GEN_XXSEL_ROW(0x0C)
10916 GEN_XXSEL_ROW(0x0D)
10917 GEN_XXSEL_ROW(0x0E)
10918 GEN_XXSEL_ROW(0x0F)
10919 GEN_XXSEL_ROW(0x10)
10920 GEN_XXSEL_ROW(0x11)
10921 GEN_XXSEL_ROW(0x12)
10922 GEN_XXSEL_ROW(0x13)
10923 GEN_XXSEL_ROW(0x14)
10924 GEN_XXSEL_ROW(0x15)
10925 GEN_XXSEL_ROW(0x16)
10926 GEN_XXSEL_ROW(0x17)
10927 GEN_XXSEL_ROW(0x18)
10928 GEN_XXSEL_ROW(0x19)
10929 GEN_XXSEL_ROW(0x1A)
10930 GEN_XXSEL_ROW(0x1B)
10931 GEN_XXSEL_ROW(0x1C)
10932 GEN_XXSEL_ROW(0x1D)
10933 GEN_XXSEL_ROW(0x1E)
10934 GEN_XXSEL_ROW(0x1F)
10936 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
10938 #undef GEN_DFP_T_A_B_Rc
10939 #undef GEN_DFP_BF_A_B
10940 #undef GEN_DFP_BF_A_DCM
10941 #undef GEN_DFP_T_B_U32_U32_Rc
10942 #undef GEN_DFP_T_A_B_I32_Rc
10943 #undef GEN_DFP_T_B_Rc
10944 #undef GEN_DFP_T_FPR_I32_Rc
10946 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10947 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10949 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10950 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10951 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10953 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10954 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10955 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10956 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10957 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10959 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10960 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10962 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10963 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10964 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10966 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10967 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10968 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10969 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10970 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10972 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10973 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10975 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10976 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10978 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10979 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10981 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10982 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10984 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10985 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10987 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10988 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10990 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10991 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10993 #define GEN_DFP_BF_A_B(name, op1, op2) \
10994 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10996 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10997 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10999 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11000 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11002 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11003 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11005 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11006 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11008 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11009 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11011 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11012 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11014 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11015 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11017 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11018 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11020 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11021 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11023 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11024 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11026 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11027 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11029 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11030 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11032 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11033 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11035 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11036 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11038 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11039 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11041 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11042 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11044 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11045 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11047 GEN_DFP_T_A_B_Rc(dadd
, 0x02, 0x00),
11048 GEN_DFP_Tp_Ap_Bp_Rc(daddq
, 0x02, 0x00),
11049 GEN_DFP_T_A_B_Rc(dsub
, 0x02, 0x10),
11050 GEN_DFP_Tp_Ap_Bp_Rc(dsubq
, 0x02, 0x10),
11051 GEN_DFP_T_A_B_Rc(dmul
, 0x02, 0x01),
11052 GEN_DFP_Tp_Ap_Bp_Rc(dmulq
, 0x02, 0x01),
11053 GEN_DFP_T_A_B_Rc(ddiv
, 0x02, 0x11),
11054 GEN_DFP_Tp_Ap_Bp_Rc(ddivq
, 0x02, 0x11),
11055 GEN_DFP_BF_A_B(dcmpu
, 0x02, 0x14),
11056 GEN_DFP_BF_Ap_Bp(dcmpuq
, 0x02, 0x14),
11057 GEN_DFP_BF_A_B(dcmpo
, 0x02, 0x04),
11058 GEN_DFP_BF_Ap_Bp(dcmpoq
, 0x02, 0x04),
11059 GEN_DFP_BF_A_DCM(dtstdc
, 0x02, 0x06),
11060 GEN_DFP_BF_Ap_DCM(dtstdcq
, 0x02, 0x06),
11061 GEN_DFP_BF_A_DCM(dtstdg
, 0x02, 0x07),
11062 GEN_DFP_BF_Ap_DCM(dtstdgq
, 0x02, 0x07),
11063 GEN_DFP_BF_A_B(dtstex
, 0x02, 0x05),
11064 GEN_DFP_BF_Ap_Bp(dtstexq
, 0x02, 0x05),
11065 GEN_DFP_BF_A_B(dtstsf
, 0x02, 0x15),
11066 GEN_DFP_BF_A_Bp(dtstsfq
, 0x02, 0x15),
11067 GEN_DFP_TE_T_B_RMC_Rc(dquai
, 0x03, 0x02),
11068 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq
, 0x03, 0x02),
11069 GEN_DFP_T_A_B_RMC_Rc(dqua
, 0x03, 0x00),
11070 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq
, 0x03, 0x00),
11071 GEN_DFP_T_A_B_RMC_Rc(drrnd
, 0x03, 0x01),
11072 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq
, 0x03, 0x01),
11073 GEN_DFP_R_T_B_RMC_Rc(drintx
, 0x03, 0x03),
11074 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq
, 0x03, 0x03),
11075 GEN_DFP_R_T_B_RMC_Rc(drintn
, 0x03, 0x07),
11076 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq
, 0x03, 0x07),
11077 GEN_DFP_T_B_Rc(dctdp
, 0x02, 0x08),
11078 GEN_DFP_Tp_B_Rc(dctqpq
, 0x02, 0x08),
11079 GEN_DFP_T_B_Rc(drsp
, 0x02, 0x18),
11080 GEN_DFP_Tp_Bp_Rc(drdpq
, 0x02, 0x18),
11081 GEN_DFP_T_B_Rc(dcffix
, 0x02, 0x19),
11082 GEN_DFP_Tp_B_Rc(dcffixq
, 0x02, 0x19),
11083 GEN_DFP_T_B_Rc(dctfix
, 0x02, 0x09),
11084 GEN_DFP_T_Bp_Rc(dctfixq
, 0x02, 0x09),
11085 GEN_DFP_SP_T_B_Rc(ddedpd
, 0x02, 0x0a),
11086 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq
, 0x02, 0x0a),
11087 GEN_DFP_S_T_B_Rc(denbcd
, 0x02, 0x1a),
11088 GEN_DFP_S_Tp_Bp_Rc(denbcdq
, 0x02, 0x1a),
11089 GEN_DFP_T_B_Rc(dxex
, 0x02, 0x0b),
11090 GEN_DFP_T_Bp_Rc(dxexq
, 0x02, 0x0b),
11091 GEN_DFP_T_A_B_Rc(diex
, 0x02, 0x1b),
11092 GEN_DFP_Tp_A_Bp_Rc(diexq
, 0x02, 0x1b),
11093 GEN_DFP_T_A_SH_Rc(dscli
, 0x02, 0x02),
11094 GEN_DFP_Tp_Ap_SH_Rc(dscliq
, 0x02, 0x02),
11095 GEN_DFP_T_A_SH_Rc(dscri
, 0x02, 0x03),
11096 GEN_DFP_Tp_Ap_SH_Rc(dscriq
, 0x02, 0x03),
11099 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11100 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11101 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11102 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11103 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11104 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11105 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11106 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11107 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11108 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
11109 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
11110 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11111 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11112 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11113 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11114 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11115 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11116 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
11117 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11118 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11119 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11120 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11121 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11122 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11123 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11124 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11125 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11126 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11127 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11128 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11129 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
11131 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11132 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11133 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11134 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11135 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11136 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11137 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11138 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11139 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11140 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11141 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11142 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11143 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11144 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11146 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11147 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11148 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11149 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11150 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11151 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
11152 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11153 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11154 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11155 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11156 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11157 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11158 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11159 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11161 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11162 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11163 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
11164 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11165 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11166 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11167 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11168 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
11169 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11170 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11171 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11172 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11173 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11174 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11175 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11176 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11178 #undef GEN_SPEOP_LDST
11179 #define GEN_SPEOP_LDST(name, opc2, sh) \
11180 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11181 GEN_SPEOP_LDST(evldd
, 0x00, 3),
11182 GEN_SPEOP_LDST(evldw
, 0x01, 3),
11183 GEN_SPEOP_LDST(evldh
, 0x02, 3),
11184 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
11185 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
11186 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
11187 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
11188 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
11189 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
11190 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
11191 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
11193 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
11194 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
11195 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
11196 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
11197 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
11198 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
11199 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
11201 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11202 PPC_NONE
, PPC2_TM
),
11203 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11204 PPC_NONE
, PPC2_TM
),
11205 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11206 PPC_NONE
, PPC2_TM
),
11207 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11208 PPC_NONE
, PPC2_TM
),
11209 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11210 PPC_NONE
, PPC2_TM
),
11211 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11212 PPC_NONE
, PPC2_TM
),
11213 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11214 PPC_NONE
, PPC2_TM
),
11215 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11216 PPC_NONE
, PPC2_TM
),
11217 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11218 PPC_NONE
, PPC2_TM
),
11219 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11220 PPC_NONE
, PPC2_TM
),
11221 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11222 PPC_NONE
, PPC2_TM
),
11225 #include "helper_regs.h"
11226 #include "translate_init.c"
11228 /*****************************************************************************/
11229 /* Misc PowerPC helpers */
11230 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
11236 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11237 CPUPPCState
*env
= &cpu
->env
;
11240 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
11241 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
11242 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
11244 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
11245 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
11246 env
->hflags
, env
->mmu_idx
);
11247 #if !defined(NO_TIMER_DUMP)
11248 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
11249 #if !defined(CONFIG_USER_ONLY)
11253 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
11254 #if !defined(CONFIG_USER_ONLY)
11255 , cpu_ppc_load_decr(env
)
11259 for (i
= 0; i
< 32; i
++) {
11260 if ((i
& (RGPL
- 1)) == 0)
11261 cpu_fprintf(f
, "GPR%02d", i
);
11262 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
11263 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
11264 cpu_fprintf(f
, "\n");
11266 cpu_fprintf(f
, "CR ");
11267 for (i
= 0; i
< 8; i
++)
11268 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
11269 cpu_fprintf(f
, " [");
11270 for (i
= 0; i
< 8; i
++) {
11272 if (env
->crf
[i
] & 0x08)
11274 else if (env
->crf
[i
] & 0x04)
11276 else if (env
->crf
[i
] & 0x02)
11278 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
11280 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
11281 env
->reserve_addr
);
11282 for (i
= 0; i
< 32; i
++) {
11283 if ((i
& (RFPL
- 1)) == 0)
11284 cpu_fprintf(f
, "FPR%02d", i
);
11285 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
11286 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
11287 cpu_fprintf(f
, "\n");
11289 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
11290 #if !defined(CONFIG_USER_ONLY)
11291 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
11292 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
11293 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
11294 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
11296 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
11297 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
11298 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
11299 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
11301 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
11302 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
11303 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
11304 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
11306 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
11307 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
11308 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
11309 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
11310 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
11312 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
11313 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
11314 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
11315 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
11317 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
11318 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
11319 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
11320 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
11322 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
11323 " EPR " TARGET_FMT_lx
"\n",
11324 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
11325 env
->spr
[SPR_BOOKE_EPR
]);
11328 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
11329 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
11330 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
11331 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
11334 * IVORs are left out as they are large and do not change often --
11335 * they can be read with "p $ivor0", "p $ivor1", etc.
11339 #if defined(TARGET_PPC64)
11340 if (env
->flags
& POWERPC_FLAG_CFAR
) {
11341 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
11345 switch (env
->mmu_model
) {
11346 case POWERPC_MMU_32B
:
11347 case POWERPC_MMU_601
:
11348 case POWERPC_MMU_SOFT_6xx
:
11349 case POWERPC_MMU_SOFT_74xx
:
11350 #if defined(TARGET_PPC64)
11351 case POWERPC_MMU_64B
:
11352 case POWERPC_MMU_2_03
:
11353 case POWERPC_MMU_2_06
:
11354 case POWERPC_MMU_2_07
:
11356 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
11357 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
11358 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
11360 case POWERPC_MMU_BOOKE206
:
11361 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
11362 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
11363 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
11364 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
11366 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
11367 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
11368 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
11369 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
11371 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
11372 " TLB1CFG " TARGET_FMT_lx
"\n",
11373 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
11374 env
->spr
[SPR_BOOKE_TLB1CFG
]);
11385 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
11386 fprintf_function cpu_fprintf
, int flags
)
11388 #if defined(DO_PPC_STATISTICS)
11389 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11390 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
11393 t1
= cpu
->env
.opcodes
;
11394 for (op1
= 0; op1
< 64; op1
++) {
11396 if (is_indirect_opcode(handler
)) {
11397 t2
= ind_table(handler
);
11398 for (op2
= 0; op2
< 32; op2
++) {
11400 if (is_indirect_opcode(handler
)) {
11401 t3
= ind_table(handler
);
11402 for (op3
= 0; op3
< 32; op3
++) {
11404 if (handler
->count
== 0)
11406 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
11407 "%016" PRIx64
" %" PRId64
"\n",
11408 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
11410 handler
->count
, handler
->count
);
11413 if (handler
->count
== 0)
11415 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
11416 "%016" PRIx64
" %" PRId64
"\n",
11417 op1
, op2
, op1
, op2
, handler
->oname
,
11418 handler
->count
, handler
->count
);
11422 if (handler
->count
== 0)
11424 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
11426 op1
, op1
, handler
->oname
,
11427 handler
->count
, handler
->count
);
11433 /*****************************************************************************/
11434 void gen_intermediate_code(CPUPPCState
*env
, struct TranslationBlock
*tb
)
11436 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
11437 CPUState
*cs
= CPU(cpu
);
11438 DisasContext ctx
, *ctxp
= &ctx
;
11439 opc_handler_t
**table
, *handler
;
11440 target_ulong pc_start
;
11445 ctx
.nip
= pc_start
;
11447 ctx
.exception
= POWERPC_EXCP_NONE
;
11448 ctx
.spr_cb
= env
->spr_cb
;
11450 ctx
.hv
= !msr_pr
&& msr_hv
;
11451 ctx
.mem_idx
= env
->mmu_idx
;
11452 ctx
.insns_flags
= env
->insns_flags
;
11453 ctx
.insns_flags2
= env
->insns_flags2
;
11454 ctx
.access_type
= -1;
11455 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
11456 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
11457 #if defined(TARGET_PPC64)
11458 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
11459 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
11461 ctx
.fpu_enabled
= msr_fp
;
11462 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
11463 ctx
.spe_enabled
= msr_spe
;
11465 ctx
.spe_enabled
= 0;
11466 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
11467 ctx
.altivec_enabled
= msr_vr
;
11469 ctx
.altivec_enabled
= 0;
11470 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
11471 ctx
.vsx_enabled
= msr_vsx
;
11473 ctx
.vsx_enabled
= 0;
11475 #if defined(TARGET_PPC64)
11476 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
11477 ctx
.tm_enabled
= msr_tm
;
11479 ctx
.tm_enabled
= 0;
11482 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
11483 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
11485 ctx
.singlestep_enabled
= 0;
11486 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
11487 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
11488 if (unlikely(cs
->singlestep_enabled
)) {
11489 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
11491 #if defined (DO_SINGLE_STEP) && 0
11492 /* Single step trace mode */
11496 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11497 if (max_insns
== 0) {
11498 max_insns
= CF_COUNT_MASK
;
11500 if (max_insns
> TCG_MAX_INSNS
) {
11501 max_insns
= TCG_MAX_INSNS
;
11505 tcg_clear_temp_count();
11506 /* Set env in case of segfault during code fetch */
11507 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
11508 tcg_gen_insn_start(ctx
.nip
);
11511 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
11512 gen_debug_exception(ctxp
);
11513 /* The address covered by the breakpoint must be included in
11514 [tb->pc, tb->pc + tb->size) in order to for it to be
11515 properly cleared -- thus we increment the PC here so that
11516 the logic setting tb->size below does the right thing. */
11521 LOG_DISAS("----------------\n");
11522 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
11523 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
11524 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
11526 if (unlikely(need_byteswap(&ctx
))) {
11527 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
11529 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
11531 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11532 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11533 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
11535 table
= env
->opcodes
;
11536 handler
= table
[opc1(ctx
.opcode
)];
11537 if (is_indirect_opcode(handler
)) {
11538 table
= ind_table(handler
);
11539 handler
= table
[opc2(ctx
.opcode
)];
11540 if (is_indirect_opcode(handler
)) {
11541 table
= ind_table(handler
);
11542 handler
= table
[opc3(ctx
.opcode
)];
11545 /* Is opcode *REALLY* valid ? */
11546 if (unlikely(handler
->handler
== &gen_invalid
)) {
11547 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
11548 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
11549 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11550 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
11554 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
11555 inval
= handler
->inval2
;
11557 inval
= handler
->inval1
;
11560 if (unlikely((ctx
.opcode
& inval
) != 0)) {
11561 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
11562 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
11563 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
11564 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11565 ctx
.opcode
, ctx
.nip
- 4);
11566 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
11570 (*(handler
->handler
))(&ctx
);
11571 #if defined(DO_PPC_STATISTICS)
11574 /* Check trace mode exceptions */
11575 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
11576 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
11577 ctx
.exception
!= POWERPC_SYSCALL
&&
11578 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
11579 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
11580 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
11581 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
11582 (cs
->singlestep_enabled
) ||
11584 num_insns
>= max_insns
)) {
11585 /* if we reach a page boundary or are single stepping, stop
11590 if (tcg_check_temp_count()) {
11591 fprintf(stderr
, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11592 opc1(ctx
.opcode
), opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11597 if (tb
->cflags
& CF_LAST_IO
)
11599 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
11600 gen_goto_tb(&ctx
, 0, ctx
.nip
);
11601 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
11602 if (unlikely(cs
->singlestep_enabled
)) {
11603 gen_debug_exception(ctxp
);
11605 /* Generate the return instruction */
11606 tcg_gen_exit_tb(0);
11608 gen_tb_end(tb
, num_insns
);
11610 tb
->size
= ctx
.nip
- pc_start
;
11611 tb
->icount
= num_insns
;
11613 #if defined(DEBUG_DISAS)
11614 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11616 flags
= env
->bfd_mach
;
11617 flags
|= ctx
.le_mode
<< 16;
11618 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11619 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
11625 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,
11626 target_ulong
*data
)
11628 env
->nip
= data
[0];