2 * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
4 * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "hw/i2c/i2c.h"
21 #include "hw/arm/omap.h"
22 #include "hw/sysbus.h"
23 #include "qemu/error-report.h"
25 #define TYPE_OMAP_I2C "omap_i2c"
26 #define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
28 typedef struct OMAPI2CState
{
29 SysBusDevice parent_obj
;
55 #define OMAP2_INTR_REV 0x34
56 #define OMAP2_GC_REV 0x34
58 static void omap_i2c_interrupts_update(OMAPI2CState
*s
)
60 qemu_set_irq(s
->irq
, s
->stat
& s
->mask
);
61 if ((s
->dma
>> 15) & 1) /* RDMA_EN */
62 qemu_set_irq(s
->drq
[0], (s
->stat
>> 3) & 1); /* RRDY */
63 if ((s
->dma
>> 7) & 1) /* XDMA_EN */
64 qemu_set_irq(s
->drq
[1], (s
->stat
>> 4) & 1); /* XRDY */
67 static void omap_i2c_fifo_run(OMAPI2CState
*s
)
71 if (!i2c_bus_busy(s
->bus
))
74 if ((s
->control
>> 2) & 1) { /* RM */
75 if ((s
->control
>> 1) & 1) { /* STP */
76 i2c_end_transfer(s
->bus
);
77 s
->control
&= ~(1 << 1); /* STP */
78 s
->count_cur
= s
->count
;
80 } else if ((s
->control
>> 9) & 1) { /* TRX */
81 while (ack
&& s
->txlen
)
82 ack
= (i2c_send(s
->bus
,
83 (s
->fifo
>> ((-- s
->txlen
) << 3)) &
85 s
->stat
|= 1 << 4; /* XRDY */
88 s
->fifo
|= i2c_recv(s
->bus
) << ((s
->rxlen
++) << 3);
89 s
->stat
|= 1 << 3; /* RRDY */
92 if ((s
->control
>> 9) & 1) { /* TRX */
93 while (ack
&& s
->count_cur
&& s
->txlen
) {
94 ack
= (i2c_send(s
->bus
,
95 (s
->fifo
>> ((-- s
->txlen
) << 3)) &
99 if (ack
&& s
->count_cur
)
100 s
->stat
|= 1 << 4; /* XRDY */
102 s
->stat
&= ~(1 << 4); /* XRDY */
104 s
->stat
|= 1 << 2; /* ARDY */
105 s
->control
&= ~(1 << 10); /* MST */
108 while (s
->count_cur
&& s
->rxlen
< 4) {
109 s
->fifo
|= i2c_recv(s
->bus
) << ((s
->rxlen
++) << 3);
113 s
->stat
|= 1 << 3; /* RRDY */
115 s
->stat
&= ~(1 << 3); /* RRDY */
118 if ((s
->control
>> 1) & 1) { /* STP */
119 i2c_end_transfer(s
->bus
);
120 s
->control
&= ~(1 << 1); /* STP */
121 s
->count_cur
= s
->count
;
124 s
->stat
|= 1 << 2; /* ARDY */
125 s
->control
&= ~(1 << 10); /* MST */
130 s
->stat
|= (!ack
) << 1; /* NACK */
132 s
->control
&= ~(1 << 1); /* STP */
135 static void omap_i2c_reset(DeviceState
*dev
)
137 OMAPI2CState
*s
= OMAP_I2C(dev
);
156 static uint32_t omap_i2c_read(void *opaque
, hwaddr addr
)
158 OMAPI2CState
*s
= opaque
;
159 int offset
= addr
& OMAP_MPUI_REG_MASK
;
163 case 0x00: /* I2C_REV */
164 return s
->revision
; /* REV */
166 case 0x04: /* I2C_IE */
169 case 0x08: /* I2C_STAT */
170 return s
->stat
| (i2c_bus_busy(s
->bus
) << 12);
172 case 0x0c: /* I2C_IV */
173 if (s
->revision
>= OMAP2_INTR_REV
)
175 ret
= ctz32(s
->stat
& s
->mask
);
182 omap_i2c_interrupts_update(s
);
185 case 0x10: /* I2C_SYSS */
186 return (s
->control
>> 15) & 1; /* I2C_EN */
188 case 0x14: /* I2C_BUF */
191 case 0x18: /* I2C_CNT */
192 return s
->count_cur
; /* DCOUNT */
194 case 0x1c: /* I2C_DATA */
196 if (s
->control
& (1 << 14)) { /* BE */
197 ret
|= ((s
->fifo
>> 0) & 0xff) << 8;
198 ret
|= ((s
->fifo
>> 8) & 0xff) << 0;
200 ret
|= ((s
->fifo
>> 8) & 0xff) << 8;
201 ret
|= ((s
->fifo
>> 0) & 0xff) << 0;
204 s
->stat
|= 1 << 15; /* SBD */
206 } else if (s
->rxlen
> 1) {
211 /* XXX: remote access (qualifier) error - what's that? */
214 s
->stat
&= ~(1 << 3); /* RRDY */
215 if (((s
->control
>> 10) & 1) && /* MST */
216 ((~s
->control
>> 9) & 1)) { /* TRX */
217 s
->stat
|= 1 << 2; /* ARDY */
218 s
->control
&= ~(1 << 10); /* MST */
221 s
->stat
&= ~(1 << 11); /* ROVR */
222 omap_i2c_fifo_run(s
);
223 omap_i2c_interrupts_update(s
);
226 case 0x20: /* I2C_SYSC */
229 case 0x24: /* I2C_CON */
232 case 0x28: /* I2C_OA */
235 case 0x2c: /* I2C_SA */
238 case 0x30: /* I2C_PSC */
241 case 0x34: /* I2C_SCLL */
244 case 0x38: /* I2C_SCLH */
247 case 0x3c: /* I2C_SYSTEST */
248 if (s
->test
& (1 << 15)) { /* ST_EN */
252 return s
->test
& ~0x300f;
259 static void omap_i2c_write(void *opaque
, hwaddr addr
,
262 OMAPI2CState
*s
= opaque
;
263 int offset
= addr
& OMAP_MPUI_REG_MASK
;
267 case 0x00: /* I2C_REV */
268 case 0x0c: /* I2C_IV */
269 case 0x10: /* I2C_SYSS */
273 case 0x04: /* I2C_IE */
274 s
->mask
= value
& (s
->revision
< OMAP2_GC_REV
? 0x1f : 0x3f);
277 case 0x08: /* I2C_STAT */
278 if (s
->revision
< OMAP2_INTR_REV
) {
283 /* RRDY and XRDY are reset by hardware. (in all versions???) */
284 s
->stat
&= ~(value
& 0x27);
285 omap_i2c_interrupts_update(s
);
288 case 0x14: /* I2C_BUF */
289 s
->dma
= value
& 0x8080;
290 if (value
& (1 << 15)) /* RDMA_EN */
291 s
->mask
&= ~(1 << 3); /* RRDY_IE */
292 if (value
& (1 << 7)) /* XDMA_EN */
293 s
->mask
&= ~(1 << 4); /* XRDY_IE */
296 case 0x18: /* I2C_CNT */
297 s
->count
= value
; /* DCOUNT */
300 case 0x1c: /* I2C_DATA */
302 /* XXX: remote access (qualifier) error - what's that? */
307 if (s
->control
& (1 << 14)) { /* BE */
308 s
->fifo
|= ((value
>> 8) & 0xff) << 8;
309 s
->fifo
|= ((value
>> 0) & 0xff) << 0;
311 s
->fifo
|= ((value
>> 0) & 0xff) << 8;
312 s
->fifo
|= ((value
>> 8) & 0xff) << 0;
314 s
->stat
&= ~(1 << 10); /* XUDF */
316 s
->stat
&= ~(1 << 4); /* XRDY */
317 omap_i2c_fifo_run(s
);
318 omap_i2c_interrupts_update(s
);
321 case 0x20: /* I2C_SYSC */
322 if (s
->revision
< OMAP2_INTR_REV
) {
328 omap_i2c_reset(DEVICE(s
));
332 case 0x24: /* I2C_CON */
333 s
->control
= value
& 0xcf87;
334 if (~value
& (1 << 15)) { /* I2C_EN */
335 if (s
->revision
< OMAP2_INTR_REV
) {
336 omap_i2c_reset(DEVICE(s
));
340 if ((value
& (1 << 15)) && !(value
& (1 << 10))) { /* MST */
341 fprintf(stderr
, "%s: I^2C slave mode not supported\n",
345 if ((value
& (1 << 15)) && value
& (1 << 8)) { /* XA */
346 fprintf(stderr
, "%s: 10-bit addressing mode not supported\n",
350 if ((value
& (1 << 15)) && value
& (1 << 0)) { /* STT */
351 nack
= !!i2c_start_transfer(s
->bus
, s
->addr
[1], /* SA */
352 (~value
>> 9) & 1); /* TRX */
353 s
->stat
|= nack
<< 1; /* NACK */
354 s
->control
&= ~(1 << 0); /* STT */
357 s
->control
&= ~(1 << 1); /* STP */
359 s
->count_cur
= s
->count
;
360 omap_i2c_fifo_run(s
);
362 omap_i2c_interrupts_update(s
);
366 case 0x28: /* I2C_OA */
367 s
->addr
[0] = value
& 0x3ff;
370 case 0x2c: /* I2C_SA */
371 s
->addr
[1] = value
& 0x3ff;
374 case 0x30: /* I2C_PSC */
378 case 0x34: /* I2C_SCLL */
382 case 0x38: /* I2C_SCLH */
386 case 0x3c: /* I2C_SYSTEST */
387 s
->test
= value
& 0xf80f;
388 if (value
& (1 << 11)) /* SBB */
389 if (s
->revision
>= OMAP2_INTR_REV
) {
391 omap_i2c_interrupts_update(s
);
393 if (value
& (1 << 15)) /* ST_EN */
394 fprintf(stderr
, "%s: System Test not supported\n", __FUNCTION__
);
403 static void omap_i2c_writeb(void *opaque
, hwaddr addr
,
406 OMAPI2CState
*s
= opaque
;
407 int offset
= addr
& OMAP_MPUI_REG_MASK
;
410 case 0x1c: /* I2C_DATA */
412 /* XXX: remote access (qualifier) error - what's that? */
417 s
->fifo
|= value
& 0xff;
418 s
->stat
&= ~(1 << 10); /* XUDF */
420 s
->stat
&= ~(1 << 4); /* XRDY */
421 omap_i2c_fifo_run(s
);
422 omap_i2c_interrupts_update(s
);
431 static const MemoryRegionOps omap_i2c_ops
= {
434 omap_badwidth_read16
,
436 omap_badwidth_read16
,
439 omap_i2c_writeb
, /* Only the last fifo write can be 8 bit. */
441 omap_badwidth_write16
,
444 .endianness
= DEVICE_NATIVE_ENDIAN
,
447 static int omap_i2c_init(SysBusDevice
*sbd
)
449 DeviceState
*dev
= DEVICE(sbd
);
450 OMAPI2CState
*s
= OMAP_I2C(dev
);
453 error_report("omap_i2c: fclk not connected");
456 if (s
->revision
>= OMAP2_INTR_REV
&& !s
->iclk
) {
457 /* Note that OMAP1 doesn't have a separate interface clock */
458 error_report("omap_i2c: iclk not connected");
462 sysbus_init_irq(sbd
, &s
->irq
);
463 sysbus_init_irq(sbd
, &s
->drq
[0]);
464 sysbus_init_irq(sbd
, &s
->drq
[1]);
465 memory_region_init_io(&s
->iomem
, OBJECT(s
), &omap_i2c_ops
, s
, "omap.i2c",
466 (s
->revision
< OMAP2_INTR_REV
) ? 0x800 : 0x1000);
467 sysbus_init_mmio(sbd
, &s
->iomem
);
468 s
->bus
= i2c_init_bus(dev
, NULL
);
472 static Property omap_i2c_properties
[] = {
473 DEFINE_PROP_UINT8("revision", OMAPI2CState
, revision
, 0),
474 DEFINE_PROP_PTR("iclk", OMAPI2CState
, iclk
),
475 DEFINE_PROP_PTR("fclk", OMAPI2CState
, fclk
),
476 DEFINE_PROP_END_OF_LIST(),
479 static void omap_i2c_class_init(ObjectClass
*klass
, void *data
)
481 DeviceClass
*dc
= DEVICE_CLASS(klass
);
482 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
483 k
->init
= omap_i2c_init
;
484 dc
->props
= omap_i2c_properties
;
485 dc
->reset
= omap_i2c_reset
;
486 /* Reason: pointer properties "iclk", "fclk" */
487 dc
->cannot_instantiate_with_device_add_yet
= true;
490 static const TypeInfo omap_i2c_info
= {
491 .name
= TYPE_OMAP_I2C
,
492 .parent
= TYPE_SYS_BUS_DEVICE
,
493 .instance_size
= sizeof(OMAPI2CState
),
494 .class_init
= omap_i2c_class_init
,
497 static void omap_i2c_register_types(void)
499 type_register_static(&omap_i2c_info
);
502 I2CBus
*omap_i2c_bus(DeviceState
*omap_i2c
)
504 OMAPI2CState
*s
= OMAP_I2C(omap_i2c
);
508 type_init(omap_i2c_register_types
)