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spice: fix display initialization
[qemu/kevin.git] / hw / sparc / sun4m.c
blob942ca37c541f6fb2b3a9f3fa3d59b1c3c8e29a2e
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sparc/sun4m.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/sparc/sparc32_dma.h"
29 #include "hw/block/fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/nvram/openbios_firmware_abi.h"
34 #include "hw/scsi/esp.h"
35 #include "hw/i386/pc.h"
36 #include "hw/isa/isa.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/char/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/loader.h"
41 #include "elf.h"
42 #include "sysemu/blockdev.h"
43 #include "trace.h"
44
45 /*
46 * Sun4m architecture was used in the following machines:
47 *
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
56 * SPARCstation 4
57 *
58 * See for example: http://www.sunhelp.org/faq/sunref1.html
59 */
60
61 #define KERNEL_LOAD_ADDR 0x00004000
62 #define CMDLINE_ADDR 0x007ff000
63 #define INITRD_LOAD_ADDR 0x00800000
64 #define PROM_SIZE_MAX (1024 * 1024)
65 #define PROM_VADDR 0xffd00000
66 #define PROM_FILENAME "openbios-sparc32"
67 #define CFG_ADDR 0xd00000510ULL
68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
71
72 #define MAX_CPUS 16
73 #define MAX_PILS 16
74 #define MAX_VSIMMS 4
75
76 #define ESCC_CLOCK 4915200
77
78 struct sun4m_hwdef {
79 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
80 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
81 hwaddr serial_base, fd_base;
82 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
83 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
84 hwaddr bpp_base, dbri_base, sx_base;
85 struct {
86 hwaddr reg_base, vram_base;
87 } vsimm[MAX_VSIMMS];
88 hwaddr ecc_base;
89 uint64_t max_mem;
90 const char * const default_cpu_model;
91 uint32_t ecc_version;
92 uint32_t iommu_version;
93 uint16_t machine_id;
94 uint8_t nvram_machine_id;
95 };
96
97 int DMA_get_channel_mode (int nchan)
98 {
99 return 0;
100 }
101 int DMA_read_memory (int nchan, void *buf, int pos, int size)
102 {
103 return 0;
104 }
105 int DMA_write_memory (int nchan, void *buf, int pos, int size)
106 {
107 return 0;
108 }
109 void DMA_hold_DREQ (int nchan) {}
110 void DMA_release_DREQ (int nchan) {}
111 void DMA_schedule(int nchan) {}
112
113 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
114 {
115 }
116
117 void DMA_register_channel (int nchan,
118 DMA_transfer_handler transfer_handler,
119 void *opaque)
120 {
121 }
122
123 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
124 {
125 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
126 return 0;
127 }
128
129 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
130 const char *cmdline, const char *boot_devices,
131 ram_addr_t RAM_size, uint32_t kernel_size,
132 int width, int height, int depth,
133 int nvram_machine_id, const char *arch)
134 {
135 unsigned int i;
136 uint32_t start, end;
137 uint8_t image[0x1ff0];
138 struct OpenBIOS_nvpart_v1 *part_header;
139
140 memset(image, '\0', sizeof(image));
141
142 start = 0;
143
144 // OpenBIOS nvram variables
145 // Variable partition
146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
147 part_header->signature = OPENBIOS_PART_SYSTEM;
148 pstrcpy(part_header->name, sizeof(part_header->name), "system");
149
150 end = start + sizeof(struct OpenBIOS_nvpart_v1);
151 for (i = 0; i < nb_prom_envs; i++)
152 end = OpenBIOS_set_var(image, end, prom_envs[i]);
153
154 // End marker
155 image[end++] = '\0';
156
157 end = start + ((end - start + 15) & ~15);
158 OpenBIOS_finish_partition(part_header, end - start);
159
160 // free partition
161 start = end;
162 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
163 part_header->signature = OPENBIOS_PART_FREE;
164 pstrcpy(part_header->name, sizeof(part_header->name), "free");
165
166 end = 0x1fd0;
167 OpenBIOS_finish_partition(part_header, end - start);
168
169 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
170 nvram_machine_id);
171
172 for (i = 0; i < sizeof(image); i++)
173 m48t59_write(nvram, i, image[i]);
174 }
175
176 static DeviceState *slavio_intctl;
177
178 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
179 {
180 if (slavio_intctl)
181 slavio_pic_info(mon, slavio_intctl);
182 }
183
184 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
185 {
186 if (slavio_intctl)
187 slavio_irq_info(mon, slavio_intctl);
188 }
189
190 void cpu_check_irqs(CPUSPARCState *env)
191 {
192 CPUState *cs;
193
194 if (env->pil_in && (env->interrupt_index == 0 ||
195 (env->interrupt_index & ~15) == TT_EXTINT)) {
196 unsigned int i;
197
198 for (i = 15; i > 0; i--) {
199 if (env->pil_in & (1 << i)) {
200 int old_interrupt = env->interrupt_index;
201
202 env->interrupt_index = TT_EXTINT | i;
203 if (old_interrupt != env->interrupt_index) {
204 cs = CPU(sparc_env_get_cpu(env));
205 trace_sun4m_cpu_interrupt(i);
206 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
207 }
208 break;
209 }
210 }
211 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
212 cs = CPU(sparc_env_get_cpu(env));
213 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
214 env->interrupt_index = 0;
215 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
216 }
217 }
218
219 static void cpu_kick_irq(SPARCCPU *cpu)
220 {
221 CPUSPARCState *env = &cpu->env;
222 CPUState *cs = CPU(cpu);
223
224 cs->halted = 0;
225 cpu_check_irqs(env);
226 qemu_cpu_kick(cs);
227 }
228
229 static void cpu_set_irq(void *opaque, int irq, int level)
230 {
231 SPARCCPU *cpu = opaque;
232 CPUSPARCState *env = &cpu->env;
233
234 if (level) {
235 trace_sun4m_cpu_set_irq_raise(irq);
236 env->pil_in |= 1 << irq;
237 cpu_kick_irq(cpu);
238 } else {
239 trace_sun4m_cpu_set_irq_lower(irq);
240 env->pil_in &= ~(1 << irq);
241 cpu_check_irqs(env);
242 }
243 }
244
245 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
246 {
247 }
248
249 static void main_cpu_reset(void *opaque)
250 {
251 SPARCCPU *cpu = opaque;
252 CPUState *cs = CPU(cpu);
253
254 cpu_reset(cs);
255 cs->halted = 0;
256 }
257
258 static void secondary_cpu_reset(void *opaque)
259 {
260 SPARCCPU *cpu = opaque;
261 CPUState *cs = CPU(cpu);
262
263 cpu_reset(cs);
264 cs->halted = 1;
265 }
266
267 static void cpu_halt_signal(void *opaque, int irq, int level)
268 {
269 if (level && current_cpu) {
270 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
271 }
272 }
273
274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
275 {
276 return addr - 0xf0000000ULL;
277 }
278
279 static unsigned long sun4m_load_kernel(const char *kernel_filename,
280 const char *initrd_filename,
281 ram_addr_t RAM_size)
282 {
283 int linux_boot;
284 unsigned int i;
285 long initrd_size, kernel_size;
286 uint8_t *ptr;
287
288 linux_boot = (kernel_filename != NULL);
289
290 kernel_size = 0;
291 if (linux_boot) {
292 int bswap_needed;
293
294 #ifdef BSWAP_NEEDED
295 bswap_needed = 1;
296 #else
297 bswap_needed = 0;
298 #endif
299 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
300 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
301 if (kernel_size < 0)
302 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
303 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
304 TARGET_PAGE_SIZE);
305 if (kernel_size < 0)
306 kernel_size = load_image_targphys(kernel_filename,
307 KERNEL_LOAD_ADDR,
308 RAM_size - KERNEL_LOAD_ADDR);
309 if (kernel_size < 0) {
310 fprintf(stderr, "qemu: could not load kernel '%s'\n",
311 kernel_filename);
312 exit(1);
313 }
314
315 /* load initrd */
316 initrd_size = 0;
317 if (initrd_filename) {
318 initrd_size = load_image_targphys(initrd_filename,
319 INITRD_LOAD_ADDR,
320 RAM_size - INITRD_LOAD_ADDR);
321 if (initrd_size < 0) {
322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
323 initrd_filename);
324 exit(1);
325 }
326 }
327 if (initrd_size > 0) {
328 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
329 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
330 if (ldl_p(ptr) == 0x48647253) { // HdrS
331 stl_p(ptr + 16, INITRD_LOAD_ADDR);
332 stl_p(ptr + 20, initrd_size);
333 break;
334 }
335 }
336 }
337 }
338 return kernel_size;
339 }
340
341 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
342 {
343 DeviceState *dev;
344 SysBusDevice *s;
345
346 dev = qdev_create(NULL, "iommu");
347 qdev_prop_set_uint32(dev, "version", version);
348 qdev_init_nofail(dev);
349 s = SYS_BUS_DEVICE(dev);
350 sysbus_connect_irq(s, 0, irq);
351 sysbus_mmio_map(s, 0, addr);
352
353 return s;
354 }
355
356 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
357 void *iommu, qemu_irq *dev_irq, int is_ledma)
358 {
359 DeviceState *dev;
360 SysBusDevice *s;
361
362 dev = qdev_create(NULL, "sparc32_dma");
363 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
364 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
365 qdev_init_nofail(dev);
366 s = SYS_BUS_DEVICE(dev);
367 sysbus_connect_irq(s, 0, parent_irq);
368 *dev_irq = qdev_get_gpio_in(dev, 0);
369 sysbus_mmio_map(s, 0, daddr);
370
371 return s;
372 }
373
374 static void lance_init(NICInfo *nd, hwaddr leaddr,
375 void *dma_opaque, qemu_irq irq)
376 {
377 DeviceState *dev;
378 SysBusDevice *s;
379 qemu_irq reset;
380
381 qemu_check_nic_model(&nd_table[0], "lance");
382
383 dev = qdev_create(NULL, "lance");
384 qdev_set_nic_properties(dev, nd);
385 qdev_prop_set_ptr(dev, "dma", dma_opaque);
386 qdev_init_nofail(dev);
387 s = SYS_BUS_DEVICE(dev);
388 sysbus_mmio_map(s, 0, leaddr);
389 sysbus_connect_irq(s, 0, irq);
390 reset = qdev_get_gpio_in(dev, 0);
391 qdev_connect_gpio_out(dma_opaque, 0, reset);
392 }
393
394 static DeviceState *slavio_intctl_init(hwaddr addr,
395 hwaddr addrg,
396 qemu_irq **parent_irq)
397 {
398 DeviceState *dev;
399 SysBusDevice *s;
400 unsigned int i, j;
401
402 dev = qdev_create(NULL, "slavio_intctl");
403 qdev_init_nofail(dev);
404
405 s = SYS_BUS_DEVICE(dev);
406
407 for (i = 0; i < MAX_CPUS; i++) {
408 for (j = 0; j < MAX_PILS; j++) {
409 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
410 }
411 }
412 sysbus_mmio_map(s, 0, addrg);
413 for (i = 0; i < MAX_CPUS; i++) {
414 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
415 }
416
417 return dev;
418 }
419
420 #define SYS_TIMER_OFFSET 0x10000ULL
421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
422
423 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
424 qemu_irq *cpu_irqs, unsigned int num_cpus)
425 {
426 DeviceState *dev;
427 SysBusDevice *s;
428 unsigned int i;
429
430 dev = qdev_create(NULL, "slavio_timer");
431 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
432 qdev_init_nofail(dev);
433 s = SYS_BUS_DEVICE(dev);
434 sysbus_connect_irq(s, 0, master_irq);
435 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
439 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
440 }
441 }
442
443 static qemu_irq slavio_system_powerdown;
444
445 static void slavio_powerdown_req(Notifier *n, void *opaque)
446 {
447 qemu_irq_raise(slavio_system_powerdown);
448 }
449
450 static Notifier slavio_system_powerdown_notifier = {
451 .notify = slavio_powerdown_req
452 };
453
454 #define MISC_LEDS 0x01600000
455 #define MISC_CFG 0x01800000
456 #define MISC_DIAG 0x01a00000
457 #define MISC_MDM 0x01b00000
458 #define MISC_SYS 0x01f00000
459
460 static void slavio_misc_init(hwaddr base,
461 hwaddr aux1_base,
462 hwaddr aux2_base, qemu_irq irq,
463 qemu_irq fdc_tc)
464 {
465 DeviceState *dev;
466 SysBusDevice *s;
467
468 dev = qdev_create(NULL, "slavio_misc");
469 qdev_init_nofail(dev);
470 s = SYS_BUS_DEVICE(dev);
471 if (base) {
472 /* 8 bit registers */
473 /* Slavio control */
474 sysbus_mmio_map(s, 0, base + MISC_CFG);
475 /* Diagnostics */
476 sysbus_mmio_map(s, 1, base + MISC_DIAG);
477 /* Modem control */
478 sysbus_mmio_map(s, 2, base + MISC_MDM);
479 /* 16 bit registers */
480 /* ss600mp diag LEDs */
481 sysbus_mmio_map(s, 3, base + MISC_LEDS);
482 /* 32 bit registers */
483 /* System control */
484 sysbus_mmio_map(s, 4, base + MISC_SYS);
485 }
486 if (aux1_base) {
487 /* AUX 1 (Misc System Functions) */
488 sysbus_mmio_map(s, 5, aux1_base);
489 }
490 if (aux2_base) {
491 /* AUX 2 (Software Powerdown Control) */
492 sysbus_mmio_map(s, 6, aux2_base);
493 }
494 sysbus_connect_irq(s, 0, irq);
495 sysbus_connect_irq(s, 1, fdc_tc);
496 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
498 }
499
500 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
501 {
502 DeviceState *dev;
503 SysBusDevice *s;
504
505 dev = qdev_create(NULL, "eccmemctl");
506 qdev_prop_set_uint32(dev, "version", version);
507 qdev_init_nofail(dev);
508 s = SYS_BUS_DEVICE(dev);
509 sysbus_connect_irq(s, 0, irq);
510 sysbus_mmio_map(s, 0, base);
511 if (version == 0) { // SS-600MP only
512 sysbus_mmio_map(s, 1, base + 0x1000);
513 }
514 }
515
516 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
517 {
518 DeviceState *dev;
519 SysBusDevice *s;
520
521 dev = qdev_create(NULL, "apc");
522 qdev_init_nofail(dev);
523 s = SYS_BUS_DEVICE(dev);
524 /* Power management (APC) XXX: not a Slavio device */
525 sysbus_mmio_map(s, 0, power_base);
526 sysbus_connect_irq(s, 0, cpu_halt);
527 }
528
529 static void tcx_init(hwaddr addr, int vram_size, int width,
530 int height, int depth)
531 {
532 DeviceState *dev;
533 SysBusDevice *s;
534
535 dev = qdev_create(NULL, "SUNW,tcx");
536 qdev_prop_set_uint32(dev, "vram_size", vram_size);
537 qdev_prop_set_uint16(dev, "width", width);
538 qdev_prop_set_uint16(dev, "height", height);
539 qdev_prop_set_uint16(dev, "depth", depth);
540 qdev_init_nofail(dev);
541 s = SYS_BUS_DEVICE(dev);
542 /* 8-bit plane */
543 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
544 /* DAC */
545 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
546 /* TEC (dummy) */
547 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
548 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
549 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
550 if (depth == 24) {
551 /* 24-bit plane */
552 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
553 /* Control plane */
554 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
555 } else {
556 /* THC 8 bit (dummy) */
557 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
558 }
559 }
560
561 /* NCR89C100/MACIO Internal ID register */
562
563 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
564
565 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
566
567 static void idreg_init(hwaddr addr)
568 {
569 DeviceState *dev;
570 SysBusDevice *s;
571
572 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
573 qdev_init_nofail(dev);
574 s = SYS_BUS_DEVICE(dev);
575
576 sysbus_mmio_map(s, 0, addr);
577 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
578 }
579
580 #define MACIO_ID_REGISTER(obj) \
581 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
582
583 typedef struct IDRegState {
584 SysBusDevice parent_obj;
585
586 MemoryRegion mem;
587 } IDRegState;
588
589 static int idreg_init1(SysBusDevice *dev)
590 {
591 IDRegState *s = MACIO_ID_REGISTER(dev);
592
593 memory_region_init_ram(&s->mem, OBJECT(s),
594 "sun4m.idreg", sizeof(idreg_data));
595 vmstate_register_ram_global(&s->mem);
596 memory_region_set_readonly(&s->mem, true);
597 sysbus_init_mmio(dev, &s->mem);
598 return 0;
599 }
600
601 static void idreg_class_init(ObjectClass *klass, void *data)
602 {
603 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
604
605 k->init = idreg_init1;
606 }
607
608 static const TypeInfo idreg_info = {
609 .name = TYPE_MACIO_ID_REGISTER,
610 .parent = TYPE_SYS_BUS_DEVICE,
611 .instance_size = sizeof(IDRegState),
612 .class_init = idreg_class_init,
613 };
614
615 #define TYPE_TCX_AFX "tcx_afx"
616 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
617
618 typedef struct AFXState {
619 SysBusDevice parent_obj;
620
621 MemoryRegion mem;
622 } AFXState;
623
624 /* SS-5 TCX AFX register */
625 static void afx_init(hwaddr addr)
626 {
627 DeviceState *dev;
628 SysBusDevice *s;
629
630 dev = qdev_create(NULL, TYPE_TCX_AFX);
631 qdev_init_nofail(dev);
632 s = SYS_BUS_DEVICE(dev);
633
634 sysbus_mmio_map(s, 0, addr);
635 }
636
637 static int afx_init1(SysBusDevice *dev)
638 {
639 AFXState *s = TCX_AFX(dev);
640
641 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4);
642 vmstate_register_ram_global(&s->mem);
643 sysbus_init_mmio(dev, &s->mem);
644 return 0;
645 }
646
647 static void afx_class_init(ObjectClass *klass, void *data)
648 {
649 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
650
651 k->init = afx_init1;
652 }
653
654 static const TypeInfo afx_info = {
655 .name = TYPE_TCX_AFX,
656 .parent = TYPE_SYS_BUS_DEVICE,
657 .instance_size = sizeof(AFXState),
658 .class_init = afx_class_init,
659 };
660
661 #define TYPE_OPENPROM "openprom"
662 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
663
664 typedef struct PROMState {
665 SysBusDevice parent_obj;
666
667 MemoryRegion prom;
668 } PROMState;
669
670 /* Boot PROM (OpenBIOS) */
671 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
672 {
673 hwaddr *base_addr = (hwaddr *)opaque;
674 return addr + *base_addr - PROM_VADDR;
675 }
676
677 static void prom_init(hwaddr addr, const char *bios_name)
678 {
679 DeviceState *dev;
680 SysBusDevice *s;
681 char *filename;
682 int ret;
683
684 dev = qdev_create(NULL, TYPE_OPENPROM);
685 qdev_init_nofail(dev);
686 s = SYS_BUS_DEVICE(dev);
687
688 sysbus_mmio_map(s, 0, addr);
689
690 /* load boot prom */
691 if (bios_name == NULL) {
692 bios_name = PROM_FILENAME;
693 }
694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
695 if (filename) {
696 ret = load_elf(filename, translate_prom_address, &addr, NULL,
697 NULL, NULL, 1, ELF_MACHINE, 0);
698 if (ret < 0 || ret > PROM_SIZE_MAX) {
699 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
700 }
701 g_free(filename);
702 } else {
703 ret = -1;
704 }
705 if (ret < 0 || ret > PROM_SIZE_MAX) {
706 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
707 exit(1);
708 }
709 }
710
711 static int prom_init1(SysBusDevice *dev)
712 {
713 PROMState *s = OPENPROM(dev);
714
715 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX);
716 vmstate_register_ram_global(&s->prom);
717 memory_region_set_readonly(&s->prom, true);
718 sysbus_init_mmio(dev, &s->prom);
719 return 0;
720 }
721
722 static Property prom_properties[] = {
723 {/* end of property list */},
724 };
725
726 static void prom_class_init(ObjectClass *klass, void *data)
727 {
728 DeviceClass *dc = DEVICE_CLASS(klass);
729 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
730
731 k->init = prom_init1;
732 dc->props = prom_properties;
733 }
734
735 static const TypeInfo prom_info = {
736 .name = TYPE_OPENPROM,
737 .parent = TYPE_SYS_BUS_DEVICE,
738 .instance_size = sizeof(PROMState),
739 .class_init = prom_class_init,
740 };
741
742 #define TYPE_SUN4M_MEMORY "memory"
743 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
744
745 typedef struct RamDevice {
746 SysBusDevice parent_obj;
747
748 MemoryRegion ram;
749 uint64_t size;
750 } RamDevice;
751
752 /* System RAM */
753 static int ram_init1(SysBusDevice *dev)
754 {
755 RamDevice *d = SUN4M_RAM(dev);
756
757 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size);
758 vmstate_register_ram_global(&d->ram);
759 sysbus_init_mmio(dev, &d->ram);
760 return 0;
761 }
762
763 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
764 uint64_t max_mem)
765 {
766 DeviceState *dev;
767 SysBusDevice *s;
768 RamDevice *d;
769
770 /* allocate RAM */
771 if ((uint64_t)RAM_size > max_mem) {
772 fprintf(stderr,
773 "qemu: Too much memory for this machine: %d, maximum %d\n",
774 (unsigned int)(RAM_size / (1024 * 1024)),
775 (unsigned int)(max_mem / (1024 * 1024)));
776 exit(1);
777 }
778 dev = qdev_create(NULL, "memory");
779 s = SYS_BUS_DEVICE(dev);
780
781 d = SUN4M_RAM(dev);
782 d->size = RAM_size;
783 qdev_init_nofail(dev);
784
785 sysbus_mmio_map(s, 0, addr);
786 }
787
788 static Property ram_properties[] = {
789 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
790 DEFINE_PROP_END_OF_LIST(),
791 };
792
793 static void ram_class_init(ObjectClass *klass, void *data)
794 {
795 DeviceClass *dc = DEVICE_CLASS(klass);
796 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
797
798 k->init = ram_init1;
799 dc->props = ram_properties;
800 }
801
802 static const TypeInfo ram_info = {
803 .name = TYPE_SUN4M_MEMORY,
804 .parent = TYPE_SYS_BUS_DEVICE,
805 .instance_size = sizeof(RamDevice),
806 .class_init = ram_class_init,
807 };
808
809 static void cpu_devinit(const char *cpu_model, unsigned int id,
810 uint64_t prom_addr, qemu_irq **cpu_irqs)
811 {
812 CPUState *cs;
813 SPARCCPU *cpu;
814 CPUSPARCState *env;
815
816 cpu = cpu_sparc_init(cpu_model);
817 if (cpu == NULL) {
818 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
819 exit(1);
820 }
821 env = &cpu->env;
822
823 cpu_sparc_set_id(env, id);
824 if (id == 0) {
825 qemu_register_reset(main_cpu_reset, cpu);
826 } else {
827 qemu_register_reset(secondary_cpu_reset, cpu);
828 cs = CPU(cpu);
829 cs->halted = 1;
830 }
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void dummy_fdc_tc(void *opaque, int irq, int level)
836 {
837 }
838
839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
840 const char *boot_device,
841 const char *kernel_filename,
842 const char *kernel_cmdline,
843 const char *initrd_filename, const char *cpu_model)
844 {
845 unsigned int i;
846 void *iommu, *espdma, *ledma, *nvram;
847 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
848 espdma_irq, ledma_irq;
849 qemu_irq esp_reset, dma_enable;
850 qemu_irq fdc_tc;
851 qemu_irq *cpu_halt;
852 unsigned long kernel_size;
853 DriveInfo *fd[MAX_FD];
854 FWCfgState *fw_cfg;
855 unsigned int num_vsimms;
856
857 /* init CPUs */
858 if (!cpu_model)
859 cpu_model = hwdef->default_cpu_model;
860
861 for(i = 0; i < smp_cpus; i++) {
862 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
863 }
864
865 for (i = smp_cpus; i < MAX_CPUS; i++)
866 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
867
868
869 /* set up devices */
870 ram_init(0, RAM_size, hwdef->max_mem);
871 /* models without ECC don't trap when missing ram is accessed */
872 if (!hwdef->ecc_base) {
873 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
874 }
875
876 prom_init(hwdef->slavio_base, bios_name);
877
878 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
879 hwdef->intctl_base + 0x10000ULL,
880 cpu_irqs);
881
882 for (i = 0; i < 32; i++) {
883 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
884 }
885 for (i = 0; i < MAX_CPUS; i++) {
886 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
887 }
888
889 if (hwdef->idreg_base) {
890 idreg_init(hwdef->idreg_base);
891 }
892
893 if (hwdef->afx_base) {
894 afx_init(hwdef->afx_base);
895 }
896
897 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
898 slavio_irq[30]);
899
900 if (hwdef->iommu_pad_base) {
901 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
902 Software shouldn't use aliased addresses, neither should it crash
903 when does. Using empty_slot instead of aliasing can help with
904 debugging such accesses */
905 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
906 }
907
908 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
909 iommu, &espdma_irq, 0);
910
911 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
912 slavio_irq[16], iommu, &ledma_irq, 1);
913
914 if (graphic_depth != 8 && graphic_depth != 24) {
915 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
916 exit (1);
917 }
918 num_vsimms = 0;
919 if (num_vsimms == 0) {
920 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
921 graphic_depth);
922 }
923
924 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
925 /* vsimm registers probed by OBP */
926 if (hwdef->vsimm[i].reg_base) {
927 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
928 }
929 }
930
931 if (hwdef->sx_base) {
932 empty_slot_init(hwdef->sx_base, 0x2000);
933 }
934
935 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
936
937 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
938
939 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
940
941 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
942 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
943 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
944 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
945 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
946 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
947
948 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
949 if (hwdef->apc_base) {
950 apc_init(hwdef->apc_base, cpu_halt[0]);
951 }
952
953 if (hwdef->fd_base) {
954 /* there is zero or one floppy drive */
955 memset(fd, 0, sizeof(fd));
956 fd[0] = drive_get(IF_FLOPPY, 0, 0);
957 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
958 &fdc_tc);
959 } else {
960 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
961 }
962
963 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
964 slavio_irq[30], fdc_tc);
965
966 if (drive_get_max_bus(IF_SCSI) > 0) {
967 fprintf(stderr, "qemu: too many SCSI bus\n");
968 exit(1);
969 }
970
971 esp_init(hwdef->esp_base, 2,
972 espdma_memory_read, espdma_memory_write,
973 espdma, espdma_irq, &esp_reset, &dma_enable);
974
975 qdev_connect_gpio_out(espdma, 0, esp_reset);
976 qdev_connect_gpio_out(espdma, 1, dma_enable);
977
978 if (hwdef->cs_base) {
979 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
980 slavio_irq[5]);
981 }
982
983 if (hwdef->dbri_base) {
984 /* ISDN chip with attached CS4215 audio codec */
985 /* prom space */
986 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
987 /* reg space */
988 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
989 }
990
991 if (hwdef->bpp_base) {
992 /* parallel port */
993 empty_slot_init(hwdef->bpp_base, 0x20);
994 }
995
996 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
997 RAM_size);
998
999 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1000 boot_device, RAM_size, kernel_size, graphic_width,
1001 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1002 "Sun4m");
1003
1004 if (hwdef->ecc_base)
1005 ecc_init(hwdef->ecc_base, slavio_irq[28],
1006 hwdef->ecc_version);
1007
1008 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1009 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1010 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1011 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1013 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1014 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1015 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1017 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1018 if (kernel_cmdline) {
1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1020 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1021 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1022 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1023 strlen(kernel_cmdline) + 1);
1024 } else {
1025 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1026 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1027 }
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1029 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1030 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1031 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1032 }
1033
1034 enum {
1035 ss5_id = 32,
1036 vger_id,
1037 lx_id,
1038 ss4_id,
1039 scls_id,
1040 sbook_id,
1041 ss10_id = 64,
1042 ss20_id,
1043 ss600mp_id,
1044 };
1045
1046 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1047 /* SS-5 */
1048 {
1049 .iommu_base = 0x10000000,
1050 .iommu_pad_base = 0x10004000,
1051 .iommu_pad_len = 0x0fffb000,
1052 .tcx_base = 0x50000000,
1053 .cs_base = 0x6c000000,
1054 .slavio_base = 0x70000000,
1055 .ms_kb_base = 0x71000000,
1056 .serial_base = 0x71100000,
1057 .nvram_base = 0x71200000,
1058 .fd_base = 0x71400000,
1059 .counter_base = 0x71d00000,
1060 .intctl_base = 0x71e00000,
1061 .idreg_base = 0x78000000,
1062 .dma_base = 0x78400000,
1063 .esp_base = 0x78800000,
1064 .le_base = 0x78c00000,
1065 .apc_base = 0x6a000000,
1066 .afx_base = 0x6e000000,
1067 .aux1_base = 0x71900000,
1068 .aux2_base = 0x71910000,
1069 .nvram_machine_id = 0x80,
1070 .machine_id = ss5_id,
1071 .iommu_version = 0x05000000,
1072 .max_mem = 0x10000000,
1073 .default_cpu_model = "Fujitsu MB86904",
1074 },
1075 /* SS-10 */
1076 {
1077 .iommu_base = 0xfe0000000ULL,
1078 .tcx_base = 0xe20000000ULL,
1079 .slavio_base = 0xff0000000ULL,
1080 .ms_kb_base = 0xff1000000ULL,
1081 .serial_base = 0xff1100000ULL,
1082 .nvram_base = 0xff1200000ULL,
1083 .fd_base = 0xff1700000ULL,
1084 .counter_base = 0xff1300000ULL,
1085 .intctl_base = 0xff1400000ULL,
1086 .idreg_base = 0xef0000000ULL,
1087 .dma_base = 0xef0400000ULL,
1088 .esp_base = 0xef0800000ULL,
1089 .le_base = 0xef0c00000ULL,
1090 .apc_base = 0xefa000000ULL, // XXX should not exist
1091 .aux1_base = 0xff1800000ULL,
1092 .aux2_base = 0xff1a01000ULL,
1093 .ecc_base = 0xf00000000ULL,
1094 .ecc_version = 0x10000000, // version 0, implementation 1
1095 .nvram_machine_id = 0x72,
1096 .machine_id = ss10_id,
1097 .iommu_version = 0x03000000,
1098 .max_mem = 0xf00000000ULL,
1099 .default_cpu_model = "TI SuperSparc II",
1100 },
1101 /* SS-600MP */
1102 {
1103 .iommu_base = 0xfe0000000ULL,
1104 .tcx_base = 0xe20000000ULL,
1105 .slavio_base = 0xff0000000ULL,
1106 .ms_kb_base = 0xff1000000ULL,
1107 .serial_base = 0xff1100000ULL,
1108 .nvram_base = 0xff1200000ULL,
1109 .counter_base = 0xff1300000ULL,
1110 .intctl_base = 0xff1400000ULL,
1111 .dma_base = 0xef0081000ULL,
1112 .esp_base = 0xef0080000ULL,
1113 .le_base = 0xef0060000ULL,
1114 .apc_base = 0xefa000000ULL, // XXX should not exist
1115 .aux1_base = 0xff1800000ULL,
1116 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1117 .ecc_base = 0xf00000000ULL,
1118 .ecc_version = 0x00000000, // version 0, implementation 0
1119 .nvram_machine_id = 0x71,
1120 .machine_id = ss600mp_id,
1121 .iommu_version = 0x01000000,
1122 .max_mem = 0xf00000000ULL,
1123 .default_cpu_model = "TI SuperSparc II",
1124 },
1125 /* SS-20 */
1126 {
1127 .iommu_base = 0xfe0000000ULL,
1128 .tcx_base = 0xe20000000ULL,
1129 .slavio_base = 0xff0000000ULL,
1130 .ms_kb_base = 0xff1000000ULL,
1131 .serial_base = 0xff1100000ULL,
1132 .nvram_base = 0xff1200000ULL,
1133 .fd_base = 0xff1700000ULL,
1134 .counter_base = 0xff1300000ULL,
1135 .intctl_base = 0xff1400000ULL,
1136 .idreg_base = 0xef0000000ULL,
1137 .dma_base = 0xef0400000ULL,
1138 .esp_base = 0xef0800000ULL,
1139 .le_base = 0xef0c00000ULL,
1140 .bpp_base = 0xef4800000ULL,
1141 .apc_base = 0xefa000000ULL, // XXX should not exist
1142 .aux1_base = 0xff1800000ULL,
1143 .aux2_base = 0xff1a01000ULL,
1144 .dbri_base = 0xee0000000ULL,
1145 .sx_base = 0xf80000000ULL,
1146 .vsimm = {
1147 {
1148 .reg_base = 0x9c000000ULL,
1149 .vram_base = 0xfc000000ULL
1150 }, {
1151 .reg_base = 0x90000000ULL,
1152 .vram_base = 0xf0000000ULL
1153 }, {
1154 .reg_base = 0x94000000ULL
1155 }, {
1156 .reg_base = 0x98000000ULL
1157 }
1158 },
1159 .ecc_base = 0xf00000000ULL,
1160 .ecc_version = 0x20000000, // version 0, implementation 2
1161 .nvram_machine_id = 0x72,
1162 .machine_id = ss20_id,
1163 .iommu_version = 0x13000000,
1164 .max_mem = 0xf00000000ULL,
1165 .default_cpu_model = "TI SuperSparc II",
1166 },
1167 /* Voyager */
1168 {
1169 .iommu_base = 0x10000000,
1170 .tcx_base = 0x50000000,
1171 .slavio_base = 0x70000000,
1172 .ms_kb_base = 0x71000000,
1173 .serial_base = 0x71100000,
1174 .nvram_base = 0x71200000,
1175 .fd_base = 0x71400000,
1176 .counter_base = 0x71d00000,
1177 .intctl_base = 0x71e00000,
1178 .idreg_base = 0x78000000,
1179 .dma_base = 0x78400000,
1180 .esp_base = 0x78800000,
1181 .le_base = 0x78c00000,
1182 .apc_base = 0x71300000, // pmc
1183 .aux1_base = 0x71900000,
1184 .aux2_base = 0x71910000,
1185 .nvram_machine_id = 0x80,
1186 .machine_id = vger_id,
1187 .iommu_version = 0x05000000,
1188 .max_mem = 0x10000000,
1189 .default_cpu_model = "Fujitsu MB86904",
1190 },
1191 /* LX */
1192 {
1193 .iommu_base = 0x10000000,
1194 .iommu_pad_base = 0x10004000,
1195 .iommu_pad_len = 0x0fffb000,
1196 .tcx_base = 0x50000000,
1197 .slavio_base = 0x70000000,
1198 .ms_kb_base = 0x71000000,
1199 .serial_base = 0x71100000,
1200 .nvram_base = 0x71200000,
1201 .fd_base = 0x71400000,
1202 .counter_base = 0x71d00000,
1203 .intctl_base = 0x71e00000,
1204 .idreg_base = 0x78000000,
1205 .dma_base = 0x78400000,
1206 .esp_base = 0x78800000,
1207 .le_base = 0x78c00000,
1208 .aux1_base = 0x71900000,
1209 .aux2_base = 0x71910000,
1210 .nvram_machine_id = 0x80,
1211 .machine_id = lx_id,
1212 .iommu_version = 0x04000000,
1213 .max_mem = 0x10000000,
1214 .default_cpu_model = "TI MicroSparc I",
1215 },
1216 /* SS-4 */
1217 {
1218 .iommu_base = 0x10000000,
1219 .tcx_base = 0x50000000,
1220 .cs_base = 0x6c000000,
1221 .slavio_base = 0x70000000,
1222 .ms_kb_base = 0x71000000,
1223 .serial_base = 0x71100000,
1224 .nvram_base = 0x71200000,
1225 .fd_base = 0x71400000,
1226 .counter_base = 0x71d00000,
1227 .intctl_base = 0x71e00000,
1228 .idreg_base = 0x78000000,
1229 .dma_base = 0x78400000,
1230 .esp_base = 0x78800000,
1231 .le_base = 0x78c00000,
1232 .apc_base = 0x6a000000,
1233 .aux1_base = 0x71900000,
1234 .aux2_base = 0x71910000,
1235 .nvram_machine_id = 0x80,
1236 .machine_id = ss4_id,
1237 .iommu_version = 0x05000000,
1238 .max_mem = 0x10000000,
1239 .default_cpu_model = "Fujitsu MB86904",
1240 },
1241 /* SPARCClassic */
1242 {
1243 .iommu_base = 0x10000000,
1244 .tcx_base = 0x50000000,
1245 .slavio_base = 0x70000000,
1246 .ms_kb_base = 0x71000000,
1247 .serial_base = 0x71100000,
1248 .nvram_base = 0x71200000,
1249 .fd_base = 0x71400000,
1250 .counter_base = 0x71d00000,
1251 .intctl_base = 0x71e00000,
1252 .idreg_base = 0x78000000,
1253 .dma_base = 0x78400000,
1254 .esp_base = 0x78800000,
1255 .le_base = 0x78c00000,
1256 .apc_base = 0x6a000000,
1257 .aux1_base = 0x71900000,
1258 .aux2_base = 0x71910000,
1259 .nvram_machine_id = 0x80,
1260 .machine_id = scls_id,
1261 .iommu_version = 0x05000000,
1262 .max_mem = 0x10000000,
1263 .default_cpu_model = "TI MicroSparc I",
1264 },
1265 /* SPARCbook */
1266 {
1267 .iommu_base = 0x10000000,
1268 .tcx_base = 0x50000000, // XXX
1269 .slavio_base = 0x70000000,
1270 .ms_kb_base = 0x71000000,
1271 .serial_base = 0x71100000,
1272 .nvram_base = 0x71200000,
1273 .fd_base = 0x71400000,
1274 .counter_base = 0x71d00000,
1275 .intctl_base = 0x71e00000,
1276 .idreg_base = 0x78000000,
1277 .dma_base = 0x78400000,
1278 .esp_base = 0x78800000,
1279 .le_base = 0x78c00000,
1280 .apc_base = 0x6a000000,
1281 .aux1_base = 0x71900000,
1282 .aux2_base = 0x71910000,
1283 .nvram_machine_id = 0x80,
1284 .machine_id = sbook_id,
1285 .iommu_version = 0x05000000,
1286 .max_mem = 0x10000000,
1287 .default_cpu_model = "TI MicroSparc I",
1288 },
1289 };
1290
1291 /* SPARCstation 5 hardware initialisation */
1292 static void ss5_init(QEMUMachineInitArgs *args)
1293 {
1294 ram_addr_t RAM_size = args->ram_size;
1295 const char *cpu_model = args->cpu_model;
1296 const char *kernel_filename = args->kernel_filename;
1297 const char *kernel_cmdline = args->kernel_cmdline;
1298 const char *initrd_filename = args->initrd_filename;
1299 const char *boot_device = args->boot_device;
1300 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1301 kernel_cmdline, initrd_filename, cpu_model);
1302 }
1303
1304 /* SPARCstation 10 hardware initialisation */
1305 static void ss10_init(QEMUMachineInitArgs *args)
1306 {
1307 ram_addr_t RAM_size = args->ram_size;
1308 const char *cpu_model = args->cpu_model;
1309 const char *kernel_filename = args->kernel_filename;
1310 const char *kernel_cmdline = args->kernel_cmdline;
1311 const char *initrd_filename = args->initrd_filename;
1312 const char *boot_device = args->boot_device;
1313 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1314 kernel_cmdline, initrd_filename, cpu_model);
1315 }
1316
1317 /* SPARCserver 600MP hardware initialisation */
1318 static void ss600mp_init(QEMUMachineInitArgs *args)
1319 {
1320 ram_addr_t RAM_size = args->ram_size;
1321 const char *cpu_model = args->cpu_model;
1322 const char *kernel_filename = args->kernel_filename;
1323 const char *kernel_cmdline = args->kernel_cmdline;
1324 const char *initrd_filename = args->initrd_filename;
1325 const char *boot_device = args->boot_device;
1326 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1327 kernel_cmdline, initrd_filename, cpu_model);
1328 }
1329
1330 /* SPARCstation 20 hardware initialisation */
1331 static void ss20_init(QEMUMachineInitArgs *args)
1332 {
1333 ram_addr_t RAM_size = args->ram_size;
1334 const char *cpu_model = args->cpu_model;
1335 const char *kernel_filename = args->kernel_filename;
1336 const char *kernel_cmdline = args->kernel_cmdline;
1337 const char *initrd_filename = args->initrd_filename;
1338 const char *boot_device = args->boot_device;
1339 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1340 kernel_cmdline, initrd_filename, cpu_model);
1341 }
1342
1343 /* SPARCstation Voyager hardware initialisation */
1344 static void vger_init(QEMUMachineInitArgs *args)
1345 {
1346 ram_addr_t RAM_size = args->ram_size;
1347 const char *cpu_model = args->cpu_model;
1348 const char *kernel_filename = args->kernel_filename;
1349 const char *kernel_cmdline = args->kernel_cmdline;
1350 const char *initrd_filename = args->initrd_filename;
1351 const char *boot_device = args->boot_device;
1352 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1353 kernel_cmdline, initrd_filename, cpu_model);
1354 }
1355
1356 /* SPARCstation LX hardware initialisation */
1357 static void ss_lx_init(QEMUMachineInitArgs *args)
1358 {
1359 ram_addr_t RAM_size = args->ram_size;
1360 const char *cpu_model = args->cpu_model;
1361 const char *kernel_filename = args->kernel_filename;
1362 const char *kernel_cmdline = args->kernel_cmdline;
1363 const char *initrd_filename = args->initrd_filename;
1364 const char *boot_device = args->boot_device;
1365 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1366 kernel_cmdline, initrd_filename, cpu_model);
1367 }
1368
1369 /* SPARCstation 4 hardware initialisation */
1370 static void ss4_init(QEMUMachineInitArgs *args)
1371 {
1372 ram_addr_t RAM_size = args->ram_size;
1373 const char *cpu_model = args->cpu_model;
1374 const char *kernel_filename = args->kernel_filename;
1375 const char *kernel_cmdline = args->kernel_cmdline;
1376 const char *initrd_filename = args->initrd_filename;
1377 const char *boot_device = args->boot_device;
1378 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1379 kernel_cmdline, initrd_filename, cpu_model);
1380 }
1381
1382 /* SPARCClassic hardware initialisation */
1383 static void scls_init(QEMUMachineInitArgs *args)
1384 {
1385 ram_addr_t RAM_size = args->ram_size;
1386 const char *cpu_model = args->cpu_model;
1387 const char *kernel_filename = args->kernel_filename;
1388 const char *kernel_cmdline = args->kernel_cmdline;
1389 const char *initrd_filename = args->initrd_filename;
1390 const char *boot_device = args->boot_device;
1391 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1392 kernel_cmdline, initrd_filename, cpu_model);
1393 }
1394
1395 /* SPARCbook hardware initialisation */
1396 static void sbook_init(QEMUMachineInitArgs *args)
1397 {
1398 ram_addr_t RAM_size = args->ram_size;
1399 const char *cpu_model = args->cpu_model;
1400 const char *kernel_filename = args->kernel_filename;
1401 const char *kernel_cmdline = args->kernel_cmdline;
1402 const char *initrd_filename = args->initrd_filename;
1403 const char *boot_device = args->boot_device;
1404 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1405 kernel_cmdline, initrd_filename, cpu_model);
1406 }
1407
1408 static QEMUMachine ss5_machine = {
1409 .name = "SS-5",
1410 .desc = "Sun4m platform, SPARCstation 5",
1411 .init = ss5_init,
1412 .block_default_type = IF_SCSI,
1413 .is_default = 1,
1414 DEFAULT_MACHINE_OPTIONS,
1415 };
1416
1417 static QEMUMachine ss10_machine = {
1418 .name = "SS-10",
1419 .desc = "Sun4m platform, SPARCstation 10",
1420 .init = ss10_init,
1421 .block_default_type = IF_SCSI,
1422 .max_cpus = 4,
1423 DEFAULT_MACHINE_OPTIONS,
1424 };
1425
1426 static QEMUMachine ss600mp_machine = {
1427 .name = "SS-600MP",
1428 .desc = "Sun4m platform, SPARCserver 600MP",
1429 .init = ss600mp_init,
1430 .block_default_type = IF_SCSI,
1431 .max_cpus = 4,
1432 DEFAULT_MACHINE_OPTIONS,
1433 };
1434
1435 static QEMUMachine ss20_machine = {
1436 .name = "SS-20",
1437 .desc = "Sun4m platform, SPARCstation 20",
1438 .init = ss20_init,
1439 .block_default_type = IF_SCSI,
1440 .max_cpus = 4,
1441 DEFAULT_MACHINE_OPTIONS,
1442 };
1443
1444 static QEMUMachine voyager_machine = {
1445 .name = "Voyager",
1446 .desc = "Sun4m platform, SPARCstation Voyager",
1447 .init = vger_init,
1448 .block_default_type = IF_SCSI,
1449 DEFAULT_MACHINE_OPTIONS,
1450 };
1451
1452 static QEMUMachine ss_lx_machine = {
1453 .name = "LX",
1454 .desc = "Sun4m platform, SPARCstation LX",
1455 .init = ss_lx_init,
1456 .block_default_type = IF_SCSI,
1457 DEFAULT_MACHINE_OPTIONS,
1458 };
1459
1460 static QEMUMachine ss4_machine = {
1461 .name = "SS-4",
1462 .desc = "Sun4m platform, SPARCstation 4",
1463 .init = ss4_init,
1464 .block_default_type = IF_SCSI,
1465 DEFAULT_MACHINE_OPTIONS,
1466 };
1467
1468 static QEMUMachine scls_machine = {
1469 .name = "SPARCClassic",
1470 .desc = "Sun4m platform, SPARCClassic",
1471 .init = scls_init,
1472 .block_default_type = IF_SCSI,
1473 DEFAULT_MACHINE_OPTIONS,
1474 };
1475
1476 static QEMUMachine sbook_machine = {
1477 .name = "SPARCbook",
1478 .desc = "Sun4m platform, SPARCbook",
1479 .init = sbook_init,
1480 .block_default_type = IF_SCSI,
1481 DEFAULT_MACHINE_OPTIONS,
1482 };
1483
1484 static void sun4m_register_types(void)
1485 {
1486 type_register_static(&idreg_info);
1487 type_register_static(&afx_info);
1488 type_register_static(&prom_info);
1489 type_register_static(&ram_info);
1490 }
1491
1492 static void sun4m_machine_init(void)
1493 {
1494 qemu_register_machine(&ss5_machine);
1495 qemu_register_machine(&ss10_machine);
1496 qemu_register_machine(&ss600mp_machine);
1497 qemu_register_machine(&ss20_machine);
1498 qemu_register_machine(&voyager_machine);
1499 qemu_register_machine(&ss_lx_machine);
1500 qemu_register_machine(&ss4_machine);
1501 qemu_register_machine(&scls_machine);
1502 qemu_register_machine(&sbook_machine);
1503 }
1504
1505 type_init(sun4m_register_types)
1506 machine_init(sun4m_machine_init);
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