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spice: fix display initialization
[qemu/kevin.git] / hw / pci-host / piix.c
blobdc1718fe302a826f8accfa652dfeddacef98d968
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw/hw.h"
26 #include "hw/i386/pc.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/isa/isa.h"
30 #include "hw/sysbus.h"
31 #include "qemu/range.h"
32 #include "hw/xen/xen.h"
33 #include "hw/pci-host/pam.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/i386/ioapic.h"
36 #include "qapi/visitor.h"
37
38 /*
39 * I440FX chipset data sheet.
40 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
41 */
42
43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
44 #define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
46
47 typedef struct I440FXState {
48 PCIHostState parent_obj;
49 PcPciInfo pci_info;
50 uint64_t pci_hole64_size;
51 } I440FXState;
52
53 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
54 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
55 #define XEN_PIIX_NUM_PIRQS 128ULL
56 #define PIIX_PIRQC 0x60
57
58 /*
59 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
60 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
61 */
62 #define RCR_IOPORT 0xcf9
63
64 typedef struct PIIX3State {
65 PCIDevice dev;
66
67 /*
68 * bitmap to track pic levels.
69 * The pic level is the logical OR of all the PCI irqs mapped to it
70 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
71 *
72 * PIRQ is mapped to PIC pins, we track it by
73 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
74 * pic_irq * PIIX_NUM_PIRQS + pirq
75 */
76 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
77 #error "unable to encode pic state in 64bit in pic_levels."
78 #endif
79 uint64_t pic_levels;
80
81 qemu_irq *pic;
82
83 /* This member isn't used. Just for save/load compatibility */
84 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
85
86 /* Reset Control Register contents */
87 uint8_t rcr;
88
89 /* IO memory region for Reset Control Register (RCR_IOPORT) */
90 MemoryRegion rcr_mem;
91 } PIIX3State;
92
93 #define TYPE_I440FX_PCI_DEVICE "i440FX"
94 #define I440FX_PCI_DEVICE(obj) \
95 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
96
97 struct PCII440FXState {
98 /*< private >*/
99 PCIDevice parent_obj;
100 /*< public >*/
101
102 MemoryRegion *system_memory;
103 MemoryRegion *pci_address_space;
104 MemoryRegion *ram_memory;
105 MemoryRegion pci_hole;
106 MemoryRegion pci_hole_64bit;
107 PAMMemoryRegion pam_regions[13];
108 MemoryRegion smram_region;
109 uint8_t smm_enabled;
110 };
111
112
113 #define I440FX_PAM 0x59
114 #define I440FX_PAM_SIZE 7
115 #define I440FX_SMRAM 0x72
116
117 static void piix3_set_irq(void *opaque, int pirq, int level);
118 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
119 static void piix3_write_config_xen(PCIDevice *dev,
120 uint32_t address, uint32_t val, int len);
121
122 /* return the global irq number corresponding to a given device irq
123 pin. We could also use the bus number to have a more precise
124 mapping. */
125 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
126 {
127 int slot_addend;
128 slot_addend = (pci_dev->devfn >> 3) - 1;
129 return (pci_intx + slot_addend) & 3;
130 }
131
132 static void i440fx_update_memory_mappings(PCII440FXState *d)
133 {
134 int i;
135 PCIDevice *pd = PCI_DEVICE(d);
136
137 memory_region_transaction_begin();
138 for (i = 0; i < 13; i++) {
139 pam_update(&d->pam_regions[i], i,
140 pd->config[I440FX_PAM + ((i + 1) / 2)]);
141 }
142 smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
143 memory_region_transaction_commit();
144 }
145
146 static void i440fx_set_smm(int val, void *arg)
147 {
148 PCII440FXState *d = arg;
149 PCIDevice *pd = PCI_DEVICE(d);
150
151 memory_region_transaction_begin();
152 smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
153 &d->smram_region);
154 memory_region_transaction_commit();
155 }
156
157
158 static void i440fx_write_config(PCIDevice *dev,
159 uint32_t address, uint32_t val, int len)
160 {
161 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
162
163 /* XXX: implement SMRAM.D_LOCK */
164 pci_default_write_config(dev, address, val, len);
165 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
166 range_covers_byte(address, len, I440FX_SMRAM)) {
167 i440fx_update_memory_mappings(d);
168 }
169 }
170
171 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
172 {
173 PCII440FXState *d = opaque;
174 PCIDevice *pd = PCI_DEVICE(d);
175 int ret, i;
176
177 ret = pci_device_load(pd, f);
178 if (ret < 0)
179 return ret;
180 i440fx_update_memory_mappings(d);
181 qemu_get_8s(f, &d->smm_enabled);
182
183 if (version_id == 2) {
184 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
185 qemu_get_be32(f); /* dummy load for compatibility */
186 }
187 }
188
189 return 0;
190 }
191
192 static int i440fx_post_load(void *opaque, int version_id)
193 {
194 PCII440FXState *d = opaque;
195
196 i440fx_update_memory_mappings(d);
197 return 0;
198 }
199
200 static const VMStateDescription vmstate_i440fx = {
201 .name = "I440FX",
202 .version_id = 3,
203 .minimum_version_id = 3,
204 .minimum_version_id_old = 1,
205 .load_state_old = i440fx_load_old,
206 .post_load = i440fx_post_load,
207 .fields = (VMStateField []) {
208 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
209 VMSTATE_UINT8(smm_enabled, PCII440FXState),
210 VMSTATE_END_OF_LIST()
211 }
212 };
213
214 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
215 void *opaque, const char *name,
216 Error **errp)
217 {
218 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
219 uint32_t value = s->pci_info.w32.begin;
220
221 visit_type_uint32(v, &value, name, errp);
222 }
223
224 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
225 void *opaque, const char *name,
226 Error **errp)
227 {
228 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
229 uint32_t value = s->pci_info.w32.end;
230
231 visit_type_uint32(v, &value, name, errp);
232 }
233
234 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
235 void *opaque, const char *name,
236 Error **errp)
237 {
238 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
239
240 visit_type_uint64(v, &s->pci_info.w64.begin, name, errp);
241 }
242
243 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
244 void *opaque, const char *name,
245 Error **errp)
246 {
247 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
248
249 visit_type_uint64(v, &s->pci_info.w64.end, name, errp);
250 }
251
252 static void i440fx_pcihost_initfn(Object *obj)
253 {
254 PCIHostState *s = PCI_HOST_BRIDGE(obj);
255 I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
256
257 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
258 "pci-conf-idx", 4);
259 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
260 "pci-conf-data", 4);
261
262 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
263 i440fx_pcihost_get_pci_hole_start,
264 NULL, NULL, NULL, NULL);
265
266 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
267 i440fx_pcihost_get_pci_hole_end,
268 NULL, NULL, NULL, NULL);
269
270 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
271 i440fx_pcihost_get_pci_hole64_start,
272 NULL, NULL, NULL, NULL);
273
274 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
275 i440fx_pcihost_get_pci_hole64_end,
276 NULL, NULL, NULL, NULL);
277
278 d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
279 }
280
281 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
282 {
283 PCIHostState *s = PCI_HOST_BRIDGE(dev);
284 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
285
286 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
287 sysbus_init_ioports(sbd, 0xcf8, 4);
288
289 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
290 sysbus_init_ioports(sbd, 0xcfc, 4);
291 }
292
293 static int i440fx_initfn(PCIDevice *dev)
294 {
295 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
296
297 dev->config[I440FX_SMRAM] = 0x02;
298
299 cpu_smm_register(&i440fx_set_smm, d);
300 return 0;
301 }
302
303 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
304 int *piix3_devfn,
305 ISABus **isa_bus, qemu_irq *pic,
306 MemoryRegion *address_space_mem,
307 MemoryRegion *address_space_io,
308 ram_addr_t ram_size,
309 hwaddr pci_hole_start,
310 hwaddr pci_hole_size,
311 ram_addr_t above_4g_mem_size,
312 MemoryRegion *pci_address_space,
313 MemoryRegion *ram_memory)
314 {
315 DeviceState *dev;
316 PCIBus *b;
317 PCIDevice *d;
318 PCIHostState *s;
319 PIIX3State *piix3;
320 PCII440FXState *f;
321 unsigned i;
322 I440FXState *i440fx;
323
324 dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
325 s = PCI_HOST_BRIDGE(dev);
326 b = pci_bus_new(dev, NULL, pci_address_space,
327 address_space_io, 0, TYPE_PCI_BUS);
328 s->bus = b;
329 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
330 qdev_init_nofail(dev);
331
332 d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
333 *pi440fx_state = I440FX_PCI_DEVICE(d);
334 f = *pi440fx_state;
335 f->system_memory = address_space_mem;
336 f->pci_address_space = pci_address_space;
337 f->ram_memory = ram_memory;
338
339 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
340 /* Set PCI window size the way seabios has always done it. */
341 /* Power of 2 so bios can cover it with a single MTRR */
342 if (ram_size <= 0x80000000) {
343 i440fx->pci_info.w32.begin = 0x80000000;
344 } else if (ram_size <= 0xc0000000) {
345 i440fx->pci_info.w32.begin = 0xc0000000;
346 } else {
347 i440fx->pci_info.w32.begin = 0xe0000000;
348 }
349
350 memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
351 pci_hole_start, pci_hole_size);
352 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
353
354 pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
355 i440fx->pci_hole64_size);
356 memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
357 f->pci_address_space,
358 i440fx->pci_info.w64.begin,
359 i440fx->pci_hole64_size);
360 if (i440fx->pci_hole64_size) {
361 memory_region_add_subregion(f->system_memory,
362 i440fx->pci_info.w64.begin,
363 &f->pci_hole_64bit);
364 }
365 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
366 f->pci_address_space, 0xa0000, 0x20000);
367 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
368 &f->smram_region, 1);
369 memory_region_set_enabled(&f->smram_region, false);
370 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
371 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
372 for (i = 0; i < 12; ++i) {
373 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
374 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
375 PAM_EXPAN_SIZE);
376 }
377
378 /* Xen supports additional interrupt routes from the PCI devices to
379 * the IOAPIC: the four pins of each PCI device on the bus are also
380 * connected to the IOAPIC directly.
381 * These additional routes can be discovered through ACPI. */
382 if (xen_enabled()) {
383 piix3 = DO_UPCAST(PIIX3State, dev,
384 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
385 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
386 piix3, XEN_PIIX_NUM_PIRQS);
387 } else {
388 piix3 = DO_UPCAST(PIIX3State, dev,
389 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
390 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
391 PIIX_NUM_PIRQS);
392 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
393 }
394 piix3->pic = pic;
395 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
396
397 *piix3_devfn = piix3->dev.devfn;
398
399 ram_size = ram_size / 8 / 1024 / 1024;
400 if (ram_size > 255) {
401 ram_size = 255;
402 }
403 d->config[0x57] = ram_size;
404
405 i440fx_update_memory_mappings(f);
406
407 return b;
408 }
409
410 /* PIIX3 PCI to ISA bridge */
411 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
412 {
413 qemu_set_irq(piix3->pic[pic_irq],
414 !!(piix3->pic_levels &
415 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
416 (pic_irq * PIIX_NUM_PIRQS))));
417 }
418
419 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
420 {
421 int pic_irq;
422 uint64_t mask;
423
424 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
425 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
426 return;
427 }
428
429 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
430 piix3->pic_levels &= ~mask;
431 piix3->pic_levels |= mask * !!level;
432
433 piix3_set_irq_pic(piix3, pic_irq);
434 }
435
436 static void piix3_set_irq(void *opaque, int pirq, int level)
437 {
438 PIIX3State *piix3 = opaque;
439 piix3_set_irq_level(piix3, pirq, level);
440 }
441
442 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
443 {
444 PIIX3State *piix3 = opaque;
445 int irq = piix3->dev.config[PIIX_PIRQC + pin];
446 PCIINTxRoute route;
447
448 if (irq < PIIX_NUM_PIC_IRQS) {
449 route.mode = PCI_INTX_ENABLED;
450 route.irq = irq;
451 } else {
452 route.mode = PCI_INTX_DISABLED;
453 route.irq = -1;
454 }
455 return route;
456 }
457
458 /* irq routing is changed. so rebuild bitmap */
459 static void piix3_update_irq_levels(PIIX3State *piix3)
460 {
461 int pirq;
462
463 piix3->pic_levels = 0;
464 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
465 piix3_set_irq_level(piix3, pirq,
466 pci_bus_get_irq_level(piix3->dev.bus, pirq));
467 }
468 }
469
470 static void piix3_write_config(PCIDevice *dev,
471 uint32_t address, uint32_t val, int len)
472 {
473 pci_default_write_config(dev, address, val, len);
474 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
475 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
476 int pic_irq;
477
478 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
479 piix3_update_irq_levels(piix3);
480 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
481 piix3_set_irq_pic(piix3, pic_irq);
482 }
483 }
484 }
485
486 static void piix3_write_config_xen(PCIDevice *dev,
487 uint32_t address, uint32_t val, int len)
488 {
489 xen_piix_pci_write_config_client(address, val, len);
490 piix3_write_config(dev, address, val, len);
491 }
492
493 static void piix3_reset(void *opaque)
494 {
495 PIIX3State *d = opaque;
496 uint8_t *pci_conf = d->dev.config;
497
498 pci_conf[0x04] = 0x07; /* master, memory and I/O */
499 pci_conf[0x05] = 0x00;
500 pci_conf[0x06] = 0x00;
501 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
502 pci_conf[0x4c] = 0x4d;
503 pci_conf[0x4e] = 0x03;
504 pci_conf[0x4f] = 0x00;
505 pci_conf[0x60] = 0x80;
506 pci_conf[0x61] = 0x80;
507 pci_conf[0x62] = 0x80;
508 pci_conf[0x63] = 0x80;
509 pci_conf[0x69] = 0x02;
510 pci_conf[0x70] = 0x80;
511 pci_conf[0x76] = 0x0c;
512 pci_conf[0x77] = 0x0c;
513 pci_conf[0x78] = 0x02;
514 pci_conf[0x79] = 0x00;
515 pci_conf[0x80] = 0x00;
516 pci_conf[0x82] = 0x00;
517 pci_conf[0xa0] = 0x08;
518 pci_conf[0xa2] = 0x00;
519 pci_conf[0xa3] = 0x00;
520 pci_conf[0xa4] = 0x00;
521 pci_conf[0xa5] = 0x00;
522 pci_conf[0xa6] = 0x00;
523 pci_conf[0xa7] = 0x00;
524 pci_conf[0xa8] = 0x0f;
525 pci_conf[0xaa] = 0x00;
526 pci_conf[0xab] = 0x00;
527 pci_conf[0xac] = 0x00;
528 pci_conf[0xae] = 0x00;
529
530 d->pic_levels = 0;
531 d->rcr = 0;
532 }
533
534 static int piix3_post_load(void *opaque, int version_id)
535 {
536 PIIX3State *piix3 = opaque;
537 piix3_update_irq_levels(piix3);
538 return 0;
539 }
540
541 static void piix3_pre_save(void *opaque)
542 {
543 int i;
544 PIIX3State *piix3 = opaque;
545
546 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
547 piix3->pci_irq_levels_vmstate[i] =
548 pci_bus_get_irq_level(piix3->dev.bus, i);
549 }
550 }
551
552 static bool piix3_rcr_needed(void *opaque)
553 {
554 PIIX3State *piix3 = opaque;
555
556 return (piix3->rcr != 0);
557 }
558
559 static const VMStateDescription vmstate_piix3_rcr = {
560 .name = "PIIX3/rcr",
561 .version_id = 1,
562 .minimum_version_id = 1,
563 .fields = (VMStateField []) {
564 VMSTATE_UINT8(rcr, PIIX3State),
565 VMSTATE_END_OF_LIST()
566 }
567 };
568
569 static const VMStateDescription vmstate_piix3 = {
570 .name = "PIIX3",
571 .version_id = 3,
572 .minimum_version_id = 2,
573 .minimum_version_id_old = 2,
574 .post_load = piix3_post_load,
575 .pre_save = piix3_pre_save,
576 .fields = (VMStateField[]) {
577 VMSTATE_PCI_DEVICE(dev, PIIX3State),
578 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
579 PIIX_NUM_PIRQS, 3),
580 VMSTATE_END_OF_LIST()
581 },
582 .subsections = (VMStateSubsection[]) {
583 {
584 .vmsd = &vmstate_piix3_rcr,
585 .needed = piix3_rcr_needed,
586 },
587 { 0 }
588 }
589 };
590
591
592 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
593 {
594 PIIX3State *d = opaque;
595
596 if (val & 4) {
597 qemu_system_reset_request();
598 return;
599 }
600 d->rcr = val & 2; /* keep System Reset type only */
601 }
602
603 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
604 {
605 PIIX3State *d = opaque;
606
607 return d->rcr;
608 }
609
610 static const MemoryRegionOps rcr_ops = {
611 .read = rcr_read,
612 .write = rcr_write,
613 .endianness = DEVICE_LITTLE_ENDIAN
614 };
615
616 static int piix3_initfn(PCIDevice *dev)
617 {
618 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
619
620 isa_bus_new(DEVICE(d), pci_address_space_io(dev));
621
622 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
623 "piix3-reset-control", 1);
624 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
625 &d->rcr_mem, 1);
626
627 qemu_register_reset(piix3_reset, d);
628 return 0;
629 }
630
631 static void piix3_class_init(ObjectClass *klass, void *data)
632 {
633 DeviceClass *dc = DEVICE_CLASS(klass);
634 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
635
636 dc->desc = "ISA bridge";
637 dc->vmsd = &vmstate_piix3;
638 dc->no_user = 1,
639 k->no_hotplug = 1;
640 k->init = piix3_initfn;
641 k->config_write = piix3_write_config;
642 k->vendor_id = PCI_VENDOR_ID_INTEL;
643 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
644 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
645 k->class_id = PCI_CLASS_BRIDGE_ISA;
646 }
647
648 static const TypeInfo piix3_info = {
649 .name = "PIIX3",
650 .parent = TYPE_PCI_DEVICE,
651 .instance_size = sizeof(PIIX3State),
652 .class_init = piix3_class_init,
653 };
654
655 static void piix3_xen_class_init(ObjectClass *klass, void *data)
656 {
657 DeviceClass *dc = DEVICE_CLASS(klass);
658 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
659
660 dc->desc = "ISA bridge";
661 dc->vmsd = &vmstate_piix3;
662 dc->no_user = 1;
663 k->no_hotplug = 1;
664 k->init = piix3_initfn;
665 k->config_write = piix3_write_config_xen;
666 k->vendor_id = PCI_VENDOR_ID_INTEL;
667 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
668 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
669 k->class_id = PCI_CLASS_BRIDGE_ISA;
670 };
671
672 static const TypeInfo piix3_xen_info = {
673 .name = "PIIX3-xen",
674 .parent = TYPE_PCI_DEVICE,
675 .instance_size = sizeof(PIIX3State),
676 .class_init = piix3_xen_class_init,
677 };
678
679 static void i440fx_class_init(ObjectClass *klass, void *data)
680 {
681 DeviceClass *dc = DEVICE_CLASS(klass);
682 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
683
684 k->no_hotplug = 1;
685 k->init = i440fx_initfn;
686 k->config_write = i440fx_write_config;
687 k->vendor_id = PCI_VENDOR_ID_INTEL;
688 k->device_id = PCI_DEVICE_ID_INTEL_82441;
689 k->revision = 0x02;
690 k->class_id = PCI_CLASS_BRIDGE_HOST;
691 dc->desc = "Host bridge";
692 dc->no_user = 1;
693 dc->vmsd = &vmstate_i440fx;
694 }
695
696 static const TypeInfo i440fx_info = {
697 .name = TYPE_I440FX_PCI_DEVICE,
698 .parent = TYPE_PCI_DEVICE,
699 .instance_size = sizeof(PCII440FXState),
700 .class_init = i440fx_class_init,
701 };
702
703 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
704 PCIBus *rootbus)
705 {
706 /* For backwards compat with old device paths */
707 return "0000";
708 }
709
710 static Property i440fx_props[] = {
711 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
712 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
713 DEFINE_PROP_END_OF_LIST(),
714 };
715
716 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
717 {
718 DeviceClass *dc = DEVICE_CLASS(klass);
719 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
720
721 hc->root_bus_path = i440fx_pcihost_root_bus_path;
722 dc->realize = i440fx_pcihost_realize;
723 dc->fw_name = "pci";
724 dc->no_user = 1;
725 dc->props = i440fx_props;
726 }
727
728 static const TypeInfo i440fx_pcihost_info = {
729 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
730 .parent = TYPE_PCI_HOST_BRIDGE,
731 .instance_size = sizeof(I440FXState),
732 .instance_init = i440fx_pcihost_initfn,
733 .class_init = i440fx_pcihost_class_init,
734 };
735
736 static void i440fx_register_types(void)
737 {
738 type_register_static(&i440fx_info);
739 type_register_static(&piix3_info);
740 type_register_static(&piix3_xen_info);
741 type_register_static(&i440fx_pcihost_info);
742 }
743
744 type_init(i440fx_register_types)
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